Preparation method of silicon capacitor and silicon capacitor

Abstract

The invention provides a preparation method of a silicon capacitor and the silicon capacitor, and relates to the technical field of capacitors, and the preparation method comprises the steps: etching a plurality of groove regions on a substrate slice; a plurality of layers of capacitor units are stacked on a substrate sheet containing a groove region from bottom to top, and each capacitor unit comprises a plurality of conductive layers and dielectric layers which are alternately stacked in a cross shape from inside to outside; a first electrode and a second electrode of each capacitor unit are formed at the top of the uppermost capacitor unit, the first electrode is connected with all the odd-numbered conducting layers, and the second electrode is connected with the substrate slice and all the even-numbered conducting layers. The silicon capacitor has the beneficial effects that the effective capacitance is increased downwards by arranging the groove region, and the effective capacitance is increased upwards by forming the multiple layers of capacitor units through alternate stacking, so that the capacity density can be increased, and the silicon capacitor with small size and high capacitance density can be prepared; the device is small in occupied area, high in unit volume utilization rate, suitable for semiconductor manufacturing procedures and beneficial to device integration and miniaturization.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitors, and in particular to a method for preparing a silicon capacitor and a silicon capacitor. Background Art

[0002] In the complex network of electronic systems, passive components play a vital role. Although they do not directly control the flow of current, they are an indispensable part of the stable operation of the circuit. Among them, capacitors, as devices for storing charge, are widely used in filtering, decoupling, energy storage and other occasions. Traditional capacitors, depending on the different insulator materials used, have formed various types such as electrolytic capacitors, tantalum capacitors and multilayer ceramic capacitors (MLCC), each type has its specific application scenarios and advantages. However, with the continuous evolution of electronic systems towards high performance and high reliability, the failure rate of these traditional capacitors has increased significantly under certain extreme conditions, such as high temperature, high frequency or high DC bias, becoming a key factor restricting the overall performance of the system.

[0003] Faced with the limitations of traditional capacitors, silicon capacitors came into being. Silicon capacitors are manufactured using semiconductor technology, with silicon as the base material and a capacitor structure formed through precise micro-nano processing technology. This innovation not only breaks through the limitations of traditional capacitors in materials and processes, but also achieves a qualitative leap in performance. Because silicon materials themselves have excellent thermal and chemical stability, silicon capacitors can maintain a stable capacitance value in extreme environments, greatly reducing performance fluctuations caused by environmental changes.

[0004] The unique advantages of silicon capacitors make them shine in many high-end applications: 1. In the industrial field: The electronic control systems in natural gas or oil drilling equipment have extremely high requirements on the stability and reliability of capacitors. Silicon capacitors are an ideal choice due to their excellent environmental adaptability and long life.

[0005] 2. In the field of consumer electronics: Silicon capacitors are used as decoupling capacitors inside the processors (APU) and system-on-chip (SOC) of high-end smartphones, tablets and other devices, effectively reducing power supply noise and improving the overall performance of the system. With the rapid development of autonomous driving technology, automotive electronics has become one of the important application areas of silicon capacitors. High-precision sensors and actuators such as lidar and advanced driver assistance systems (ADS) have extremely high requirements for power supply stability and response speed. Silicon capacitors, with their low ESR (equivalent series resistance) and high-frequency response, provide reliable power support for these systems. In addition, in communication infrastructure such as 5G base stations and optical communication equipment, silicon capacitors also play an irreplaceable role, ensuring the stability and reliability of high-speed data transmission.

[0006] 3. In the medical field: Especially implantable medical devices, which have extremely high requirements for the reliability and biocompatibility of components. Silicon capacitors, with their non-toxic, harmless and long life, have become the preferred capacitor components for implantable cardiac pacemakers, neural stimulators and other devices.

[0007] 4. In the field of optical communications: With the vigorous development of technologies such as big data and cloud computing, data centers have an increasing demand for data transmission rate and capacity. Silicon capacitors, with their high integration and low loss characteristics, provide strong support for the miniaturization and high speed of optical modules.

[0008] As silicon capacitors play an increasingly important role in electronic systems, the requirements for silicon capacitors are also getting higher and higher. How to achieve higher density mounting and support higher integration design solutions has become the main challenge in the development of silicon capacitor technology. Summary of the invention

[0009] In view of the problems existing in the prior art, the present invention provides a method for preparing a silicon capacitor, comprising: step S1, etching a plurality of groove areas on a substrate sheet; step S2, stacking from bottom to top on the substrate sheet containing the groove areas to form multilayer capacitor units, each capacitor unit comprising a plurality of conductive layers and dielectric layers alternately stacked from inside to outside in a cross shape; the capacitor units of two adjacent layers are staggered in the stacking direction; step S3, forming a first electrode and a second electrode of each capacitor unit on the top of the capacitor unit in the uppermost layer, the first electrode connecting the conductive layers of all odd-numbered layers, and the second electrode connecting the substrate sheet and the conductive layers of all even-numbered layers.

[0010] Preferably, in the step S1, the groove region is etched out by one photolithography step, or the groove region with the first step is etched out by at least two photolithography steps.

[0011] Preferably, in step S2, the process of forming a layer of the capacitor unit on the substrate sheet including the groove area includes: step S21, alternately depositing multiple layers of first dielectric layers and first conductive layers in sequence to form a first stack; step S22, performing a stepping process on the top of the first stack to form a second step, and then alternately depositing multiple layers of second dielectric layers and second conductive layers with the same number of layers as the first stack to form a second stack; in the second stack, the topmost second conductive layer is connected to the substrate sheet, and the remaining second conductive layers are respectively connected to the corresponding first conductive layers in sequence, and each second dielectric layer is connected to the first dielectric layer in a one-to-one correspondence.

[0012] Preferably, when the capacitor unit is multi-layer, after executing step S22, the method further includes using the formed second stack as the first stack, and then repeating step S22.

[0013] Preferably, when the capacitor unit is multi-layer, in the step S22, the second step is formed on the top of the first stack deposited for odd times corresponding to the upper area between two adjacent groove areas; and the second step is formed on the top of the first stack deposited for even times corresponding to the upper area of ​​each groove area.

[0014] Preferably, the step S22 comprises: step S221, performing a stepping process on the top of the first stack to form a second step, wherein the second step of the bottom layer exposes the substrate sheet in the horizontal direction, the second steps of the remaining layers expose the first conductive layer in the horizontal direction, and the second steps of each layer expose the adjacent first dielectric layer and the first conductive layer in the vertical direction; step S222, depositing a layer of the second dielectric layer on the top of the first stack, then removing the second dielectric layer in the horizontal direction at the second step of each layer, and keeping the currently deposited second dielectric layer connected to the first dielectric layer closest to the first stack; step S223, depositing a layer of the second conductive layer on the second dielectric layer, then removing the second conductive layer in the horizontal direction at the second step of each layer, and keeping the currently deposited second conductive layer connected to the second conductive layer closest to the first stack; step S224, repeating the steps S222 and S223 until a second stack having the same number of layers as the first stack is formed.

[0015] Preferably, the step S3 includes: step S31, processing the top of the uppermost capacitor unit so that the conductive layer and the dielectric layer of each layer of the uppermost capacitor unit are exposed on the surface; step S32, depositing a third dielectric layer; step S33, forming a plurality of contact holes on the third dielectric layer, followed by metal deposition, and forming the first electrode and the second electrode by photolithography and metal etching.

[0016] Preferably, in the step S31, the top of the uppermost capacitor unit is processed by chemical mechanical polishing.

[0017] Preferably, in the step S31, the top of the uppermost capacitor unit is processed by continuously performing patterning and etching in a top-to-bottom order according to a pre-designed mask; in the step S33, before metal deposition, it also includes filling metal tungsten plugs in each of the contact holes.

[0018] The present invention also provides a silicon capacitor, which is prepared by the above-mentioned preparation method, comprising: a substrate sheet, on which a plurality of groove areas are etched; a plurality of multilayer capacitor units, which are stacked from bottom to top on the substrate sheet including the groove areas, each of which comprises a plurality of conductive layers and dielectric layers alternately stacked from inside to outside in a cross shape; electrodes, comprising a first electrode and a second electrode, which are formed on the top of the capacitor unit in the uppermost layer, the first electrode connecting the conductive layers of all odd-numbered layers, and the second electrode connecting the substrate sheet and the conductive layers of all even-numbered layers.

[0019] The above technical solution has the following advantages or beneficial effects: 1) By setting the groove area, the effective capacitance is increased downward, and by alternately stacking to form a multilayer capacitor unit, the effective capacitance is increased upward, and the capacitor units of two adjacent layers are staggered in the stacking direction, so that the capacitor unit can be stacked directly above the two adjacent capacitor units of the current level, and the upper area between the two adjacent capacitor units can also be stacked to form a capacitor unit, so that the capacitor unit can be formed not only on the substrate, but also on the upper surface of the substrate, thereby increasing the chip utilization rate and the capacitance density, and realizing the preparation of a small-sized, high-capacitance-density silicon capacitor; 2) The silicon capacitor prepared by the present invention occupies a small area and has a high unit volume utilization rate, is suitable for semiconductor manufacturing processes, and is conducive to device integration and miniaturization; 3) Each capacitor unit is cross-shaped, with a simple structure and can achieve staggered splicing between two adjacent capacitor units in two adjacent layers, further improving the chip unit volume utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a process for preparing a silicon capacitor in a preferred embodiment of the present invention; Figure 2 is a schematic diagram of forming a groove region with a first step on a substrate in Example 1; Figure 3 This is a schematic diagram of a sub-process of step S2 in Example 1; Figure 4 is a schematic diagram of forming a first stack in Example 1; Figure 5 This is a schematic diagram of a sub-process of step S22 in Example 1; Figure 6 is a schematic diagram of forming a second step in Example 1; Figure 7 is a schematic diagram of depositing the second dielectric layer 4a in Example 1; Figure 8This is a schematic diagram of Example 1 after removing the redundant second dielectric layer 4a; Fig. 9 is a schematic diagram of depositing the second conductive layer 4b and removing the excess second conductive layer 4b in Example 1; Fig.10 is a schematic diagram of depositing the second dielectric layer 5a in Example 1; Fig.11 is a schematic diagram of depositing the second conductive layer 5b in Example 1; Fig.12 is a schematic diagram of depositing the second dielectric layer 6a in Example 1; Fig.13 is a schematic diagram of depositing the second conductive layer 6b in Example 1; Fig.14 is a schematic diagram of exposing each dielectric layer and conductive layer of the second stack in Example 1; Fig.15 is a schematic diagram of depositing the second stack again in Example 1; Fig.16 In Example 1, Fig.15 A schematic diagram of forming a second step on the basis of; Fig.17 In Example 1, Fig.16 Schematic diagram of depositing a second stack of layers again on the basis of the above; Fig.18 This is a schematic diagram of a sub-process of step S3 in Example 1; Fig.19 In one embodiment of Example 1, Fig.18 A schematic diagram of exposing each dielectric layer and conductive layer of the second stack on the basis of the present invention; Fig. 20 In Example 1, Fig.19 Schematic diagram of depositing a third dielectric layer 1c on the basis of; Fig.21 In Example 1, Fig. 20 A schematic diagram of forming a first electrode and a second electrode on the basis of Fig. 22 In another embodiment of Example 1, Fig.18 A schematic diagram of exposing each dielectric layer and conductive layer of the second stack on the basis of the present invention; Fig.23 In Example 1, Fig. 22 Schematic diagram of depositing a third dielectric layer 1c on the basis of; Fig.24 In Example 1, Fig.23 A schematic diagram of forming a first electrode and a second electrode on the basis of Fig.25is a schematic structural diagram of a silicon capacitor finally obtained by forming a plurality of second stacked layers in Example 1; Fig.26 This is a schematic diagram of the structure of a silicon capacitor in Example 2. DETAILED DESCRIPTION

[0021] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0022] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a method for preparing a silicon capacitor is provided. Figure 1 As shown, it includes: step S1, etching a plurality of groove areas on a substrate sheet; step S2, stacking from bottom to top on the substrate sheet containing the groove areas to form multi-layer capacitor units, each capacitor unit includes multiple conductive layers and dielectric layers alternately stacked from inside to outside in a cross shape; each capacitor unit of two adjacent layers is staggered in the stacking direction; step S3, forming a first electrode and a second electrode of each capacitor unit on the top of the capacitor unit of the top layer, the first electrode connecting all the conductive layers of the odd layers, and the second electrode connecting the substrate sheet and all the conductive layers of the even layers.

[0023] Example 1 In this embodiment, the substrate sheet 1 should be made of low-resistance material, and the resistivity should be less than 0.1Ω·cm. A silicon substrate is preferably used. On the one hand, a relatively low-cost silicon process can be used to produce high-quality integrated surfaces of passive devices. On the other hand, since the base materials of the passive devices and the active devices are the same, when the two are connected, small-pitch internal interconnect lines can be used for interconnection. In this way, the mismatch caused by thermal expansion will be very small, thereby optimizing the device performance.

[0024] It should be noted that the substrate 1 may include semiconductor elements, such as single crystal, polycrystalline or amorphous silicon or silicon germanium, or a mixed semiconductor structure, such as silicon carbide, gallium arsenide, indium antimonide, gallium nitride, lead telluride, indium arsenide, or other alloy semiconductors or combinations thereof; or silicon on insulator (SOI). In addition, other materials may also be included, such as a multilayer structure of an epitaxial layer or a buried layer. Any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.

[0025] like Figure 2 As shown, the groove region 2 formed on the substrate 1 has a first step 3. The number of the first step 3 is not limited and can be obtained by at least two steps of photolithography. Figure 2The first step 3 shown is obtained by two-step photolithography. If there are more steps, they can be obtained by more than two-step photolithography. The cross section of the groove region 2 can be square, circular, or any polygon.

[0026] Subsequently, multiple alternating depositions are performed on the surface of the substrate sheet 1 with the groove region 2 to stack and form a multilayer capacitor unit, wherein Figure 3 As shown, the process of forming a capacitor unit layer on a substrate sheet including a groove area includes: step S21, alternately depositing multiple first dielectric layers and first conductive layers in sequence to form a first stack; step S22, performing a stepping process on the top of the first stack to form a second step, and then alternately depositing multiple second dielectric layers and second conductive layers with the same number of layers as the first stack to form a second stack; in the second stack, the topmost second conductive layer is connected to the substrate sheet, and the remaining second conductive layers are connected to the corresponding first conductive layers in sequence, and each second dielectric layer is connected to the first dielectric layer in a one-to-one correspondence.

[0027] Specifically, the number of times the first dielectric layer and the first conductive layer are alternately deposited can be manually adjusted according to the requirements of the electrostatic capacitance. In this embodiment, the first stack includes three first dielectric layers and three first conductive layers as an example. Figure 4 As shown, the first dielectric layer 1a, the first conductive layer 1b, the first dielectric layer 2a, the first conductive layer 2b, the first dielectric layer 3a, and the first conductive layer 3b are stacked.

[0028] The first dielectric layer is an insulating material, preferably, one or a combination of insulating materials such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, etc. The material and thickness of each first dielectric layer can be the same or different.

[0029] The first conductive layer is a conductive material, preferably polysilicon, titanium nitride, or other conductive metal materials. The material and thickness of each first conductive layer can be the same or different.

[0030] Then, step S22 is performed to form a second stack on the first stack. Specifically, Figure 5As shown, step S22 includes: step S221, performing a stepping process on the top of the first stack to form a second step, the second step of the bottom layer exposes the substrate sheet in the horizontal direction, the second steps of the remaining layers expose the first conductive layer in the horizontal direction, and the second steps of each layer expose the adjacent first dielectric layer and the first conductive layer in the vertical direction; step S222, depositing a second dielectric layer on the top of the first stack, then removing the second dielectric layer in the horizontal direction at the second step of each layer, and keeping the currently deposited second dielectric layer connected to the closest first dielectric layer in the first stack; step S223, depositing a second conductive layer on the second dielectric layer, then removing the second conductive layer in the horizontal direction at the second step of each layer, and keeping the currently deposited second conductive layer connected to the closest second conductive layer in the first stack; step S224, repeating step S222 and step S223 until a second stack with the same number of layers as the first stack is formed.

[0031] In this embodiment, after the first stack is formed, PR patterning and etching are preferably performed successively from top to bottom through a pre-designed mask to complete the stepping of each first conductive layer and the first dielectric layer in the first stack, forming a Figure 6 The second step 4 is shown.

[0032] When the first stack includes three first dielectric layers and three first conductive layers, the corresponding second stack also includes three second dielectric layers and three second conductive layers. The formation process of the second stack is as follows: Figure 7 As shown, a second dielectric layer 4a is deposited on the surface, and the second dielectric layer 4a is patterned and etched to remove excess dielectric at the step, so that the second dielectric layer 4a is connected to the first dielectric layer 3a, and the first conductive layer 3b is isolated from the first conductive layer 2b, as shown in FIG. Figure 8 shown.

[0033] like Fig. 9 As shown, a second conductive layer 4b is deposited on the surface, and the second conductive layer 4b is patterned and etched to remove the redundant conductive layer at the step, so that the second conductive layer 4b is connected to the first conductive layer 2b.

[0034] like Fig.10 As shown, a second dielectric layer 5a is deposited on the above surface, and the second dielectric layer 5a is patterned and etched to remove the redundant dielectric layer at the step, so that the second dielectric layer 5a is connected to the first dielectric layer 2a, and the first conductive layer 2b and the first conductive layer 1b are isolated.

[0035] like Fig.11As shown, a second conductive layer 5b is deposited on the surface, and the second conductive layer 5b is patterned and etched to remove the redundant conductive layer at the step, so that the second conductive layer 5b is connected to the first conductive layer 1b.

[0036] like Fig.12 As shown, a second dielectric layer 6a is deposited on the above surface, and the second dielectric layer 6a is patterned and etched to remove the excess dielectric layer at the step, so that the second dielectric layer 6a is connected to the first dielectric layer 1a and isolates the first conductive layer 1b from the conductive substrate 1.

[0037] like Fig.13 As shown, finally, a second conductive layer 6b is deposited on the above surface, so that the second conductive layer 6b is connected to the conductive substrate sheet 1, thereby completing the formation of the second stacked layer.

[0038] Furthermore, when the capacitor unit is multi-layered, after executing step S22, it further includes using the formed second stacked layer as the first stacked layer, and then repeating step S22.

[0039] Specifically, Fig.14 As shown, PR patterning and etching are continuously performed on the top of the second stacked layer formed above in a top-to-bottom order through a pre-designed mask to complete the stepping of the second dielectric layer 4a, the second dielectric layer 5a, the second dielectric layer 6a, and the second conductive layer 4b, the second conductive layer 5b, and the second conductive layer 6b. Fig.15 As shown, the second stacking process is repeated once to continuously stack dielectric layers and conductive layers upward. PR patterning and etching are continuously performed on the surface again to complete the stepping process, as shown in FIG. Fig.16 As shown. Fig.17 As shown, the above-mentioned second stacking process can be repeated once more to continuously stack dielectric layers and conductive layers upwards.

[0040] By analogy, the above-mentioned stepping treatment and the second stacking layer forming process can be repeated multiple times, and the number of repetitions can be manually adjusted according to the requirements of the electrostatic capacitance.

[0041] In this embodiment, when the capacitor unit is multi-layer, in step S22, a second step is formed on the top of the first stack deposited for odd times corresponding to the upper area between two adjacent groove areas; a second step is formed on the top of the first stack deposited for even times corresponding to the upper area of ​​each groove area.

[0042] Specifically, it can be seen that when the second step is formed by the first stepping treatment, the second step is formed in the upper area between the two groove areas, when the second stepping treatment forms the second step, the second step is formed in the area directly above each groove area, and when the second step is formed by the third stepping treatment, the second step is formed in the upper area between the two groove areas, that is, directly above the area of ​​the first stepping treatment, and so on. The second steps formed by odd and even times are staggered, so that the capacitor units formed in two adjacent layers are staggered.

[0043] After repeatedly forming the second stack, in this embodiment, Fig.18 As shown, step S3 includes: step S31, processing the top of the uppermost capacitor unit so that the conductive layers and dielectric layers of the uppermost capacitor unit are exposed on the surface; step S32, depositing a third dielectric layer; step S33, forming a plurality of contact holes on the third dielectric layer, then performing metal deposition, and forming a first electrode and a second electrode by photolithography and metal etching.

[0044] Specifically, as a preferred embodiment, in step S31, the top of the uppermost capacitor unit is processed by chemical mechanical polishing, so that the surfaces of the dielectric layers and the conductive layers are exposed. Fig.19 shown.

[0045] like Fig. 20 As shown, a third dielectric layer 1c is then deposited on the surface. The third dielectric layer 1c may be an oxide layer, borophosphorus glass, or a combination of multiple insulating layers.

[0046] Then, photolithography and etching are performed on the above surface to form contact holes. Then, metal deposition is performed to form a contact hole through photolithography and metal etching. Fig.21 The first electrode 5 and the second electrode 6 are shown. The first electrode 5 connects all odd-numbered conductive layers such as the first conductive layer 1b, the first conductive layer 3b, and the second conductive layer 5b; the second electrode 6 connects all even-numbered conductive layers such as the conductive substrate sheet 1, the first conductive layer 2b, and the second conductive layer 6b. The first electrode 5 and the second electrode 6 are two lead electrodes of the silicon capacitor.

[0047] As another preferred embodiment, in step S31, the top of the uppermost capacitor unit is processed by continuously performing patterning and etching processing in a top-to-bottom order according to a pre-designed mask, so that the surface of each conductive layer is exposed, such as Fig. 22 shown.

[0048] like Fig.23 As shown, a third dielectric layer 1c is then deposited on the surface. The third dielectric layer 1c may be an oxide layer, borophosphorus glass, or a combination of multiple insulating layers.

[0049] Then, a contact hole is formed on the surface, filled with a metal tungsten plug, and then metal deposition is performed. By photolithography and metal etching, a contact hole is formed. Fig.24 The first electrode 5 and the second electrode 6 are shown. The first electrode 5 connects all odd-numbered conductive layers such as the first conductive layer 1b, the first conductive layer 3b, and the second conductive layer 5b; the second electrode 6 connects all even-numbered conductive layers such as the conductive substrate sheet 1, the first conductive layer 2b, and the second conductive layer 6b. The first electrode 5 and the second electrode 6 are two lead electrodes of the silicon capacitor.

[0050] When the second stack is multiple, the structure of the silicon capacitor finally formed is as follows Fig.25 shown.

[0051] Example 2 In this embodiment, the remaining preparation steps are the same as those in Embodiment 1, except that the groove region in this embodiment is a groove region vertically downward without steps, and the groove region can be etched out by photolithography once. The structure of the silicon capacitor finally formed is as follows: Fig.26 shown.

[0052] The present invention also provides a silicon capacitor, which is prepared by the above-mentioned preparation method, such as Fig.24 or Fig.25 or Fig.26 As shown, it includes: a substrate sheet 1, on which a plurality of groove areas 2 are etched; a multilayer capacitor unit is stacked from bottom to top on the substrate sheet 1 including the groove area 2, and each capacitor unit includes a plurality of conductive layers and dielectric layers alternately stacked from inside to outside in a cross shape; electrodes, including a first electrode 5 and a second electrode 6, are formed on the top of the uppermost capacitor unit, the first electrode 5 is connected to all the odd-numbered conductive layers, and the second electrode 6 is connected to the substrate sheet and all the even-numbered conductive layers.

[0053] in, Fig.24 and Fig.25 The middle trench region 2 includes a first step, Fig.26 The middle trench region 2 does not include the first step.

[0054] In summary, the present invention increases the effective capacitance area downward by adding a groove structure to the silicon substrate and stacking multiple dielectric layers and conductive layers, and forms a Fig.24 or Fig.25 The first layer of capacitor units shown in the figure includes capacitor units C1, capacitor units C2, and capacitor units C3. On the other hand, on the substrate, through multiple photolithography, etching, and lamination, the capacitor unit C4 in the figure is a "cross" type capacitor repeating unit, and the capacitor unit C4 is stacked upward to obtain the following Fig.24The second layer of capacitor units includes capacitor unit C4 and capacitor unit C5, and the third layer of capacitor units includes capacitor unit C6, capacitor unit C7 and capacitor unit C8. In the figure, capacitor unit C1, capacitor unit C2, capacitor unit C3, capacitor unit C6, capacitor unit C7 and capacitor unit C8 use the first conductive layer 3b as the inner electrode and the second conductive layer 6b as the outer electrode; capacitor unit C4 and capacitor unit C5 use the second conductive layer 6b as the inner electrode and the first conductive layer 3b as the outer electrode. Therefore, capacitor unit C1 to capacitor unit C8 are connected in parallel with each other, so that the present invention is as follows Fig.24 The total capacitance of the silicon capacitor shown is C = C1 + C2 + C3 + C4 + C5 + C6 + C7 + C8.

[0055] It can be seen that the present invention increases the effective capacitance downward through the trench region 2 and upward through the staggered parallel repeating units ( Fig.24 and Fig.25 The invention can increase the chip utilization rate and the capacity density. The three-dimensional capacitor structure provided has a small occupied area and a high unit volume utilization rate, is suitable for semiconductor manufacturing processes, and is conducive to device integration and miniaturization.

[0056] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A method for preparing a silicon capacitor, characterized in that: include: Step S1, etching a plurality of groove regions on a substrate; Step S2, stacking from bottom to top on the substrate sheet including the groove area to form multilayer capacitor units, each capacitor unit includes multiple conductive layers and dielectric layers alternately stacked from inside to outside in a cross shape; the capacitor units of two adjacent layers are staggered in the stacking direction; Step S3, forming a first electrode and a second electrode of each capacitor unit on the top of the capacitor unit in the top layer, the first electrode connecting the conductive layers of all odd layers, and the second electrode connecting the substrate sheet and the conductive layers of all even layers.

2. The preparation method according to claim 1, characterized in that: In the step S1, the groove region is etched out by photolithography in one step, or the groove region with the first step is etched out by photolithography in at least two steps.

3. The preparation method according to claim 1, characterized in that: In the step S2, the process of forming a layer of the capacitor unit on the substrate sheet including the groove area includes: step S21, alternately depositing multiple layers of first dielectric layers and first conductive layers in sequence to form a first stack; step S22, performing a stepping process on the top of the first stack to form a second step, and then alternately depositing multiple layers of second dielectric layers and second conductive layers having the same number of layers as the first stack to form a second stack; in the second stack, the topmost second conductive layer is connected to the substrate sheet, and the remaining second conductive layers are respectively connected to the corresponding first conductive layers in sequence, and each second dielectric layer is connected to the first dielectric layer in a one-to-one correspondence.

4. The preparation method according to claim 3, characterized in that: When the capacitor unit is multi-layered, after executing step S22, the method further includes using the formed second stacked layer as the first stacked layer, and then repeating step S22.

5. The preparation method according to claim 3, characterized in that: When the capacitor unit is multi-layer, in the step S22, the second step is formed on the top of the first stack deposited for odd times corresponding to the upper area between two adjacent groove areas; the second step is formed on the top of the first stack deposited for even times corresponding to the upper area of ​​each groove area.

6. The preparation method according to claim 3, characterized in that: The step S22 comprises: step S221, performing a stepping process on the top of the first stack to form a second step, wherein the second step of the bottom layer exposes the substrate sheet in the horizontal direction, the second steps of the remaining layers expose the first conductive layer in the horizontal direction, and the second steps of each layer expose the adjacent first dielectric layer and the first conductive layer in the vertical direction; step S222, depositing a layer of the second dielectric layer on the top of the first stack, then removing the second dielectric layer in the horizontal direction at the second step of each layer, and keeping the currently deposited second dielectric layer connected to the first dielectric layer closest to the first stack; step S223, depositing a layer of the second conductive layer on the second dielectric layer, then removing the second conductive layer in the horizontal direction at the second step of each layer, and keeping the currently deposited second conductive layer connected to the second conductive layer closest to the first stack; step S224, repeating the steps S222 and S223 until a second stack having the same number of layers as the first stack is formed.

7. The preparation method according to claim 1, characterized in that: The step S3 includes: step S31, processing the top of the uppermost capacitor unit so that the conductive layer and the dielectric layer of each layer of the uppermost capacitor unit are exposed on the surface; step S32, depositing a third dielectric layer; step S33, forming a plurality of contact holes on the third dielectric layer, then performing metal deposition, and forming the first electrode and the second electrode by photolithography and metal etching.

8. The preparation method according to claim 7, characterized in that: In the step S31, the top of the uppermost capacitor unit is processed by chemical mechanical polishing.

9. The preparation method according to claim 7, characterized in that: In the step S31, the top of the uppermost capacitor unit is processed by patterning and etching in a sequential order from top to bottom according to a pre-designed mask; in the step S33, before metal deposition, a metal tungsten plug is filled in each of the contact holes.

10. A silicon capacitor, characterized in that: It is prepared by the preparation method as described in any one of claims 1 to 9, comprising: a substrate sheet, on which a plurality of groove areas are etched; a plurality of multilayer capacitor units are stacked from bottom to top on the substrate sheet including the groove areas, each of the capacitor units comprising a plurality of conductive layers and dielectric layers alternately stacked from inside to outside in a cross shape; electrodes, including a first electrode and a second electrode, are formed on the top of the uppermost capacitor unit, the first electrode is connected to the conductive layers of all odd-numbered layers, and the second electrode is connected to the substrate sheet and the conductive layers of all even-numbered layers.

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