Preparation method of a silicon capacitor and the silicon capacitor

Abstract

The present invention provides a method for manufacturing a silicon capacitor and a silicon capacitor, relating to the technical field of capacitors, including: etching a plurality of trench regions on a substrate wafer; stacking multiple capacitor units from bottom to top on the substrate wafer including the trench regions, each capacitor unit including multiple conductive layers and dielectric layers stacked alternately from the inside to the outside in a cross shape; forming a first electrode and a second electrode of each capacitor unit on the top of the uppermost capacitor unit, the first electrode being connected to all odd-numbered conductive layers, and the second electrode being connected to the substrate wafer and all even-numbered conductive layers. The beneficial effects are that by setting the trench regions, the effective capacitance is increased downward, and by alternately stacking to form multiple capacitor units, the effective capacitance is increased upward, thereby enabling the capacitance density to become larger, realizing the ability to manufacture silicon capacitors with small size and high capacitance density; occupying a small area and having a high utilization rate of unit volume, being suitable for semiconductor processes, and being beneficial to device integration and miniaturization.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitors, and particularly to a preparation method and a silicon capacitor of a silicon capacitor. Background Art

[0002] In the complex network of an electronic system, passive components play a crucial role. Although they do not directly control the current flow, they are an essential part for the stable operation of the circuit. Among them, capacitors, as devices for storing electric charges, are widely used in various applications such as filtering, decoupling, and energy storage. Traditional capacitors, according to the different insulating materials used, form various types such as electrolytic capacitors, tantalum capacitors, and multilayer ceramic capacitors (MLCCs). Each type has its specific application scenarios and advantages. However, with the continuous evolution of electronic systems towards high performance and high reliability, the failure rate of these traditional capacitors increases significantly under certain extreme conditions, such as high temperature, high frequency, or high DC bias voltage, becoming a key factor restricting the overall performance of the system.

[0003] In the face of the limitations of traditional capacitors, silicon capacitors emerge as the times require. Silicon capacitors are manufactured using semiconductor processes, with silicon as the substrate material, and a capacitive structure is formed through precise micro-nano processing techniques. This innovation not only breaks through the limitations of traditional capacitors in materials and processes, but also achieves a qualitative leap in performance. Due to the excellent thermal stability and chemical stability of silicon itself, silicon capacitors can maintain a stable capacitance value in extreme environments, greatly reducing the performance fluctuations caused by environmental changes.

[0004] The unique advantages of silicon capacitors make them shine in many high-end applications:

[0005] 1. In the industrial field: The electronic control systems in natural gas or oil drilling equipment have extremely high requirements for the stability and reliability of capacitors. Silicon capacitors, with their excellent environmental adaptability and long lifespan, become the ideal choice.

[0006] 2. In the consumer electronics field: Inside the processors (APUs) and system-on-chip (SOCs) of high-end smartphones, tablets and other devices, silicon capacitors, as decoupling capacitors, effectively reduce the power supply noise and improve the overall performance of the system. With the rapid development of autonomous driving technology, automotive electronics has become one of the important application fields of silicon capacitors. High-precision sensors and actuators such as lidar and advanced driver assistance systems (ADS) have extremely high requirements for the stability and response speed of the power supply. Silicon capacitors, with their characteristics of low ESR (equivalent series resistance) and fast high-frequency response, provide reliable power support for these systems. In addition, in communication infrastructures such as 5G base stations and optical communication devices, silicon capacitors also play an irreplaceable role, ensuring the stability and reliability of high-speed data transmission.

[0007] 3. In the medical field: especially for implantable medical devices, extremely high requirements are placed on the reliability and biocompatibility of components. Silicon capacitors, with their non-toxic, harmless, and long-life characteristics, have become the preferred capacitive components for devices such as implantable cardiac pacemakers and nerve stimulators.

[0008] 4. In the field of optical communication: With the booming development of technologies such as big data and cloud computing, the demand for data transmission rate and capacity in data centers is increasing day by day. Silicon capacitors, with their high integration and low loss characteristics, provide strong support for the miniaturization and high speed of optical modules.

[0009] As silicon capacitors play an increasingly important role in electronic systems, the requirements for silicon capacitors are also getting higher and higher. How to achieve higher-density mounting and support higher-integration design schemes has become the main challenge in the development of silicon capacitor technology. Summary of the Invention

[0010] Aiming at the problems existing in the prior art, the present invention provides a preparation method for a silicon capacitor, including: Step S1, etching a plurality of trench regions on a substrate wafer; Step S2, stacking multiple capacitive units from bottom to top on the substrate wafer including the trench regions, each capacitive unit including multiple conductive layers and dielectric layers stacked alternately from the inside to the outside in a cross shape; the adjacent two capacitive units are staggered in the stacking direction; Step S3, forming a first electrode and a second electrode for each capacitive unit on the top of the topmost capacitive unit, the first electrode connecting all odd-layer conductive layers, and the second electrode connecting the substrate wafer and all even-layer conductive layers.

[0011] Preferably, in Step S1, the trench regions are etched through one photolithography process, or the trench regions with a first step are etched through at least two photolithography processes.

[0012] Preferably, in Step S2, the process of forming one layer of the capacitive unit on the substrate wafer including the trench regions includes: Step S21, alternately depositing multiple first dielectric layers and first conductive layers in sequence to form a first stack; Step S22, performing a step-forming process on the top of the first stack to form a second step, and then alternately depositing multiple second dielectric layers and second conductive layers with the same number of layers as the first stack in sequence to form a second stack; in the second stack, the topmost second conductive layer is connected to the substrate wafer, and the remaining second conductive layers are respectively connected to the corresponding first conductive layers in sequence, and each second dielectric layer is connected to the corresponding first dielectric layer.

[0013] Preferably, when the capacitive unit is multi-layered, after performing Step S22, it further includes using the formed second stack as the first stack, and then repeating Step S22.

[0014] Preferably, when the capacitor unit is multilayered, in step S22, for the top of the first stack deposited for an odd number of times, a second step is formed in the upper region corresponding to the region between two adjacent trench regions; for the top of the first stack deposited for an even number of times, a second step is formed in the upper region corresponding to each trench region.

[0015] Preferably, step S22 includes: step S221, performing a stepwise treatment on the top of the first stack to form a second step, the bottommost second step exposing the substrate wafer in the horizontal direction, and the other layers of the second step exposing the first conductive layer in the horizontal direction, and each layer of the second step exposing the adjacent first dielectric layer and the first conductive layer in the vertical direction; step S222, depositing a layer of the second dielectric layer on the top of the first stack, and then removing the second dielectric layer in the horizontal direction at each layer of the second step, and keeping the currently deposited second dielectric layer connected to the closest first dielectric layer in the first stack; step S223, depositing a layer of the second conductive layer on the second dielectric layer, and then removing the second conductive layer in the horizontal direction at each layer of the second step, and keeping the currently deposited second conductive layer connected to the closest second conductive layer in the first stack; step S224, repeating step S222 and step S223 until a second stack having the same number of layers as the first stack is formed.

[0016] Preferably, step S3 includes: step S31, processing the top of the topmost capacitor unit so that the conductive layers and dielectric layers of each layer of the topmost capacitor unit are exposed on the surface; step S32, depositing a layer of the third dielectric layer; step S33, forming a plurality of contact holes in the third dielectric layer, then performing metal deposition, and forming the first electrode and the second electrode through photolithography and metal etching.

[0017] Preferably, in step S31, processing the top of the topmost capacitor unit is to perform chemical mechanical polishing.

[0018] Preferably, in step S31, processing the top of the topmost capacitor unit is to continuously perform patterning and etching processing in the order from top to bottom according to a pre-designed photomask; in step S33, before performing metal deposition, it further includes filling tungsten plugs in each contact hole.

[0019] The present invention also provides a silicon capacitor prepared by the above preparation method, comprising: a substrate wafer, on which a plurality of trench regions are etched; a multi-layer capacitor unit formed by stacking from bottom to top on the substrate wafer including the trench regions, each capacitor unit comprising a multi-layer conductive layer and a dielectric layer stacked alternately from inside to outside in a cross shape; an electrode, including a first electrode and a second electrode, formed on the top of the uppermost capacitor unit, the first electrode being connected to all odd-layer conductive layers, and the second electrode being connected to the substrate wafer and all even-layer conductive layers.

[0020] The above technical solution has the following advantages or beneficial effects:

[0021] 1) By providing trench regions, the effective capacitance is increased downward, and by alternately stacking to form a multi-layer capacitor unit, the effective capacitance is increased upward. Moreover, the adjacent two capacitor units of the current layer are staggered in the stacking direction, so that capacitor units can be stacked directly above the adjacent two capacitor units of the current layer, and capacitor units can also be stacked in the upper region between two adjacent capacitor units. This enables capacitor units to be formed not only on the substrate but also on the upper surface of the substrate, thereby improving the chip utilization rate and increasing the capacitance density, and achieving the ability to fabricate silicon capacitors with small size and high capacitance density;

[0022] 2) The silicon capacitor prepared by the present invention has a small occupied area and a high utilization rate of unit volume, is suitable for semiconductor manufacturing processes, and is conducive to device integration and miniaturization;

[0023] 3) Each capacitor unit is in a cross shape, with a simple structure and capable of realizing staggered splicing between two adjacent capacitor units of adjacent layers, further improving the utilization rate of the unit volume of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic flow chart of a preparation method of a silicon capacitor in a preferred embodiment of the present invention;

[0025] Figure 2 It is a schematic diagram of forming a trench region with a first step on a substrate wafer in Embodiment 1;

[0026] Figure 3 It is a schematic sub-flow chart of step S2 in Embodiment 1;

[0027] Figure 4 It is a schematic diagram of forming a first stack in Embodiment 1;

[0028] Figure 5 It is a schematic sub-flow chart of step S22 in Embodiment 1;

[0029] Figure 6Schematic diagram of forming the second step in Embodiment 1;

[0030] Figure 7 Schematic diagram of depositing the second dielectric layer 4a in Embodiment 1;

[0031] Figure 8 Schematic diagram after removing the redundant second dielectric layer 4a in Embodiment 1;

[0032] Figure 9 Schematic diagram of depositing the second conductive layer 4b and removing the redundant second conductive layer 4b in Embodiment 1;

[0033] Figure 10 Schematic diagram of depositing the second dielectric layer 5a in Embodiment 1;

[0034] Figure 11 Schematic diagram of depositing the second conductive layer 5b in Embodiment 1;

[0035] Figure 12 Schematic diagram of depositing the second dielectric layer 6a in Embodiment 1;

[0036] Figure 13 Schematic diagram of depositing the second conductive layer 6b in Embodiment 1;

[0037] Figure 14 Schematic diagram of exposing the dielectric layers and conductive layers of the second stack in Embodiment 1;

[0038] Figure 15 Schematic diagram of redepositing the second stack in Embodiment 1;

[0039] Figure 16 For Embodiment 1, Figure 15 Schematic diagram of forming the second step on the basis of;

[0040] Figure 17 For Embodiment 1, Figure 16 Schematic diagram of redepositing the second stack on the basis of;

[0041] Figure 18 Schematic diagram of the sub - process of step S3 in Embodiment 1;

[0042] Figure 19 For an implementation manner of Embodiment 1, Figure 18 Schematic diagram of exposing the dielectric layers and conductive layers of the second stack on the basis of;

[0043] Figure 20 For Embodiment 1, Figure 19 Schematic diagram of depositing the third dielectric layer 1c on the basis of;

[0044] Figure 21In Example 1, on the basis of Figure 20 Schematic diagram of forming a first electrode and a second electrode;

[0045] Figure 22 In another embodiment of Example 1, on the basis of Figure 18 Schematic diagram of exposing each dielectric layer and conductive layer of the second stack;

[0046] Figure 23 In Example 1, on the basis of Figure 22 Schematic diagram of depositing a third dielectric layer 1c;

[0047] Figure 24 In Example 1, on the basis of Figure 23 Schematic diagram of forming a first electrode and a second electrode;

[0048] Figure 25 In Example 1, schematic diagram of the structure of a silicon capacitor finally obtained by forming a plurality of second stacks;

[0049] Figure 26 In Example 2, schematic diagram of the structure of a silicon capacitor. Detailed implementation manners

[0050] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0051] In a preferred embodiment of the present invention, in view of the above problems existing in the prior art, a method for manufacturing a silicon capacitor is provided. As Figure 1 shown, it includes: Step S1, etching a plurality of trench regions on a substrate wafer; Step S2, stacking a plurality of capacitor units from bottom to top on the substrate wafer including the trench regions, each capacitor unit including a plurality of conductive layers and dielectric layers stacked alternately from the inside to the outside in a cross shape; adjacent two layers of each capacitor unit are staggered in the stacking direction; Step S3, forming a first electrode and a second electrode of each capacitor unit on the top of the uppermost capacitor unit, the first electrode connecting all odd-numbered conductive layers, and the second electrode connecting the substrate wafer and all even-numbered conductive layers.

[0052] Example 1

[0053] In this embodiment, the above-mentioned substrate wafer 1 should be made of a low-resistance material, and the resistivity should be less than 0.1 Ω·cm. Preferably, a silicon substrate is used. On the one hand, a high-quality integrated surface of passive devices can be fabricated using a relatively low-cost silicon process. On the other hand, since the substrate materials of passive devices and active devices are the same, when connecting the two, internal interconnections with a small pitch can be used for interconnection, so that the mismatch caused by thermal expansion will be very small, thereby optimizing the device performance.

[0054] It should be noted that the above-mentioned substrate wafer 1 may include semiconductor elements, such as silicon or silicon germanium in single-crystal, polycrystalline or amorphous structures, or may include a mixed semiconductor structure, such as silicon carbide, gallium arsenide, indium antimonide, gallium nitride, lead telluride, indium arsenide, etc. alloy semiconductors or combinations thereof; it may also be silicon-on-insulator (SOI). In addition, it may also include other materials, such as a multi-layer structure of an epitaxial layer or a buried layer. Any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.

[0055] As Figure 2 shown, the trench region 2 formed on the substrate wafer 1 has a first step 3. The number of steps of the first step 3 is not limited and can be obtained by at least two-step photolithographic etching. As Figure 2 shown, the first step 3 shown is obtained by two-step photolithographic etching. If the number of steps is more, it can be obtained by more than two-step photolithographic etching. Among them, the cross-section of the trench region 2 can be square, circular, or any polygon.

[0056] Subsequently, multiple alternating depositions are performed on the surface of the substrate wafer 1 with the trench region 2 to stack and form a multi-layer capacitor unit. Among them, as Figure 3 shown, the process of forming a layer of capacitor unit on the substrate wafer including the trench region includes: Step S21, alternately depositing multiple layers of a first dielectric layer and a first conductive layer in sequence to form a first stack; Step S22, performing a stepwise treatment on the top of the first stack to form a second step, and then alternately depositing multiple layers of a second dielectric layer and a second conductive layer with the same number of layers as the first stack in sequence to form a second stack; in the second stack, the topmost second conductive layer is connected to the substrate wafer, and the remaining second conductive layers are respectively connected to the corresponding first conductive layers in sequence, and each second dielectric layer is connected to the first dielectric layer in one-to-one correspondence.

[0057] Specifically, the number of times of alternately depositing the first dielectric layer and the first conductive layer can be artificially adjusted according to the requirement of the electrostatic capacitance. In this embodiment, taking the first stack including three layers of the first dielectric layer and three layers of the first conductive layer as an example, as Figure 4 shown, the stacking is performed in the order of the first dielectric layer 1a, the first conductive layer 1b, the first dielectric layer 2a, the first conductive layer 2b, the first dielectric layer 3a, and the first conductive layer 3b.

[0058] Among them, the first dielectric layer is an insulating material. As a preference, it can be one or a combination of insulating materials such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, etc. The material and thickness of each first dielectric layer can be the same or different.

[0059] The first conductive layer is a conductive material. As a preference, it can be polysilicon, titanium nitride, or other conductive metal materials. The material and thickness of each first conductive layer can be the same or different.

[0060] Subsequently, step S22 is performed to form a second stack on the first stack. Specifically, as Figure 5 shown, step S22 includes: step S221, performing a stepped treatment on the top of the first stack to form a second step. The bottommost second step exposes the substrate wafer in the horizontal direction, and the second steps of the remaining layers expose the first conductive layer in the horizontal direction. The second steps of each layer expose the adjacent first dielectric layer and the first conductive layer in the vertical direction; step S222, depositing a layer of second dielectric layer on the top of the first stack, and then removing the second dielectric layer in the horizontal direction at each second step, and maintaining the currently deposited second dielectric layer connected to the closest first dielectric layer in the first stack; step S223, depositing a layer of second conductive layer on the second dielectric layer, and then removing the second conductive layer in the horizontal direction at each second step, and maintaining the currently deposited second conductive layer connected to the closest second conductive layer in the first stack; step S224, repeating step S222 and step S223 until a second stack with the same number of layers as the first stack is formed.

[0061] In this embodiment, after forming the first stack, preferably, subsequent to this, PR patterning and etching processes are continuously performed in order from top to bottom through a pre-designed photomask to complete the stepped treatment of each first conductive layer and first dielectric layer in the first stack, forming a second step 4 as Figure 6 shown.

[0062] When the first stack includes three first dielectric layers and three first conductive layers, the corresponding second stack also includes three second dielectric layers and three second conductive layers. The formation process of the second stack is as follows: as Figure 7 shown, depositing a layer of second dielectric layer 4a on the above-mentioned surface, and performing patterning and etching processes on the second dielectric layer 4a to remove the redundant dielectric at the steps, so that the second dielectric layer 4a is connected to the first dielectric layer 3a and isolates the first conductive layer 3b and the first conductive layer 2b, as Figure 8 shown.

[0063] As Figure 9 shown, depositing a layer of second conductive layer 4b on the above-mentioned surface, and performing patterning and etching processes on the second conductive layer 4b to remove the redundant conductive layer at the steps, so that the second conductive layer 4b is connected to the first conductive layer 2b.

[0064] As Figure 10 shown, depositing a layer of second dielectric layer 5a on the above-mentioned surface, and performing patterning and etching processes on the second dielectric layer 5a to remove the redundant dielectric layer at the steps, so that the second dielectric layer 5a is connected to the first dielectric layer 2a and isolates the first conductive layer 2b and the first conductive layer 1b.

[0065] AsFigure 11 As shown, a second conductive layer 5b is deposited on the above-mentioned surface, and the second conductive layer 5b is patterned and etched to remove the excess conductive layer at the steps, so that the second conductive layer 5b is connected to the first conductive layer 1b.

[0066] As Figure 12 shown, a second dielectric layer 6a is deposited on the above-mentioned surface, and the second dielectric layer 6a is patterned and etched to remove the excess dielectric layer at the steps, so that the second dielectric layer 6a is connected to the first dielectric layer 1a and isolates the first conductive layer 1b from the conductive substrate wafer 1.

[0067] As Figure 13 shown, finally, a second conductive layer 6b is deposited on the above-mentioned surface, so that the second conductive layer 6b is connected to the conductive substrate wafer 1, and the formation of the second stack is completed.

[0068] Further, when the capacitor unit is multi-layered, after performing step S22, it further includes using the formed second stack as the first stack, and then repeating step S22.

[0069] Specifically, as Figure 14 shown, on the top of the formed second stack above, PR patterning and etching are continuously performed in sequence from top to bottom through a pre-designed photomask to complete the step treatment of the second dielectric layer 4a, the second dielectric layer 5a, the second dielectric layer 6a and the second conductive layer 4b, the second conductive layer 5b, the second conductive layer 6b. Subsequently, as Figure 15 shown, the above process of forming the second stack is repeated once to continuously stack dielectric layers and conductive layers upward. PR patterning and etching are continuously performed on the above-mentioned surface again to complete the step treatment, as Figure 16 shown. Subsequently, as Figure 17 shown, the above process of forming the second stack can be repeated once again to continuously stack dielectric layers and conductive layers upward.

[0070] And so on, the above step treatment and the process of forming the second stack can be repeated multiple times, and the number of repetitions can be manually adjusted according to the requirement of the electrostatic capacitance.

[0071] In this embodiment, when the capacitor unit is multi-layered, in step S22, a second step is formed in the upper region corresponding to the area between two adjacent trench regions at the top of the first stack deposited for the odd number of times; a second step is formed in the upper region corresponding to each trench region at the top of the first stack deposited for the even number of times.

[0072] Specifically, it can be seen that when the second step is formed through the first stepwise treatment, the second step is formed in the upper region between the two trench regions. When the second step is formed through the second stepwise treatment, the second step is formed in the region directly above each trench region. When the second step is formed through the third stepwise treatment, the second step is formed in the upper region between the two trench regions, that is, directly above the region of the first stepwise treatment. And so on, the second steps formed in odd numbers and even numbers are arranged alternately, thereby enabling the capacitor units in adjacent two layers to be arranged alternately.

[0073] After the second stack is formed multiple times, in this embodiment, as Figure 18 shown, step S3 includes: step S31, processing the top of the capacitor unit in the topmost layer to expose the surfaces of the conductive layers and dielectric layers of each layer of the capacitor unit in the topmost layer; step S32, depositing a layer of third dielectric layer; step S33, forming a plurality of contact holes on the third dielectric layer, then performing metal deposition, and forming the first electrode and the second electrode through photolithography and metal etching.

[0074] Specifically, as a preferred embodiment, in step S31, processing the top of the capacitor unit in the topmost layer is to perform chemical mechanical polishing treatment to expose the surfaces of the dielectric layers and conductive layers, as Figure 19 shown.

[0075] As Figure 20 shown, then the third dielectric layer 1c is deposited on the above surface. The third dielectric layer 1c can be an oxide layer, or borophosphosilicate glass, or a combination of multiple insulating layers.

[0076] Furthermore, photolithography and etching are performed on the above surface to form contact holes. Then metal deposition is carried out, and through photolithography and metal etching, the first electrode 5 and the second electrode 6 as Figure 21 shown are formed. The first electrode 5 is connected to all odd-numbered conductive layers such as the first conductive layer 1b, the first conductive layer 3b, and the second conductive layer 5b; the second electrode 6 is connected to all even-numbered conductive layers such as the conductive substrate 1, the first conductive layer 2b, and the second conductive layer 6b. Among them, the first electrode 5 and the second electrode 6 are the two lead electrodes of the silicon capacitor.

[0077] As another preferred embodiment, in step S31, processing the top of the capacitor unit in the topmost layer is to continuously perform patterning and etching treatment in the order from top to bottom according to a pre-designed photomask to expose the surfaces of the conductive layers, as Figure 22 shown.

[0078] As Figure 23 shown, then the third dielectric layer 1c is deposited on the surface. The third dielectric layer 1c can be an oxide layer, or borophosphosilicate glass, or a combination of multiple insulating layers.

[0079] Furthermore, contact holes are formed on the above surface, tungsten plugs are filled, and then metal deposition is carried out. Through photolithography and metal etching, the first electrode 5 and the second electrode 6 as shown in Figure 24 are formed. The first electrode 5 is connected to all odd-numbered conductive layers such as the first conductive layer 1b, the first conductive layer 3b, and the second conductive layer 5b; the second electrode 6 is connected to all even-numbered conductive layers such as the conductive substrate wafer 1, the first conductive layer 2b, and the second conductive layer 6b. Among them, the first electrode 5 and the second electrode 6 are two lead-out electrodes of the silicon capacitor.

[0080] When there are multiple second stacks, the structure of the finally formed silicon capacitor is as shown in Figure 25 shown.

[0081] Embodiment 2

[0082] In this embodiment, the remaining preparation steps are the same as those in Embodiment 1, except that the trench region in this embodiment is a trench region without steps vertically downward. Specifically, the trench region can be etched out through one photolithography. The structure of the finally formed silicon capacitor is as shown in Figure 26 shown.

[0083] The present invention also provides a silicon capacitor prepared by the above preparation method, as shown in Figure 24 or Figure 25 or Figure 26 shown, including: a substrate wafer 1, on which several trench regions 2 are etched; a multi-layer capacitor unit, stacked from bottom to top on the substrate wafer 1 including the trench region 2, and each capacitor unit includes multi-layer conductive layers and dielectric layers stacked alternately from the inside to the outside in a cross shape; electrodes, including a first electrode 5 and a second electrode 6, formed on the top of the topmost capacitor unit, the first electrode 5 is connected to the conductive layers of all odd-numbered layers, and the second electrode 6 is connected to the substrate wafer and the conductive layers of all even-numbered layers.

[0084] Among them, Figure 24 and Figure 25 the trench region 2 in includes a first step, Figure 26 the trench region 2 in does not include a first step.

[0085] In summary, on the one hand, the present invention increases the effective capacitance area downward by adding a trench structure to the silicon substrate and stacking multiple dielectric layers and conductive layers, and forms the first-layer capacitor unit as shown in Figure 24 or Figure 25 shown, including capacitor unit C1, capacitor unit C2, and capacitor unit C3; on the other hand, above the substrate, through multiple photolithographies, etchings, and laminations, taking the capacitor unit C4 in the figure as a "cross"-shaped capacitor repeating unit, stack upward alternately to obtain as shown in Figure 24The second-layer capacitor units therein include capacitor unit C4, capacitor unit C5, and the third-layer capacitor units include capacitor unit C6, capacitor unit C7, and capacitor unit C8. In the figure, capacitor unit C1, capacitor unit C2, capacitor unit C3, capacitor unit C6, capacitor unit C7, and capacitor unit C8 use the first conductive layer 3b as the inner electrode and the second conductive layer 6b as the outer electrode; capacitor unit C4 and capacitor unit C5 use the second conductive layer 6b as the inner electrode and the first conductive layer 3b as the outer electrode. Therefore, capacitor units C1 to C8 are connected in parallel with each other, such that the total capacitance of the silicon capacitor as shown in Figure 24 of the present invention is C = C1 + C2 + C3 + C4 + C5 + C6 + C7 + C8.

[0086] It can be seen that the present invention increases the effective capacitance downward through the trench region 2 and upward through the interleaved parallel repeating units ( Figure 24 and Figure 25 the region boxed by the dashed line in the figure). The present invention can improve the chip utilization rate and increase the capacitance density. The provided three-dimensional capacitor structure has a small occupied area and a high unit volume utilization rate, is applicable to semiconductor processes, and is beneficial to device integration and miniaturization.

[0087] The above are only the preferred embodiments of the present invention, and do not limit the implementation manners and protection scope of the present invention accordingly. For those skilled in the art, it should be realized that all equivalent replacements and obvious changes made by using the content of this specification and the drawings should be included in the protection scope of the present invention.

Claims

1. A method for preparing a silicon capacitor, characterized in that: include: Step S1, etching a plurality of groove regions on a substrate, wherein the groove regions have a first step; Step S2, stacking from bottom to top on the substrate sheet including the groove region to form a multilayer capacitor unit, each capacitor unit including a plurality of conductive layers and dielectric layers alternately stacked from inside to outside in a cross shape; The process of forming a layer of the capacitor unit on the substrate sheet including the groove region includes: Step S21, alternately depositing multiple layers of first dielectric layers and first conductive layers in sequence to form a first stack; Step S22, performing a stepping process on the top of the first stack to form a second step, and then alternately depositing a plurality of second dielectric layers and second conductive layers having the same number of layers as the first stack to form a second stack; Repeating the step S21 to the step S22 to form multiple layers of the capacitor units, and making the capacitor units of two adjacent layers alternately arranged in a stacking direction; Step S3, forming a first electrode and a second electrode of each capacitor unit on the top of the uppermost capacitor unit, wherein the first electrode connects the conductive layers of all odd-numbered layers, and the second electrode connects the substrate sheet and the conductive layers of all even-numbered layers.

2. The preparation method according to claim 1, characterized in that: In the step S1, the trench region with the first step is etched out by at least two steps of photolithography.

3. The preparation method according to claim 1, characterized in that: In the second stack, the topmost second conductive layer is connected to the substrate sheet, and the remaining second conductive layers are sequentially connected to the corresponding first conductive layers, and each second dielectric layer is connected to the first dielectric layer in a one-to-one correspondence.

4. The preparation method according to claim 3, characterized in that: When the capacitor unit is multi-layered, after executing step S22, the method further includes using the formed second stacked layer as the first stacked layer, and then repeating step S22.

5. The preparation method according to claim 3, characterized in that: When the capacitor unit is multi-layered, in the step S22, the second step is formed on the top of the first stacked layer deposited for an odd number of times corresponding to the upper area between two adjacent groove areas; The second steps are formed on the top of the first stack deposited for even times, corresponding to the upper regions of the respective trench regions.

6. The preparation method according to claim 3, characterized in that: The step S22 comprises: Step S221, performing a stepping process on the top of the first stack to form a second step, wherein the second step of the bottom layer exposes the substrate sheet in a horizontal direction, the second steps of the remaining layers expose the first conductive layer in a horizontal direction, and the second steps of each layer expose the adjacent first dielectric layer and the first conductive layer in a vertical direction; Step S222, depositing a second dielectric layer on top of the first stack, then removing the second dielectric layer in the horizontal direction at each second step, and keeping the currently deposited second dielectric layer connected to the closest first dielectric layer in the first stack; Step S223, depositing a second conductive layer on the second dielectric layer, then removing the second conductive layer in the horizontal direction at each second step, and keeping the currently deposited second conductive layer connected to the second conductive layer closest to the first stack; Step S224, repeating the step S222 and the step S223 until the second stack having the same number of layers as the first stack is formed.

7. The preparation method according to claim 1, characterized in that: The step S3 comprises: Step S31, processing the top of the capacitor unit at the top layer so that the conductive layer and the dielectric layer of each layer of the capacitor unit at the top layer are exposed on the surface; Step S32, depositing a third dielectric layer; Step S33, forming a plurality of contact holes on the third dielectric layer, then performing metal deposition, and forming the first electrode and the second electrode by photolithography and metal etching.

8. The preparation method according to claim 7, characterized in that: In the step S31, the top of the uppermost capacitor unit is processed by chemical mechanical polishing.

9. The preparation method according to claim 7, characterized in that: In the step S31, the top of the capacitor unit at the top layer is processed by continuously performing patterning and etching processing in a top-to-bottom order according to a pre-designed mask; In the step S33, before metal deposition, a metal tungsten plug is filled in each of the contact holes.

10. A silicon capacitor, characterized in that: Prepared by the preparation method according to any one of claims 1 to 9, comprising: A substrate sheet having a plurality of groove regions formed by etching; Multilayer capacitor units are stacked from bottom to top on the substrate sheet including the groove region, each of the capacitor units comprising multiple conductive layers and dielectric layers alternately stacked from inside to outside in a cross shape; The electrodes, including a first electrode and a second electrode, are formed on the top of the uppermost capacitor unit, the first electrode is connected to the conductive layers of all odd layers, and the second electrode is connected to the substrate sheet and the conductive layers of all even layers.

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