Groove type device integrated with SBD and preparation method thereof

Abstract

The invention provides an SBD-integrated groove type device and a preparation method thereof, and relates to the technical field of semiconductors, the SBD-integrated groove type device comprises a substrate, a first groove gate structure, a second groove gate structure, a first emission electrode, a second emission electrode and a back electrode, a first Schottky diode is formed between the side wall of the first emission electrode and the substrate, and a second Schottky diode is formed between the side wall of the second emission electrode and the back electrode. And a second Schottky diode is formed between the side wall of the second emission electrode and the substrate. Compared with the prior art, the Schottky diode is integrated into the MOSFET device, so that the MOSFET device has the advantages of high integration level and reduced area and cost, the overall performance of the device can be further improved, an external parallel diode does not need to be introduced, four chips in the conventional technology can be replaced by one chip, and the manufacturing cost is reduced. The reverse recovery process can be further optimized while the cost is saved, the reverse recovery loss is reduced, and the efficiency of the system is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench device with an integrated SBD and a preparation method thereof. Background Art

[0002] The T-type three-level topology is an important topology in the field of power electronic conversion. It is widely used in medium-high voltage and high-power frequency conversion, uninterruptible power supply (UPS), active filter and wind power converter. In the T-type three-level topology, the chip layout is generally compact, and the cross tube often uses two IGBTs and two FRD devices or two SiCMOSFETs and two SiC SBD devices. This will undoubtedly introduce more leads and lines, bring more parasitic inductance, and the freedom of package design layout is also low, thus affecting the performance and cost of the module.

[0003] Among them, the Schottky barrier diode is a metal-semiconductor contact diode with low forward voltage drop and fast switching characteristics. In the prior art, two SiC MOSFETs and two SiCSBD devices are usually used to form a T-type three-level topology package chip, so an external parallel silicon carbide SBD diode is required. However, this external layout method introduces additional leads and lines, which brings more parasitic inductance and interferes with the performance of the device. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a trench device with integrated SBD and a preparation method thereof, which can integrate a Schottky diode into a trench device, further improve the overall performance of the device, and do not require the introduction of an external parallel diode. One chip can replace four chips in conventional technology, saving costs while further optimizing the reverse recovery process, reducing reverse recovery losses, and further improving system efficiency.

[0005] In a first aspect, the present invention provides a trench device with an integrated SBD, comprising:

[0006] A substrate of a first conductivity type, on which a doped well region of a second conductivity type is formed, in which a first source region and a second source region are formed, and the first source region and the second source region extend to a surface of the doped well region away from the substrate;

[0007] a first trench gate structure and a second trench gate structure, wherein the first trench gate structure passes through the first source region and the doped well region and extends to the substrate; and the second trench gate structure passes through the second source region and the doped well region and extends to the substrate;

[0008] a first emitting electrode and a second emitting electrode, wherein the first emitting electrode is spaced apart from the first trench gate structure and passes through the doped well region, and the first emitting electrode is in electrical contact with the first source region; and the second emitting electrode is spaced apart from the second trench gate structure and passes through the doped well region, and the second emitting electrode is in electrical contact with the second source region;

[0009] A back electrode, the back electrode being arranged on the other side surface of the substrate;

[0010] The first emitting electrode extends to the substrate, and a first Schottky diode is formed between a side wall of the first emitting electrode and the substrate; the second emitting electrode extends to the substrate, and a second Schottky diode is formed between a side wall of the second emitting electrode and the substrate.

[0011] In an optional embodiment, a first source trench and a second source trench are provided on the substrate, the first source trench passes through the first source region and the doped well region, the first emitter electrode is filled in the first source trench, and extends to a side surface of the first source region away from the substrate; the second source trench passes through the second source region and the doped well region, the second emitter electrode is filled in the second source trench, and extends to a side surface of the second source region away from the substrate.

[0012] In an optional embodiment, the first source region includes a first channel doping region and a first ohmic doping region both extending to the surface of the doped well region, one side of the first channel doping region is connected to the first trench gate structure, and the other side is connected to the first ohmic doping region, the first ohmic doping region is connected to the first emitting electrode, and the first emitting electrode covers the surface of the first ohmic doping region and partially covers the surface of the first channel doping region;

[0013] The second source region includes a second channel doping region and a second ohmic doping region both extending to the surface of the doped well region, one side of the second channel doping region is connected to the second trench gate structure, and the other side is connected to the second ohmic doping region, the second ohmic doping region is connected to the second emitting electrode, and the second emitting electrode covers the surface of the second ohmic doping region and partially covers the surface of the second channel doping region;

[0014] The first channel doping region and the second channel doping region are both of the first conductivity type, and the first ohmic doping region and the second ohmic doping region are both of the second conductivity type.

[0015] In an optional embodiment, a first electrical contact layer is formed between a surface of the first source region away from the substrate and the first emitting electrode; a second electrical contact layer is formed between a surface of the second source region away from the substrate and the second emitting electrode.

[0016] In an optional embodiment, the first trench gate structure includes a first gate conductive layer, a first gate oxide layer and a first electrode layer, a first gate trench is provided on the substrate, the first gate trench passes through the first source region and the doped well region, the first gate oxide layer is formed on the sidewall and bottom wall of the first gate trench, the first gate conductive layer is filled in the first gate trench, and the first electrode layer is provided on the first gate conductive layer;

[0017] The second trench gate structure includes a second gate conductive layer, a second gate oxide layer and a second electrode layer. A second gate trench is arranged on the substrate. The second gate trench passes through the second source region and the doped well region. The second gate oxide layer is formed on the sidewall and bottom wall of the second gate trench. The second gate conductive layer fills the first gate trench. The second electrode layer is arranged on the second gate conductive layer.

[0018] In an optional embodiment, a plurality of spaced-apart third gate trenches are formed on the substrate between the first gate trench and the second gate trench, each of the third gate trenches passes through the doped well region and extends to the substrate, a third gate oxide layer is formed on the sidewalls and bottom walls of each of the third gate trenches, and the third gate trenches are filled with a third gate conductive layer.

[0019] In an optional embodiment, an electric field shielding region of the second conductivity type is formed at the bottom of the first source trench, the second source trench, the first gate trench, the second gate trench, and the third gate trench.

[0020] In an optional embodiment, the trench device with integrated SBD further includes an insulating dielectric layer, the insulating dielectric layer is disposed on the substrate, and the first trench gate structure, the second trench gate structure, the first emitter electrode and the second emitter electrode all pass through the insulating dielectric layer.

[0021] In an optional embodiment, the trench-type device of the integrated SBD further includes a first buffer layer and a second buffer layer, wherein the first buffer layer is disposed on the insulating dielectric layer, the second buffer layer is disposed on the first buffer layer, and both the first buffer layer and the second buffer layer at least partially expose the first trench gate structure, the second trench gate structure, the first emitter electrode, and the second emitter electrode.

[0022] In a second aspect, the present invention provides a method for preparing a trench device with an integrated SBD, which is used to prepare the trench device with an integrated SBD as described in the above embodiment, and the preparation method comprises:

[0023] providing a substrate of a first conductivity type;

[0024] Implanting to form a doped well region on the substrate, wherein the doped well region is located on the substrate;

[0025] Implanting a first source region and a second source region into the doped well region, wherein the first source region and the second source region are formed in the doped well region and extend to a surface of the doped well region away from the substrate;

[0026] forming a first gate trench, a second gate trench, a first source trench, and a second source trench on the substrate;

[0027] forming a first trench gate structure and a second trench gate structure in the first gate trench and the second gate trench, respectively, wherein the first trench gate structure passes through the first source region and the doped well region and extends to the substrate; and the second trench gate structure passes through the second source region and the doped well region and extends to the substrate;

[0028] A first emitting electrode and a second emitting electrode are formed in the first source trench and the second source trench, respectively, wherein the first emitting electrode is in electrical contact with the first source region, the first emitting electrode passes through the doped well region and extends to the substrate, and a first Schottky diode is formed between a sidewall of the first emitting electrode and the substrate; the second emitting electrode is in electrical contact with the second source region, the second emitting electrode passes through the doped well region and extends to the substrate, and a second Schottky diode is formed between a sidewall of the second emitting electrode and the substrate;

[0029] A back electrode is formed on the other side surface of the substrate.

[0030] The trench device of the integrated SBD and the preparation method thereof provided in the embodiment of the present invention form a doped well region, a first source region and a second source region on a substrate, and simultaneously form a first gate trench structure and a second gate trench structure on the substrate. The first gate trench structure passes through the first source region and the doped well region and extends to the substrate, and the second gate trench structure passes through the second source region and the doped well region and extends to the substrate. The first emitter electrode passes through the doped well region and extends to the substrate, and the second emitter electrode passes through the doped well region and extends to the substrate. Among them, the side wall of the first emitter electrode is in Schottky contact with the substrate, and a first Schottky diode is formed, and the side wall of the second emitter electrode is in Schottky contact with the substrate, and a second Schottky diode is formed. Compared with the prior art, the present application integrates two sets of trench gate MOS devices together, and integrates a first Schottky diode and a second Schottky diode, thereby integrating the Schottky diode into the MOSFET device, which has the advantages of high integration, reduced area and cost, and can bring higher design freedom to the package design layout, especially in T-type three-level topology applications, its cross tube only needs to use one chip to achieve the function of four chips in conventional technology, without the need to introduce external parallel diodes, which saves costs and can further optimize the reverse recovery process, reduce reverse recovery losses, and further improve the efficiency of the system.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A schematic structural diagram of a trench device with integrated SBD provided in an embodiment of the present invention is shown;

[0034] Figure 2 The working circuit diagram of the trench device with integrated SBD provided by the embodiment of the present invention is shown;

[0035] Figures 3 to 11 The process flow chart of the method for preparing a trench device with integrated SBD provided by an embodiment of the present invention is shown.

[0036] Description of main component symbols:

[0037] 100-trench device with integrated SBD; 110-substrate; 111-doped well region; 112-first source region; 113-second source region; 114-first channel doping region; 115-second channel doping region; 116-first ohmic doping region; 117-second ohmic doping region; 118-electric field shielding region; 120-first trench gate structure; 121-first gate conductive layer; 122-first gate oxide layer; 123-first electrode layer; 124-first gate trench; 125-third gate trench; 126-third gate conductive layer; 127-third gate oxide layer; 130 -second trench gate structure; 131-second gate conductive layer; 132-second gate oxide layer; 133-second electrode layer; 134-second gate trench; 140-first emitter electrode; 141-first Schottky diode; 142-first source trench; 150-second emitter electrode; 151-second Schottky diode; 152-second source trench; 160-back electrode; 170-insulating dielectric layer; 171-first electrical contact layer; 172-second electrical contact layer; 180-first buffer layer; 190-second buffer layer; 200-hard mask layer; 300-blocking layer. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0039] As disclosed in the background technology, the T-type three-level topology package chip layout in the prior art is generally compact, and the cross tube often uses two IGBTs and two FRD devices, or two SiC MOSFETs and two SiC SBD devices, which will undoubtedly introduce more leads and lines, bring more parasitic inductance, and the freedom of package design layout is also low, thereby affecting the performance and cost of the module.

[0040] Moreover, the trench gate silicon carbide MOSFET device used in the present invention has the advantages of lower on-resistance, higher current density, faster switching speed, smaller chip size, etc. compared with the planar gate silicon carbide MOSFET. However, the trench gate silicon carbide MOSFET is prone to electric field concentration due to the corner of the bottom of the gate oxide, which is prone to early failure of the gate oxide layer during the application process, affecting the use of the device. Therefore, how to better protect the bottom of the trench gate oxide is crucial for the development of trench gate silicon carbide MOSFET devices.

[0041] The Schottky barrier diode is a metal-semiconductor contact diode with low forward voltage drop and fast switching characteristics. An external parallel silicon carbide SBD diode is usually used, but this external layout introduces additional leads and lines, which brings more parasitic inductance and interferes with the performance of the device. The present invention integrates the Schottky diode into the SiC MOSFET device, which can further improve the overall performance of the device. This integration can reduce the switching loss of the device, improve efficiency, and help simplify the circuit design because the external reverse recovery diode can be omitted. Integrating the Schottky diode in the SiC MOSFET device can realize the "synchronous rectification" function, which is particularly useful in applications such as DC-DC converters and inverters. Synchronous rectification can reduce energy loss and improve the overall efficiency of the system. In addition, the fast recovery characteristics of the Schottky diode help reduce electromagnetic interference (EMI) and increase the switching frequency, which is crucial to the performance of modern power electronic equipment. Therefore, SiC MOSFET devices with integrated Schottky diodes have broad application prospects in high-performance power electronic systems.

[0042] In view of the above problems, the main scheme of the present invention is to integrate a four-terminal SiC device in a chip, including two sets of SiC trench gate MOS structures with SBD integrated on the sidewalls of the trench. Each set of MOS devices has a separate gate and emitter electrode control, and its four terminals are G1 and G2, E1 and E2 respectively. The specific chip internal structure design can be achieved by setting a P+ type electric field shielding area 118 directly below the trench, integrating the SBD on both sides of the trench, and then connecting the two sets of SiC trench gate MOS devices with SBD integrated on the sidewalls of the trench through a transition withstand voltage area. The transition withstand voltage area structure is designed as a series of trench structures connected by a P-type region and provided with a P+ type electric field shielding area 118 below the trench. The P+ type electric field shielding area 118 is set directly below the trench to avoid the electric field concentration at the bottom corner of the trench gate oxide of SiC MOS, prevent the early failure of the gate oxide, and avoid the generation of high electric fields on both sides of the SBD to prevent the SBD withstand voltage from decreasing. The sidewall-integrated SBD has a low forward voltage drop, which reduces the device's freewheeling loss and makes the SiC MOS device have lower conduction loss and switching loss. The four-terminal SiC device has the advantages of high integration, reduced area and cost, and can bring higher design freedom to the package design layout. The independent control design of the dual gate and dual emitter electrodes can enable the chip to achieve bidirectional conduction and bidirectional blocking, especially in T-type three-level topology applications. Its lateral circuit only needs to use one chip of this invention to achieve the functions of the previous four chips.

[0043] The specific structure of the SBD-integrated trench device and its preparation method are described in detail below.

[0044] See also Figure 1 and Figure 2 The embodiment of the present invention provides a trench device 100 with an integrated SBD, which can integrate a Schottky diode into a trench device, further improving the overall performance of the device without introducing an external parallel diode. One chip can replace four chips in conventional technology, saving costs while further optimizing the reverse recovery process, reducing reverse recovery losses, and further improving system efficiency.

[0045] The trench device 100 with integrated SBD provided in an embodiment of the present invention may be a SiC MOSFET device. The trench device 100 with integrated SBD includes a substrate 110, a first trench gate structure 120, a second trench gate structure 130, a first emitter electrode 140, a second emitter electrode 150 and a back electrode 160, wherein the substrate 110 is of a first conductivity type. A doped well region 111 of a second conductivity type is formed on the substrate 110, and a first source region 112 and a second source region 113 are formed in the doped well region 111, wherein the first source region 112 and the second source region 113 extend to a side surface of the doped well region 111 away from the substrate 110. The first trench gate structure 120 passes through the first source region 112 and the doped well region 111 and extends to the substrate 110. The second trench gate structure 130 passes through the second source region 113 and the doped well region 111 and extends to the substrate 110. The first emitter electrode 140 is spaced apart from the first trench gate structure 120 and passes through the doped well region 111, and the first emitter electrode 140 is in electrical contact with the first source region 112. The second emitter electrode is spaced apart from the second trench gate structure 130 and passes through the doped well region 111, and the second emitter electrode 150 is in electrical contact with the second source region 113. The back electrode 160 is disposed on the other side surface of the substrate 110. The first emitter electrode 140 extends to the substrate 110, and a first Schottky diode 141 is formed between the sidewall of the first emitter electrode 140 and the substrate 110, and the second emitter electrode 150 extends to the substrate 110, and a second Schottky diode 151 is formed between the sidewall of the second emitter electrode 150 and the substrate 110.

[0046] It should be noted that the embodiment of the present invention can integrate two sets of trench gate MOS devices on the same substrate 110, and each set of trench gate MOS devices is integrated with a Schottky barrier diode, thereby integrating the Schottky diode into the MOSFET device, which has the advantages of high integration, reduced area and cost, and can bring higher design freedom to the package design layout, especially in T-type three-level topology applications, its cross pipe only needs to use one chip to achieve the function of four chips in conventional technology, without the need to introduce external parallel diodes, which saves costs and can further optimize the reverse recovery process, reduce reverse recovery losses, and further improve the efficiency of the system.

[0047] It is worth noting that the material of the substrate 110 here includes but is not limited to silicon carbide, silicon, gallium nitride, gallium arsenide, diamond, etc., and the conductivity type is N-type, referred to as the first conductivity type. At the same time, the doped well region 111 can be formed on the substrate 110 by ion implantation, which is a P-type semiconductor, referred to as the second conductivity type, and the doped impurities include aluminum, boron, gallium, etc., wherein the implantation energy of the doped well region 111 is 200-800keV, and the dose is 3E11-3E14.

[0048] In some embodiments, a first source trench 142 and a second source trench 152 are provided on the substrate 110. The first source trench 142 passes through the first source region 112 and the doped well region 111. The first emitter electrode 140 is filled in the first source trench 142 and extends to a side surface of the first source region 112 away from the substrate 110. The second source trench 152 passes through the second source region 113 and the doped well region 111. The second emitter electrode 150 is filled in the second source trench 152 and extends to a side surface of the second source region 113 away from the substrate 110. Preferably, the first source trench 142 and the second source trench 152 can be provided near the two side edges of the substrate 110. The substrate 110 at the sidewall of the first source trench 142 is integrated with the first emitter electrode 140 to form a first Schottky diode 141. At the same time, the substrate 110 at the sidewall of the second source trench 152 is integrated with the second emitter electrode 150 to form a second Schottky diode 151.

[0049] In some embodiments, the first source region 112 includes a first channel doping region 114 and a first ohmic doping region 116, both extending to the surface of the doped well region 111. One side of the first channel doping region 114 is connected to the first trench gate structure 120, and the other side is connected to the first ohmic doping region 116. The first ohmic doping region 116 is connected to the first emitter electrode 140. The first emitter electrode 140 covers the surface of the first ohmic doping region 116 and partially covers the surface of the first channel doping region 114. The second source region 113 includes a second channel doping region 115 and a second ohmic doping region 117, both extending to the surface of the doped well region 111. One side of the second channel doping region 115 is connected to the second trench gate structure 130, and the other side is connected to the second ohmic doping region 117. The second ohmic doping region 117 is connected to the second emitter electrode 150. The second emitter electrode 150 covers the surface of the second ohmic doping region 117 and partially covers the surface of the second channel doping region 115.

[0050] Among them, the first channel doping region 114 and the second channel doping region 115 are both of the first conductivity type, and the first ohmic doping region 116 and the second ohmic doping region 117 are both of the second conductivity type. Specifically, the first channel doping region 114 and the second channel doping region 115 can be formed simultaneously by ion implantation in the doped well region 111, and both are N-type semiconductors, called the first conductivity type, and their doping concentration is higher than that of the substrate 110. The doping impurities include nitrogen, phosphorus, arsenic, selenium, sulfur, etc., and the implantation energy is 50-500keV, and the dose is 3E11-3E14. The first ohmic doping region 116 and the second ohmic doping region 117 are both P-type semiconductors, called the second conductivity type, and the doping impurities include aluminum, boron, gallium, etc., and the implantation energy is 50-500keV, and the dose is 3E11-3E14.

[0051] In some embodiments, the first trench gate structure 120 includes a first gate conductive layer 121, a first gate oxide layer 122 and a first electrode layer 123, a first gate trench 124 is provided on the substrate 110, the first gate trench 124 passes through the first source region 112 and the doped well region 111, the first gate oxide layer 122 is formed on the side wall and the bottom wall of the first gate trench 124, the first gate conductive layer 121 is filled in the first gate trench 124, the first electrode layer 123 is provided on the first gate conductive layer 121, and is used to lead out the gate G1. The second trench gate structure 130 includes a second gate conductive layer 131, a second gate oxide layer 132 and a second electrode layer 133. A second gate trench 134 is provided on the substrate 110. The second gate trench 134 passes through the second source region 113 and the doped well region 111. The second gate oxide layer 132 is formed on the sidewalls and bottom walls of the second gate trench 134. The second gate conductive layer 131 fills the first gate trench 124. The second electrode layer 133 is provided on the second gate conductive layer 131 and is used to lead out the gate G2.

[0052] Specifically, the first gate conductive layer 121 and the second gate conductive layer 131 can be formed by a deposition process and through a photolithography pattern mask and etching, and the first gate conductive layer 121 and the second gate conductive layer 131 can be formed together. The first gate conductive layer 121 and the second gate conductive layer 131 are used to form the first gate and the second gate respectively, and the materials include but are not limited to nickel, polysilicon, doped polysilicon, metal aluminum, copper, titanium, tungsten and their stacks or alloys, and alloys of the above metals and silicon. The thickness of the first gate conductive layer 121 and the second gate conductive layer 131 is 1000A-10000A, and they are prepared by CVD, and the etching process is dry etching or wet etching. The first gate oxide layer 122 covers the side walls and bottom walls of the first gate trench 124, and the second gate oxide layer 132 covers the side walls and bottom walls of the second gate trench 134, wherein the first gate oxide layer 122 and the second gate oxide layer 132 can be prepared together by etching after thermal growth, and the thickness of both is 500A-5000A, and the etching process is dry etching or wet etching.

[0053] It should be noted that the first electrode layer 123 and the second electrode layer 133 are used to lead out the first gate and the second gate respectively, and the first electrode layer 123, the second electrode layer 133, the first emitting electrode 140 and the second emitting electrode 150 can be formed together. The thickness of the first electrode layer 123 and the second electrode layer 133 can be 2-6 μm, and can be formed by etching after being deposited together, wherein the deposition process is evaporation or sputtering, and the etching process is dry etching or wet etching. In addition, the materials of the first electrode layer 123, the second electrode layer 133, the first emitting electrode 140 and the second emitting electrode 150 include but are not limited to nickel, polysilicon, doped polysilicon, metal aluminum, copper, titanium, tungsten and their stacks or alloys, and alloys of the above metals and silicon. At the same time, the material of the back electrode 160 also includes but is not limited to nickel, polysilicon, doped polysilicon, metal aluminum, copper, titanium, tungsten and their stacks or alloys, as well as alloys of the above metals and silicon, etc. The thickness of the back electrode 160 is 0.5-3μm, the deposition process is evaporation or sputtering, and the etching process is dry etching or wet etching.

[0054] In some embodiments, a plurality of third gate trenches 125 are formed on the substrate 110 between the first gate trench 124 and the second gate trench 134. Each third gate trench 125 passes through the doped well region 111 and extends to the substrate 110. A third gate oxide layer 127 is formed on the sidewall and bottom wall of each third gate trench 125. The third gate trench 125 is filled with a third gate conductive layer 126. The first gate trench 124, the second gate trench 134, the third gate trench 125, the first source trench 142 and the second source trench 152 can be formed by etching together, and the depth and width of the plurality of trenches are equal. The trench etching is dry etching or wet etching. The trench etching depth is 0.5-2 μm, the trench width is 0.5-2 μm, and the trench spacing is 0.2-2 μm.

[0055] In some embodiments, the bottom of the first source trench 142, the second source trench 152, the first gate trench 124, the second gate trench 134 and the third gate trench 125 are all formed with an electric field shielding region 118 of the second conductivity type. Specifically, after the trenches are formed, the electric field shielding region 118 can be formed on the bottom wall of the trenches by ion implantation, wherein the electric field shielding region 118 is a P-type semiconductor, referred to as the second conductivity type, and the doped impurities include aluminum, boron, gallium, etc. At the same time, the injection energy of the electric field shielding region 118 is 20-200keV, and the dose is 3E11-3E13. By setting a doped shielding layer, the problem of electric field concentration caused by the bottom corner of the gate oxide can be solved, and the early failure of the gate oxide can be prevented. It can also avoid the generation of high electric fields on both sides of the SBD and prevent the SBD withstand voltage from decreasing.

[0056] It should be noted that in the present application, a transition voltage-resistant region is formed between the first gate trench 124 structure and the second gate trench 134 structure, and a plurality of third gate trenches 125 are arranged in the transition voltage-resistant region, and an electric field shielding region 118 is formed at the bottom of each of the third gate trenches 125. By arranging a P+ type electric field shielding region 118 directly below the plurality of trenches, and then integrating the SBD on both sides of the trench, and connecting two sets of SiC trench gate MOS devices with SBD integrated on the sidewalls of the trench through the transition voltage-resistant region, the transition voltage-resistant region structure is designed as a series of third gate trenches 125 connected by a P-type region and having a P+ type electric field shielding region 118 arranged below the trench. Arranging a P+ type electric field shielding region 118 directly below the trench can avoid electric field concentration at the bottom corner of the gate oxide layer of the SiC MOS trench, prevent early failure of the gate oxide, and avoid high electric fields on both sides of the SBD, thereby preventing the SBD voltage resistance from decreasing. The sidewall-integrated SBD has a low forward voltage drop, which reduces the device's freewheeling loss and enables the SiC MOS device to have lower conduction loss and switching loss.

[0057] Furthermore, the trench device 100 with integrated SBD further includes an insulating dielectric layer 170, which is disposed on the substrate 110, and the first trench gate structure 120, the second trench gate structure 130, the first emitter electrode 140, and the second emitter electrode 150 all pass through the insulating dielectric layer 170. Specifically, the material of the insulating dielectric layer 170 includes, but is not limited to, silicon oxide, silicon nitride, and the like. In addition, the insulating dielectric layer 170 has a thickness of 5000A-20000A, is prepared by CVD, and the etching process is dry etching or wet etching, and a contact hole is formed by etching, so that the first emitter electrode 140, the second emitter electrode 150, the first electrode layer 123, and the second electrode layer 133 formed subsequently can pass through the insulating dielectric layer 170.

[0058] In some embodiments, a first electrical contact layer 171 is formed between a side surface of the first source region 112 away from the substrate 110 and the first emitter electrode 140; a second electrical contact layer 172 is formed between a side surface of the second source region 113 away from the substrate 110 and the second emitter electrode 150. Specifically, the first electrical contact layer 171 and the second electrical contact layer 172 can be deposited and formed simultaneously. And the first electrical contact layer 171 partially covers the first source region 112, preferably completely covers a side surface of the first ohmic doping region 116 away from the substrate 110 and partially covers a side surface of the first channel doping region 114 away from the substrate 110. The second electrical contact layer 172 partially covers the second source region 113, preferably completely covers a side surface of the second ohmic doping region 117 away from the substrate 110 and partially covers a side surface of the second channel doping region 115 away from the substrate 110. The materials of the first electrical contact layer 171 and the second electrical contact layer 172 include but are not limited to nickel, polysilicon, doped polysilicon, metal aluminum, copper, titanium, tungsten and their stacks or alloys, and alloys of the above metals and silicon, etc. The thickness of the first electrical contact layer 171 and the second electrical contact layer 172 is 500-2000A, the deposition process is evaporation or sputtering, and the etching process is dry etching or wet etching.

[0059] During actual preparation, the first electrical contact layer 171 will also cover the bottom wall of the first source trench 142 , and the second electrical contact layer 172 will also cover the bottom wall of the second source trench 152 .

[0060] Furthermore, the trench device 100 with integrated SBD further includes a first buffer layer 180 and a second buffer layer 190, wherein the first buffer layer 180 is disposed on the insulating dielectric layer 170, and the second buffer layer 190 is disposed on the first buffer layer, and the first buffer layer 180 and the second buffer layer 190 both at least partially expose the first trench gate structure 120, the second trench gate structure 130, the first emitter electrode 140 and the second emitter electrode 150. Specifically, the material of the first buffer layer 180 includes but is not limited to silicon oxide, silicon nitride, etc., and is formed by photolithography pattern masking and etching. The first buffer layer 180 has a thickness of 1000A-20000A, is prepared by CVD, and the etching process is dry etching or wet etching. The material of the second buffer layer 190 includes but is not limited to polyimide, is prepared by photolithography process, and has a thickness of 50000A-150000A.

[0061] See also Figure 2The trench device 100 with integrated SBD provided in the embodiment of the present invention comprises two sets of SiC trench gate MOS devices with integrated SBD on the sidewall of the trench, namely, a first trench gate structure 120, a second trench gate structure 130, a first emitter electrode 140 and a second emitter electrode 150 are designed. The two sets of devices are connected through a transition voltage-resistant region, and the structure of the transition voltage-resistant region is designed as a series of third gate trenches 125 connected by a P-type region and provided with a P+ type electric field shielding region 118 under the trench. A P+ type electric field shielding region 118 is provided directly under all trenches. By integrating four-terminal SiC devices, it has the advantages of high integration, reduced area and cost, and can bring higher design freedom to the package design layout, especially in T-type three-level topology applications, its cross pipe only needs to use one chip of this invention to realize its function. The working principle is that when the first electrode layer 123 (G1) and the second electrode layer 133 (G2) are short-circuited with their respective terminals, the first emitting electrode 140 (E1) and the second emitting electrode 150 (E2), both quadrants can achieve high voltage blocking capability, and when a positive gate bias is applied between the gates G1 and G2 and the terminals E1 and E2, an on-current is generated in both quadrants, and the on-resistance is low.

[0062] The embodiment of the present invention further provides a method for preparing a trench device 100 with an integrated SBD, which is used to prepare the aforementioned trench device 100 with an integrated SBD. The method comprises the following steps:

[0063] S1: providing a substrate 110 of a first conductivity type.

[0064] Specifically, a substrate 110 is first provided. The material of the substrate 110 includes but is not limited to silicon carbide, silicon, gallium nitride, gallium arsenide, diamond, etc. The conductivity type is N-type, called the first conductivity type, the implantation energy is 200-800keV, and the dose is 3E11-3E14.

[0065] S2: implanting sequentially on the substrate 110 to form a doped well region 111 .

[0066] See also Figure 3 Specifically, a doped well region 111 of the second conductivity type is formed on the substrate 110 by ion implantation, wherein the doped well region 111 is located on the substrate 110 .

[0067] S3 : implanting into the doped well region 111 to form a first source region 112 and a second source region 113 .

[0068] See also Figure 4Specifically, the first source region 112 and the second source region 113 are formed in the doped well region 111 and extend to the side surface of the doped well region 111 away from the substrate 110. In actual preparation, ion implantation can be first performed in the doped well region 111 through a photolithography pattern mask to form a first channel doping region 114 and a second channel doping region 115 of the first conductivity type, and the first channel doping region 114 and the second channel doping region 115 are both formed on the side surface of the doped well region 111 away from the substrate 110. Then, ion implantation is performed in the doped well region 111 again through a photolithography pattern mask to form a first ohmic doping region 116 and a second ohmic doping region 117 of the second conductivity type. The doping concentrations of the first ohmic doping region 116 and the second ohmic doping region 117 are greater than the doping concentration of the doped well region 111.

[0069] After the preparation of the first ohmic doping region 116 and the second ohmic doping region 117 is completed, activation annealing is required. Specifically, a cap layer is first deposited to prevent Si evaporation during the activation annealing process, and then the cap layer is removed. The material of the cap layer includes but is not limited to carbon, which is prepared by CVD with a thickness of 1000-5000A. After the activation annealing, there will be lateral diffusion between the first channel doping region 114 and the first ohmic doping region 116, and between the second channel doping region 115 and the second ohmic doping region 117, so that the first channel doping region 114 and the first ohmic doping region 116 are in contact with each other, and the second channel doping region 115 and the second ohmic doping region 117 are in contact with each other.

[0070] The first ohmic doping region 116 and the second ohmic doping region 117 are P-type semiconductors, called the second conductivity type, and the doping impurities include aluminum, boron, gallium, etc.; the injection energy is 50-500keV, and the dose is 3E11-3E14. The first channel doping region 114 and the second channel doping region 115 are N-type semiconductors, called the first conductivity type, and the doping concentration is higher than that of the substrate 110. The doping impurities include nitrogen, phosphorus, arsenic, selenium, sulfur, etc.; the injection energy is 50-500keV, and the dose is 3E11-3E14.

[0071] S3 : forming a first gate trench 124 , a second gate trench 134 , a third gate trench 125 , a first source trench 142 , and a second source trench 152 on the substrate 110 .

[0072] See also Figure 5 Specifically, after completing the activation annealing, a first mask hard layer is deposited, the hard mask layer 200 is patterned by photolithography mask etching, and then the hard mask layer 200 is used to etch a plurality of grooves on the substrate 110, that is, a first gate trench 124, a second gate trench 134, a third gate trench 125, a first source trench 142 and a second source trench 152 are formed simultaneously.

[0073] The material of the hard mask layer 200 includes but is not limited to silicon oxide, silicon nitride, etc., and the thickness of the hard mask layer 200 is 1000A-10000A, and it is prepared by CVD, and the etching process is dry etching or wet etching. The multiple grooves are respectively the first gate groove 124, the second gate groove 134, the third gate groove 125, the first source groove 142 and the second source groove 152, and the groove etching is dry etching or wet etching, the groove etching depth is 0.5-2μm, the groove width is 0.5-2μm, and the groove spacing is 0.2-2μm.

[0074] S4 : forming a first trench gate structure 120 and a second trench gate structure 130 in the first gate trench 124 and the second gate trench 134 , respectively.

[0075] Specifically, the first trench gate structure 120 passes through the first source region 112 and the doped well region 111 and extends to the substrate 110 , and the second trench gate structure 130 passes through the second source region 113 and the doped well region 111 and extends to the substrate 110 .

[0076] In actual preparation, the electric field shielding region 118 may be prepared first, see Figure 6 Specifically, a barrier layer 300 is first deposited in the trench through a hard mask layer 200, and the barrier layer 300 on the bottom wall of the trench is removed by etching, so as to form a sidewall on the sidewall of the trench, and then a second conductive type electric field shielding region 118 is formed by photolithography pattern mask or direct ion implantation, and then the hard mask layer 200 and the barrier layer 300 are removed by etching. The electric field shielding region 118 is a P-type semiconductor, called the second conductive type, and the doping impurities include aluminum, boron, gallium, etc.; the implantation energy is 20-200keV, and the dose is 3E11-3E13.

[0077] See also Figure 7After the preparation of the electric field shielding region 118 is completed, an insulating layer can be formed by thermal growth in the trench, a first gate oxide layer 122 is formed on the sidewall and bottom wall of the first gate trench 124, a second gate oxide layer 132 is formed on the sidewall and bottom wall of the second gate trench 134, and a third gate oxide layer 127 is formed on the sidewall and bottom wall of the third gate trench 125; then, a conductive material is deposited in the first gate trench 124, the second gate trench 134 and the third gate trench 125, and the conductive material layer is made flush with the trench opening by photolithography pattern masking and etching, so that the first gate conductive layer 121 is deposited in the first gate trench 124, the second gate conductive layer 131 is deposited in the second gate trench 134, and the third gate conductive layer 126 is deposited in the third gate trench 125. Then, the insulating layer outside the trench is etched away. The materials of the first gate conductive layer 121, the second gate conductive layer 131 and the third gate conductive layer 126 include but are not limited to nickel, polysilicon, doped polysilicon, metal aluminum, copper, titanium, tungsten and their stacks or alloys, and alloys of the above metals and silicon, etc. Meanwhile, the first electrode layer 123 and the second electrode layer 133 can be formed together when preparing the first emitting electrode 140 and the second emitting electrode 150.

[0078] S5: forming an insulating dielectric layer 170 by deposition.

[0079] See also Figure 8 Specifically, after the first gate conductive layer 121, the second gate conductive layer 131 and the third gate conductive layer 126 are prepared, a layer of insulating material can be deposited, and then a contact hole on the insulating dielectric layer 170 is formed by photolithography pattern masking and etching. The material of the insulating dielectric layer 170 includes but is not limited to silicon oxide, silicon nitride, etc., and has a thickness of 5000A-20000A. It is prepared by CVD, and the etching process is dry etching or wet etching. The contact hole is formed by etching. Different contact holes can expose the first gate conductive layer 121, the second gate conductive layer 131, the first source region 112 and the second source region 113.

[0080] S6 : forming the first emitter electrode 140 and the second emitter electrode 150 in the first source trench 142 and the second source trench 152 , respectively.

[0081] Among them, the first emitting electrode 140 is electrically in contact with the first source region 112, the first emitting electrode 140 passes through the doped well region 111 and extends to the substrate 110, and a first Schottky diode 141 is formed between the side wall of the first emitting electrode 140 and the substrate 110; the second emitting electrode 150 is electrically in contact with the second source region 113, the second emitting electrode 150 passes through the doped well region 111 and extends to the substrate 110, and a second Schottky diode 151 is formed between the side wall of the second emitting electrode 150 and the substrate 110.

[0082] See also Fig. 9 In actual preparation, the preparation of the first electrical contact layer 171 and the second electrical contact layer 172 must be completed first, for example, by photolithography pattern masking and etching to form the first electrical contact layer 171 and the second electrical contact layer 172 on the surface of the first source region 112 and the second source region 113, respectively. The materials of the first electrical contact layer 171 and the second electrical contact layer 172 include but are not limited to nickel, polysilicon, doped polysilicon, metal aluminum, copper, titanium, tungsten and their stacks or alloys, and alloys of the above metals and silicon. At the same time, the thickness of the first electrical contact layer 171 and the second electrical contact layer 172 is 500-2000A, the deposition process is evaporation or sputtering, and the etching process is dry etching or wet etching. In actual preparation, the first electrical contact layer 171 will also cover the bottom wall of the first source trench 142, and the second electrical contact layer 172 will also cover the bottom wall of the second source trench 152.

[0083] See also Fig.10 After the preparation of the first electrical contact layer 171 and the second electrical contact layer 172 is completed, the first emitter electrode 140 can be formed in the first source groove 142 by photolithography pattern mask and etching, and the second emitter electrode 150 can be formed in the second source groove 152 at the same time. In addition, the first electrode layer 123 and the second electrode layer 133 will also be formed together. Among them, the materials of the first emitter electrode 140, the second emitter electrode 150, the first electrode layer 123 and the second electrode layer 133 include but are not limited to nickel, polysilicon, doped polysilicon, metal aluminum, copper, titanium, tungsten and their stacks or alloys, as well as alloys of the above metals and silicon, etc.; the deposition thickness is 2-6μm, the deposition process is evaporation or sputtering, and the etching process is dry etching or wet etching.

[0084] S7: forming a first buffer layer 180 and a second buffer layer 190 by sequential deposition.

[0085] See also Fig.11 Specifically, the first buffer layer 180 can be formed by photolithography pattern mask and etching. The material of the first buffer layer 180 includes but is not limited to silicon oxide, silicon nitride, etc.; the deposition thickness is 1000A-20000A, and it is prepared by CVD, and the etching process is dry etching or wet etching. Then, the second buffer layer 190 is formed by exposure and development process to complete the front processing. The material of the second buffer layer 190 includes but is not limited to polyimide, the thickness is 50000A-150000A, and it is prepared by photolithography process.

[0086] S8 : forming a back electrode 160 on the other side surface of the substrate 110 .

[0087] Please continue to see Figure 1Specifically, the back side of the substrate 110 is first thinned, and then the back electrode 160 is deposited. The material of the back electrode 160 includes but is not limited to metal nickel, aluminum, copper, silver, titanium, tungsten, and their stacks or alloys, etc.; the thickness is 0.5-3 μm, the deposition process is evaporation or sputtering, and the etching process is dry etching or wet etching.

[0088] It should be noted that the parameters and methods disclosed in the patent are for reference only, and the protection content is not limited to the parameters described in the text. Technicians in this field can apply it after appropriate adjustments.

[0089] In summary, the trench device 100 with integrated SBD and the method for manufacturing the same provided by the embodiment of the present invention form a doped well region 111, a first source region 112, and a second source region 113 on a substrate 110, and simultaneously form a first gate trench 124 structure and a second gate trench 134 structure on the substrate 110. The first gate trench 124 structure passes through the first source region 112 and the doped well region 111 and extends to the substrate 110, and the second gate trench 134 structure passes through the second source region 113 and the doped well region 111 and extends to the substrate 110. The first emitter electrode 140 passes through the doped well region 111 and extends to the substrate 110, and the second emitter electrode 150 passes through the doped well region 111 and extends to the substrate 110. The sidewall of the first emitter electrode 140 is in Schottky contact with the substrate 110, and a first Schottky diode 141 is formed, and the sidewall of the second emitter electrode 150 is in Schottky contact with the substrate 110, and a second Schottky diode 151 is formed. Compared with the prior art, the present application integrates two sets of trench gate MOS devices together, and integrates the first Schottky diode 141 and the second Schottky diode 151, thereby integrating the Schottky diode into the MOSFET device, which has the advantages of high integration, reduced area and cost, and can bring higher design freedom to the package design layout, especially in T-type three-level topology applications, its cross tube only needs to use one chip to achieve the function of four chips in conventional technology, without the need to introduce external parallel diodes, which saves costs and can further optimize the reverse recovery process, reduce reverse recovery losses, and further improve the efficiency of the system.

[0090] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0091] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0092] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0093] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can still modify the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or perform equivalent replacements on some of the technical features thereof; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. They should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A trench device with integrated SBD, characterized in that: include: A substrate of a first conductivity type, on which a doped well region of a second conductivity type is formed, in which a first source region and a second source region are formed, and the first source region and the second source region extend to a surface of the doped well region away from the substrate; a first trench gate structure and a second trench gate structure, wherein the first trench gate structure passes through the first source region and the doped well region and extends to the substrate; The second trench gate structure passes through the second source region and the doped well region and extends to the substrate; a first emitting electrode and a second emitting electrode, wherein the first emitting electrode is spaced apart from the first trench gate structure and passes through the doped well region, and the first emitting electrode is in electrical contact with the first source region; and the second emitting electrode is spaced apart from the second trench gate structure and passes through the doped well region, and the second emitting electrode is in electrical contact with the second source region; A back electrode, the back electrode being arranged on the other side surface of the substrate; The first emitting electrode extends to the substrate, and the side wall of the first emitting electrode extends to form a Schottky contact with the substrate to form a first Schottky diode, and the second emitting electrode extends to the substrate, and the side wall of the second emitting electrode extends to the substrate to form a Schottky contact with the substrate to form a second Schottky diode.

2. The trench device with integrated SBD according to claim 1, characterized in that: A first source trench and a second source trench are provided on the substrate, the first source trench passes through the first source region and the doped well region, the first emitter electrode is filled in the first source trench, and extends to a side surface of the first source region away from the substrate; the second source trench passes through the second source region and the doped well region, the second emitter electrode is filled in the second source trench, and extends to a side surface of the second source region away from the substrate.

3. The trench device with integrated SBD according to claim 2, characterized in that: The first source region includes a first channel doping region and a first ohmic doping region, both of which extend to the surface of the doped well region, one side of the first channel doping region is connected to the first trench gate structure, and the other side is connected to the first ohmic doping region, the first ohmic doping region is connected to the first emitting electrode, and the first emitting electrode covers the surface of the first ohmic doping region and partially covers the surface of the first channel doping region; The second source region includes a second channel doping region and a second ohmic doping region both extending to the surface of the doped well region, one side of the second channel doping region is connected to the second trench gate structure, and the other side is connected to the second ohmic doping region, the second ohmic doping region is connected to the second emitting electrode, and the second emitting electrode covers the surface of the second ohmic doping region and partially covers the surface of the second channel doping region; The first channel doping region and the second channel doping region are both of the first conductivity type, and the first ohmic doping region and the second ohmic doping region are both of the second conductivity type.

4. The trench device with integrated SBD according to claim 2 or 3, characterized in that: The first trench gate structure includes a first gate conductive layer, a first gate oxide layer and a first electrode layer, a first gate trench is provided on the substrate, the first gate trench passes through the first source region and the doped well region, the first gate oxide layer is formed on the sidewall and bottom wall of the first gate trench, the first gate conductive layer is filled in the first gate trench, and the first electrode layer is provided on the first gate conductive layer; The second trench gate structure includes a second gate conductive layer, a second gate oxide layer and a second electrode layer. A second gate trench is arranged on the substrate. The second gate trench passes through the second source region and the doped well region. The second gate oxide layer is formed on the sidewall and bottom wall of the second gate trench. The second gate conductive layer fills the first gate trench. The second electrode layer is arranged on the second gate conductive layer.

5. The trench device with integrated SBD according to claim 4, characterized in that: A plurality of spaced-apart third gate trenches are also formed on the substrate between the first gate trench and the second gate trench, each of the third gate trenches passes through the doped well region and extends to the substrate, and a third gate oxide layer is formed on the sidewalls and bottom walls of each of the third gate trenches, and the third gate trenches are filled with a third gate conductive layer.

6. The trench device with integrated SBD according to claim 5, characterized in that: An electric field shielding region of the second conductivity type is formed at the bottom of the first source trench, the second source trench, the first gate trench, the second gate trench, and the third gate trench.

7. The trench device with integrated SBD according to claim 1, characterized in that: The trench device with integrated SBD further includes an insulating dielectric layer, which is disposed on the substrate, and the first trench gate structure, the second trench gate structure, the first emitter electrode, and the second emitter electrode all pass through the insulating dielectric layer.

8. The trench device with integrated SBD according to claim 7, characterized in that: A first electrical contact layer is formed between a surface of the first source region away from the substrate and the first emitting electrode; a second electrical contact layer is formed between a surface of the second source region away from the substrate and the second emitting electrode.

9. The trench device with integrated SBD according to claim 7, characterized in that: The trench-type device with integrated SBD also includes a first buffer layer and a second buffer layer, wherein the first buffer layer is arranged on the insulating dielectric layer, and the second buffer layer is arranged on the first buffer layer, and both the first buffer layer and the second buffer layer at least partially expose the first trench gate structure, the second trench gate structure, the first emitter electrode and the second emitter electrode.

10. A method for preparing a trench-type device with integrated SBD, for preparing the trench-type device with integrated SBD as claimed in claim 1, characterized in that: The preparation method comprises: providing a substrate of a first conductivity type; Implanting to form a doped well region on the substrate, wherein the doped well region is located on the substrate; Implanting a first source region and a second source region into the doped well region, wherein the first source region and the second source region are formed in the doped well region and extend to a surface of the doped well region away from the substrate; forming a first gate trench, a second gate trench, a first source trench, and a second source trench on the substrate; A first trench gate structure and a second trench gate structure are formed in the first gate trench and the second gate trench, respectively, wherein the first trench gate structure passes through the first source region and the doped well region and extends to the substrate; and the second trench gate structure passes through the second source region and the doped well region and extends to the substrate; A first emitting electrode and a second emitting electrode are formed in the first source trench and the second source trench, respectively, wherein the first emitting electrode is in electrical contact with the first source region, the first emitting electrode passes through the doped well region and extends to the substrate, and a first Schottky diode is formed between a sidewall of the first emitting electrode and the substrate; the second emitting electrode is in electrical contact with the second source region, the second emitting electrode passes through the doped well region and extends to the substrate, and a second Schottky diode is formed between a sidewall of the second emitting electrode and the substrate; A back electrode is formed on the other side surface of the substrate.

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