Semiconductor device and manufacturing method thereof
By adopting N-type ring gate transistors and P-type ring gate transistors with opposite conductivity types in CFET devices, and setting the specific crystal direction and alignment relationship of their channel regions, the problems of poor operating performance and difficulty in integration of existing CFET devices are solved, and higher integration and yield are achieved.
Patent Information
- Application Number
- CN202411640488.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-03-28
AI Technical Summary
The existing CFET devices have poor working performance and are difficult to integrate, which affects their yield.
An N-type ring gate transistor and a P-type ring gate transistor with opposite conductivity types are distributed spaced along the thickness direction of the semiconductor substrate. The channel region crystal direction of the N-type ring gate transistor is [111] crystal direction, and the channel region crystal direction of the P-type ring gate transistor is [110] crystal direction, and the channel regions of the two are self-aligned.
It improves the integration and working performance of CFET devices, reduces integration difficulty and leakage risks, and improves the yield of semiconductor devices.
Smart Images
Figure CN119730375A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art
[0002] Complementary Field Effect Transistor (CFET) devices include vertically stacked N-type transistors and P-type transistors to improve the integration density of CMOS devices. In addition, ring-gate transistors have advantages such as higher gate control capability compared to planar transistors and fin field effect transistors. Therefore, when both the N-type transistors and the P-type transistors included in the CFET device are ring-gate transistors, the working performance of the CMOS device can be improved.
[0003] However, the working performance of the existing CFET device is not good. In addition, the integration difficulty of the CFET device manufactured by the existing manufacturing method is relatively large, which is not conducive to improving the yield of the CFET device. Summary of the invention
[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the yield and working performance of the semiconductor device and reduce the difficulty of integrating the semiconductor device.
[0005] In order to achieve the above-mentioned object, the present invention provides a semiconductor device, which includes: a semiconductor substrate, an N-type ring-gate transistor, a P-type ring-gate transistor and an insulating layer. The N-type ring-gate transistor and the P-type ring-gate transistor are spaced apart along the thickness direction of the semiconductor substrate. The insulating layer is arranged between the source / drain region included in the N-type ring-gate transistor and the source / drain region included in the P-type ring-gate transistor. Among them, the crystal orientation of the nanostructure in the channel region included in the N-type ring-gate transistor is a
[111] crystal orientation. The crystal orientation of the nanostructure in the channel region included in the P-type ring-gate transistor is a
[110] crystal orientation. The channel region included in the N-type ring-gate transistor is self-aligned with the channel region included in the P-type ring-gate transistor.
[0006] When the above technical solution is adopted, the N-type ring-gate transistor and the P-type ring-gate transistor of opposite conductivity types are spaced apart along the thickness direction of the semiconductor substrate. At this time, the two constitute a CFET device to improve the integration of the semiconductor device and facilitate the miniaturization of the semiconductor device. Among them, the two transistors of opposite conductivity types included in the CFET device are both ring-gate transistors. In other words, the two transistors included in the CFET device have strong gate control capabilities. In addition, because the channel with a
[111] crystal orientation is conducive to the transmission of electrons, and the channel with a
[110] crystal orientation is conducive to the transmission of holes, when the channel of the N-type ring-gate transistor included in the CFET device has a crystal orientation of
[111] , and the channel of the P-type ring-gate transistor has a crystal orientation of
[110] , it is conducive to making the channels of the N-type ring-gate transistor and the P-type ring-gate transistor, which are both ring-gate transistors, have higher carrier mobility, so that both have good conductivity at the same time.
[0007] In addition, in the semiconductor device provided by the present invention, the channel region included in the N-type ring-gate transistor is self-aligned with the channel region included in the P-type ring-gate transistor, which is beneficial to reducing the difficulty of subsequent interconnection processes and reducing the risk of leakage. It is also beneficial to reduce parasitic capacitance, which is beneficial to improving the yield and working performance of the semiconductor device and reducing the difficulty of integration of the semiconductor device.
[0008] In one example, a material of a channel region included in the N-type gate-all-around transistor is different from a material of a channel region included in the P-type gate-all-around transistor.
[0009] In one example, the carrier mobility corresponding to the channel region material included in the P-type all-around gate transistor is greater than the carrier mobility corresponding to the channel region material included in the N-type all-around gate transistor.
[0010] In one example, the material of the channel region of the N-type gate-all-around transistor includes silicon.
[0011] In one example, the material of the channel region included in the P-type all-around gate transistor includes silicon germanium or germanium.
[0012] In one example, the source / drain regions included in the N-type gate-all-around transistor are respectively in direct contact with the gate stack structure included in the N-type gate-all-around transistor.
[0013] In one example, the P-type gate-all-around transistor further includes an inner sidewall, and the inner sidewall is located between the source / drain region and the gate stack structure included in the P-type gate-all-around transistor.
[0014] In one example, the material and / or thickness of the gate stack structure included in the N-type gate-all-around transistor are respectively the same as the material and / or thickness of the gate stack structure included in the P-type gate-all-around transistor.
[0015] In a second aspect, the present invention provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising: first, providing a semiconductor substrate. Next, forming an N-type ring gate transistor, a P-type ring gate transistor and an insulating layer on the semiconductor substrate. The N-type ring gate transistor and the P-type ring gate transistor are spaced apart along the thickness direction of the semiconductor substrate. The insulating layer is arranged between the source / drain region included in the N-type ring gate transistor and the source / drain region included in the P-type ring gate transistor. Among them, the crystal orientation of the nanostructure in the channel region included in the N-type ring gate transistor is a
[111] crystal orientation. The crystal orientation of the nanostructure in the channel region included in the P-type ring gate transistor is a
[110] crystal orientation. The channel region included in the N-type ring gate transistor is self-aligned with the channel region included in the P-type ring gate transistor.
[0016] In one example, an N-type all-around gate transistor, a P-type all-around gate transistor, and an insulating layer are formed on a semiconductor substrate, including: forming a semiconductor stack, a first sacrificial layer, and a first channel layer stacked on the semiconductor substrate along the thickness direction of the semiconductor substrate. The semiconductor stack includes a second sacrificial layer and a second channel layer stacked alternately. The film layers at the bottom layer and the top layer in the semiconductor stack are both second sacrificial layers. Next, under the masking action of the first mask structure, an isotropic etching process is used to etch the first channel layer to form a notch structure. An anisotropic etching process is used to form a fin under the notch structure, and a passivation layer is formed around the notch structure and the fin by a passivation process. The operation is repeated until a first fin-shaped structure is formed, and the number of layers of the notch structure included in the first fin-shaped structure is one more than the number of layers of the nanostructure included in the N-type all-around gate transistor. Next, under the masking action of the same first mask structure, the first sacrificial layer is etched; and the semiconductor stack is etched to form a second fin-shaped structure. Next, the first mask structure is removed; and the passivation layer is removed. Next, an N-type all-around gate transistor is formed based on the first fin structure; and a P-type all-around gate transistor is formed based on the second fin structure.
[0017] In one example, an N-type ring gate transistor is formed based on a first fin structure; and a P-type ring gate transistor is formed based on a second fin structure, including: forming a second mask structure spanning the first fin structure and the second fin structure. Next, the portion of the first fin structure exposed outside the second mask structure is processed to form a source / drain region included in the N-type ring gate transistor. The portion of the second fin structure exposed outside the second mask structure is processed to form a source / drain region included in the P-type ring gate transistor; and an insulating layer is formed between the source / drain region included in the N-type ring gate transistor and the source / drain region included in the P-type ring gate transistor. Next, at least a portion of the second mask structure is removed. Next, the remaining first fin structure is selectively etched to form a nanostructure included in the N-type ring gate transistor. Next, the remaining second sacrificial layer is selectively removed so that the remaining second channel layer forms a nanostructure included in the P-type ring gate transistor. Next, a gate stack structure is formed around the periphery of the nanostructure included in the N-type ring gate transistor; and a gate stack structure is formed around the nanostructure included in the P-type ring gate transistor.
[0018] In one example, after removing at least a portion of the second mask structure, a gate stack structure is formed surrounding the periphery of the nanostructure included in the N-type ring-gate transistor; and before forming the gate stack structure surrounding the nanostructure included in the P-type ring-gate transistor, the method for manufacturing the semiconductor device also includes: removing the remaining first sacrificial layer.
[0019] In one example, after removing the remaining first sacrificial layer, a gate stack structure is formed surrounding the periphery of the nanostructure included in the N-type ring gate transistor; and before forming the gate stack structure surrounding the nanostructure included in the P-type ring gate transistor, the method for manufacturing a semiconductor device also includes: forming a middle dielectric isolation layer in the space released by removing the remaining first sacrificial layer.
[0020] In one example, after forming a second mask structure spanning the first fin structure and the second fin structure, and before forming the source / drain region included in the N-type ring gate transistor and the source / drain region included in the P-type ring gate transistor, the method for manufacturing a semiconductor device further includes: selectively removing at least a portion of the first sacrificial layer to form a dielectric filling region. Next, forming a middle dielectric isolation layer in the dielectric filling region. Next, removing a portion of the middle dielectric isolation layer exposed outside the second mask structure.
[0021] In an example, the material of the second sacrificial layer is the same as the material of the first channel layer, and the remaining second sacrificial layer is selectively removed while the remaining first fin structure is selectively etched.
[0022] In one example, the portion of the second fin structure exposed outside the second mask structure is processed to form a source / drain region included in a P-type ring-gate transistor, including: removing the portion of the second fin structure exposed outside the second mask structure. Next, along the length direction of the gate stack structure, the edge portions on both sides of the remaining second sacrificial layer are removed to form a second dielectric filling region. Next, an inner sidewall is formed in the second dielectric filling region. Next, the source / drain region included in the P-type ring-gate transistor is formed on both sides of the remaining second channel layer.
[0023] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0025] Figures 1 to 47 A schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present invention.
[0026] Figure numerals: 11 is a semiconductor substrate, 12 is an N-type ring-gate transistor, 13 is a P-type ring-gate transistor, 14 is an insulating layer, 15 is a source / drain region, 16 is a nanostructure, 17 is a gate stack structure, 18 is an inner sidewall, 19 is a gate sidewall, 20 is a shallow trench isolation structure, 21 is an interlayer dielectric layer, 22 is a semiconductor stack, 23 is a first sacrificial layer, 24 is a first channel layer, 25 is a second channel layer, 26 is a second sacrificial layer, 27 is a first mask structure, 28 is a notch structure, 29 is a fin, 30 is a passivation layer, 31 is a first fin-shaped structure, 32 is a second fin-shaped structure, 33 is a second mask structure, and 34 is a middle dielectric isolation layer. DETAILED DESCRIPTION
[0027] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.
[0028] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0029] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.
[0031] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0032] Complementary Field Effect Transistor (CFET) devices include vertically stacked N-type transistors and P-type transistors to improve the integration density of CMOS devices. In addition, ring-gate transistors have advantages such as higher gate control capability compared to planar transistors and fin field effect transistors. Therefore, when both the N-type transistors and the P-type transistors included in the CFET device are ring-gate transistors, the working performance of the CMOS device can be improved.
[0033] However, the crystal orientation of the channel included in the existing ring-gate transistor is usually
[100] . At this time, the channel included in the ring-gate transistor is conducive to the transmission of electrons, but not conducive to the transmission of holes. Based on this, because the channel carriers of the N-type ring-gate transistor in the CFET device are electrons and the channel carriers of the P-type ring-gate transistor are holes, when the ring-gate transistor including the
[100] crystal orientation channel is applied to the above-mentioned CFET device, the above-mentioned ring-gate transistor is only conducive to improving the electron mobility of the N-type ring-gate transistor, but not conducive to the hole mobility of the P-type ring-gate transistor, resulting in the working performance of the CFET device with the above-mentioned ring-gate transistor as the application structure is not good. In addition, the integration difficulty of manufacturing CFET devices using the existing manufacturing method is also relatively large, which is not conducive to improving the yield of CFET devices.
[0034] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the embodiment of the present invention, the crystal orientation of the channel included in the N-type ring-gate transistor is
[111] , and the crystal orientation of the channel included in the P-type ring-gate transistor is
[110] , which is conducive to making the channels included in the N-type ring-gate transistor and the P-type ring-gate transistor, which are both ring-gate transistors in the CFET device, have higher carrier mobility.
[0035] Specifically, in a first aspect, an embodiment of the present invention provides a semiconductor device. Figure 43 to Figure 47 As shown, the semiconductor device includes: a semiconductor substrate 11, an N-type ring-gate transistor 12, a P-type ring-gate transistor 13 and an insulating layer 14. The N-type ring-gate transistor 12 and the P-type ring-gate transistor 13 are spaced apart along the thickness direction of the semiconductor substrate 11. The insulating layer 14 is arranged between the source / drain region 15 included in the N-type ring-gate transistor 12 and the source / drain region 15 included in the P-type ring-gate transistor 13. Among them, the crystal orientation of the nanostructure 16 in the channel region included in the N-type ring-gate transistor 12 is a
[111] crystal orientation. The crystal orientation of the nanostructure 16 in the channel region included in the P-type ring-gate transistor 13 is a
[110] crystal orientation. The channel region included in the N-type ring-gate transistor 12 is self-aligned with the channel region included in the P-type ring-gate transistor 13.
[0036] When the above technical solution is adopted, Figure 43 to Figure 47 As shown, the N-type ring-gate transistor 12 and the P-type ring-gate transistor 13 of opposite conductivity types are spaced apart along the thickness direction of the semiconductor substrate 11. At this time, the two constitute a CFET device to improve the integration of the semiconductor device and facilitate the miniaturization of the semiconductor device. Among them, the two transistors of opposite conductivity types included in the CFET device are both ring-gate transistors. In other words, the two transistors included in the CFET device have strong gate control capabilities. In addition, because the channel with a
[111] crystal orientation is conducive to the transmission of electrons, and the channel with a
[110] crystal orientation is conducive to the transmission of holes, when the channel of the N-type ring-gate transistor 12 included in the CFET device has a crystal orientation of
[111] , and the channel of the P-type ring-gate transistor 13 has a crystal orientation of
[110] , it is conducive to making the channels of the N-type ring-gate transistor 12 and the P-type ring-gate transistor 13, which are both ring-gate transistors, have higher carrier mobility, so that both have good conductivity at the same time. In addition, in the semiconductor device provided by the embodiment of the present invention, the channel region included in the N-type ring-gate transistor 12 is self-aligned with the channel region included in the P-type ring-gate transistor 13, which is beneficial to reducing the difficulty of subsequent interconnection processes and reducing the risk of leakage. It is also beneficial to reducing parasitic capacitance, which is beneficial to improving the yield and working performance of the semiconductor device and reducing the difficulty of integration of the semiconductor device.
[0037] In actual application, the embodiment of the present invention does not specifically limit the material and structure of the semiconductor substrate, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention.
[0038] Exemplarily, the semiconductor substrate may be a semiconductor substrate on which no structure is formed, such as a silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate or a germanium substrate.
[0039] Alternatively, the semiconductor substrate may also be a semiconductor substrate with some structures formed thereon. For example, when the semiconductor device in the embodiment of the present invention is a semiconductor device of the second layer or higher layer in an integrated circuit, the semiconductor substrate includes a semiconductor structure and an interlayer dielectric layer located below an N-type gate-all-around transistor or a P-type gate-all-around transistor.
[0040] For the N-type gate-all-around transistor and the P-type gate-all-around transistor, in terms of the formation position, the embodiment of the present invention does not specifically limit the upper and lower relative position relationship between the N-type gate-all-around transistor and the P-type gate-all-around transistor. Fig.43 and Fig.45 As shown, the N-type gate-all-around transistor 12 may be arranged directly above the P-type gate-all-around transistor 13. Alternatively, Fig.44 and Fig.46 As shown, the P-type gate-all-around transistor 13 may also be arranged directly above the N-type gate-all-around transistor 12 .
[0041] From a structural point of view, the N-type ring-gate transistor includes a source / drain region, a channel region and a gate stack structure. In the N-type ring-gate transistor, the channel region is located between the source / drain region, and the two ends of the channel region along the length direction are respectively in contact with the channel region. The channel region may include only one layer of nanostructure, or may include multiple layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate. Moreover, in the N-type ring-gate transistor, the crystal orientation of each layer of nanostructure in the channel region is the
[111] crystal orientation, and the longitudinal section of the nanostructure is prism-like. The gate stack structure included in the N-type ring-gate transistor surrounds the periphery of each layer of nanostructure in the
[111] crystal orientation.
[0042] As for the P-type ring-gate transistor, the P-type ring-gate transistor includes a source / drain region, a channel region and a gate stack structure. Among them, the relative position relationship between the source / drain region, the channel region and the gate stack structure of the P-type ring-gate transistor can refer to the relative position relationship between the source / drain region, the channel region and the gate stack structure of the N-type ring-gate transistor described above, which will not be repeated here. In the P-type ring-gate transistor, the crystal orientation of each layer of nanostructure included in the channel region is the
[110] crystal orientation, and the longitudinal cross-section of the nanostructure is a rectangular shape.
[0043] Secondly, the channel region included in the N-type all-around gate transistor is self-aligned with the channel region included in the P-type all-around gate transistor. Figures 1 to 47 As shown, the first fin structure 31 for manufacturing the channel region included in the N-type ring-gate transistor 12 and the second fin structure 32 for manufacturing the channel region included in the P-type ring-gate transistor 13 can be manufactured based on the same first mask structure 27, which not only improves the manufacturing efficiency but also helps to reduce the difficulty of the subsequent interconnection process.
[0044] In terms of materials, the source / drain region and channel region included in the N-type all-around gate transistor, and the source / drain region and channel region included in the P-type all-around gate transistor may include any semiconductor material such as silicon, silicon germanium or germanium. Among them, the source / drain region included in the N-type all-around gate transistor and the source / drain region included in the P-type all-around gate transistor may be the same material or different material.
[0045] The material of the channel region included in the N-type ring-gate transistor can be the same as the material of the channel region included in the P-type ring-gate transistor. In this case, during the actual manufacturing process, if the P-type ring-gate transistor is located directly above the N-type ring-gate transistor, after forming a second fin structure for manufacturing the channel region included in the P-type ring-gate transistor, it is necessary to form a protective layer on the periphery of the second fin structure to prevent the second channel layer in the second fin structure from being affected when the first channel layer in the channel region included in the N-type ring-gate transistor is subsequently etched, thereby further improving the yield of the semiconductor device.
[0046] Alternatively, the material of the channel region included in the N-type ring-gate transistor may be different from the material of the channel region included in the P-type ring-gate transistor. In this case, there is no need to form the above-mentioned protective layer, which improves the manufacturing efficiency of the semiconductor device and helps control the manufacturing cost of the semiconductor device. In this case, the specific types of the material of the channel region included in the N-type ring-gate transistor and the material of the channel region included in the P-type ring-gate transistor can be set according to the conductivity type of the two and actual needs, and are not specifically limited here.
[0047] Exemplarily, the carrier mobility corresponding to the channel region material included in the P-type all-around gate transistor may be greater than the carrier mobility corresponding to the channel region material included in the N-type all-around gate transistor, so as to further improve the operating performance of the P-type all-around gate transistor. Alternatively, the carrier mobility corresponding to the channel region material included in the P-type all-around gate transistor may also be equal to the carrier mobility corresponding to the channel region material included in the N-type all-around gate transistor.
[0048] As for the specific types of materials of the channel region included in the N-type ring-gate transistor and the channel region included in the P-type ring-gate transistor, for example: the material of the channel region included in the N-type ring-gate transistor may include silicon. For example: the material of the channel region included in the P-type ring-gate transistor includes silicon germanium or germanium. In the above case, high-mobility materials such as silicon germanium and germanium have the characteristics of high carrier mobility. Specifically, the nanostructure in the P-type ring-gate transistor is manufactured using high-mobility semiconductor materials such as silicon germanium or germanium, which can improve the hole mobility of the P-type ring-gate transistor. When the nanostructure in the N-type ring-gate transistor is manufactured using the above-mentioned high-mobility materials, there are problems such as poor interface state and high source-drain contact resistance. Therefore, when the material of the channel region included in the P-type ring-gate transistor includes silicon germanium or germanium, and the material of the channel region included in the N-type ring-gate transistor may include silicon, the performance of the semiconductor device can be improved, and it is beneficial to reduce the difference between the working performance of the N-type ring-gate transistor and the P-type ring-gate transistor. Alternatively, the N-type ring-gate transistor can also use silicon germanium or III-V materials with a lower germanium content to manufacture the nanostructure.
[0049] As for the above-mentioned gate stack structure, the gate stack structure may include a gate dielectric layer surrounding the outer periphery of the nanostructure, and a gate formed on the gate dielectric layer. The gate dielectric layer included in the gate stack structure may include HfO 2 、ZrO 2 、TiO 2 or Al 2 O 3 The gate material may include any conductive material such as TiN, TaN or TiSiN.
[0050] Specifically, the material and / or thickness of the gate stack structure included in the N-type ring gate transistor are respectively the same as the material and / or thickness of the gate stack structure included in the P-type ring gate transistor. At this time, the gate stack structure included in the N-type ring gate transistor and the gate stack structure included in the P-type ring gate transistor can be formed simultaneously, which can simplify the manufacturing process of the semiconductor device and improve the manufacturing efficiency of the semiconductor device. Alternatively, the material and / or thickness of the gate stack structure included in the N-type ring gate transistor are respectively different from the material and / or thickness of the gate stack structure included in the P-type ring gate transistor, so as to adjust the material and / or thickness of the gate stack structure of the N-type ring gate transistor and the P-type ring gate transistor according to the requirements of the threshold voltage and the like in the actual application scenario, so as to improve the applicability of the semiconductor device provided by the embodiment of the present invention in different application scenarios.
[0051] In some cases, such as Figure 43 to Figure 46 As shown, the P-type ring-gate transistor 13 also includes an inner sidewall 18. The inner sidewall 18 is located between the source / drain region 15 and the gate stack structure 17 included in the P-type ring-gate transistor 13 to limit the length of the gate stack structure 17 and improve the yield of the P-type ring-gate transistor 13. The material of the inner sidewall 18 can include any insulating material such as silicon oxide, silicon oxynitride or silicon oxynitride.
[0052] like Figure 43 to Figure 46 As shown, the source / drain regions 15 that the N-type all-around gate transistor 12 may include are in direct contact with the gate stack structure 17 that the N-type all-around gate transistor 12 includes. In this case, the nanostructure 16 included in the N-type all-around gate transistor 12 is released by etching a notch in the entire first channel layer 24 and selectively etching with an alkaline solution such as TMAH, and no sacrificial layer is used. Therefore, when the N-type all-around gate transistor 12 does not include the inner sidewall 18, the manufacturing difficulty of the N-type all-around gate transistor 12 can be reduced.
[0053] For the above-mentioned insulating layer, the embodiment of the present invention does not specifically limit the material and thickness of the insulating layer, as long as the source / drain regions of the P-type all-around gate transistor and the N-type all-around gate transistor can be separated by the insulating layer. For example, the material of the insulating layer may include any insulating material such as silicon oxide, silicon oxynitride or silicon oxynitride.
[0054] In some cases, such as Fig.45 and Fig.46As shown, the semiconductor device provided by the embodiment of the present invention may further include a middle dielectric isolation layer 34 located between the gate stack structure 17 of the N-type ring gate transistor 12 and the gate stack structure 17 of the P-type ring gate transistor 13, so as to reduce leakage and interference, and further improve the working performance of the semiconductor device. The embodiment of the present invention does not specifically limit the material and thickness of the middle dielectric isolation layer 34. The materials of different regions of the middle dielectric isolation layer 34 along the thickness direction of the semiconductor substrate 11 may be the same or different. Secondly, the middle dielectric isolation layer may include a plurality of dielectric isolation sublayers spaced apart along the thickness direction of the semiconductor substrate, and the gate stack structure surrounds the periphery of the dielectric isolation sublayer through the gap between two adjacent dielectric isolation sublayers; or, as Fig.45 and Fig.46 As shown, the middle dielectric isolation layer 34 may also be a structure of a continuous portion along the thickness direction of the semiconductor substrate 11 to further reduce leakage and interference.
[0055] In some cases, such as Figure 43 to Figure 47 As shown, the semiconductor device provided by the embodiment of the present invention may also include a shallow trench isolation structure 20, a gate sidewall 19 and an interlayer dielectric layer 21. The shallow trench isolation structure 20 is located on the semiconductor substrate 11 and is used to define different active areas of the semiconductor substrate 11. The gate sidewalls 19 are located on both sides of the gate stack structure 17 along the length direction to separate the gate stack structure 17 from other conductive structures formed subsequently to reduce the risk of leakage. The interlayer dielectric layer 21 covers the semiconductor substrate 11 and is used to protect the source / drain region 15 located on the top layer from being affected by subsequent etching or cleaning operations, thereby further improving the yield of the semiconductor device. As for the materials of the shallow trench isolation structure 20, the gate sidewall 19 and the interlayer dielectric layer 21, they may include any insulating material such as silicon oxide, silicon oxynitride or silicon oxynitride, which is not specifically limited here.
[0056] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 1 to 47 The manufacturing process is described in detail with reference to the cross-sectional view or stereoscopic view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:
[0057] First, a semiconductor substrate is provided. The structure and material of the semiconductor substrate can be referred to above and will not be described in detail here.
[0058] Next, if Figure 43 to Figure 47As shown, an N-type ring-gate transistor 12, a P-type ring-gate transistor 13 and an insulating layer 14 are formed on a semiconductor substrate 11. The N-type ring-gate transistor 12 and the P-type ring-gate transistor 13 are spaced apart in the thickness direction of the semiconductor substrate 11. The insulating layer 14 is arranged between the source / drain region 15 included in the N-type ring-gate transistor 12 and the source / drain region 15 included in the P-type ring-gate transistor 13. Among them, the crystal orientation of the nanostructure 16 in the channel region included in the N-type ring-gate transistor 12 is a
[111] crystal orientation. The crystal orientation of the nanostructure 16 in the channel region included in the P-type ring-gate transistor 13 is a
[110] crystal orientation. The channel region included in the N-type ring-gate transistor 12 is self-aligned with the channel region included in the P-type ring-gate transistor 13.
[0059] Among them, the structural materials of the above-mentioned N-type ring-gate transistor and P-type ring-gate transistor, and the relative position relationship between the two can be referred to the above description, and will not be repeated here. As for the specific manufacturing order of the N-type ring-gate transistor and the P-type ring-gate transistor, it can be determined according to the actual relative position relationship between the N-type ring-gate transistor and the P-type ring-gate transistor, and actual needs, and is not specifically limited here.
[0060] Exemplarily, forming an N-type all-around gate transistor, a P-type all-around gate transistor and an insulating layer on a semiconductor substrate may include the following steps:
[0061] like Figure 1 and Figure 2 As shown, epitaxy or other processes can be used to form a semiconductor stack 22, a first sacrificial layer 23, and a first channel layer 24 stacked on the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11. The semiconductor stack 22 includes alternately stacked second sacrificial layers 26 and second channel layers 25. The film layers at the bottom layer and the top layer in the semiconductor stack 22 are both the second sacrificial layers 26.
[0062] Specifically, the second channel layer in the semiconductor stack is used to manufacture the nanostructure included in the P-type ring gate transistor, so the number of layers, materials and thickness of the second channel layer in the semiconductor stack can be set with reference to the number of layers, materials and thickness of the nanostructure in the P-type ring gate transistor, which will not be repeated here. The second sacrificial layer is used to release the two adjacent layers of nanostructures in the P-type ring gate transistor, so the material of the second sacrificial layer can be any semiconductor material different from the first sacrificial layer and the second channel layer. Among them, the material of the second sacrificial layer can be the same as or different from the material of the first channel layer.
[0063] As for the first sacrificial layer, an insulating layer will be formed between the source / drain region of the N-type all-around gate transistor and the source / drain region of the P-type all-around gate transistor by removing part of the first sacrificial layer. Therefore, the thickness of the first sacrificial layer can be determined according to the thickness of the insulating layer. The material of the first sacrificial layer can be any semiconductor material different from the first channel layer, the second channel layer, and the second sacrificial layer, and is not specifically limited here.
[0064] As for the first channel layer, the first channel layer is used to manufacture the nanostructure included in the N-type all-around gate transistor. Therefore, the material and thickness of the first channel layer can be determined according to the material, number of layers and size of the nanostructure included in the N-type all-around gate transistor. Specifically, the thickness of the first channel layer is greater than the total height of the channel region included in the N-type all-around gate transistor.
[0065] Next, an N-type gate-all-around transistor is located above a P-type gate-all-around transistor as an example for explanation: Figures 3 to 8 As shown, the first channel layer 24 can be etched by an isotropic etching process under the masking effect of the first mask structure 27 to form a notch structure 28. A fin 29 is formed under the notch structure 28 by an anisotropic etching process, and a passivation layer 30 is formed around the notch structure 28 and the fin 29 by a passivation process. The operation is repeated until a first fin structure 31 is formed, and the number of layers of the notch structure 28 included in the first fin structure 31 is one more than the number of layers of the nanostructure 16 included in the N-type all-around gate transistor 12.
[0066] In the actual manufacturing process, deposition, photolithography and etching processes can be used to form a first mask structure on the first channel layer. Then, under the masking action of the first mask structure, an isotropic etching process is used to etch the first channel layer to form a notch structure; then, an anisotropic etching process is used to form a fin under the notch structure, and a passivation process (such as an oxidation process, etc.) is used to form a passivation layer on the periphery of the notch structure and the fin to protect the notch structure and the fin from being affected by the etchant during the subsequent etching process, so as to ensure that the crystal orientation of the nanostructure included in the N-type ring gate transistor formed based on the first fin structure is the
[111] crystal orientation, thereby improving the yield of the semiconductor device. Next, the number of repetitions of the above-mentioned isotropic etching-anisotropic etching-passivation process can be determined according to the number of layers of the nanostructure included in the N-type ring gate transistor. For example: if the number of layers of the nanostructure included in the N-type ring gate transistor is two layers, the operation needs to be repeated three times.
[0067] The etchants used in the above-mentioned isotropic etching process and anisotropic etching process can be determined according to the material of the nanostructure included in the N-type all-around gate transistor, and are not specifically limited here. For example, HBr and Cl 2 Mixed etching gas.
[0068] Next, if Fig. 9 As shown, under the masking effect of the same first mask structure 27, the first sacrificial layer can be etched by wet etching or dry etching, and the semiconductor stack can be etched to form the second fin structure 32. It can be seen that the first fin structure 31 and the second fin structure 32 are formed by etching based on the same first mask structure 27, so that the channel region of the N-type all-around gate transistor formed based on the first fin structure 31 and the channel region of the P-type all-around gate transistor formed based on the second fin structure 32 can be self-aligned.
[0069] Next, a process such as dry etching or wet etching is used to remove the first mask structure; and the passivation layer is removed. The embodiment of the present invention does not specifically limit the order of removing the first mask structure and the passivation layer, and can be set according to the actual application scenario. The first mask structure can be removed first, and then the passivation layer; or the passivation layer can be removed first, and then the first mask structure can be removed.
[0070] Next, if Figures 11 to 47 As shown, an N-type all-around gate transistor 12 is formed based on the first fin structure 31 ; and a P-type all-around gate transistor 13 is formed based on the second fin structure 32 .
[0071] Exemplarily, forming an N-type gate-all-around transistor and forming a P-type gate-all-around transistor may include the following steps: Fig.11 As shown, a second mask structure 33 is formed across the first fin structure 31 and the second fin structure 32. The embodiment of the present invention does not specifically limit the specific structure and material of the second mask structure 33, as long as it can play a protective role. For example: the second mask structure 33 may include a sacrificial gate. For another example: the second mask structure 33 may include a gate oxide layer, and a sacrificial gate located on the gate oxide layer. For another example: the second mask structure 33 may include a sacrificial gate, and gate sidewalls 19 located on both sides of the sacrificial gate along the length direction.
[0072] The specific formation process of the second mask structure can be determined according to the specific structure of the second mask structure. For example, when the second mask structure may include a gate oxide layer and a sacrificial gate, the second mask structure may be formed by sequentially using deposition and etching processes.
[0073] In one example, after forming a second mask structure spanning the first fin structure and the second fin structure, before forming the source / drain region included in the N-type all-around gate transistor and the source / drain region included in the P-type all-around gate transistor, the method for manufacturing the semiconductor device may further include the following steps: Fig.13 As shown, a dry etching or wet etching process is used to selectively remove at least a portion of the first sacrificial layer to form a dielectric filling area. Next, as shown Fig.15As shown, a middle dielectric isolation layer 34 is formed in the dielectric filling region by using processes such as deposition and etching. The material of the middle dielectric isolation layer 34 can be referred to above and will not be described again here.
[0074] Next, if Figures 17 to 32 As shown, the portion of the first fin structure 31 exposed outside the second mask structure 33 is processed to form the source / drain region 15 included in the N-type ring-gate transistor; the portion of the second fin structure 32 exposed outside the second mask structure 33 is processed to form the source / drain region 15 included in the P-type ring-gate transistor; and an insulating layer 14 is formed between the source / drain region 15 included in the N-type ring-gate transistor and the source / drain region 15 included in the P-type ring-gate transistor.
[0075] In the actual manufacturing process, if the above-mentioned middle dielectric isolation layer is not formed before forming the source / drain region, the first fin structure, the second fin structure and the first sacrificial layer exposed outside the second mask structure can be removed by etching and other processes under the masking action of the second mask structure. Then, epitaxy and other processes are used to form the source / drain regions included in the P-type ring-gate transistor on both sides of the remaining second fin structure. Then, deposition and other processes are used to form an insulating layer on the source / drain regions included in the P-type ring-gate transistor. Next, epitaxy and other processes are used to form the source / drain regions included in the N-type ring-gate transistor on the insulating layer.
[0076] If the above-mentioned middle dielectric isolation layer has been formed before forming the source / drain region, then under the masking action of the second mask structure, the first fin structure, the second fin structure and the portion of the middle dielectric isolation layer exposed outside the second mask structure are removed by etching or other processes. Then, the formation process of the source / drain region, the insulating layer included in the P-type all-around gate transistor and the source / drain region included in the N-type all-around gate transistor can refer to the above text.
[0077] It should be noted that, in the case where the P-type gate-all-around transistor in the semiconductor device further includes an inner sidewall, after removing the portion of the second fin structure exposed outside the second mask structure, Figure 21 to Figure 24 As shown, it is also necessary to use a dry etching or wet etching process to remove the remaining side edge portions of the second sacrificial layer 26 along the length direction of the gate stack structure to form a second dielectric filling area. Figure 25 to Figure 28 As shown, deposition and etching processes are used to form inner sidewalls 18 in the second dielectric filling region. The material of the inner sidewalls 18 can be referred to above and will not be described again here.
[0078] Next, if Figure 33 to Figure 36As shown, dry etching or wet etching or other processes can be used to remove at least part of the second mask structure. Specifically, the removal range of the second mask structure can be determined according to the specific structure of the second mask structure. If the second mask structure only includes a sacrificial gate, or includes a sacrificial gate and a gate oxide layer, the second mask structure needs to be completely removed. If the second mask structure includes a sacrificial gate and a gate sidewall 19, only the sacrificial gate needs to be removed.
[0079] Next, if Figures 39 to 42 As shown, the remaining first fin structure is selectively etched to form the nanostructure 16 included in the N-type all-around gate transistor. Specifically, an alkaline solution such as TMAH can be used to selectively etch the first fin structure to release the nanostructure 16 included in the N-type all-around gate transistor. Of course, other etching solutions can be selected according to the material of the nanostructure 16 included in the N-type all-around gate transistor, and no specific limitation is made here.
[0080] It should be noted that if the material of the nanostructure included in the N-type ring-gate transistor is the same as or similar to the material of the nanostructure included in the P-type ring-gate transistor, it is necessary to form a mask material covering the remaining periphery of the second channel layer through processes such as deposition and etching to prevent the second channel layer from being affected, thereby further improving the yield of the P-type ring-gate transistor.
[0081] Next, if Figures 39 to 42 As shown, a dry etching process or a wet etching process may be used to selectively remove the remaining second sacrificial layer 26 , so that the remaining second channel layer 25 forms the nanostructure 16 included in the P-type all-around gate transistor 13 .
[0082] It should be noted that the embodiment of the present invention does not specifically limit the execution order of selectively removing the remaining second sacrificial layer and selectively etching the remaining first fin-shaped structure. The remaining first fin-shaped structure may be selectively etched first, and then the remaining second sacrificial layer may be selectively removed. Alternatively, the remaining second sacrificial layer may be selectively removed first, and then the remaining first fin-shaped structure may be selectively etched. Alternatively, when the material of the second sacrificial layer is the same as that of the first channel layer, the remaining second sacrificial layer may be selectively removed while the remaining first fin structure is selectively etched.
[0083] It should be noted that, if the above-mentioned middle dielectric isolation layer is not formed before removing at least part of the second mask structure, Fig.39 and Fig.40 As shown, a dry or wet etching process is required to remove the remaining first sacrificial layer. After removing the first sacrificial layer, a subsequent gate stack structure formation operation is performed.
[0084] Alternatively, if the above-mentioned middle dielectric isolation layer is not formed before removing at least part of the second mask structure, the following method may be used: Fig.35 and Fig.36 As shown, a dry etching or wet etching process is first used to remove the remaining first sacrificial layer, and before forming a gate stack structure, deposition and etching operations are performed, such as Fig.37 and Fig.38 As shown, a middle dielectric isolation layer 34 is formed in the space released by removing the remaining first sacrificial layer. The material of the middle dielectric isolation layer 34 can refer to the above.
[0085] If the middle dielectric isolation layer is formed before the source / drain regions are formed, it is only necessary to selectively remove the remaining second sacrificial layer and selectively etch the remaining first fin structure to perform the subsequent gate stack structure formation operation.
[0086] Next, if Figure 43 to Figure 47 As shown, atomic layer deposition and other processes can be used to form a gate stack structure 17 surrounding the nanostructure 16 included in the N-type all-around gate transistor 12; and to form a gate stack structure 17 surrounding the nanostructure 16 included in the P-type all-around gate transistor 13. The material of the gate stack structure 17 can be referred to above and will not be repeated here.
[0087] It should be noted that the above description is based on the example of an N-type gate-all-around transistor being located above a P-type gate-all-around transistor, which does not mean that an N-type gate-all-around transistor can only be located above a P-type gate-all-around transistor. In addition, the description of "under the masking effect of the same first mask structure, a wet etching or dry etching process can be used to etch the first sacrificial layer; and the semiconductor stack 22 is etched to form a second fin structure 32" is not a limitation on the order of the steps. Figure 2 , Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 , Fig.26 , Fig.28 , Fig.30 , Fig.32 , Fig.34 , Fig.36 , Fig.38 , Fig.40 , Fig.42 , Fig.44 and Fig.46As shown, when the P-type all-around gate transistor 13 is located above the N-type all-around gate transistor 12, along the thickness direction of the semiconductor substrate 11, when a semiconductor stack 22, a first sacrificial layer 23 and a first channel layer 24 are stacked and formed on the semiconductor substrate 11, the semiconductor stack 22 is located above the first channel layer 24. Next, under the masking action of the first mask structure 27, the semiconductor stack 22 is etched to form a second fin structure 32; and the first sacrificial layer 23 is etched. Next, under the masking action of the same first mask structure 27, an isotropic etching process is used to etch the first channel layer 24 to form a notch structure 28; an anisotropic etching process is used to form a fin 29 below the notch structure 28, and a passivation process is used to form a passivation layer 30 around the notch structure 28 and the fin 29; the operation is repeated until a first fin structure 31 is formed, and the number of layers of the notch structure 28 included in the first fin structure 31 is one more than the number of layers of the nanostructure 16 included in the N-type ring gate transistor 12. Next, the first mask structure 27 is removed; and the passivation layer 30 is removed. Next, an N-type ring gate transistor 12 is formed based on the first fin structure 31; and a P-type ring gate transistor 13 is formed based on the second fin structure 32.
[0088] Furthermore, when the P-type ring-gate transistor is located above the N-type ring-gate transistor, the source / drain regions included in the N-type ring-gate transistor are formed first, and then an insulating layer is formed on the source / drain regions included in the N-type ring-gate transistor, and then the source / drain regions included in the P-type ring-gate transistor are formed on the insulating layer.
[0089] As for when the P-type ring-gate transistor is located above the N-type ring-gate transistor, the execution of other operations can refer to the previous text and will not be repeated here.
[0090] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.
[0091] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.
[0092] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.
Claims
1. A semiconductor device, characterized in that: include: A semiconductor substrate, an N-type gate-all-around transistor, a P-type gate-all-around transistor and an insulating layer; The N-type all-around gate transistor and the P-type all-around gate transistor are spaced apart and distributed along the thickness direction of the semiconductor substrate; the insulating layer is arranged between the source / drain region included in the N-type all-around gate transistor and the source / drain region included in the P-type all-around gate transistor; Among them, the crystal orientation of the nanostructure in the channel region included in the N-type ring-gate transistor is [111]; the crystal orientation of the nanostructure in the channel region included in the P-type ring-gate transistor is [110]; the channel region included in the N-type ring-gate transistor is self-aligned with the channel region included in the P-type ring-gate transistor.
2. The semiconductor device according to claim 1, wherein: The material of the channel region included in the N-type all-around gate transistor is different from the material of the channel region included in the P-type all-around gate transistor; And / or, the carrier mobility corresponding to the channel region material included in the P-type all-around gate transistor is greater than the carrier mobility corresponding to the channel region material included in the N-type all-around gate transistor.
3. The semiconductor device according to claim 1, wherein: The material of the channel region of the N-type gate-all-around transistor includes silicon; And / or, the material of the channel region included in the P-type all-around gate transistor includes silicon germanium or germanium.
4. The semiconductor device according to claim 1, wherein: The source / drain regions included in the N-type all-around gate transistor are respectively in direct contact with the gate stack structure included in the N-type all-around gate transistor; And / or, the P-type gate-all-around transistor further includes an inner sidewall; the inner sidewall is located between the source / drain region and the gate stack structure included in the P-type gate-all-around transistor.
5. The semiconductor device according to claim 1, wherein: The material and / or thickness of the gate stack structure included in the N-type all-around gate transistor are respectively the same as the material and / or thickness of the gate stack structure included in the P-type all-around gate transistor.
6. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate; forming an N-type all-around gate transistor, a P-type all-around gate transistor and an insulating layer on the semiconductor substrate; The N-type all-around gate transistor and the P-type all-around gate transistor are spaced apart and distributed along the thickness direction of the semiconductor substrate; the insulating layer is arranged between the source / drain region included in the N-type all-around gate transistor and the source / drain region included in the P-type all-around gate transistor; Among them, the crystal orientation of the nanostructure in the channel region included in the N-type ring-gate transistor is [111]; the crystal orientation of the nanostructure in the channel region included in the P-type ring-gate transistor is [110]; the channel region included in the N-type ring-gate transistor is self-aligned with the channel region included in the P-type ring-gate transistor.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: The method of forming an N-type gate-all-around transistor, a P-type gate-all-around transistor and an insulating layer on the semiconductor substrate comprises: A semiconductor stack, a first sacrificial layer and a first channel layer are stacked on the semiconductor substrate along the thickness direction of the semiconductor substrate; the semiconductor stack comprises a second sacrificial layer and a second channel layer which are alternately stacked; and the film layers at the bottom layer and the top layer in the semiconductor stack are both the second sacrificial layer; Under the masking action of the first mask structure, an isotropic etching process is used to etch the first channel layer to form a notch structure; an anisotropic etching process is used to form a fin under the notch structure, and a passivation process is used to form a passivation layer around the notch structure and the fin; the operation is repeated until a first fin structure is formed, and the number of layers of the notch structure included in the first fin structure is one more than the number of layers of the nanostructure included in the N-type all-around gate transistor; Under the masking action of the same first mask structure, etching the first sacrificial layer; and etching the semiconductor stack to form a second fin structure; removing the first mask structure; and removing the passivation layer; The N-type all-around gate transistor is formed based on the first fin structure; and the P-type all-around gate transistor is formed based on the second fin structure.
8. The method for manufacturing a semiconductor device according to claim 7, wherein: The forming of the N-type gate-all-around transistor based on the first fin structure; and the forming of the P-type gate-all-around transistor based on the second fin structure, comprises: forming a second mask structure spanning the first fin structure and the second fin structure; Processing the portion of the first fin structure exposed outside the second mask structure to form a source / drain region included in an N-type all-around gate transistor; processing the portion of the second fin structure exposed outside the second mask structure to form a source / drain region included in a P-type all-around gate transistor; and forming the insulating layer between the source / drain region included in the N-type all-around gate transistor and the source / drain region included in the P-type all-around gate transistor; removing at least a portion of the second mask structure; Selectively etching the remaining first fin structure to form a nanostructure included in the N-type all-around gate transistor; Selectively removing the remaining second sacrificial layer so that the remaining second channel layer forms a nanostructure included in the P-type all-around gate transistor; A gate stack structure is formed around the periphery of the nanostructure included in the N-type all-around gate transistor; and a gate stack structure is formed around the nanostructure included in the P-type all-around gate transistor.
9. The method for manufacturing a semiconductor device according to claim 8, wherein: After removing at least a portion of the second mask structure, forming a gate stack structure surrounding the periphery of the nanostructure included in the N-type all-around gate transistor; Before forming a gate stack structure surrounding the nanostructure included in the P-type ring-gate transistor, the method for manufacturing the semiconductor device further includes: removing the remaining first sacrificial layer.
10. The method for manufacturing a semiconductor device according to claim 9, wherein: After removing the remaining first sacrificial layer, forming a gate stack structure surrounding the periphery of the nanostructure included in the N-type all-around gate transistor; Before forming a gate stack structure surrounding the nanostructure included in the P-type ring-gate transistor, the method for manufacturing the semiconductor device further includes: forming a middle dielectric isolation layer in the space released by removing the remaining first sacrificial layer.
11. The method for manufacturing a semiconductor device according to claim 8, wherein: After forming the second mask structure spanning the first fin structure and the second fin structure, and before forming the source / drain region included in the N-type all-around gate transistor and the source / drain region included in the P-type all-around gate transistor, the method for manufacturing the semiconductor device further includes: selectively removing at least a portion of the first sacrificial layer to form a dielectric filling region; forming a middle dielectric isolation layer in the dielectric filling region; The portion of the middle dielectric isolation layer exposed outside the second mask structure is removed.
12. The method for manufacturing a semiconductor device according to claim 8, wherein: The material of the second sacrificial layer is the same as that of the first channel layer. While the remaining first fin-shaped structure is selectively etched, the remaining second sacrificial layer is selectively removed.
13. The method for manufacturing a semiconductor device according to claim 8, wherein: The processing of the portion of the second fin structure exposed outside the second mask structure to form a source / drain region of the P-type gate-all-around transistor includes: removing a portion of the second fin structure exposed outside the second mask structure; Removing the remaining edge portions of the second sacrificial layer on both sides along the length direction of the gate stack structure to form a second dielectric filling region; forming an inner side wall in the second medium-filled area; The source / drain regions of the P-type gate-all-around transistor are formed on both sides of the remaining second channel layer.