Two-dimensional semiconductor in-plane integration method and device

By selectively removing the upper layer material of the stacked area of ​​the two-dimensional semiconductor material by using photochemical reactions at room temperature, high-precision preparation of two-dimensional semiconductor in-plane heterojunction is achieved, solving the problems of high-temperature process limitations and insufficient material design freedom in the prior art, and achieving low cost and high-precision integration.

CN119730378AActive Publication Date: 2025-03-28NANJING UNIV
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Patent Information

Application Number
CN202411632516.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-15
Publication Date
2025-03-28
Estimated Expiration
2044-11-15

AI Technical Summary

Technical Problem

When preparing two-dimensional semiconductor in-plane heterojunctions, the prior art faces the problems of high-temperature process limitations, material design freedom and processing accuracy, and it is difficult to achieve low-cost and high-precision integration.

Method used

By providing a two-dimensional semiconductor in-plane integration method, the in-plane splicing of two-dimensional materials is achieved by utilizing the differences in electron state distribution of different two-dimensional materials in the stacking region and the single-layer region, combined with a photochemical reaction, selectively removing the upper material of the stacking region. This method can be performed at room temperature, avoiding the limitations of high-temperature processes, and achieving high-precision heterojunction patterning by precisely controlling the photochemical reaction zone.

Benefits of technology

The high-precision preparation of two-dimensional semiconductor in-plane heterojunctions at room temperature is achieved, which improves the freedom of material selection and torsion angle design, avoids the limitations of high-temperature processes, and requires no additional micro-nano processing steps.

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Abstract

The invention discloses a two-dimensional semiconductor in-plane integration method and device, and the method comprises the steps: providing a first two-dimensional single-layer material, and placing the first two-dimensional single-layer material on a target substrate; partially stacking the second two-dimensional single-layer material on the first two-dimensional single-layer material to form a Van der Waals heterojunction comprising a stacking region and a single-layer region; an excitation light source of which the photon energy is greater than the luminous band gap of the first two-dimensional single-layer material and / or the second two-dimensional single-layer material is utilized, so that the van der Waals heterojunction is subjected to selective photochemical reaction, and the second two-dimensional single-layer material in the stacking region is removed through selective reaction; and the first two-dimensional single-layer material and the second two-dimensional single-layer material are integrated and spliced in the same plane. According to the two-dimensional semiconductor in-plane integration method and the two-dimensional semiconductor in-plane integration device provided by the invention, the upper-layer material in the stacking region is selectively removed by utilizing the electronic state distribution difference of different two-dimensional materials in the stacking region and the single-layer region in combination with the photochemical reaction, so that the in-plane splicing of the two-dimensional materials is realized.
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