Chip layout structure

Abstract

The invention discloses a layout structure of a chip, which comprises a high-voltage module, a plurality of first bonding pad pins are arranged on the high-voltage module, and a high-voltage electrostatic discharge circuit is arranged around the first bonding pad pins; the low-voltage module is provided with a plurality of second bonding pad pins, and a low-voltage electrostatic discharge circuit is arranged around the second bonding pad pins; a power conversion circuit is arranged around the low-voltage electrostatic discharge circuit, and the low-voltage module can be connected with a high-voltage power supply through the power conversion circuit; wherein the first bonding pad pin is packaged out of the chip / the first bonding pad pin and the second bonding pad pin are packaged out of the chip so as to be connected with a high-voltage power supply and / or a low-voltage power supply to supply power to the chip. The chip structure provided by the invention can realize multiple power supply modes, and is relatively good in compatibility and relatively low in cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip layout, and in particular relates to a chip layout structure. Background Art

[0002] In order to meet the market's demand for more power supply voltages, a chip will support more power supply modes. Therefore, a metal option method will be used in the chip to support multiple power supply modes, effectively reducing the circuit area to achieve higher integration.

[0003] In order to meet the various power supply modes of the chip, higher requirements are placed on the electrostatic discharge (ESD) circuit of the chip. Not only the ESD problem of the high-voltage version of the chip must be solved, but also the ESD problem of the low-voltage version of the chip. The ESD circuit in the chip protects the chip from damage caused by electrostatic discharge, and the area overhead is large. Especially for multi-power and multi-pin chips such as field programmable gate arrays (FPGAs), the ESD circuit area occupies a large area. The metal selection method makes the chip into multiple power supply versions, such as high-voltage version and low-voltage version, and selects a certain version for tape-out according to demand; its purpose is to reduce the area overhead of the ESD circuit. However, the chip layout differences between different power supply versions are large, which brings great difficulties to the production and manufacturing of the chip and increases the production cost.

[0004] Therefore, there is currently a lack of a chip with an ESD circuit that can simultaneously implement high voltage power supply and / or low voltage power supply. Summary of the invention

[0005] The embodiment of the present invention provides a chip layout structure, which can solve the problem that the current chip cannot realize high voltage power supply and / or low voltage power supply at the same time on the same chip structure.

[0006] An embodiment of the present invention provides a layout structure of a chip, including: A high-voltage module, wherein a plurality of first pad pins are arranged on the high-voltage module, and a high-voltage electrostatic discharge circuit is arranged around the first pad pins; A low-voltage module, wherein a plurality of second solder pads are provided on the low-voltage module, a low-voltage electrostatic discharge circuit is provided around the second solder pads; a power conversion circuit is also provided around the low-voltage electrostatic discharge circuit, and the low-voltage module is connected to a high-voltage power supply through the power conversion circuit; The first pad foot is packaged out of the chip or the first pad foot and the second pad foot are packaged out of the chip to connect a high voltage power supply and / or a low voltage power supply to power the chip.

[0007] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: according to the layout structure of the chip provided by the present invention, an electrostatic discharge circuit is arranged at the position where the low-voltage module and the high-voltage module are connected to the external power supply, and solder pads for connecting the external power supply are arranged around the electrostatic discharge circuit. By allowing the chip to connect to different solder pads according to different power supply voltages, multiple modes of power supply can be achieved, thereby improving the compatibility of the chip structure and reducing the chip manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of a chip layout structure provided by an embodiment of the present invention; Figure 2 A schematic diagram of a specific layout structure of a chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0009] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0010] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0011] It should also be understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0012] As used in the present specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]", depending on the context.

[0013] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0014] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0015] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0016] Example 1 Figure 1 The schematic diagram of the layout structure of a chip provided by an embodiment of the present invention is shown. As an example but not a limitation, see Figure 1 , the chip may include a high voltage module 1 and a low voltage module 2 .

[0017] In one possible implementation, see Figure 1 , a plurality of first pad pins P1 may be provided on the high voltage module 1, and a high voltage electrostatic discharge circuit E1 may be provided around the first pad pins P1. Similarly, a plurality of second pad pins P2 may be provided on the low voltage module 2, and a low voltage electrostatic discharge circuit E2 may be provided around the second pad pins. In addition, a power conversion circuit V2 may be provided on the low voltage module 2, and the power conversion circuit V2 may be provided around the low voltage electrostatic discharge circuit E2.

[0018] Specifically, the high-voltage electrostatic discharge circuit E1 can be used to protect other components in the high-voltage module 1 from electrostatic hazards. Correspondingly, the low-voltage electrostatic discharge circuit E2 can be used to protect other components in the low-voltage module 2 from electrostatic hazards, and the power conversion circuit V2 can be used to convert the input high-voltage power supply into the low-voltage power supply required by the low-voltage module 2.

[0019] Exemplarily, the high-voltage module 1 may include some components in the chip that require high-voltage power supply, the low-voltage module 2 may include some components in the chip that require low-voltage power supply, and the power conversion circuit V2 may be a low-voltage dropout linear regulator.

[0020] Based on the different power supplies, the first pad pin can be packaged outside the chip or the first pad pin and the second pad pin can be packaged outside the chip, and the first pad pin or the first pad pin and the second pad pin outside the chip can be led out of the chip and connected to the power supply. Specifically, the first pad pin and the high-voltage power supply and the low-voltage power supply can be connected, and the second pad pin and the low-voltage power supply can be connected to realize the power supply of the chip. When the power supplies are different, it is only necessary to package different pad pins out of the chip, and there is no need to design different chip layout structures for different power supplies; the compatibility of the chip structure can be improved, thereby reducing the chip manufacturing cost.

[0021] In an example, if the chip is powered by a high-voltage power supply, the first pad pin P1 can be packaged outside the chip, and the first pad pin P1 can be led out to connect to the high-voltage power supply.

[0022] At this time, the second pad pin P2 is idle and is packaged in the chip. The high voltage power supply can supply power to the high voltage module 1 , and the power conversion circuit V2 can convert the high voltage power supply into a low voltage power supply to supply power to the low voltage module 2 .

[0023] In another example, if the chip is powered by a low-voltage power supply, the first pad foot P1 and the second pad foot P2 can be packaged outside the chip, and the first pad foot P1 and the second pad foot P2 can be led out and connected to the low-voltage power supply.

[0024] For example, the first pad pin P1 and the second pad pin P2 can be connected and then connected to the low voltage power supply. Since the working range of the high voltage module is wide, the low voltage power supply can directly power the high voltage module 1 and the low voltage module 2, and the connection between the high voltage module 1 and the power conversion circuit V2 can be disconnected by metal option.

[0025] In another example, if the chip is powered by both a low voltage power supply and a high voltage power supply, the first pad pin P1 and the second pad pin P2 can be packaged out of the chip at the same time. The first pad pin P1 is led out to connect to the high voltage power supply, and the second pad pin P2 is led out to connect to the low voltage power supply.

[0026] At this time, the high voltage power supply supplies power to the high voltage module 1, and the low voltage power supply supplies power to the low voltage module 2. Similarly, the connection between the high voltage module 1 and the power conversion circuit V2 can be disconnected by metal option.

[0027] Therefore, the layout structure of the chip provided by the present invention only needs to select different packaging methods according to different power supply requirements of users, and can use only one chip layout structure to realize multiple modes of power supply. Therefore, the layout structure of the chip provided by the present invention has good compatibility and can reduce the manufacturing cost of the chip.

[0028] Example 2 Based on Example 1, Figure 2 Shown is a schematic diagram of a specific layout structure of a chip provided by an embodiment of the present invention.

[0029] In one possible implementation, see Figure 2 In order to provide a more uniform input current, the first pad pin P1 can be evenly surrounded by the inner boundary of the high-voltage module 1. Since the purpose of setting the high-voltage electrostatic discharge circuit E1 is to protect the high-voltage module 1 from electrostatic damage, the high-voltage electrostatic discharge circuit E1 can be set around the first pad pin P1 used to connect the power supply. In order to better realize the circuit protection function and reduce the number of high-voltage electrostatic discharge circuits in the chip, a high-voltage electrostatic discharge circuit E1 can be set between every two first pad pins P1.

[0030] Similarly, the second pad pins P2 can be evenly surrounded by the outer boundary of the low-voltage module 2, and a group of low-voltage electrostatic discharge circuits E2 and power conversion circuits V2 are arranged between every two second pad pins P2. Since the power conversion circuit V2 will provide low-voltage power to the low-voltage module when the chip is powered by a high-voltage power supply, it is also necessary to arrange a low-voltage electrostatic discharge circuit E2 around the power conversion circuit V2.

[0031] Similarly, in order to reduce the number of low-voltage electrostatic discharge circuits E2 in the chip, the power conversion circuits V2 and the low-voltage electrostatic discharge circuits E2 may be arranged alternately.

[0032] According to the layout structure of the chip provided by the present invention, an electrostatic discharge circuit is arranged at the position where the low-voltage module and the high-voltage module are connected to the external power supply, and solder pads for connecting the external power supply are arranged around the electrostatic discharge circuit. By connecting the chip to different solder pads according to different power supply voltages, multiple modes of power supply can be realized, thereby improving the compatibility of the chip structure and reducing the chip manufacturing cost.

[0033] In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

Claims

1. A chip layout structure, characterized in that: include: A high-voltage module, wherein a plurality of first pad pins are arranged on the high-voltage module, and a high-voltage electrostatic discharge circuit is arranged around the first pad pins; A low-voltage module, wherein a plurality of second solder pads are provided on the low-voltage module, a low-voltage electrostatic discharge circuit is provided around the second solder pads; a power conversion circuit is also provided around the low-voltage electrostatic discharge circuit, and the low-voltage module can be connected to a high-voltage power supply through the power conversion circuit; The first pad foot is packaged out of the chip / the first pad foot and the second pad foot are packaged out of the chip to connect a high voltage power supply and / or a low voltage power supply to power the chip.

2. The chip layout structure according to claim 1, characterized in that: The chip is powered by the high voltage power supply, and the first pad pin is packaged out of the chip; The high-voltage power supply is connected to the high-voltage module via the first solder pad pin, and the second solder pad pin is idle; The high voltage power supply supplies power to the high voltage module, and the power conversion circuit is used to convert the high voltage power supply into a low voltage power supply to supply power to the low voltage module.

3. The chip layout structure according to claim 1, characterized in that: The chip is powered by the low voltage power supply, and the first pad foot and the second pad foot are packaged out of the chip; The low voltage power supply is connected to the high voltage module via the first solder pad pin, and the low voltage power supply is connected to the low voltage module via the second solder pad pin; The low voltage power supply supplies power to the low voltage module and the high voltage module.

4. The chip layout structure according to claim 1, characterized in that: The chip is powered by the high voltage power supply and the low voltage power supply, and the first pad foot and the second pad foot are packaged out of the chip; The high voltage power supply is connected to the high voltage module via the first solder pad pin, and the low voltage power supply is connected to the low voltage module via the second solder pad pin; The high voltage power supply supplies power to the high voltage module, and the low voltage power supply supplies power to the low voltage module.

5. The chip layout structure according to claim 1, characterized in that: The first pad legs are uniformly surrounded on the inner boundary of the high-voltage module, and one high-voltage electrostatic discharge circuit is arranged between every two of the first pad legs.

6. The chip layout structure according to claim 1 or 5, characterized in that: The second pad legs are uniformly arranged around the outer boundary of the low-voltage module, and a group of the low-voltage electrostatic discharge circuit and the power conversion circuit is arranged between every two of the second pad legs.

7. The chip layout structure according to claim 6, characterized in that: The low-voltage electrostatic discharge circuit and the power conversion circuit are arranged alternately.

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