Semiconductor die, semiconductor package and method of forming same

Abstract

In an embodiment, a method includes forming a first integrated circuit die, the first integrated circuit die including: a first active device along a first substrate; a first electrostatic discharge well along the first substrate; a first bond pad over the first substrate and electrically connected to the first active device; and a first lightning conductor over the first substrate and electrically connected to the first electrostatic discharge well; forming a second integrated circuit die, the second integrated circuit die including: a second active device along a second substrate; a second electrostatic discharge well along the second substrate; a second bond pad over the second substrate and electrically coupled to the second active device; and a second lightning conductor over the second substrate and electrically connected to the second electrostatic discharge well; and bonding the first integrated circuit die to the second integrated circuit die. The embodiments of the application also relate to a semiconductor die, a semiconductor package, and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor dies, semiconductor packages, and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there has been a trend towards smaller and more creative packaging technologies for semiconductor die. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is typically capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor package, comprising: forming a first integrated circuit die, the first integrated circuit die comprising: a first active device, along a first substrate; a first electrostatic discharge well, along the first substrate; a first bonding pad, located above the first substrate and electrically connected to the first active device; and a first lightning conductor, located above the first substrate and electrically connected to the first electrostatic discharge well; forming a second integrated circuit die, the second integrated circuit die comprising: a second active device, along a second substrate; a second electrostatic discharge well, along the second substrate; a second bonding pad, located above the second substrate and electrically coupled to the second active device; and a second lightning conductor, located above the second substrate and electrically connected to the second electrostatic discharge well; and bonding the first integrated circuit die to the second integrated circuit die.

[0004] Other embodiments of the present application provide a semiconductor die, comprising: an active device along the front side of a semiconductor substrate; an electrostatic discharge well along the front side of the semiconductor substrate; an interconnect structure located above the semiconductor substrate; a dielectric layer located above the interconnect structure; a bonding pad embedded in the dielectric layer, the bonding pad being electrically connected to the active device; and an electrostatic discharge conductor embedded in the dielectric layer, the electrostatic discharge conductor being electrically connected to the electrostatic discharge well, wherein the electrostatic discharge conductor includes a protruding point farthest from the back side of the semiconductor die, wherein the electrostatic discharge conductor is along a bonding side of the semiconductor die, and wherein the bonding side faces an opposite side of the back side.

[0005] Still other embodiments of the present application provide a semiconductor package, comprising: a first active device, along a first substrate; a first electrostatic discharge well, along the first substrate; a first interconnect structure, located above the first active device and the first electrostatic discharge well; a first bonding pad, located above the first interconnect structure and electrically connected to the first active device; a first lightning conductor, located above the first interconnect structure and electrically connected to the first electrostatic discharge well; a second bonding pad, located above the first bonding pad and directly bonded to the first bonding pad; a second lightning conductor, located above the first lightning conductor and directly bonded to the first lightning conductor; a second interconnect structure, located above the second bonding pad and the second lightning conductor; a second active device, located above the second interconnect structure and electrically connected to the second bonding pad; and a second electrostatic discharge well, located above the second interconnect structure and electrically connected to the second lightning conductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1A to 1D Cross-sectional views of intermediate steps during a process for forming an integrated circuit die are shown in accordance with some embodiments.

[0008] FIG. 2A to FIG. 2D Cross-sectional views of intermediate steps during a process for forming an integrated circuit die are shown in accordance with some embodiments.

[0009] Figure 3 to Figure 4 Cross-sectional views of intermediate steps during a process for forming a semiconductor package are shown in accordance with some embodiments.

[0010] Figures 5 to 8 Cross-sectional views of intermediate steps during a process for forming a semiconductor package are shown in accordance with some embodiments.

[0011] Figures 9 to 12 Cross-sectional views of intermediate steps during a process for forming a semiconductor package are shown in accordance with some embodiments.

[0012] Fig.13 Cross-sectional views of intermediate steps during a process for forming a semiconductor package are shown in accordance with some embodiments.

[0013] Figures 14 to 18 A plan view of an integrated circuit die is shown in accordance with some embodiments.

[0014] FIG. 19A to FIG. 19D A cross-sectional view of a semiconductor package including a plurality of integrated circuit dies is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] According to some embodiments, a semiconductor package is formed by bonding a first integrated circuit die to a second integrated circuit die. The integrated circuit die may be formed with complementary lightning conductor components designed to attract electrostatic discharge during bonding and route current through the integrated circuit die along the corresponding semiconductor substrate to the electrostatic discharge well. In some embodiments, the first integrated circuit die is segmented from the wafer (e.g., kept in wafer form) before being attached to the second integrated circuit die. The segmentation process may, for example, cause electrostatic charge (e.g., positive charge) to accumulate on the first integrated circuit die. However, other manufacturing steps may cause the charge to accumulate on any one of the integrated circuit dies. As the integrated circuit dies move toward each other during the bonding process, electrostatic discharge may occur, such as between the nearest positions on each component. Therefore, the integrated circuit die includes a lightning conductor, which serves as the closest (or most electrically attractive) conductive point on each of the components. Therefore, electrostatic discharge will occur between the lightning conductors, which thereby prevents electrostatic discharge from occurring with the conductive components of the integrated circuit electrically connected to the integrated circuit die. Since the integrated circuit avoids damage or short circuit caused by electrostatic discharge, the resulting semiconductor package can be formed to have a greater yield and improved reliability. Furthermore, directing electrostatic discharge to specific locations allows fewer electrostatic discharge wells to be required within the integrated circuit of the integrated circuit die, thereby allowing more area along the semiconductor substrate to be used for active devices, vias, or other features.

[0018] Various embodiments are described below in a specific context. Specifically, a chip-on-wafer (CoW) type system on an integrated chip (SoIC) package is described. However, various embodiments may also be applicable to other types of semiconductor packaging technologies, such as integrated fan-out (InFO) packages, etc. An embodiment is discussed below in which a first integrated circuit die (e.g., in the form of a segmented die) is attached to a second integrated circuit die (e.g., in the form of a wafer). It should be understood that the first integrated circuit die can remain in wafer form, while the second integrated circuit die is in segmented die form. In addition, the first integrated circuit die and the second integrated circuit die can be attached to each other when they are both in wafer form or both in segmented die form.

[0019] Figures 1A to 12 An intermediate step of forming and bonding integrated circuit dies 50 / 150 to each other is shown, wherein each of the integrated circuit dies includes a lightning conductor for electrostatic discharge (e.g., an electrostatic discharge conductor). In particular, at least one of the integrated circuit dies 50 / 150 includes a protruding lightning conductor, while another of the integrated circuit dies 50 / 150 includes an inserted or planar lightning conductor (e.g., coplanar with the bonding pad). Figures 13 to 18Other embodiments of the integrated circuit die 50 / 150 are shown, wherein each of the integrated circuit die 50 / 150 includes a planar lightning conductor. In particular, the sub-step of the bonding process including, for example, moving the integrated circuit die 50 toward the integrated circuit die 150 also includes bending the central region of the integrated circuit die 50 toward the integrated circuit die 150. Thus, during this sub-step, the planar lightning conductor of the integrated circuit die effectively protrudes.

[0020] Figures 1A to 1D Intermediate steps in the formation of a first integrated circuit die 50 (eg, a first die) are described, including forming an integrated circuit over a substrate and forming a bonding structure and a lightning conductor structure over the integrated circuit. Figure 1A An integrated circuit of a first integrated circuit die 50 according to some embodiments is shown. The integrated circuit die 50 will be further processed and packaged into a semiconductor package. The integrated circuit die 50 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof.

[0021] The integrated circuit die 50 can be formed at a wafer level, which may include different device regions that are segmented in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 50 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52, such as doped or undoped silicon or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 52 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., Figure 1A the upward-facing surface) (sometimes referred to as the front side) and the inactive surface (e.g. Figure 1A The downward-facing surface (sometimes called the dorsal side) is the central surface of the brain.

[0022] Devices (represented by transistors) 54 may be formed at the front side of semiconductor substrate 52. Devices 54 may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interlayer dielectric (ILD) 56 is located over the front side of semiconductor substrate 52. ILD 56 surrounds device 54 and may cover device 54. ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0023] According to various embodiments, an electrostatic discharge (ESD) well 70 (e.g., a discharge well) is formed along the semiconductor substrate 52. The ESD well 70 can be formed before, after, or during the formation of active devices. For example, the ESD well 70 can be formed by implanting a region of the semiconductor substrate 52 having a first conductivity type (e.g., p-type) at a desired depth and then implanting the region having a second conductivity type (e.g., n-type) at a smaller depth. It should be noted that the first conductivity type and the second conductivity type are opposite to each other and can be counterexamples to the above examples. In other embodiments, some of the devices 54 (e.g., field effect transistors, such as MOSFETs) can be used as ESD wells 70.

[0024] Conductive plug 58 extends through ILD 56 to electrically and physically couple device 54 and ESD well 70. For example, when device 54 is a transistor, conductive plug 58 can couple the gate and source / drain regions of the transistor. Similarly, some of conductive plug 58 can extend to ESD well 70 in substrate or to transistors that can be used as ESD well 70. Conductive plug 58 can be formed by tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc. or a combination thereof. Interconnect structure 60 is located above ILD 56 and conductive plug 58. Interconnect structure 60 interconnects device 54 to form an integrated circuit. Interconnect structure 60 can be formed by a metallization pattern in a dielectric layer on ILD 56, for example. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of interconnect structure 60 is electrically coupled to device 54 through conductive plug 58.

[0025] The first integrated circuit die 50 also includes pads 62, such as aluminum pads, that make external connections. The pads 62 are located on the active side of the first integrated circuit die 50, such as in and / or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit die 50, such as on portions of the interconnect structure 60 and the pads 62.

[0026] According to various embodiments, pads 62 include one or more pads 62E electrically connected to ESD well 70 through interconnect structure 60. Furthermore, pads 62E may be electrically isolated from the integrated circuits of integrated circuit die 50, such as from device 54. In some embodiments, a single or multiple pads 62E may be connected to multiple ESD wells 70.

[0027] In some embodiments, some of the pads 62 electrically connected to the devices 54 may be used as test pads before additional processing steps are performed. For example, the pads 62 may be probed as part of a wafer acceptance test, a circuit test, a known good die (KGD) test, etc. Probing may be performed to verify the functionality of various electrical connections within the devices 54 (e.g., active or passive devices), other electronic components, or integrated circuits. For example, probing may be performed by contacting a probe (not specifically shown) to the metal pads 62. The integrated circuit dies 50 within the wafer that pass the circuit probing test will be considered KGDs and may be used for further processing after a subsequent singulation process.

[0028] After the circuit probing test is performed, a bonding layer 82 may be formed over the pads 62 and the interconnect structure 60. The bonding layer 82 may be any material suitable for achieving dielectric-to-dielectric bonding. For example, the bonding layer 82 may include silicon oxide, silicon nitride, silicon oxynitride, etc., and the bonding layer 82 may be deposited using a suitable deposition process, such as PVD, CVD, ALD, etc.

[0029] Figures 1B to 1D The bonding pad 84 and the lightning conductor structure formed through the bonding layer 82 and the passivation film 64 are shown. The bonding pad 84 can also be used to attach the integrated circuit die 50 to another semiconductor component (see, for example, Figure 3 ). As discussed in more detail below, the lightning conductor structure can facilitate the attachment of other semiconductor components.

[0030] exist Figure 1B , an opening 74 is formed in the bonding layer 82 and the passivation film 64 to expose the pad 62 below. In some embodiments, the opening 74 can extend beyond the pad 62 to expose the upper components of the interconnect structure 60. As shown, the opening 74 can expose the pad 62 of the active device and the integrated circuit connected to the integrated circuit die 50. In contrast, the pad 62E electrically connected to the ESD well 70 can remain covered by the passivation film 64 and the bonding layer 82. The opening 74 can be patterned in the bonding layer 82 and the passivation film 64 using photolithography or any suitable method. For example, the opening 74 can be patterned with multiple photomasking steps and etching steps to form the shown shape of the opening 74.

[0031] exist Figure 1CIn the embodiment of the present invention, a bonding pad 84 is formed in the opening 74 in the bonding layer 82. The bonding pad 84 is formed to be connected to the pad 62 and / or the interconnect structure 60 externally. As shown in the figure, the bonding pad 84 can be arranged in the bonding layer 82, and the extension portion passes through the passivation film 64. The bonding pad 84 has a bonding pad portion located on the main surface of the bonding layer 82 and extending along the main surface of the bonding layer 82, and has a through-hole portion extending through the bonding layer 82 (and the passivation film 64) to physically and electrically couple the pad 62. The bonding pad 84 is formed by a material similar to that described above with respect to the interconnect structure 60 and using a similar process. Then, a planarization step can be implemented to make the surfaces of the bonding pad 84 and the bonding layer 82 substantially flush. Although the formation of the bonding pad 84 is described in the dual damascene process, the through-hole portion and the bonding pad portion of the bonding pad 84 can be formed in different processes, such as a single damascene process.

[0032] exist Figure 1D In the embodiment of the present invention, one or more openings 76 are formed through the bonding layer 82 and partially through the passivation film 64 to expose the pad 62E. The opening 76 can be patterned in the bonding layer 82 and the passivation film 64 using photolithography or any suitable method, similarly as described above in conjunction with the opening 74. For example, the formation of the opening 76 can include a single photomasking and etching step. As discussed in more detail below, the opening 76 together with the pad 62E below can form a lightning conductor (e.g., an inserted lightning conductor).

[0033] In some embodiments, a singulation process is performed to separate the integrated circuit die 50 from other integrated circuit dies 50 within the wafer. The singulated integrated circuit die 50 (e.g., the KGD in the integrated circuit die 50) will be attached to other semiconductor components, as discussed in more detail below. In some embodiments, the integrated circuit die 50 can remain in wafer form and be attached to other semiconductor components in die or wafer form.

[0034] FIG. 2A to FIG. 2D Intermediate steps in the formation of a second integrated circuit die 150 (eg, a second die) are described, including forming an integrated circuit over a substrate and forming a bonding structure and a lightning conductor structure over the integrated circuit. Figure 2AAn integrated circuit of an integrated circuit die 150 according to some embodiments is shown. The integrated circuit die 150 will be packaged together with the integrated circuit die 50 in subsequent processing to form a semiconductor package. The integrated circuit die 150 can be a logic die (e.g., a CPU, a GPU, a SoC, an application processor (AP), a microcontroller, etc.), a memory die (e.g., a DRAM die, an SRAM die, etc.), a power management die (e.g., a PMIC die), a radio frequency (RF) die, a sensor die, a MEMS die, a signal processing die (e.g., a DSP die), a front-end die (e.g., an AFE die), etc., or a combination thereof. In some embodiments, the integrated circuit die 150 is of the same type as the integrated circuit die 50. In other embodiments, the integrated circuit die 150 is a memory die and the integrated circuit die 50 is a logic die, or vice versa. Any suitable combination can be used.

[0035] The illustrated components of integrated circuit die 150 may be similar to the illustrated components of integrated circuit die 50. Thus, the components of integrated circuit die 150 may be labeled with the same reference numerals, albeit with a reference numeral "1" in the hundreds place. Similarly, like integrated circuit die 50, integrated circuit die 150 may undergo a circuit probing test to identify a known good die (KGD). In embodiments where integrated circuit die 150 remains in wafer form during attachment of integrated circuit die 50, a dummy die or integrated circuit die 50 that does not pass the circuit probing test may be attached to an integrated circuit die 150 that also does not pass the circuit probing test. After the circuit probing test is performed, an additional passivation film 164 (if desired) and a bonding layer 182 may be formed over the passivation film 164.

[0036] exist Figure 2B In the embodiment, an opening 174 is formed through the bonding layer 182 and the passivation layer 164 to expose the pad 162, similarly as described above in conjunction with the opening 74 (see Figure 1B ). For example, opening 174 may be formed by one or more patterning and etching steps. It should be noted that opening 174E exposes pad 162E (eg, electrically connected to ESD well 170).

[0037] exist Figure 2C In the embodiment, a bonding pad 184 is formed in the opening 174, similarly as described above in conjunction with the bonding pad 84 (see Figure 1C ). It should be noted that the bonding pad 184E is formed in the opening 174E, and thus the bonding pad 184E is electrically connected to the ESD well 170. The planarization process may be performed so that the bonding pad 184 and the bonding layer 182 are substantially coplanar within process variations.

[0038] exist Figure 2DIn the embodiment of the present invention, a column 186 is formed on the bonding pad 184E, while the other bonding pads 184 remain without the column 186. For example, a mask (not specifically shown) can be formed and patterned above the integrated circuit die 150 to have an opening above the bonding pad 184E. Then, a conductive material can be deposited in the opening, and the mask is removed thereafter. In some embodiments, the column 186 can be solder-free and have a substantially vertical sidewall. In addition, a metal capping layer can be formed on the top of the column 186. The metal capping layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and can be formed by a plating process. According to various embodiments, the height of the column 186 is less than or equal to the depth of the opening 76. The bonding pad 184E and the column 186 can form a lightning conductor (e.g., a protruding lightning conductor) together. In the bonding step discussed below, the protruding lightning conductor corresponds to the inserted lightning conductor (e.g., opening 76 and pad 62E).

[0039] Figure 3 to Figure 4 A cross-sectional view of an intermediate step during attaching an integrated circuit die 50 to an integrated circuit die 150 to form a semiconductor package is shown. According to various embodiments, the integrated circuit die 150 remains in wafer form for attachment to the integrated circuit die 50. Although one integrated circuit die 50 is shown, more than one integrated circuit die 50 may be attached to form a semiconductor package.

[0040] For example, the integrated circuit die 50A is bonded to the integrated circuit die 150A via the bonding pad 84 / 184 and the bonding layer 82 / 182. Any of the integrated circuit die 50A / 150A can be a logic device or a memory device as described above. In some embodiments, the integrated circuit die 50A / 150A can be a die of the same type, such as a SoC die. The integrated circuit die 50A / 150A can be formed in a process of the same technology node, or can be formed in a process of a different technology node. For example, the integrated circuit die 150A can have a more advanced process node than the integrated circuit die 50A, and vice versa. Other combinations of integrated circuit die 50A / 150A can be utilized.

[0041] The integrated circuit die 50A is bonded to the integrated circuit die 150A, for example, in a dielectric-to-dielectric and metal-to-metal bonding configuration. The integrated circuit die 50A is arranged face-down so that the front side of the integrated circuit die 50A faces the front side of the integrated circuit die 150A. The bonding layer 82 of the integrated circuit die 50A can be directly bonded to the bonding layer 182 of the integrated circuit die 150A, and the bonding pad 84 of the integrated circuit die 50A can be directly bonded to the bonding pad 184 of the integrated circuit die 150A. In an embodiment, the bonding between the bonding layer 82 and the bonding layer 182 is a dielectric-to-dielectric (e.g., oxide-to-oxide) bonding, etc. The bonding process also directly bonds the bonding pad 84 to the bonding pad 184 by direct metal-to-metal bonding. Therefore, the electrical connection between the integrated circuit die 50A and the integrated circuit die 150A is provided by the physical and electrical connection of the bonding pad 84 and the bonding pad 184. In some embodiments, the interface also includes a dielectric-to-metal interface between the integrated circuit dies 50A / 150A (eg, where the bond pads 84 and the bond pads 184 are not perfectly aligned and / or have different widths).

[0042] Still reference Figure 3 and Figure 4 The bonding process begins by applying a surface treatment to one or both of the respective bonding layers 82 / 182. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or both of the bonding layers 82 / 182.

[0043] The bonding process can then proceed to align the bonding pads 84 of the integrated circuit die 50A with the bonding pads 184 of the integrated circuit die 150A. The integrated circuit die 50A can first be fixed to a chuck (not specifically shown) using a vacuum or suitable means. When the integrated circuit dies 50A / 150A are aligned, the bonding pads 84 can overlap with the corresponding bonding pads 184. After alignment, the integrated circuit dies 50A / 150A are moved toward each other (e.g., the integrated circuit die 50A moves downward toward the integrated circuit die 150).

[0044] As the integrated circuit dies 50A / 150A move closer to each other, electrostatic charge on one or both may cause a discharge between the two components. Electrostatic charge may have accumulated during previous processing steps, such as during the singulation of the integrated circuit die 50A. For example, the singulation process may cause positive charge to accumulate on the integrated circuit die 50A, which may discharge when placed in close proximity to the integrated circuit die 150A, which may have a negative or neutral charge.

[0045] Pillar 186 can be used as a lightning conductor with pad 62E to route electrostatic discharge to ESD well 170 of integrated circuit die 150A and ESD well 70 of integrated circuit die 50A. Similarly, pad 62E together with opening 76 can also be used as a lightning conductor for electrostatic discharge. As integrated circuit die 50A / 150A move closer and eventually make physical contact with each other, pillar 186 fits within opening 76. Therefore, when integrated circuit die 50A is bonded to integrated circuit die 150A, bonding layer 82 / 182 and bonding pad 84 / 184 can form a seamless interface.

[0046] Bonding includes a pre-bonding step during which the integrated circuit die 50A is placed in contact with the bonding layer 182 and the bonding pads 184. In some embodiments, the vacuum or other means of securing the integrated circuit die 50A to the chuck can be adjusted so that the central region 51 of the integrated circuit die 50A bends outward (e.g., downward as shown) toward the integrated circuit die 150A (see, e.g., Fig.13 ). Additionally or alternatively, the pins can be pressed against the back side of the integrated circuit die 50A so as to bend toward the integrated circuit die 150A. Pre-bonding can be performed at room temperature (e.g., between about 21°C and about 25°C). The bonding process continues with annealing, for example, at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, so that the metal (e.g., copper) of the bonding pad 84 and the metal (e.g., copper) of the bonding pad 184 diffuse into each other and thereby form a direct metal-to-metal bond. In other embodiments, other direct bonding processes can be used (e.g., using adhesives, polymer-to-polymer bonding, etc.). Notably, the integrated circuit die 50A is bonded to the integrated circuit die 150A without using a solder connection (e.g., microbumps, etc.).

[0047] As discussed above, the height of post 186 can be the same as or less than the depth of opening 76. In some embodiments, after the bonding process, post 186 is in physical contact with pad 62E. Therefore, ESD trap 70 remains electrically connected to ESD trap 170 to continue to help charge balance (if necessary). In addition, because post 186 may not completely fill opening 76, the gap around post 186 may have an annular shape. In the embodiment where the height of post 186 is less than the depth of opening 76, after the bonding process, post 186 remains separated from pad 62E by the gap. The gap can insulate ESD trap 70 / 170 without direct electrical connection, and if necessary, post 186 and pad 62E can continue to provide electrostatic discharge benefits. In addition, the gap in opening 76 and around post 186 can have a dome shape.

[0048] After the attachment process, the semiconductor package may undergo further processing (not specifically shown). For example, gap fill material may be formed over and between adjacent integrated circuit dies 50A, additional semiconductor components may be attached to the semiconductor package, external connectors may be formed, and / or the semiconductor package may be attached to a package substrate. At any stage, the structure may undergo additional testing (e.g., thermal cycle testing).

[0049] Figures 5 to 8 The formation of another semiconductor package according to various embodiments is shown. The formation of the semiconductor package includes forming integrated circuit die 50B / 150B and attaching them to each other, similarly as described above, unless otherwise specified. In particular, integrated circuit die 150B is formed to include solder balls that serve as lightning conductors during the attachment of integrated circuit die 50B to integrated circuit die 150B.

[0050] exist Figure 5 , the integrated circuit die 50B is formed to include most of the same components as the integrated circuit die 50A described above (see Figures 1A to 1D ). However, instead of forming opening 76 above pad 62E, opening 74E is formed above pad 62E, in which bonding pad 84E (e.g., electrically connected to ESD well 70) is formed. Opening 74E and bonding pad 84E are formed simultaneously with other openings 74 and bonding pad 84, similarly as described above. Therefore, the formation of integrated circuit die 50B can include fewer steps than the formation of integrated circuit die 50A. In some embodiments, integrated circuit die 50B is then separated from the wafer. As discussed above, the separation process can contribute to the accumulation of electrostatic charge on integrated circuit die 50B. Bonding pad 84E can form a planar lightning conductor.

[0051] exist Figure 6 1, the integrated circuit die 150B is formed to include most of the same components as the integrated circuit die 150A described above (see FIG. 2A to FIG. 2D ). However, solder ball 188 (eg, instead of post 186) is deposited on bonding pad 184E (eg, which is electrically connected to ESD well 170). In a subsequent attachment process (see Figures 7 and 8 ), the solder balls 188 will act as lightning conductors to facilitate electrostatic discharge between the integrated circuit dies 50B / 150B.

[0052] In some embodiments, a mask (not specifically shown) may be formed or placed over the integrated circuit die 150B, and solder balls 188 may be deposited onto the bonding pads 184E through openings in the mask. In some embodiments, solder balls 188 may be deposited onto the bonding pads 184E without the use of a mask. Solder balls 188 may be formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Optionally, once a solder layer has been formed on the structure, a reflow may be implemented to shape the material into a desired bump shape. The bonding pads 184E together with the solder balls 188 may form a protruding lightning conductor.

[0053] Figures 7 and 8 A cross-sectional view of an intermediate step during attaching an integrated circuit die 50B to an integrated circuit die 150B is shown. According to various embodiments, the integrated circuit die 150B remains in wafer form for attachment to an integrated circuit die 50B (e.g., a singulated die). Although one integrated circuit die 50B is shown, more than one integrated circuit die 50B may be attached to form a semiconductor package.

[0054] For example, the integrated circuit die 50B is bonded to the integrated circuit die 150B via the bonding pad 84 / 184 and the bonding layer 82 / 182. Any of the integrated circuit die 50B / 150B can be a logic device or a memory device as described above. In some embodiments, the integrated circuit die 50B / 150B can be a die of the same type, such as a SoC die. The integrated circuit die 50B / 150B can be formed in a process of the same technology node, or can be formed in a process of a different technology node. For example, the integrated circuit die 150B can have a more advanced process node than the integrated circuit die 50B, and vice versa. Other combinations of integrated circuit die 50B / 150B can be utilized.

[0055] Integrated circuit die 50B is bonded to integrated circuit die 150B, for example, in a dielectric-to-dielectric and metal-to-metal bonding configuration, similarly as described above in conjunction with integrated circuit die 50A / 150A (see Figure 3 to Figure 4). The integrated circuit die 50B is arranged face down so that the front side of the integrated circuit die 50B faces the front side of the integrated circuit die 150B. The bonding layer 82 of the integrated circuit die 50B can be directly bonded to the bonding layer 182 of the integrated circuit die 150B, and the bonding pad 84 of the integrated circuit die 50B can be directly bonded to the bonding pad 184 of the integrated circuit die 150B. In an embodiment, the bonding between the bonding layer 82 and the bonding layer 182 is a dielectric to dielectric (e.g., oxide to oxide) bonding, etc. The bonding process also directly bonds the bonding pad 84 to the bonding pad 184 by direct metal to metal bonding. Therefore, the electrical connection between the integrated circuit die 50B and the integrated circuit die 150B is provided by the physical and electrical connection of the bonding pad 84 and the bonding pad 184. In some embodiments, the interface also includes a dielectric to metal interface between the integrated circuit die 50B / 150B (e.g., where the bonding pad 84 and the bonding pad 184 are not completely aligned and / or have different widths).

[0056] In addition, the interface between the integrated circuit die 50B / 150B includes a metal-to-metal bond between the solder ball 188 and the bonding pad 84E of the integrated circuit die 50B. As discussed in more detail below, during the bonding process, the solder ball 188 is reflowed, which can cause the solder ball 188 to expand when in contact with the integrated circuit die 50B. Therefore, the flat solder ball 188 is directly between the bonding pads 84E / 184E. In some embodiments, the flat solder ball 188 can expand beyond the width of the bonding pad 84E / 184E, and therefore directly between the portions of the bonding layer 82 / 182. In other embodiments, the flat solder ball 188 can remain within the width of the bonding pad 84 / 184.

[0057] Still reference Figure 7 and Figure 8, and similarly as described above, the bonding process can begin with the surface treatment and cleaning process implemented on the integrated circuit die 50B / 150B. Next, the bonding process continues by aligning the bonding pad 84 with the bonding pad 184. When the integrated circuit die 50B / 150B is aligned, the bonding pad 84 can overlap with the corresponding bonding pad 184. After alignment, the integrated circuit die 50B / 150B moves toward each other (for example, the integrated circuit die 50B moves downward toward the integrated circuit die 150B). In some embodiments, before moving the integrated circuit die 50B, heat can be applied to soften or partially reflow the solder ball 188, and the solder ball 188 can change shape or maintain substantially the same shape. As the integrated circuit die 50B / 150B moves closer to each other, the electrostatic charge on one or both may cause a discharge between the two components. As discussed above, the electrostatic charge may have accumulated during previous processing steps, such as during the segmentation of the integrated circuit die 50B.

[0058] Solder balls 188 act as lightning conductors with bonding pads 84E to route electrostatic discharge to the ESD well 170 of the integrated circuit die 150B and the ESD well 70 of the integrated circuit die 50B. Similarly, bonding pads 84E may also act as lightning conductors because the bending of the integrated circuit die 50B causes the bonding pads 84E to become the conductive component closest to the solder balls 188 of the integrated circuit die 150B during the approach. As the integrated circuit die 50B / 150B moves closer, the solder balls 188 of the integrated circuit die 150B first make physical contact with the bonding pads 84E of the integrated circuit die 50B. As the integrated circuit die 50B / 150B continues to move toward each other, the solder balls 188 flatten and spread along the bonding pads 84E / 184E. According to some embodiments, the solder balls 188 are deposited in a volume such that the flattened solder balls 188 can have a sufficiently small thickness to allow direct bonding between the bonding pads 84 / 184. Thus, the bonding layer 82 / 182 and the bonding pads 84 / 184 may form a substantially seamless interface when the integrated circuit die 50B is bonded to the integrated circuit die 150B.

[0059] The bonding includes a pre-bonding step during which the integrated circuit die 50B is placed in contact with the solder ball 188 first and in contact with the bonding layer 182 and the bonding pad 184 in the next step. The integrated circuit die 50B can be fixed to the chuck by vacuum or any suitable means, similarly as described above in conjunction with the integrated circuit die 50A. In addition, the pin can be pressed against the back side of the integrated circuit die 50B so as to bend toward the integrated circuit die 150B. The pre-bonding can be performed at room temperature (e.g., between about 21°C and about 25°C). The bonding process continues with annealing, for example, at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, so that the metal (e.g., copper) of the bonding pad 84 and the metal (e.g., copper) of the bonding pad 184 diffuse into each other, and thus form a direct metal-to-metal bond. In other embodiments, other direct bonding processes (e.g., using adhesives, polymer-to-polymer bonding, etc.) can be used. Notably, the connection of solder balls 188 to bond pads 84E / 184E assists in bonding integrated circuit die 50B to integrated circuit die 150B.

[0060] As discussed above, the volume of solder ball 188 will have an impact on the size of flat solder ball 188 after the bonding process. In some embodiments, after the bonding process, solder ball 188 is directly between and in physical contact with bonding pads 84E / 184E. Therefore, ESD well 70 remains electrically connected to ESD well 170 to continue to help charge balance (if necessary). As discussed above, flat solder ball 188 can improve the bonding of integrated circuit die 50B / 150B, with a stronger bond to each of bonding pads 84E / 184E.

[0061] After the attachment process, the semiconductor package may undergo further processing (not specifically shown). For example, gap fill material may be formed over and between adjacent integrated circuit dies 50B, additional semiconductor components may be attached to the semiconductor package, external connectors may be formed, and / or the semiconductor package may be attached to a package substrate. At any stage, the structure may undergo additional testing (e.g., thermal cycle testing).

[0062] Figures 9 to 12 1 shows the formation of another semiconductor package according to various embodiments. The formation of the semiconductor package includes forming integrated circuit die 50C / 150C and attaching them to each other, similarly as described above, unless otherwise noted. In particular, integrated circuit die 150C is formed to have a recessed bonding pad 184E and a solder column 190 formed thereon, which serves as a lightning conductor during the attachment of integrated circuit die 50C to integrated circuit die 150C.

[0063] exist Fig. 9 , the integrated circuit die 50C is formed to include most of the same components as the integrated circuit die 50A / 50B described above (see Figures 1A to 1D and Figure 5 ). However, instead of forming opening 76 above pad 62E, opening 74E is formed above pad 62E, in which bonding pad 84E (e.g., electrically connected to ESD well 70) is formed. Opening 74E and bonding pad 84E are formed simultaneously with other openings 74 and bonding pad 84, similarly as described above. Therefore, the formation of integrated circuit die 50C can include fewer steps than the formation of integrated circuit die 50A. In some embodiments, integrated circuit die 50C is then separated from the wafer. As discussed above, the separation process can contribute to the accumulation of electrostatic charge on integrated circuit die 50C. Bonding pad 84E can form a planar lightning conductor.

[0064] exist Fig.10 1, the integrated circuit die 150C is formed to include most of the same components as the integrated circuit die 150A / 150B described above (see FIG. 2A to FIG. 2D and Figure 6 ). According to the present embodiment, the formation of the bonding pad 184 is adjusted to form a bonding pad 184E that is recessed compared to the other bonding pads 184 (e.g., electrically connected to the ESD well 170). Then, the solder column 190 is deposited onto the recessed bonding pad 184E. In a subsequent attachment process (see Figure 11 to Figure 12 ), the solder column 190 will act as a lightning conductor to promote electrostatic discharge between the integrated circuit tube core 50C / 150C.

[0065] In some embodiments, the formation of bonding pad 184 is adjusted to form bonding pad 184E that is recessed from bonding layer 182, while other bonding pads 184 are substantially flush with bonding layer 182. For example, the upper surface of recessed bonding pad 184E can have a dish or bowl shape. In some embodiments, this is achieved by forming the bonding pad portion of bonding pad 184E to have a different size than the bonding pad portion of other bonding pads 184. For example, when forming opening 174 (see Figure 2B ), opening 174E exposing pad 162E may be patterned to have a larger volume than other openings 174 exposing other pads 162 (e.g., by having a larger width or by increasing other dimensions of the shape of opening 174E). Then, conductive material for bonding pad 184 may be deposited in opening 174 (and opening 174E). Deposition may be stopped when opening 174 is filled and when opening 174E is partially filled. The remaining unfilled portion of opening 174E becomes recess 174R.

[0066] In forming the opening 174E (see Figure 2B ), a solder column 190 is formed on the recessed bonding pad 184E. For example, a mask or sacrificial material (not specifically shown) may be placed above the integrated circuit die 150C, and the solder column 190 may be deposited onto the recessed bonding pad 184E through an opening in the mask or sacrificial material. In an embodiment with a sacrificial material, the sacrificial material may be patterned to form an opening, and then the sacrificial material may be removed after the solder column 190 is deposited using a suitable method. In some embodiments, the solder column 190 is formed by sputtering, printing, electroplating, chemical plating, CVD, etc. As shown, the resulting solder column 190 may have substantially straight and vertical sidewalls. The bonding pad 184E and the solder column 190 together may form a protruding lightning conductor.

[0067] Figure 11 to Figure 12 A cross-sectional view of an intermediate step during attaching an integrated circuit die 50C to an integrated circuit die 150C is shown. According to various embodiments, the integrated circuit die 150C remains in wafer form for attachment to an integrated circuit die 50C (e.g., a singulated die). Although one integrated circuit die 50C is shown, more than one integrated circuit die 50C may be attached to form a semiconductor package.

[0068] For example, the integrated circuit die 50C is bonded to the integrated circuit die 150C via the bonding pad 84 / 184 and the bonding layer 82 / 182. Any of the integrated circuit die 50C / 150C may be a logic device or a memory device as described above. In some embodiments, the integrated circuit die 50C / 150C may be a die of the same type, such as a SoC die. The integrated circuit die 50C / 150C may be formed in a process of the same technology node, or may be formed in a process of a different technology node. For example, the integrated circuit die 150C may have a more advanced process node than the integrated circuit die 50C, and vice versa. Other combinations of integrated circuit die 50C / 150C may be utilized.

[0069] Integrated circuit die 50C is bonded to integrated circuit die 150C, for example, in a dielectric-to-dielectric and metal-to-metal bonding configuration, similarly as described above in conjunction with integrated circuit die 50A / 150A (see Figure 3 to Figure 4). The integrated circuit die 50C is arranged face down so that the front side of the integrated circuit die 50C faces the front side of the integrated circuit die 150C. The bonding layer 82 of the integrated circuit die 50C can be directly bonded to the bonding layer 182 of the integrated circuit die 150C, and the bonding pad 84 of the integrated circuit die 50C can be directly bonded to the bonding pad 184 of the integrated circuit die 150C. In an embodiment, the bonding between the bonding layer 82 and the bonding layer 182 is a dielectric to dielectric (e.g., oxide to oxide) bonding, etc. The bonding process also directly bonds the bonding pad 84 to the bonding pad 184 by direct metal to metal bonding. Therefore, the electrical connection between the integrated circuit die 50C and the integrated circuit die 150C is provided by the physical and electrical connection of the bonding pad 84 and the bonding pad 184. In some embodiments, the interface also includes a dielectric to metal interface between the integrated circuit die 50C / 150C (e.g., where the bonding pad 84 and the bonding pad 184 are not completely aligned and / or have different widths).

[0070] In addition, the interface between the integrated circuit die 50C / 150C includes a metal-to-metal bond between the solder column 190 and the bonding pad 84E of the integrated circuit die 50C. As discussed in more detail below, during the bonding process, the solder column 190 is reflowed, which can cause the solder column 190 to expand when in contact with the integrated circuit die 50C. Therefore, the flat solder column 190 is directly between the bonding pads 84 / 184. In some embodiments, the flat solder column 190 can fill the groove 174R above the bonding pad 184E, and thus fill the area directly between the bonding pads 84E / 184E. For example, the flat solder column 190 can remain in the area, or can expand further than the bonding pad 84 / 184, and thus directly between the parts of the bonding layer 82 / 182. In other embodiments, the flat solder column 190 can partially fill the area, thereby leaving one or more gaps between the bonding pads 84E / 184E.

[0071] Still reference Fig.11 and Fig.12, and similarly as described above, the bonding process can begin with the surface treatment and cleaning process implemented on the integrated circuit die 50C / 150C. Next, the bonding process continues by aligning the bonding pad 84 with the bonding pad 184. When the integrated circuit die 50C / 150C is aligned, the bonding pad 84 can overlap with the corresponding bonding pad 184. After alignment, the integrated circuit die 50C / 150C moves toward each other (for example, the integrated circuit die 50C moves downward toward the integrated circuit die 150C). In some embodiments, before moving the integrated circuit die 50C, heat can be applied to soften or partially reflow the solder column 190, and the solder column 190 can change shape or maintain substantially the same shape. As the integrated circuit die 50C / 150C moves closer to each other, the electrostatic charge on one or both may cause a discharge between the two components. As discussed above, the electrostatic charge may have accumulated during previous processing steps, such as during the segmentation of the integrated circuit die 50C.

[0072] The solder pillars 190 act as lightning conductors with the bonding pads 84E to route electrostatic discharge to the ESD wells 170 of the integrated circuit die 150C and the ESD wells 70 of the integrated circuit die 50C. Similarly, the bonding pads 84E may also act as lightning conductors because the bending of the integrated circuit die 50C causes the bonding pads 84E to become the closest conductive component to the solder pillars 190 of the integrated circuit die 150C during the approach. As the integrated circuit die 50C / 150C moves closer, the solder pillars 190 of the integrated circuit die 150C first make physical contact with the bonding pads 84E of the integrated circuit die 50C. As the integrated circuit die 50C / 150C continues to move toward each other, the solder pillars 190 flatten and spread along the bonding pads 84E / 184E. According to some embodiments, the solder pillars 190 have a volume that is substantially the same as the volume of the recesses 174R, and therefore, after the bonding process is completed, the recesses 174R are filled without excess. Thus, when the integrated circuit die 50C is bonded to the integrated circuit die 150C, the bonding layer 82 / 182 and the bonding pads 84 / 184 may form a substantially seamless interface.

[0073] The bonding includes a pre-bonding step during which the integrated circuit die 50C is placed in contact with the solder pillar 190 first and in contact with the bonding layer 182 and the bonding pad 184 in the next step. The integrated circuit die 50C can be fixed to the chuck by vacuum or any suitable means, similarly as described above in conjunction with the integrated circuit die 50A / 50B. In addition, the pin can be pressed against the back side of the integrated circuit die 50C so as to bend toward the integrated circuit die 150C. The pre-bonding can be performed at room temperature (e.g., between about 21°C and about 25°C). The bonding process continues with annealing, for example, at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, so that the metal (e.g., copper) of the bonding pad 84 and the metal (e.g., copper) of the bonding pad 184 diffuse into each other, and thus form a direct metal-to-metal bond. In other embodiments, other direct bonding processes (e.g., using adhesives, polymer-to-polymer bonding, etc.) can be used. Notably, the connection of solder pillars 190 to bond pads 84E / 184E assists in bonding integrated circuit die 50C to integrated circuit die 150C.

[0074] As discussed above, the solder column 190 can be deposited so that the flat solder column 190 fills the dish shape (e.g., groove 174R) of the bonding pad 184E without excessive volume. In other embodiments, the flat solder column 190 partially fills or overfills the dish shape of the bonding pad 184E. In any case, after the bonding process, the flat solder column 190 is directly between two of the bonding pads 84E / 184E and can be in physical contact with two of the bonding pads 84E / 184E. Therefore, the ESD well 70 remains electrically connected to the ESD well 170 to continue to help charge balance (if necessary). As discussed above, the flat solder column 190 can improve the bonding of the integrated circuit die 50C / 150C, with each of the bonding pads 84E / 184E having a stronger bond.

[0075] After the attachment process, the semiconductor package may undergo further processing (not specifically shown). For example, gap fill material may be formed over and between adjacent integrated circuit dies 50C, additional semiconductor components may be attached to the semiconductor package, external connectors may be formed, and / or the semiconductor package may be attached to a package substrate. At any stage, the structure may undergo additional testing (e.g., thermal cycle testing).

[0076] Figures 13 to 18An embodiment is shown in which the bonding pad 84E / 184E is used as a lightning conductor to provide the electrostatic discharge benefits described above. For example, the integrated circuit die 50D / 150D is formed to include a bonding pad 84E / 184E electrically connected to the corresponding ESD well 70 / 170 without forming a conductive column 186, a solder ball 188, or a solder column 190 thereon. Therefore, the bonding pad 84E / 184E can be referred to as a planar lightning conductor. As discussed in more detail below, bending of the integrated circuit die 50D can be caused so that the bonding pad 84E effectively protrudes from the integrated circuit die 50D.

[0077] Fig.13 A cross-sectional view of an intermediate stage of bonding the integrated circuit die 50D to the integrated circuit die 150D is shown. The integrated circuit die 50D / 150D is manufactured, similarly as described above, until the bonding pads 84 / 184 (e.g., including the bonding pads 84E / 184E) are formed. As discussed above, during the bonding substep of moving the integrated circuit die 50D, the integrated circuit die 50D can be fixed to the chuck (not specifically shown) while moving toward the integrated circuit die 150D. In addition, the pin 192 can press the back side of the integrated circuit die 50D so that it bends toward the integrated circuit die 150D during the approach. Therefore, before the components are in physical contact with each other, the central area 51 (e.g., the bending area) of the integrated circuit die 50D is closest to the integrated circuit die 150D. Similarly as discussed above, when the components are close enough to each other, the electrostatic charge that has accumulated on either or both components can be discharged between the integrated circuit die 50D / 150D. According to the present embodiment, electrostatic discharge occurs between bonding pads 84E / 184E located in corresponding central regions 51 of the integrated circuit die 50D / 150D (e.g., central region 51 of the integrated circuit die 50D and a corresponding region of the integrated circuit die 150D) or having a portion located in corresponding central region 51 of the integrated circuit die 50D / 150D.

[0078] Figures 14 to 18 A plan view of the integrated circuit die 50D / 150D is provided to illustrate various layouts (e.g., shapes, sizes, and locations) of the bonding pads 84E / 184E according to various embodiments. The various layouts are designed so that at least one bonding pad 84E or a portion of at least one bonding pad 84E is located in the bend region of the integrated circuit die 50D. In some embodiments, a dummy bonding pad 84D / 184D may be formed adjacent to the bonding pad 84E / 184E for structural integrity and to provide a buffer region between the bonding pad 84E / 184E and other bonding pads 84 / 184 electrically connected to their corresponding integrated circuits.

[0079] Fig.14A plan view of a first exemplary integrated circuit die 50D / 150D group having a layout for directing electrostatic discharge to a bonding pad 84E / 184E in accordance with some embodiments is shown. For example, the integrated circuit die 50D can include a single bonding pad 84E located in the center region 51. As discussed above, as the integrated circuit die 50D moves toward the integrated circuit die 150D, the center region 51 can bend outward. In addition, the integrated circuit die 150D can include a single corresponding bonding pad 184E that is aligned with the bonding pad 84E during and after the bonding process. Fig.13 In the bonding sub-step, the closest point to the integrated circuit die 50D / 150D is the bonding pad 84E / 184E. Since it includes conductive material and is electrically connected to the ESD well 70 / 170, the bonding pad 84E / 184E acts as a lightning conductor to discharge electrostatic charge that may have accumulated on either or both of the integrated circuit dies 50D / 150D.

[0080] As shown, the bonding pad 84E / 184E can have a larger width than other bonding pads 84 / 184 (e.g., electrically connected to the corresponding integrated circuit) to increase the possibility of receiving any electrostatic discharge and preventing electrostatic discharge with those other bonding pads 84 / 184. The larger width better ensures that this benefit can be achieved regardless of whether the integrated circuit die 50D / 150D is aligned or misaligned. In some embodiments, the bonding pad 84E / 184E has a width substantially the same as other bonding pads 84 / 184. For example, the bonding pad 84E / 184E can have any suitable width equal to or greater than the width of other bonding pads 84 / 184, such as up to twice or three times larger. In addition, the bonding pad 84E / 184E can have the same shape as other bonding pads 84 / 184 or a different shape, including an ellipse (e.g., a circle) or a rectangle (e.g., a square).

[0081] Alternatively and as discussed above, the dummy bonding pads 84D / 184D can separate the bonding pads 84E / 184E from other bonding pads 84 / 184 (e.g., electrically connected to the corresponding integrated circuit). Therefore, the dummy bonding pads 84D / 184D help prevent static discharge to any of those other bonding pads 84 / 184. The dummy bonding pads 84D / 184D also provide additional areas for metal-to-metal bonding between the integrated circuit dies 50D / 150D. In some embodiments (not specifically shown), each of the dummy bonding pads 84D / 184D can include a continuous conductive material (e.g., a ring) around the bonding pads 84E / 184E.

[0082] Fig.15A plan view of a second exemplary integrated circuit die 50D / 150D group having a layout for directing electrostatic discharge to a bonding pad 84E / 184E in accordance with some embodiments is shown. For example, the integrated circuit die 50D can include: a single bonding pad 84E including a line segment extending across a majority of the integrated circuit die 50D and through the central region 51. In addition, the integrated circuit die 150D can include a single corresponding bonding pad 184E aligned with the bonding pad 84E during and after the bonding process. Fig.13 During the bonding sub-step, the closest point of approach of the integrated circuit die 50D / 150D includes a portion of the bonding pad 84E / 184E, which thus acts as a lightning conductor to discharge the accumulated electrostatic charge.

[0083] As shown, the bonding pad 84E / 184E can have substantially the same width as the other bonding pads 84 / 184 (e.g., electrically connected to the corresponding integrated circuit). The longer length of the bonding pad 84E / 184E achieves the benefit of increasing the likelihood of receiving any electrostatic discharge and preventing discharge from those other bonding pads 84 / 184. In some embodiments, the bonding pad 84E / 184E can have a larger width than the other bonding pads 84 / 184 to better ensure that this benefit is achieved, for example, regardless of whether the integrated circuit die 50D / 150D is aligned or misaligned. The bonding pad 84E / 184E and the other bonding pads 84 / 184 of this embodiment can have a width as described above in conjunction with Fig.14 Any of the relative widths and shapes described.

[0084] Optionally and as discussed above, for the purposes and benefits described above, the dummy bonding pad 84D / 184D can provide a buffer region between the bonding pad 84E / 184E and other bonding pads 84 / 184 (e.g., electrically connected to a corresponding integrated circuit). In some embodiments (not specifically shown), the dummy bonding pad 84D / 184D is a continuous line segment extending along each side of the bonding pad 84E / 184E and parallel thereto.

[0085] Fig.16 A plan view of a third exemplary integrated circuit die 50D / 150D group having a layout for directing electrostatic discharge to bonding pads 84E / 184E according to some embodiments is shown. For example, integrated circuit die 50D may include one or more cross shapes including, for example, a combination of Fig.15The integrated circuit die 150D is shown as extending a small portion of the width of the integrated circuit die 50D (or its bonding pad region), however the vertical line segments may extend for most or all of that width. Fig.13 In the bonding sub-step, the closest point of the integrated circuit die 50D / 150D includes a portion of the bonding pad 84E / 184E, which thus acts as a lightning conductor to discharge the accumulated electrostatic charge. The vertical line segment achieves the benefit of increasing the likelihood that the bonding pad 84E / 184E will receive any electrostatic discharge, whether aligned or misaligned, or when the warpage of either or both of the integrated circuit dies 50D / 150D causes the closest point of approach to be located outside the central area 51.

[0086] As shown, the bonding pads 84E / 184E can have substantially the same width as other bonding pads 84 / 184 (e.g., electrically connected to the corresponding integrated circuit). In some embodiments, the bonding pads 84E / 184E (e.g., the main line segments and / or the vertical line segments) can have a larger width than other bonding pads 84 / 184 to better ensure that this benefit is achieved, for example, regardless of whether the integrated circuit die 50D / 150D is aligned or misaligned. The bonding pads 84E / 184E (e.g., either or both types of segments) and other bonding pads 84 / 184 of this embodiment can have a width as described above in combination Fig.14 Any of the relative widths and shapes described.

[0087] Optionally and as discussed above, for the purposes and benefits described above, the dummy bonding pad 84D / 184D can provide a buffer area between the bonding pad 84E / 184E and other bonding pads 84 / 184 (e.g., electrically connected to the corresponding integrated circuit). As shown, the dummy bonding pad 84D / 184D can surround (e.g., roughly outline) the pattern of the bonding pad 84E / 184E. In some embodiments (not specifically shown), the dummy bonding pad 84D / 184D includes a continuous portion extending around and along the bonding pad 84E / 184E.

[0088] Fig.17A plan view of a fourth exemplary integrated circuit die 50D / 150D group having a layout for directing electrostatic discharge to the bonding pads 84E / 184E according to some embodiments is shown. For example, the integrated circuit die 50D may include a plurality of line segments extending linearly across a majority of the integrated circuit die 50D and through the central region 51, similarly as described above in conjunction with Fig.15 In some embodiments, at least one of the main line segments may also extend through the central region 51. In other embodiments, the central region 51 includes portions of two main line segments. In addition, the integrated circuit die 150D may include a corresponding bonding pad 184E having the same shape and position to align with the bonding pad 84E. The bonding pads 84E / 184E of this embodiment implement the above combination Fig.15 By using multiple line segments for the bonding pads 84E / 184E, the bond between the integrated circuit dies 50D / 150D can be stronger and more reliable even if the bonding pads 84E / 184E are warped or misaligned. For example, the bonded semiconductor package may be less prone to separation or delamination.

[0089] As shown, the bonding pad 84E / 184E can have substantially the same width as the other bonding pads 84 / 184 (e.g., electrically connected to the corresponding integrated circuit). The longer length of the bonding pad 84E / 184E achieves the benefit of increasing the likelihood of receiving any electrostatic discharge and preventing discharge from those other bonding pads 84 / 184. In some embodiments, the bonding pad 84E / 184E can have a larger width than the other bonding pads 84 / 184 to better ensure that this benefit is achieved, for example, regardless of whether the integrated circuit die 50D / 150D is aligned or misaligned. The bonding pad 84E / 184E and the other bonding pads 84 / 184 of this embodiment can have a width as described above in conjunction with Fig.14 Any of the relative widths and shapes described.

[0090] Optionally and as discussed above, for the purposes and benefits described above, the dummy bonding pads 84D / 184D can provide a buffer region between the bonding pads 84E / 184E and other bonding pads 84 / 184 (e.g., electrically connected to the corresponding integrated circuit). In some embodiments (not specifically shown), the dummy bonding pads 84D / 184D include a plurality of continuous line segments extending parallel to each side of the bonding pads 84E / 184E and along each side of the bonding pads 84E / 184E. Optionally, additional dummy bonding pads 84D / 184D can be located between the bonding pads 84E / 184E.

[0091] Fig.18A plan view of a fifth exemplary integrated circuit die 50D / 150D group having a layout for directing electrostatic discharge to bonding pads 84E / 184E according to some embodiments is shown. For example, integrated circuit die 50D may include one or more cross shapes including, for example, a combination of Fig.17 The multiple main line segments described and the combination of Fig.16 In some embodiments, at least one of the main line segments extends through the central region 51. In such embodiments, at least one of the vertical line segments may also extend through the central region 51. In other embodiments, the central region 51 includes portions of two main line segments and no vertical line segments. In addition, the integrated circuit die 150D may include a corresponding bonding pad 184E having the same shape and position to align with the bonding pad 84E. The bonding pads 84E / 184E of this embodiment implement the above combination Fig.16 By using multiple main line segments for the bonding pads 84E / 184E, the bond between the integrated circuit dies 50D / 150D can be stronger and more reliable even in the event of warping or misalignment of the bonding pads 84E / 184E. For example, the bonded semiconductor package may be less prone to separation or delamination.

[0092] As shown, the bonding pad 84E / 184E can have substantially the same width as the other bonding pads 84 / 184 (e.g., electrically connected to the corresponding integrated circuit). The longer length of the bonding pad 84E / 184E achieves the benefit of increasing the likelihood of receiving any electrostatic discharge and preventing discharge from those other bonding pads 84 / 184. In some embodiments, the bonding pad 84E / 184E can have a larger width than the other bonding pads 84 / 184 to better ensure that this benefit is achieved, for example, regardless of whether the integrated circuit die 50D / 150D is aligned or misaligned. The bonding pad 84E / 184E and the other bonding pads 84 / 184 of this embodiment can have a width as described above in conjunction with Fig.14 Any of the relative widths and shapes described.

[0093] Alternatively and as discussed above, for the purposes and benefits described above, dummy bonding pads 84D / 184D can provide a buffer region between bonding pads 84E / 184E and other bonding pads 84 / 184 (e.g., electrically connected to a corresponding integrated circuit). As shown, dummy bonding pads 84D / 184D can surround the pattern of bonding pads 84E / 184E. In some embodiments (not specifically shown), dummy bonding pads 84D / 184D include continuous portions extending around each side of bonding pads 84E / 184E and along each side of bonding pads 84E / 184E. Optionally, additional dummy bonding pads 84D / 184D can be located between bonding pads 84E / 184E.

[0094] exist Figure 8 In the embodiment, the singulation process is performed by sawing along the scribe line region between the first package region 100A and the second package region 100B, for example. The sawing separates the first package region 100A from the second package region 100B. The resulting, singulated devices 100 come from one of the first package region 100A or the second package region 100B.

[0095] exist Fig. 9 In the embodiment, each segmented first package component 100 can be mounted to a package substrate 200 using a conductive connector 124. The package substrate 200 includes a substrate core 202 and a bonding pad 204 above the substrate core 202. The substrate core 202 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, etc. can also be used. In addition, the substrate core 202 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an optional embodiment, the substrate core 202 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Optional materials for the core material include bismaleimide-triazine (BT) resin, or optionally other PCB materials or films. A build-up film such as ABF or other laminate material may be used for the substrate core 202 .

[0096] The substrate core 202 may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to generate the structural and functional requirements for the design of the device stack. The devices may be formed using any suitable method.

[0097] The substrate core 202 may also include metallization layers and through holes (not shown), wherein the bonding pads 204 are physically and / or electrically coupled to the metallization layers and through holes. The metallization layers may be formed above the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed by alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), wherein the through holes interconnect the conductive material layers and may be formed by any suitable process (such as deposition, inlay, dual inlay, etc.). In some embodiments, the substrate core 202 is substantially free of active and passive devices. Conductive connectors 210 (e.g., ball grid array (BGA) balls, etc.) may be disposed on the surface of the substrate core 202 opposite to the first package assembly 100. The conductive connectors 210 may allow the package substrate 200 to be attached to another component, such as a motherboard, a printed circuit board (PCB), etc.

[0098] In some embodiments, the conductive connectors 124 are reflowed to attach the first package component 100 to the bonding pads 204. The conductive connectors 124 electrically and / or physically couple the package substrate 200 (including the metallization layers in the substrate core 202) to the first package component 100. In some embodiments, a solder resist 206 is formed on the substrate core 202. The conductive connectors 124 can be disposed in openings in the solder resist 206 to electrically and mechanically couple to the bonding pads 204. The solder resist 206 can be used to protect areas of the substrate 202 from external damage.

[0099] The conductive connector 124 may be formed with an epoxy flux (not shown) thereon, and then at least some epoxy portions of the epoxy flux remaining after the first package component 100 is attached to the package substrate 200 are reflowed. The remaining epoxy portion may be used as an underfill to reduce stress and protect joints created by reflowing the conductive connector 124. In some embodiments, an underfill 208 surrounding the conductive connector 124 may be formed between the first package component 100 and the package substrate 200. The underfill 208 may be formed by a capillary flow process after the first package component 100 is attached, or may be formed by a suitable deposition method before the first package component 100 is attached. Thus, a package 300A including the first package component 100 and the package substrate 200 is formed.

[0100] The first package assembly 100 may be implemented in other device stacks. For example, a wafer-on-substrate structure is shown, but the first package assembly 100 may also be implemented in a package-on-package (PoP) configuration (e.g., with an integrated fan-out (InFO) configuration), a flip chip ball grid array (FCBGA) package, etc. Optionally, a lid or heat sink (not specifically shown) may be attached to the surface of the first package assembly 100 opposite to the substrate.

[0101] FIG. 19A to FIG. 19D Various packaging structures that can utilize embodiments disclosed herein are shown. In addition, multiple versions of lightning conductors can be utilized in semiconductor packages. For example, attaching the intermediate integrated circuit die 50 to the integrated circuit die 150 (e.g., wafer) can include a protruding lightning conductor structure (see Figures 1A to 12 ), while attaching the top integrated circuit die 50 to the middle integrated circuit die 50 may include a planar lightning conductor that protrudes during the bonding process until physical contact is made (see Figures 13 to 18 ). However, any suitable combination may be utilized.

[0102] Fig.19A The packaging of multiple chip layers (eg, integrated circuit die 50 ) on multiple chip layers (eg, integrated circuit die 50 ) on a wafer layer (eg, integrated circuit die 150 ) is shown. Fig.19B Multiple chip layers (eg, integrated circuit die 50 ) are shown packaged on a single chip layer (eg, integrated circuit die 50 ) on a wafer layer (eg, integrated circuit die 150 ). Fig.19C The packaging of a single chip layer (eg, integrated circuit die 50 ) on a multiple chip layer (eg, integrated circuit die 50 ) on a wafer layer (eg, integrated circuit die 150 ) is shown. Fig.19D Multiple chip layers (eg, integrated circuit die 50 ) are shown packaged on a wafer layer (eg, integrated circuit die 150 ), however any number of the multiple layers may be a single chip layer.

[0103] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.

[0104] Achieve various advantages. In particular, directing electrostatic discharge to a lightning conductor (e.g., bonding pad 84E / 184E and related conductive components, if present) prevents or reduces damage to the integrated circuit from electrostatic discharge to other conductive components (e.g., other bonding pads 84 / 184). The lightning conductor is designed so that electrostatic discharge is concentrated at or directed to the lightning conductor due to a phenomenon known as the cusp effect. Therefore, semiconductor packages can be manufactured with greater yields and with improved performance. In addition, the integrated circuit die 50 / 150 of the semiconductor package can be manufactured to have more semiconductor substrate areas dedicated to components of the integrated circuit and fewer areas dedicated to the electrostatic discharge well and the parts of the interconnect structure connected to the electrostatic discharge well. In addition, in the formation of various types of lightning conductors, the integrated circuit die 50 / 150 can be manufactured with very few or zero additional steps.

[0105] In an embodiment, a method includes: forming a first integrated circuit die, the first integrated circuit die including: a first active device, along a first substrate; a first electrostatic discharge well, along the first substrate; a first bonding pad, located above the first substrate and electrically connected to the first active device; and a first lightning conductor, located above the first substrate and electrically connected to the first electrostatic discharge well; forming a second integrated circuit die, the second integrated circuit die including: a second active device, along a second substrate; a second electrostatic discharge well, along the second substrate; a second bonding pad, located above the second substrate and electrically coupled to the second active device; and a second lightning conductor, located above the second substrate and electrically connected to the second electrostatic discharge well; and bonding the first integrated circuit die to the second integrated circuit die. In another embodiment, bonding includes: moving the first integrated circuit die toward the second integrated circuit die, generating an electrostatic discharge between the first lightning conductor and the second lightning conductor; and bonding the first bonding pad directly to the second bonding pad. In another embodiment, the method also includes singulating the first integrated circuit die from the wafer, wherein singulating includes accumulating positive charge on the first integrated circuit die. In another embodiment, during the movement of the first integrated circuit die: the pin causes the first integrated circuit die to bend toward the second integrated circuit die; and the first lightning conductor and the second lightning conductor are the closest components between the first integrated circuit die and the second integrated circuit die. In another embodiment, each of the first lightning conductor and the second lightning conductor is shaped as a line segment or a cross. In another embodiment, the first lightning conductor includes an opening in the first surface of the first integrated circuit die, wherein the opening has a depth, wherein the second lightning conductor includes a conductive component protruding from the second surface of the second integrated circuit die, and wherein the conductive component has a height. In another embodiment, the depth is greater than or equal to the height. In another embodiment, the first lightning conductor includes a third bonding pad, and wherein the second lightning conductor includes a fourth bonding pad and a conductive component disposed on the fourth bonding pad. In another embodiment, bonding the first integrated circuit die to the second integrated circuit die includes flattening the conductive component between the third bonding pad and the fourth bonding pad. In another embodiment, the fourth bonding pad has a dished shape, and wherein, after bonding the first integrated circuit die to the second integrated circuit die, the entirety of the conductive component is contained within the space between the third bonding pad and the fourth bonding pad.

[0106] In an embodiment, a semiconductor die includes: an active device along a front side of a semiconductor substrate; an electrostatic discharge well along the front side of the semiconductor substrate; an interconnect structure located above the semiconductor substrate; a dielectric layer located above the interconnect structure; a bonding pad embedded in the dielectric layer, the bonding pad being electrically connected to the active device; and an electrostatic discharge conductor embedded in the dielectric layer, the electrostatic discharge conductor being electrically connected to the electrostatic discharge well, wherein the electrostatic discharge conductor includes a protrusion farthest from the back side of the semiconductor die, wherein the electrostatic discharge conductor is along a bonding side of the semiconductor die, and wherein the bonding side faces the opposite side of the back side. In another embodiment, the electrostatic discharge conductor includes a conductive column disposed on an additional bonding pad. In another embodiment, the conductive column includes solder. In another embodiment, the additional bonding pad is a recessed bonding pad. In another embodiment, the electrostatic discharge conductor is another bonding pad having a cross shape, wherein the main axis of the cross shape extends across a majority of the semiconductor die.

[0107] In an embodiment, a semiconductor package includes: a first active device, along a first substrate; a first electrostatic discharge well, along the first substrate; a first interconnect structure, located above the first active device and the first electrostatic discharge well; a first bonding pad, located above the first interconnect structure and electrically connected to the first active device; a first lightning conductor, located above the first interconnect structure and electrically connected to the first electrostatic discharge well; a second bonding pad, located above the first bonding pad and directly bonded to the first bonding pad; a second lightning conductor, located above the first lightning conductor and directly bonded to the first lightning conductor; a second interconnect structure, located above the second bonding pad and the second lightning conductor; a second active device, located above the second interconnect structure and electrically connected to the second bonding pad; and a second electrostatic discharge well, located above the second interconnect structure and electrically connected to the second lightning conductor. In another embodiment, the first lightning conductor includes a third bonding pad and a flat solder material. In another embodiment, the third bonding pad is recessed compared to the first bonding pad. In another embodiment, each of the first lightning conductor and the second lightning conductor includes a main line segment and one or more vertical line segments. In another embodiment, each of the first lightning conductor and the second lightning conductor includes a plurality of cross shapes.

[0108] Some embodiments of the present application provide a method for forming a semiconductor package, comprising: forming a first integrated circuit die, the first integrated circuit die comprising: a first active device, along a first substrate; a first electrostatic discharge well, along the first substrate; a first bonding pad, located above the first substrate and electrically connected to the first active device; and a first lightning conductor, located above the first substrate and electrically connected to the first electrostatic discharge well; forming a second integrated circuit die, the second integrated circuit die comprising: a second active device, along a second substrate; a second electrostatic discharge well, along the second substrate; a second bonding pad, located above the second substrate and electrically coupled to the second active device; and a second lightning conductor, located above the second substrate and electrically connected to the second electrostatic discharge well; and bonding the first integrated circuit die to the second integrated circuit die.

[0109] In some embodiments, the bonding includes: moving the first integrated circuit die toward the second integrated circuit die, generating an electrostatic discharge between the first lightning conductor and the second lightning conductor; and directly bonding the first bonding pad to the second bonding pad. In some embodiments, the method also includes singulating the first integrated circuit die from the wafer, wherein the singulation includes accumulating a positive charge on the first integrated circuit die. In some embodiments, during the movement of the first integrated circuit die: the pin causes the first integrated circuit die to bend toward the second integrated circuit die; and the first lightning conductor and the second lightning conductor are the closest components between the first integrated circuit die and the second integrated circuit die. In some embodiments, each of the first lightning conductor and the second lightning conductor is shaped as a line segment or a cross. In some embodiments, the first lightning conductor includes an opening in a first surface of the first integrated circuit die, wherein the opening has a depth, wherein the second lightning conductor includes a conductive component protruding from a second surface of the second integrated circuit die, and wherein the conductive component has a height. In some embodiments, the depth is greater than or equal to the height. In some embodiments, the first lightning conductor includes a third bonding pad, and wherein the second lightning conductor includes a fourth bonding pad and a conductive component disposed on the fourth bonding pad. In some embodiments, bonding the first integrated circuit die to the second integrated circuit die includes flattening the conductive feature between the third bonding pad and the fourth bonding pad. In some embodiments, the fourth bonding pad has a dished shape, and wherein, after bonding the first integrated circuit die to the second integrated circuit die, the entirety of the conductive feature is contained within the space between the third bonding pad and the fourth bonding pad.

[0110] Other embodiments of the present application provide a semiconductor die, comprising: an active device along the front side of a semiconductor substrate; an electrostatic discharge well along the front side of the semiconductor substrate; an interconnect structure located above the semiconductor substrate; a dielectric layer located above the interconnect structure; a bonding pad embedded in the dielectric layer, the bonding pad being electrically connected to the active device; and an electrostatic discharge conductor embedded in the dielectric layer, the electrostatic discharge conductor being electrically connected to the electrostatic discharge well, wherein the electrostatic discharge conductor includes a protruding point farthest from the back side of the semiconductor die, wherein the electrostatic discharge conductor is along a bonding side of the semiconductor die, and wherein the bonding side faces an opposite side of the back side.

[0111] In some embodiments, the electrostatic discharge conductor comprises a conductive post disposed on an additional bonding pad. In some embodiments, the conductive post comprises solder. In some embodiments, the additional bonding pad is a recessed bonding pad. In some embodiments, the electrostatic discharge conductor is another bonding pad having a cross shape, wherein a major axis of the cross shape extends across a majority of the semiconductor die.

[0112] Still other embodiments of the present application provide a semiconductor package, comprising: a first active device, along a first substrate; a first electrostatic discharge well, along the first substrate; a first interconnect structure, located above the first active device and the first electrostatic discharge well; a first bonding pad, located above the first interconnect structure and electrically connected to the first active device; a first lightning conductor, located above the first interconnect structure and electrically connected to the first electrostatic discharge well; a second bonding pad, located above the first bonding pad and directly bonded to the first bonding pad; a second lightning conductor, located above the first lightning conductor and directly bonded to the first lightning conductor; a second interconnect structure, located above the second bonding pad and the second lightning conductor; a second active device, located above the second interconnect structure and electrically connected to the second bonding pad; and a second electrostatic discharge well, located above the second interconnect structure and electrically connected to the second lightning conductor.

[0113] In some embodiments, the first lightning conductor includes a third bonding pad and a flat solder material. In some embodiments, the third bonding pad is recessed compared to the first bonding pad. In some embodiments, each of the first lightning conductor and the second lightning conductor includes a main line segment and one or more vertical line segments. In some embodiments, each of the first lightning conductor and the second lightning conductor includes a plurality of cross shapes.

[0114] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor package, comprising: A first integrated circuit die is formed, the first integrated circuit die comprising: a first active device along the first substrate; a first electrostatic discharge well along the first substrate; a first bonding pad over the first substrate and electrically connected to the first active device; and a first lightning conductor, located above the first substrate and electrically connected to the first electrostatic discharge well; forming a second integrated circuit die, the second integrated circuit die comprising: a second active device along the second substrate; a second electrostatic discharge well along the second substrate; a second bonding pad over the second substrate and electrically coupled to the second active device; and a second lightning conductor located above the second substrate and electrically connected to the second electrostatic discharge well; and The first integrated circuit die is bonded to the second integrated circuit die.

2. The method according to claim 1, wherein: The joining includes: moving the first integrated circuit die toward the second integrated circuit die to generate an electrostatic discharge between the first lightning conductor and the second lightning conductor; and The first bonding pad is directly bonded to the second bonding pad.

3. The method of claim 2, further comprising singulating the first integrated circuit die from a wafer, wherein: The segmenting includes accumulating positive charge on the first integrated circuit die.

4. The method according to claim 2, wherein: During moving the first integrated circuit die: pins causing the first integrated circuit die to bend toward the second integrated circuit die; and The first lightning conductor and the second lightning conductor are proximal components between the first integrated circuit die and the second integrated circuit die.

5. The method according to claim 1, wherein: Each of the first lightning conductor and the second lightning conductor is shaped as a line segment or a cross.

6. The method according to claim 1, wherein: The first lightning conductor comprises an opening in a first surface of the first integrated circuit die, wherein the opening has a depth, wherein the second lightning conductor comprises a conductive feature protruding from a second surface of the second integrated circuit die, and wherein the conductive feature has a height.

7. The method according to claim 6, wherein: The depth is greater than or equal to the height.

8. The method according to claim 1, wherein: The first lightning conductor includes a third bonding pad, and wherein the second lightning conductor includes a fourth bonding pad and a conductive component disposed on the fourth bonding pad.

9. A semiconductor die, comprising: active devices along the front side of the semiconductor substrate; an electrostatic discharge well along the front side of the semiconductor substrate; an interconnect structure located above the semiconductor substrate; a dielectric layer located above the interconnect structure; a bonding pad embedded in the dielectric layer, the bonding pad being electrically connected to the active device; and an electrostatic discharge conductor embedded in the dielectric layer, the electrostatic discharge conductor being electrically connected to the electrostatic discharge well, wherein the electrostatic discharge conductor includes a protruding point farthest relative to the back side of the semiconductor die, wherein the electrostatic discharge conductor is along a bonding side of the semiconductor die, and wherein the bonding side faces an opposite side of the back side.

10. A semiconductor package, comprising: a first active device along the first substrate; a first electrostatic discharge well along the first substrate; a first interconnect structure located above the first active device and the first electrostatic discharge well; a first bonding pad located over the first interconnect structure and electrically connected to the first active device; a first lightning conductor located above the first interconnect structure and electrically connected to the first electrostatic discharge well; a second bonding pad located above the first bonding pad and directly bonded to the first bonding pad; a second lightning conductor, located above the first lightning conductor and directly connected to the first lightning conductor; a second interconnect structure located above the second bonding pad and the second lightning conductor; a second active device over the second interconnect structure and electrically connected to the second bonding pad; as well as A second electrostatic discharge well is located above the second interconnect structure and electrically connected to the second lightning conductor.

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