Transistor and method of manufacturing the same, electronic device

Abstract

The disclosure provides a transistor and a preparation method thereof and an electronic device, and relates to the technical field of semiconductor chips, and aims to solve the problem of slow self-destruction of protection devices. The transistor comprises a semiconductor layer, a source, a drain, a first well region, a second well region, a gate structure and a first doped part. The source and the drain are respectively located on both sides of the semiconductor layer along a first direction. The first well region and the second well region are arranged at intervals, and both extend from the surface of the semiconductor layer away from the drain to the inside of the semiconductor layer, and the first well region and the second well region have first doped ions. The gate structure is located on the side of the semiconductor layer away from the drain. The first doped part has second doped ions and comprises a first subpart and a second subpart connected in series; in the first direction, the gate structure shields the first subpart and the first well region, the gate structure exposes at least part of the second subpart, and the second subpart is connected with the source. Through the above arrangement, the local overheating of the transistor is facilitated, so that the transistor is quickly self-destroyed.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chips, and particularly relates to a transistor, a preparation method thereof, and an electronic device. BACKGROUND

[0002] In a protection circuit design in which a protection device needs to be burned out to play a protection role, the burning-out time of the protection device determines the effectiveness of the protection circuit.

[0003] In a circuit in which a MOSFET is used as a protection device, the device needs to be burned out by a short circuit to rapidly increase the current. However, in the prior art, the MOSFET as a protection device for circuit overload still needs a period of time to reach a large current, and in this period of time, there is still a risk of damaging other devices in the circuit. SUMMARY

[0004] Embodiments of the present disclosure provide a transistor, a preparation method thereof, and an electronic device, and aim to solve the problem of slow self-destruction of a protection device.

[0005] To achieve the above object, embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a transistor is provided, comprising: a semiconductor layer, a source, a drain, a first well region, a second well region, a gate structure, and a first doped part. The source and the drain are respectively located on two sides of the semiconductor layer along a first direction. The first well region and the second well region are spaced apart, and both extend from a surface of the semiconductor layer away from the drain to an interior of the semiconductor layer, and the first well region and the second well region have first doped ions. The gate structure is located on a side of the semiconductor layer away from the drain. The first doped part has second doped ions, and comprises a first sub-part and a second sub-part connected to each other, the first sub-part is located in the first well region, and the second sub-part is located in the second well region; a projection of the first sub-part on the first direction is located within a projection of the gate structure on the first direction; and a projection of the second sub-part on the first direction partially overlaps with the projection of the gate structure on the first direction. The first direction is parallel to a thickness direction of the semiconductor layer.

[0007] In some embodiments, the first well region, the second well region, the first sub-part, and the second sub-part all extend along a second direction, the first sub-part has a first end and a second end along the second direction, the second sub-part has a third end and a fourth end along the second direction, and the first end and the third end are arranged along a third direction; the second direction and the third direction are both parallel to the semiconductor layer, and the third direction intersects the second direction. The first doped part further comprises a third sub-part, the third sub-part extends along the third direction, and the third sub-part is connected to the first end and the third end.

[0008] In some embodiments, the second end and the fourth end are arranged along the third direction; and the first doped portion further comprises a fourth sub-portion connected to the second end and the fourth end.

[0009] In some embodiments, a dimension of the first sub-portion in the second direction is greater than a dimension of the second sub-portion in the second direction.

[0010] In some embodiments, the first well region comprises a plurality of sub-well regions arranged in the second direction with intervals, the first sub-portion comprises a plurality of first connecting portions and a plurality of second connecting portions connected to each other in the second direction in turn, and the first connecting portions are located in the sub-well regions.

[0011] In some embodiments, the first connecting portions have the same shape as the sub-well regions.

[0012] In some embodiments, the first connecting portions have at least one of a strip shape, a polygonal shape, a circular shape, and an elliptical shape; and / or the second connecting portions have at least one of a strip shape, a polygonal shape, a circular shape, and an elliptical shape.

[0013] In some embodiments, the first doped ions comprise B and Al, and the second doped ions comprise N, P, As, and Sb; and / or the first doped ions comprise N, P, As, and Sb, and the second doped ions comprise B and Al.

[0014] In some embodiments, a doping depth of the first doped ions in the first well region is 0.5 μm-15 μm; and / or a doping concentration of the first doped ions is 1E16 atom / cm 3 -1E18 atom / cm 3 .

[0015] In some embodiments, a doping depth of the second doped ions in the first doped portion is 0.2 μm-0.5 μm; and / or a doping concentration of the second doped ions is 1E18 atom / cm 3 -1E20 atom / cm 3 .

[0016] In some embodiments, the transistor further comprises: a third well region extending from a surface of the semiconductor layer away from the drain to an interior of the semiconductor layer, the third well region is arranged apart from the first well region, and the third well region is located on a side of the first well region away from the second well region. The first doped portion further comprises: a fifth sub-portion located in the third well region, a projection of the fifth sub-portion in the first direction partially overlaps with a projection of the gate structure in the first direction.

[0017] In some embodiments, the transistor further comprises a second doped portion, the second doped portion is located in the second well region, and the second doped portion penetrates the second sub-portion along the first direction, the second doped portion has the first doped ions.

[0018] In some embodiments, the transistor further comprises a connection structure and an isolation layer, the connection structure is located between the source and the first doped portion, and the connection structure connects the source and the first doped portion; the isolation layer is located between the gate structure and the connection structure, and between the gate structure and the source.

[0019] In another aspect, a method for manufacturing a transistor is provided, comprising: performing a doping process on a semiconductor layer to form a first well region and a second well region, the first well region and the second well region are spaced apart and both extend from a surface of the semiconductor layer to an interior of the semiconductor layer, and the first well region and the second well region have first doped ions; performing a doping process on the semiconductor layer to form a first doped portion, the first doped portion has second doped ions, and the first doped portion comprises a first sub-portion and a second sub-portion connected to each other, the first sub-portion is located in the first well region, and the second sub-portion is located in the second well region; forming a gate structure, the gate structure is located on one side of the semiconductor layer, and in a first direction, the gate structure shields the first sub-portion and the first well region, and the gate structure exposes at least part of the second sub-portion, wherein the first direction is parallel to a thickness direction of the semiconductor layer; forming a source, the source is located on a side of the semiconductor layer close to the gate structure; and forming a drain, the drain is located on a side of the semiconductor layer away from the gate structure.

[0020] In some embodiments, the forming of the gate structure comprises: forming a gate dielectric layer on one side of the semiconductor layer; forming a gate electrode layer on a side of the gate dielectric layer away from the semiconductor layer; and forming an isolation layer covering the gate electrode layer and the gate dielectric layer; the forming of the source comprises: removing part of the isolation layer to expose at least part of the second sub-portion; forming a connection structure on a side of the first doped portion away from the semiconductor layer; and depositing a conductive material to form the source, the source being in contact with the connection structure.

[0021] In yet another aspect, an electronic device is provided, the electronic device comprising the transistor as described above. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure.

[0023] Figure 1 Structure schematic of a transistor according to some embodiments Figure 1 ;

[0024] Figure 2 Current path schematic of a transistor in forward on state according to some embodiments Figure 1 ;

[0025] Figure 3 Current path schematic of a transistor in forward on state according to some embodiments Figure 2 ;

[0026] Figure 4 Schematic of a local current overdrive point of a transistor according to some embodiments Figure 1 ;

[0027] Figure 5 Schematic of a local current overdrive point of a transistor according to some embodiments Figure 2 ;

[0028] Figure 6 Structure schematic of a transistor according to some embodiments Figure 2 ;

[0029] Figure 7 Structure schematic of a transistor according to some embodiments Figure 3 ;

[0030] Figure 8 Structure schematic of a transistor according to some embodiments Figure 4 ;

[0031] Figure 9 Flowchart schematic of a method of fabricating a transistor according to some embodiments

[0032] Figure 10 Structure schematic after forming a first well region and a second well region according to some embodiments

[0033] Figure 11 Structure schematic after forming a first doped region according to some embodiments

[0034] Figure 12 Structure schematic after forming a second doped region according to some embodiments

[0035] Figure 13 Structure schematic after forming a gate structure according to some embodiments

[0036] Figure 14 Structure schematic after forming an isolation layer according to some embodiments

[0037] Figure 15A schematic diagram of a structure after forming a connection structure according to some embodiments;

[0038] Figure 16 A schematic diagram of a structure after forming a source according to some embodiments;

[0039] Figure 17 A schematic diagram of a structure after forming a drain according to some embodiments;

[0040] Figure 18 A block diagram of an electronic device according to some embodiments.

[0041] Fig. 1 shows a block diagram of an electronic device according to some embodiments. The electronic device 1000 includes a transistor 100. The transistor 100 includes a semiconductor layer 1, a source 2, a drain 3, a first well region 4, a second well region 5, a gate structure 6, a first doped portion 7, a second doped portion 9, and a connection structure 10. The semiconductor layer 1 includes a first sub-well region 41. The gate structure 6 includes a gate dielectric layer 61 and a gate layer 62. The first doped portion 7 includes a first sub-portion 71, a second sub-portion 72, a third sub-portion 73, and a fourth sub-portion 74. The first sub-portion 71 includes a first end 711, a second end 712, a first connecting portion 713, and a second connecting portion 714. The second sub-portion 72 includes a third end 721 and a fourth end 722. The third sub-portion 73 includes a fifth end 75. The connection structure 10 includes an isolation layer 11. DETAILED DESCRIPTION

[0042] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0043] In the description of the present disclosure, it should be understood that the terms “center”, “upper”, “lower”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer” and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0044] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed to be inclusive in a manner consistent with the term "include," and variations thereof (e.g., "includes" and "including"). Descriptions of some embodiments do not specify to what extent an embodiment or example might be implemented. Such omissions are for the sake of clarity only and do not imply that an embodiment or example must necessarily be limited to a certain set of features. Unless otherwise noted, modifications to an embodiment or example are possible.

[0045] The terms "first", "second", and the like, as used herein, do not imply either a relative importance or a specific order, except when explicitly discussed to do so. Thus, a feature specified as "first" can implicitly or explicitly include one or more of the same feature. In the description of embodiments of the present disclosure, the meaning of "a", "an", and "the" includes two or more, unless otherwise specified.

[0046] In describing some embodiments, it will be understood that the terms "connect," "exhibiting," "connecting," "coupling," and "coupled" are not restricted to direct physical or electrical connections, but can include indirect coupled through intervening components where the intervening components are known to function in a similar manner.

[0047] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C," and includes the following combinations: only A, only B, only C, A and B, A and C, B and C, and A and B and C.

[0048] "A and / or B" includes the following combinations: A alone, B alone, and A and B together.

[0049] The use of "adapted to" or "configured to" herein means open and inclusive language that does not foreclose devices adapted to or configured to perform additional tasks or steps.

[0050] As used herein, "approximately" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement at issue and the error (i.e., limitations of the measurement system) associated with measuring the particular quantity.

[0051] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0052] It should be noted that, in this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0053] Control modules or test modules typically include protection circuits to prevent abnormal circuit conditions (such as overvoltage, overcurrent, and short circuits) from damaging components. These circuits contain protective devices. When an abnormal circuit condition occurs, the protective devices burn out, disconnecting the circuit. These devices can include fuses, protectors, and semiconductor devices such as MOSFETs. Fuses, the most common circuit protection device, operate by melting themselves to disconnect the circuit, taking seconds to complete. Before the fuse disconnects the circuit, the excessive current can damage other components in the test module, preventing effective failure analysis.

[0054] In circuits where MOSFETs are used as protection devices, a short circuit is required to rapidly increase the current and burn out the device. However, existing MOSFETs used as circuit overload protection devices still take some time to reach their maximum current, and during this time, there is still a risk of damaging other components in the circuit.

[0055] On the other hand, in a circuit under debug test conditions, a short period of high current overload can gradually damage the device, but the temperature does not rise significantly before the device fails. Therefore, when the current in the test module is too high, the MOSFET device cannot burn out quickly, and the information about the current overload in the test module cannot be quickly transmitted, resulting in an abnormal test current that is difficult to detect. Because the MOSFET device fails to burn out in time, the overloaded current is mistaken for normal test current. Without further changing the test conditions, testing under these abnormal current conditions is not conducive to obtaining valuable test results.

[0056] In summary, in the protection circuit design in which the protection device needs to be burned out to play a protection role, the burning time of the protection device determines the effectiveness of the protection circuit. Therefore, a new protection device needs to be developed, which can quickly react to burn out under current overload.

[0057] Based on this, some embodiments of the present disclosure provide a transistor. As shown in the figure, the transistor 100 includes a semiconductor layer 1, a source 2, a drain 3, a first well region 4, a second well region 5, a gate structure 6, and a first doped part 7. Figure 1

[0058] Semiconductor is a material with electrical conductivity between conductor and insulator at room temperature. Among them, the pure semiconductor without impurities and defects has equal internal electron and hole concentration, which is called intrinsic semiconductor. The semiconductor doped with a certain amount of impurities is called impurity semiconductor or non-intrinsic semiconductor. Among them, the impurities doped in the impurity semiconductor can improve the conductivity of the intrinsic semiconductor when a certain concentration of carriers (such as holes or electrons, where the impurity semiconductor doped with impurities that provide electrons (such as 5-valence phosphorus element) is also called electron-type semiconductor or N (negative) type semiconductor, and the impurity semiconductor doped with impurities that provide holes (such as 3-valence boron element) is also called hole-type semiconductor or P (positive) type semiconductor) is provided. Generally, the greater the carrier concentration, the lower the resistivity of the semiconductor, and the better the conductivity.

[0059] In the present embodiment, the material of the semiconductor layer 1 can be silicon carbide (SiC) material, at this time, the transistor 100 can be called SiC MOSFET. SiC is a semiconductor material with large band gap, which can make the transistor 100 have high voltage resistance. In addition, the material of the semiconductor layer 1 can also include, for example, monocrystalline silicon, monocrystalline germanium, III-V compound semiconductor material, II-VI compound, and other suitable semiconductor materials.

[0060] It can be understood that the material of the semiconductor layer 1 is not limited to SiC. For example, gallium nitride (GaN) materials, diamond and other semiconductor materials also have large band gaps, so that gallium nitride materials, diamond and other semiconductor materials can also be applied to the above-mentioned transistor 100.

[0061] The source 2 and the drain 3 are respectively located on both sides of the semiconductor layer 1 along the first direction X. Among them, the first direction X is parallel to the thickness direction of the semiconductor layer 1.

[0062] ​The first well region 4 and the second well region 5 have first doping ions, and the first well region 4 and the second well region 5 have the same doping type. The first doping part 7 has second doping ions, and the doping type of the first doping part 7 is different from the doping type of the first well region 4 and the second well region 5. In some embodiments, the first well region 4 and the second well region 5 are both P-wells, and the first doping part 7 is an N-type semiconductor. In other embodiments, the first well region 4 and the second well region 5 are both N-wells, and the first doping part 7 is a P-type semiconductor. The embodiments of the present application are explained by taking the first well region 4 and the second well region 5 as P-wells and the first doping part 7 as an N-type semiconductor as an example.

[0063] In the present embodiment, the first well region 4 and the second well region 5 are formed by P-type doping of the semiconductor layer 1, and the first well region 4 and the second well region 5 both extend from the surface of the semiconductor layer 1 away from the drain 3 to the inside of the semiconductor layer 1. The first well region 4 is spaced apart from the second well region 5.

[0064] The first doping part 7 can be an N+ region, and the first doping part 7 can be formed by N-type high doping of the semiconductor layer 1. The first doping part 7 includes a first sub-part 71 and a second sub-part 72 connected in series, wherein the first sub-part 71 can be formed by N-type high doping of the first well region 4, and the second sub-part 72 can be formed by N-type high doping of the second well region 5. The first sub-part 71 extends from the surface of the first well region 4 away from the drain 3 to the inside of the first well region 4, and the depth of the first sub-part 71 is less than the depth of the first well region 4. The second sub-part 72 extends from the surface of the second well region 5 away from the drain 3 to the inside of the second well region 5, and the depth of the second sub-part 72 is less than the depth of the second well region 5.

[0065] The gate structure 6 is located on the side of the semiconductor layer 1 away from the drain 3. The projection of the first sub-part 71 on the first direction X is located within the projection of the gate structure 6 on the first direction X. Then the orthographic projection of the first sub-part 71 and the first well region 4 on the semiconductor layer 1 is located within the edge of the orthographic projection of the gate structure 6 on the semiconductor layer 1. Then the gate structure 6 can completely cover the first sub-region and the first well region 4 in the first direction X, so as to shield the first sub-part 71 and the first well region 4.

[0066] In this embodiment, the projection of the second sub-portion 72 on the first direction X partially overlaps with the projection of the gate structure 6 on the first direction X. Then, the orthographic projection of the second sub-portion 72 on the semiconductor layer 1 partially overlaps with the orthographic projection of the gate structure 6 on the semiconductor layer 1, and partially does not overlap. In the first direction X, the gate structure 6 can expose at least part of the second sub-portion 72. In the first direction X, the gate structure 6 can cover part of the second sub-portion 72, and expose at least part of the second sub-portion 72, so that the source 2 can be connected with the second sub-portion 72, for example, the source 2 can be in contact with the second sub-portion 72. When the second sub-portion 72 is an N-type semiconductor, the second sub-portion 72 has a very small resistivity, and the second sub-portion 72 can form a good ohmic contact with the source 2.

[0067] In some examples, the gate structure 6 can include a gate dielectric layer 61 and a gate electrode layer 62. The gate dielectric layer 61 is located between the gate electrode layer 62 and the semiconductor layer 1. The orthographic projection of the gate dielectric layer 61 on the semiconductor layer 1 can coincide with the orthographic projection of the gate electrode layer 62 on the semiconductor layer 1. Since the gate dielectric layer 61 and the gate electrode layer 62 are tiled above the semiconductor layer 1, the transistor 100 can become a planar gate device.

[0068] For example, the material of the gate dielectric layer 61 includes but is not limited to silicon dioxide (SiO2). The material of the gate electrode layer 62 includes but is not limited to polysilicon. The material of the source 2 can include but is not limited to metal materials such as nickel, titanium, etc. The material of the drain 3 can include but is not limited to metal materials such as nickel, titanium, etc.

[0069] As shown in FIGS. 1A and 1B, the transistor 100 can be in a forward conduction state. In the forward conduction state, the source 2 can be connected with the drain 3 through the second sub-portion 72, and the second sub-portion 72 can be in a conductive state. Figure 2 And Figure 3 As shown in FIGS. 1A and 1B, the transistor 100 can be in a forward conduction state. In the forward conduction state, the source 2 can be connected with the drain 3 through the second sub-portion 72, and the second sub-portion 72 can be in a conductive state.

[0070] Since the source 2 can be in contact with the second sub-portion 72, and the source 2 can include metal materials. Metal materials not only have good electrical conductivity, but also have good thermal conductivity. Therefore, the source 2 can help the second sub-portion 72 dissipate heat, and help the second sub-portion 72 alleviate the local overheating condition generated during work.

[0071] The source electrode 2 is not directly connected to the first sub-section 71. The source electrode 2 is connected to the second sub-section 72, and the second sub-section 72 is connected to the first sub-section 71. Therefore, the current flowing out of the source electrode 2 has to pass through the second sub-section 72 to the first sub-section 71.

[0072] On one hand, if the resistance of the first sub-section 71 and the resistance of the second sub-section 72 are the same or approximately the same, the current can be quickly and evenly distributed in the current path A and the current path B. Then, the current of the transistor 100 in normal operation is increased, which is beneficial to improve the electrical performance of the transistor 100. Wherein, the resistance of the first sub-section 71 and the resistance of the second sub-section 72 are approximately the same, which can be understood as that the difference between the resistance of the first sub-section 71 and the resistance of the second sub-section 72 is within an acceptable deviation range, for example, the difference between the resistance of the first sub-section 71 and the resistance of the second sub-section 72 is less than or equal to 5% of either one.

[0073] On the other hand, if the resistance of the first sub-section 71 is greater than the resistance of the second sub-section 72, the current tends to go through the path with smaller resistance, so the current will tend to go through the current path A, and the current will also go through the current path B, but the current at the current path B is smaller. The greater the resistance of the first sub-section 71, the more uneven the current of the current path A and the current path B, and there is uneven heat distribution. Figure 4 Schematic diagram of local current overlarge point of transistor according to some embodiments Figure 1 , Figure 5 Schematic diagram of local current overlarge point of transistor according to some embodiments Figure 2 . Referring to Figure 4 and Figure 5 Since the resistance of the first sub-section 71 is greater than the resistance of the second sub-section 72, the current is easy to be overlarge at the connection between the first sub-section 71 and the second sub-section 72, which leads to uneven current distribution of the transistor 100 in operation.

[0074] According to Joule's law, in the same time period, the greater the current and resistance, the higher the heat generated. And in the first direction X, the gate structure 6 covers and shields the first sub-section 71, the first sub-section 71 is in contact with the gate dielectric layer 61, and the thermal conductivity of the gate dielectric layer 61 is poor, so the heat dissipation of the first sub-section 71 is poor.

[0075] When the voltage is normal working voltage, the current can flow in the current path A and the current path B for a certain time, although the current distribution is uneven, but the size of the current and the heat dissipation of the transistor 100 are within a controllable range, and the device can normally work at a high power loss. When the voltage is overloaded, a large current flows through the current path A and the current path B instantaneously, and the first sub-part 71 generates a large amount of heat, but the heat dissipation at the first sub-part 71 is poor, so the first sub-part 71 will accumulate heat sharply, and under the impact of heat and large current, the device will be broken down, causing a short circuit of the circuit, and the triggering time is short.

[0076] When the above transistor 100 is applied to a protection circuit as a protection device, due to the poor heat dissipation of the first sub-part 71 and the uneven current distribution of the transistor 100, the local current of the transistor 100 is too large, and the transistor 100 will be broken down rapidly under the impact of the overload current, so as to disconnect the protection circuit, which is beneficial to improve the self-destruction speed of the protection device and speed up the reaction time of the transistor 100 as a protection device, thereby protecting other devices from being damaged by the overload current, and improving the effectiveness of the protection circuit.

[0077] When the above transistor 100 is applied to a circuit for debugging test conditions, when the voltage is normal working voltage, the above transistor 100 has already worked at a high power loss, and there is heat accumulation at the first sub-part 71, when the voltage is overloaded, the first sub-part 71 is impacted by the overload current, the transistor 100 can be heated rapidly and self-destructed quickly, thereby reacting to the problem existing in the test condition, guiding the change of the test condition, and thereby being beneficial to obtain valuable test results.

[0078] In addition, since the first sub-part 71 is shielded by the gate structure 6 in the first direction X, the transistor 100 provided by the application and the conventional transistor 100 cannot be distinguished from the appearance. In a circuit for the purpose of information protection, a protection circuit with the above transistor 100 can be arranged near the device to be protected. When starting information protection, the transistor 100 provided by the application has local current accumulation, which causes the overall circuit to be damaged due to short circuit, thereby playing a role in information security.

[0079] The resistance of the first sub-part 71 and the resistance of the second sub-part 72 can be controlled by doping process and annealing process, etc. The resistance of the first sub-part 71 needs to be controlled within a suitable range to avoid that the resistance of the first sub-part 71 is too large, which causes local overheating and damage of the device when it is normally working.

[0080] In some embodiments, reference is made to Figure 6The first well region 4, the second well region 5, the first sub-portion 71 and the second sub-portion 72 all extend along the second direction Y. The first sub-portion 71 has a first end 711 and a second end 712 along the second direction Y. The second sub-portion 72 has a third end 721 and a fourth end 722 along the second direction Y. The first end 711 and the third end 721 are arranged along the third direction Z. The second direction Y and the third direction Z are both parallel to the semiconductor layer 1. The third direction Z intersects the second direction Y. In the embodiments of the present application, the second direction Y and the third direction Z are perpendicular to each other as an example.

[0081] In the embodiments, the two ends of the first sub-portion 71 and the second sub-portion 72 close to each other can be connected together. For example, the first doped portion 7 further includes a third sub-portion 73. The third sub-portion 73 extends along the third direction Z. The third sub-portion 73 is connected to the first end 711 and the third end 721. The first sub-portion 71, the second sub-portion 72 and the third sub-portion 73 can be formed in the same doping process.

[0082] Through the above arrangement, the first sub-portion 71 and the second sub-portion 72 can be connected through the third sub-portion 73. The current flowing out of the source 2 can be conducted to the first sub-portion 71 through the second sub-portion 72 and the third sub-portion 73. If considering the normal use of the transistor 100, the electrical connection performance between the second sub-portion 72, the third sub-portion 73 and the first sub-portion 71 can be improved by optimizing the doping process, increasing the doping concentration and the like. In this way, the current can be quickly distributed to the first sub-portion 71, the second sub-portion 72 and the third sub-portion 73. If considering the fast self-destruction of the transistor 100, the electrical connection performance between the second sub-portion 72, the third sub-portion 73 and the first sub-portion 71 can be made poor by adjusting the doping process and the like. In this way, the current is unevenly distributed in the transistor 100, which causes the local overheating of the transistor 100 and thus the fast self-destruction of the transistor 100. In addition, through the above arrangement, the electrical connection performance between the second sub-portion 72, the third sub-portion 73 and the first sub-portion 71 can be improved, and the resistance of the first sub-portion 71 can be reduced. In this way, the resistance of the first sub-portion 71 can be controlled within a proper range, and the resistance of the first sub-portion 71 is prevented from being too large, which causes the local overheating of the device and thus the damage of the device during the normal operation.

[0083] In some embodiments, with reference to Figure 6The first end 711 and the third end 721 are arranged along the third direction Z, and the second end 712 and the fourth end 722 are arranged along the third direction Z. The length of the first sub-portion 71 in the second direction Y is the same as the length of the second sub-portion 72 in the second direction Y, and the first sub-portion 71 and the second sub-portion 72 are arranged in alignment in the third direction Z. The third sub-portion 73 is connected to the first end 711 and the third end 721. The first doped portion 7 further includes a fourth sub-portion 74 connected to the second end 712 and the fourth end 722. From the perspective of the first direction X, the first sub-portion 71, the second sub-portion 72, the third sub-portion 73, and the fourth sub-portion 74 can be connected to form a rectangle. The first sub-portion 71, the second sub-portion 72, the third sub-portion 73, and the fourth sub-portion 74 can be formed as connected regions in the same doping process.

[0084] In this embodiment, the second end 712 and the fourth end 722 are further connected through the fourth sub-portion 74, which is beneficial to improve the electrical connection performance between the first sub-portion 71 and the second sub-portion 72. This is beneficial to further improve the current transmission capability of the second sub-portion 72 to the first sub-portion 71.

[0085] In some embodiments, as shown in Figure 6 The size of the first sub-portion 71 in the second direction Y is greater than the size of the second sub-portion 72 in the second direction Y. Here, the size of the first sub-portion 71 in the second direction Y can be understood as the extension length of the first sub-portion 71 in the second direction Y. The size of the second sub-portion 72 in the second direction Y can be understood as the extension length of the second sub-portion 72 in the second direction Y.

[0086] In this embodiment, only one end of the first sub-portion 71 and the second sub-portion 72 can be arranged in alignment in the third direction Z, for example, the first end 711 and the second end 712 are arranged in alignment in the third direction Z, or the second end 712 and the fourth end 722 are arranged in alignment in the third direction Z.

[0087] Through the above arrangement, the size of the second sub-portion 72 in the second direction Y is smaller than the size of the first sub-portion 71 in the second direction Y, and the position of the second sub-portion 72 can be reserved to facilitate the subsequent arrangement of the lead-out structure and the like.

[0088] In some embodiments, as shown in Figure 6 and Figure 7As shown, the first well region 4 can include a plurality of sub-well regions 41 arranged along the second direction Y. The first sub-portion 71 can include a plurality of first connecting portions 713 and a plurality of second connecting portions 714 connected in sequence along the second direction Y. Here, the plurality of first connecting portions 713 and the plurality of second connecting portions 714 connected in sequence can be understood as the plurality of first connecting portions 713 and the plurality of second connecting portions 714 being arranged alternately, forming a plurality of first connecting portions 713 spaced apart from each other and a plurality of second connecting portions 714 spaced apart from each other.

[0089] One first connecting portion 713 is located in one sub-well region 41. The number of first connecting portions 713 is the same as the number of sub-well regions 41, and the plurality of first connecting portions 713 are arranged one-to-one with the plurality of sub-well regions 41.

[0090] Through the above arrangement, the number and position of the sub-well regions 41 can be flexibly arranged according to the space of the semiconductor layer 1, so that the size of the first sub-portion 71 in the second direction Y can be adjusted, which is beneficial to avoid other lead-out structures and leave arrangement space for other lead-out structures.

[0091] In addition, reducing the number of sub-well regions 41 can correspondingly reduce the size of the first sub-portion 71 in the second direction Y, thereby facilitating the reduction of the resistance of the first sub-portion 71. Exemplarily, the above-mentioned manner can be one of the methods for controlling the resistance of the first sub-portion 71, so that the resistance value of the first sub-portion 71 is within a suitable range, avoiding that the resistance of the first sub-portion 71 is too large to cause local overheating and damage of the device during normal operation.

[0092] In some embodiments, as Figure 7 As shown, the first connecting portion 713 has the same shape as the sub-well region 41. Here, "the same shape" can be understood as, from the perspective of the first direction X, i.e. in the Y-Z plane, the shape of the first connecting portion 713 is the same as or approximately the same as the shape of the sub-well region 41. Alternatively, it can be understood that the shape of the orthographic projection of the first connecting portion 713 on the semiconductor layer 1 is the same as or approximately the same as the shape of the orthographic projection of the sub-well region 41 on the semiconductor layer 1. The shape of the first connecting portion 713 is approximately the same as the shape of the sub-well region 41, which can be understood as the shape of the first connecting portion 713 and the shape of the sub-well region 41 both tend to the same shape, for example, both tend to be a square. However, due to process errors, the shape of the first connecting portion 713 or the shape of the sub-well region 41 may not be a regular square, as long as the shape of the first connecting portion 713 and the shape of the sub-well region 41 both tend to the same shape.

[0093] It should be noted that the shape of the first connection part 713 can be the same as or approximately the same as the shape of the sub-well region 41, and the size of the shape of the first connection part 713 can be different from the size of the shape of the sub-well region 41, that is, the shape of the first connection part 713 is similar to the shape of the sub-well region 41. For example, in the Y-Z plane, the shape of the first connection part 713 is a square with a side length of a, and the shape of the sub-well region 41 is also a square with a side length of b, a < b. In the Y-Z plane, the shape of the first connection part 713 is the same as the shape of the sub-well region 41, but the size of the shape of the first connection part 713 is different from the size of the shape of the sub-well region 41.

[0094] In this embodiment, the sub-well region 41 can be doped to form the first connection part 713. Through the above arrangement, it is beneficial to design the shape of the sub-well region 41, and then design the shape of the first connection part 713. Moreover, the shape of the first connection part 713 is the same as the shape of the sub-well region 41, which is beneficial to improve the structural regularity of the transistor 100.

[0095] In some embodiments, as shown in FIG. 7A, the shape of the first connection part 713 can include at least one of a strip shape, a polygonal shape, a circular shape, and an elliptical shape. Correspondingly, the shape of the sub-well region 41 can also include at least one of a strip shape, a polygonal shape, a circular shape, and an elliptical shape. The shape of the sub-well region 41 is the same as the shape of the first connection part 713. Figure 7 In some embodiments, the shape of the second connection part 714 can include at least one of a strip shape, a polygonal shape, a circular shape, and an elliptical shape.

[0096] In some embodiments, the shape of the first well region 4 can include at least one of a strip shape, a polygonal shape, a circular shape, and an elliptical shape. Correspondingly, the shape of the first sub-part 71 can also include at least one of a strip shape, a polygonal shape, a circular shape, and an elliptical shape.

[0097] Through the above arrangement, the shape of the first well region 4, the shape of the second well region 5, the shape of the first connection part 713, the shape of the second connection part 714, and the shape of the first sub-part 71 can be freely combined. Different shape combinations can be selected according to process requirements or layout design, which is beneficial to adapt to different preparation scenes.

[0098] In some embodiments, the first doping ions include B and Al, and the second doping ions include N, P, As, and Sb. At this time, the doping type of the first well region 4 and the second well region 5 is P-type doping, and the first well region 4 and the second well region 5 are both P-wells. The doping type of the first doping part 7 is N-type doping, and the first doping part 7 is an N-type semiconductor.

[0099]

[0100] ​In other embodiments, the first doping ions include N, P, As and Sb, and the second doping ions include B and Al. In this case, the doping type of the first well region 4 and the second well region 5 is N-type doping, and the first well region 4 and the second well region 5 are both N-wells. The doping type of the first doped portion 7 is P-type doping, and the first doped portion 7 is a P-type semiconductor.

[0101] In some examples, the doping depth of the first doping ions in the first well region 4 is 0.5 μm-15 μm. In some examples, the doping concentration of the first doping ions is 1E16 atom / cm 3 -1E18 atom / cm 3 By the above arrangement, the first well region 4 and the second well region 5 are formed.

[0102] In some examples, the doping depth of the second doping ions in the first doped portion 7 is 0.2 μm-0.5 μm. In some examples, the doping concentration of the second doping ions is 1E18 atom / cm 3 -1E20 atom / cm 3 By the above arrangement, the first doped region is formed.

[0103] In some embodiments, as shown in Figure 8 the transistor 100 further includes a third well region 8. The third well region 8 is formed by doping the semiconductor layer 1, and the doping type of the third well region 8 is the same as that of the first well region 4. The doping depths of the first well region 4, the second well region 5 and the third well region 8 can be the same. The third well region 8 extends from the surface of the semiconductor layer 1 away from the drain 3 to the inside of the semiconductor layer 1, the third well region 8 is arranged apart from the first well region 4, and the third well region 8 is located on the side of the first well region 4 away from the second well region 5.

[0104] The first doped portion 7 further comprises a fifth sub-portion 75. The fifth sub-portion 75 can be formed by doping the third well region 8. The fifth sub-portion 75 can have the same doping type as the first sub-portion 71. The first sub-portion 71, the second sub-portion 72 and the fifth sub-portion 75 can be formed in the same doping process. The first sub-portion 71, the second sub-portion 72 and the fifth sub-portion 75 can have the same doping depth. The fifth sub-portion 75 is located in the third well region 8, and the fifth sub-portion 75 extends from the surface of the drain 3 to the inside of the third well region 8. The projection of the fifth sub-portion 75 on the first direction X partially overlaps with the projection of the gate structure 6 on the first direction X. The orthographic projection of the fifth sub-portion 75 on the semiconductor layer 1 partially overlaps with the orthographic projection of the gate structure 6 on the semiconductor layer 1, and partially does not overlap. In the first direction X, the gate layer 62 exposes at least part of the fifth sub-portion 75. The fifth sub-portion 75 can be connected with the source 2, for example, the fifth sub-portion 75 can be in contact with the source 2. When the fifth sub-portion 75 is an N-type semiconductor, the fifth sub-portion 75 has a very small resistivity, and the fifth sub-portion 75 can form a good ohmic contact with the source 2.

[0105] In some examples, the transistor 100 can have a center plane, the center plane passes through the center of the first well region 4, and is perpendicular to the surface of the semiconductor layer 1 away from the drain 3. The second well region 5 and the third well region 8 are located on both sides of the center plane, and are symmetrically arranged about the center plane. The second sub-portion 72 and the fifth sub-portion 75 are located on both sides of the center plane, and are symmetrically arranged about the center plane.

[0106] Through the above arrangement, it is beneficial to improve the design regularity of the transistor 100, and facilitate the preparation and formation of the transistor 100.

[0107] In some embodiments, referring to Figure 8 The transistor 100 further comprises a second doped portion 9. The second doped portion 9 can have the same doping type as the first well region 4. The second doped portion 9 has first doping ions. The second doped portion 9 is located in the second well region 5, and the second doped portion 9 extends through the second sub-portion 72 along the first direction X. For example, the second doped portion 9 can be formed by P-type high doping of the second well region 5. The second doped portion 9 extends from the surface of the drain 3 to the inside of the second well region 5. The depth of the second doped portion 9 can be less than the depth of the second well region 5, or the depth of the second doped portion 9 can also be greater than or equal to the depth of the second well region 5. Then the current flowing out of the source 2 can be conducted to the second sub-portion 72 through the second doped portion 9. The second doped portion 9 is beneficial to improve the reverse voltage withstand capability of the transistor 100.

[0108] In some embodiments, referring to Figure 8Transistor 100 further includes a connection structure 10. Connection structure 10 is located between source 2 and first doped portion 7, and connects source 2 and first doped portion 7. Connection structure 10 may cover a portion of the surface of second sub-portion 72, thereby achieving contact with first doped portion 7. Connection structure 10 may be made of a metal material, such as nickel. This configuration allows connection structure 10 to not only conduct electricity but also conduct heat, helping dissipate heat from second sub-portion 72. Connection structure 10 may form an ohmic contact with source 2.

[0109] The transistor 100 may further include an isolation layer 11. The isolation layer 11 is located between the gate structure 6 and the connection structure 10, and between the gate structure 6 and the source 2. The isolation layer 11 may cover the gate structure 6, wrapping the gate dielectric layer 61 and the gate layer 62, and isolating the gate layer 62 from the source 2 and the connection structure 10.

[0110] Some embodiments of the present application also provide a method for preparing a transistor. The method is used, for example, to prepare the transistor 100 as described in some of the above embodiments. Figure 9 As shown, the preparation method includes: S100-S500.

[0111] S100, performing doping treatment on the semiconductor layer to form a first well region and a second well region, the first well region and the second well region are spaced apart and both extend from the surface of the semiconductor layer to the interior of the semiconductor layer, and the first well region and the second well region have first doping ions.

[0112] For example, Figure 10 As shown, the material of the semiconductor layer 1 includes but is not limited to SiC. For example, the material of the semiconductor layer 1 may also include GaN-based materials, diamond, etc.

[0113] For example, Figure 10 As shown, the first doping ions may include B and Al, and the second doping ions may include N, P, As, and Sb. Alternatively, the first doping ions may include N, P, As, and Sb, and the second doping ions may include B and Al. This embodiment is explained by taking the first doping ions as P-type ions and the second doping ions as N-type ions as an example.

[0114] In this step, refer to Figure 10 The semiconductor layer 1 is doped by ion implantation, wherein P-type ions, such as B and Al, are implanted into the semiconductor layer 1. The implantation depth of the P-type ions can be between 0.5 μm and 1 μm, and the implantation concentration of the P-type ions can be 1E16 atom / cm 3 -1E18atom / cm 3The doping depth and doping concentration of the second well region 5 can be the same as those of the first well region 4. In this step, the third well region 8 can also be formed at the same time as the first well region 4 and the second well region 5.

[0115] S200, performing a doping treatment on the semiconductor layer to form a first doped part, the first doped part having second doped ions, the first doped part including a first sub-part and a second sub-part connected to each other, the first sub-part being located in the first well region, and the second sub-part being located in the second well region.

[0116] In this step, referring to Figure 10 and Figure 11 , an ion implantation process can be used to implant N-type ions, such as N, P, As, Sb, etc., into the semiconductor layer 1, thereby forming the first doped part 7, which is an N-type semiconductor. The doping depth of the first doped part 7 can be between 0.2 μm and 0.5 μm. The doping concentration of the first doped part 7 can be between 1E18 atom / cm 3 - 1E20 atom / cm 3 In this step, the fifth sub-part 75, which is located in the third well region 8, can be formed at the same time as the first sub-part 71 and the second sub-part 72.

[0117] After the formation of the first doped part 7, referring to Figure 11 and Figure 12 , a P-type ion implantation process can also be used to implant P-type ions, such as B, Al, etc., into the first sub-part 71 and the fifth sub-part 75, thereby forming the second doped part 9. The doping depth of the second doped part 9 can be between 0.5 μm and 1 μm. The doping concentration of the second doped part 9 can be between 1E18 atom / cm 3 - 1E20 atom / cm 3 .

[0118] S300, forming a gate structure, the gate structure being located on one side of the semiconductor layer and, in a first direction, shielding the first sub-part and the first well region, and exposing at least part of the second sub-part, wherein the first direction is parallel to the thickness direction of the semiconductor layer.

[0119] In this step, referring to Figure 13For example, a deposition process can be used to form the gate dielectric layer 61 and the gate electrode layer 62 on one side of the semiconductor layer 1 in sequence. The gate electrode layer 62 is located on the side of the gate dielectric layer 61 away from the semiconductor layer 1. The material of the gate dielectric layer 61 can include, but is not limited to, silicon oxide, and the material of the gate electrode layer 62 can include, but is not limited to, polysilicon. For example, the thickness of the gate dielectric layer 61 can be in the range of 30 nm to 200 nm, and the thickness of the polysilicon can be in the range of 300 nm to 1000 nm. For example, the polysilicon can be doped with P elements to form the gate electrode layer 62, and the doping concentration can be in the range of 1E20 atom / cm 3 to 8E20 atom / cm 3 . The width of the gate electrode layer 62 is less than or equal to the width of the gate dielectric layer 61. For example, the normal projection of the gate dielectric layer 61 and the gate electrode layer 62 on the semiconductor layer 1 coincides.

[0120] Referring to Figure 13 and Figure 14 , after the gate structure 6 is formed, a deposition process can be used to form the isolation layer 11 on the side of the gate structure 6 away from the semiconductor layer 1. The width of the isolation layer 11 is greater than the width of any one of the gate dielectric layer 61 and the gate electrode layer 62. The isolation layer 11 covers the upper surface and the side surface of the gate structure 6, and it can be understood that the isolation layer 11 wraps the gate electrode layer 62 and the gate dielectric layer 61. The isolation layer 11 can be in contact with the gate dielectric layer 61, the second sub-portion 72 and the fifth sub-portion 75, and the isolation layer 11 can cooperate with the gate dielectric layer 61 to achieve the wrapping coverage of the gate electrode layer 62. For example, the material of the isolation layer 11 includes, but is not limited to, a single layer or any multi-layer combination of silicon dioxide, boron phosphorus glass and silicon nitride. For example, the thickness of the isolation layer 11 is in the range of 0.6 μm to 2 μm.

[0121] S400, forming a source electrode, the source electrode is located on the side of the semiconductor layer close to the gate structure.

[0122] In this step, referring to Figure 14 and Figure 15 , an etching process can be used to remove part of the isolation layer 11 to expose at least part of the second sub-portion 72. A deposition process can be used to form a connection structure 10 on the side of the first doped portion 7 away from the semiconductor layer 1, for example, Ni can be deposited and then a high-temperature annealing process is used to process the Ni to form an ohmic contact between the connection structure 10 and the first doped portion 7.

[0123] Referring to Figure 15 and Figure 16 , after the connection structure 10 is formed, a deposition process can be used to deposit a conductive material to form a source electrode 2, and the source electrode 2 is in contact with the connection structure 10. The conductive material includes, but is not limited to, metal materials such as nickel.

[0124] S500, forming a drain electrode, the drain electrode is located at the side of the semiconductor layer far away from the gate structure.

[0125] Exemplarily, referring to Figure 16 and Figure 17 , the embodiment of the present application can adopt a sputtering process to form a drain electrode 3 on the side of the semiconductor layer 1 far away from the source electrode 2, the drain electrode 3 can be in the form of a flat plate, and then a high-temperature annealing process is adopted to process the drain electrode 3, so that the drain electrode 3 forms an ohmic contact with the semiconductor layer 1. Optionally, the material of the drain electrode 3 includes but is not limited to nickel.

[0126] In some embodiments of the present application, the "width" of each structure refers to the lateral dimension in the cross-sectional view shown in the drawings. The "depth" of each structure refers to the vertical dimension in the cross-sectional view shown in the drawings.

[0127] As Figure 18 shown, some embodiments of the present disclosure also provide an electronic device 1000. The electronic device 1000 can be a power electronic device 1000, that is, a device with power electronic devices (also known as semiconductor devices or power semiconductor devices) as the main functional elements. For example, the electronic device 1000 can be a converter, an electronic switch, an electronic AC power controller, etc. Among them, the converter includes but is not limited to a DC chopper (DC / DC, or a direct current to direct current power supply), a rectifier (AC / DC, or an alternating current to direct current converter), an inverter (DC / AC, or a direct current to alternating current converter), etc., and the electronic switch includes but is not limited to a power switch power supply circuit, etc. The electronic device 1000 can also be a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device, etc. Different types of user devices or terminal devices; the electronic device 1000 can also be a network device such as a base station. The electronic device 1000 can also be a device such as a power amplifier in the above-mentioned electronic device 1000. The specific form of the electronic device 1000 is not specially limited in the embodiments of the present application. The specific type of the electronic device 1000 is not specially limited in the embodiments of the present application.

[0128] Figure 18 is a block diagram of an electronic device according to some embodiments. The electronic device 1000 includes a circuit board and a transistor 100 provided by some embodiments described above, the circuit board and the transistor 100 are electrically connected, and the circuit board is used to provide the transistor 100 with the required electrical signal.

[0129] It can be understood that the structure shown in the embodiments of the present application does not constitute a specific limitation on the electronic device 1000. In some other embodiments of the present application, the electronic device 1000 can include more components than shown, or combine some components, or split some components, or different component arrangements. The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0130] Some embodiments of the present application provide that the transistor 100 can be applied in the electronic device 1000 described above. Of course, the specific application scenarios of the transistor 100 described above are not limited thereto. It can be understood that any electronic device 1000 requiring the use of the transistor 100 belongs to the application scenarios of the embodiments of the present application.

[0131] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, and should be encompassed within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A transistor, comprising: include: semiconductor layer; a source electrode and a drain electrode, respectively located on two sides of the semiconductor layer along a first direction; a first well region and a second well region, wherein the first well region and the second well region are spaced apart from each other and both extend from a surface of the semiconductor layer away from the drain electrode to an interior of the semiconductor layer, and the first well region and the second well region have first dopant ions; a gate structure, located on a side of the semiconductor layer away from the drain; a first doped portion having a second dopant ion, comprising a first sub-portion and a second sub-portion connected to each other, wherein the first sub-portion is located in the first well region, and the second sub-portion is located in the second well region; a projection of the first sub-portion in the first direction is located within a projection of the gate structure in the first direction; and a projection of the second sub-portion in the first direction partially overlaps with a projection of the gate structure in the first direction; The first direction is parallel to the thickness direction of the semiconductor layer.

2. The transistor according to claim 1, wherein: The first well region, the second well region, the first sub-portion, and the second sub-portion all extend along a second direction, the first sub-portion has a first end and a second end along the second direction, the second sub-portion has a third end and a fourth end along the second direction, and the first end and the third end are arranged along a third direction; the second direction and the third direction are both parallel to the semiconductor layer, and the third direction intersects the second direction; The first doped portion further includes a third sub-portion, the third sub-portion extending along the third direction, and the third sub-portion connected to the first end and the third end.

3. The transistor of claim 2, wherein The second end and the fourth end are arranged along the third direction; The first doped portion further includes a fourth sub-portion connected to the second end and the fourth end.

4. The transistor of claim 2, wherein A size of the first sub-portion in the second direction is larger than a size of the second sub-portion in the second direction.

5. The transistor according to claim 2, wherein: The first well region includes a plurality of sub-well regions spaced apart along the second direction. The first sub-portion includes a plurality of first connecting portions and a plurality of second connecting portions alternately connected in sequence along the second direction. The first connecting portions are located in the sub-well regions.

6. The transistor of claim 5, wherein The first connecting portion has the same shape as the sub-well region.

7. The transistor of claim 6, wherein The shape of the first connecting portion includes at least one of polygonal, circular, and elliptical; and / or, The shape of the second connection portion includes at least one of a polygon, a circle, and an ellipse.

8. The transistor of claim 1, wherein The first doping ions include B and Al, and the second doping ions include N, P, As and Sb; and / or, The first doping ions include N, P, As, and Sb, and the second doping ions include B and Al.

9. The transistor of claim 8, wherein, The doping depth of the first doping ions in the first well region is 0.5 μm-15 μm; and / or, The first dopant ion has a doping concentration of 1E16 atom / cm 3 -1E18 atom / cm 3 .

10. The transistor of claim 8, wherein The doping depth of the second doping ions in the first doping portion is 0.2 μm-0.5 μm; and / or, The doping concentration of the second dopant ions is 1E18 atom / cm 3 -1E20 atom / cm 3 .

11. The transistor according to claim 1, wherein: The transistor further includes: a third well region extending from a surface of the semiconductor layer away from the drain to an interior of the semiconductor layer, the third well region being spaced apart from the first well region and located on a side of the first well region away from the second well region; the first doped portion further includes: a fifth sub-portion located in the third well region, a projection of the fifth sub-portion in the first direction partially overlapping a projection of the gate structure in the first direction.

12. The transistor of claim 1, wherein further includes a second doped portion located in the second well region, the second doped portion extending through the second sub-portion in the first direction, the second doped portion having first dopant ions.

13. The transistor of claim 1, wherein further includes: a connection structure located between the source and the first doped portion, the connection structure connecting the source and the first doped portion; an isolation layer located between the gate structure and the connection structure, and between the gate structure and the source.

14. A method for manufacturing a transistor, the method comprising: performing a doping process on a semiconductor layer to form a first well region and a second well region, the first well region and the second well region being spaced apart and each extending from a surface of the semiconductor layer to an interior of the semiconductor layer, the first well region and the second well region having first dopant ions therein; performing a doping process on the semiconductor layer to form a first doped portion having second dopant ions, the first doped portion including a first sub-portion and a second sub-portion, the first sub-portion being located in the first well region, the second sub-portion being located in the second well region; forming a gate structure located on a side of the semiconductor layer, the gate structure shielding the first sub-portion and the first well region and exposing at least part of the second sub-portion in a first direction, the first direction being parallel to a thickness direction of the semiconductor layer; forming a source located on a side of the semiconductor layer proximate to the gate structure; forming a drain located on a side of the semiconductor layer distal to the gate structure.

15. The method of claim 14, wherein the method further comprises: the forming of the gate structure includes: forming a gate dielectric layer located on a side of the semiconductor layer; forming a gate electrode layer located on a side of the gate dielectric layer distal to the semiconductor layer; forming an isolation layer covering the gate electrode layer and the gate dielectric layer; the forming of the source includes: removing part of the isolation layer to expose at least part of the second sub-portion; forming a connection structure located on a side of the first doped portion distal to the semiconductor layer; depositing a conductive material to form the source in contact with the connection structure.

16. An electronic device, comprising: the electronic device includes the transistor of any one of claims 1-13.

Images