Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device, and relates to but is not limited to the technical field of display, and the display substrate comprises a source / drain electrode which is arranged at one side of a substrate; the active layer is arranged on one side, far away from the substrate, of the source / drain electrode, and the active layer comprises a channel region, a first contact region and a second contact region; the grid electrode is arranged on one side, far away from the substrate, of the active layer, and at least part of the grid electrode is overlapped with the orthographic projection of the channel region on the substrate; the pixel electrode is arranged on one side, far away from the substrate, of the grid electrode; the pixel electrode is in direct contact with the first contact area; the second contact area is connected with the source / drain electrode through the connecting electrode, the connecting electrode and the pixel electrode are located on the same film layer, and the connecting electrode and the pixel electrode comprise the same conductive material.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically relate to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display Device) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Liquid crystal display (LCD) has the characteristics of small size, low power consumption and no radiation, and has been developed rapidly. The liquid crystal display panel includes a thin film transistor array (TFT) substrate and a color filter (CF) substrate of a cell. Liquid crystal (LC) molecules are arranged between the array substrate and the color filter substrate. The electric field that drives the liquid crystal deflection is formed by controlling the common electrode and the pixel electrode to realize grayscale display. Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] A source / drain electrode is disposed on one side of the substrate;

[0007] An active layer is arranged on a side of the source / drain electrode away from the substrate, the active layer comprising a channel region and a first contact region and a second contact region;

[0008] A gate is arranged on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0009] A pixel electrode is arranged on a side of the gate away from the substrate; the pixel electrode is in direct contact with the first contact area;

[0010] A connecting electrode connects the second contact area to the source / drain electrode, and the connecting electrode and the pixel electrode are located in the same film layer and include the same conductive material.

[0011] In an exemplary embodiment, a first hole is further included on the substrate and extends in a direction perpendicular to the substrate, the first hole exposes at least a portion of the first contact area, and the pixel electrode is in direct contact with the exposed first contact area through the first hole.

[0012] In an exemplary embodiment, it also includes a second inorganic dielectric layer, an organic dielectric layer, and a third inorganic dielectric layer, which are arranged in sequence on the side of the gate close to the pixel electrode along a direction away from the substrate, and the first hole extends from the surface of the third inorganic dielectric layer away from the substrate, penetrates the third inorganic dielectric layer, the organic dielectric layer and the second inorganic dielectric layer in sequence, and extends to the active layer, exposing at least a portion of the first contact area.

[0013] In an exemplary embodiment, at least a portion of the pixel electrode covers a side wall and a bottom wall of the first hole.

[0014] In an exemplary embodiment, it also includes a second via hole arranged on the substrate and extending in a direction perpendicular to the substrate, the second via hole exposing at least a portion of the source / drain electrode and at least a portion of the second contact area, and the connecting electrode connects the exposed source / drain electrode with the exposed second contact area through the second via hole.

[0015] In an exemplary embodiment, it also includes a first inorganic dielectric layer arranged between the source / drain electrode and the active layer, and a second inorganic dielectric layer, an organic dielectric layer, and a third inorganic dielectric layer are arranged in sequence on the side of the gate close to the pixel electrode along a direction away from the substrate, and the second via hole extends from the surface of the third inorganic dielectric layer away from the substrate, penetrates the third inorganic dielectric layer, the organic dielectric layer, the second inorganic dielectric layer and the first inorganic dielectric layer in sequence, and extends to the source / drain electrode, the side wall of the second via hole exposes at least a portion of the second contact area, and the bottom wall of the second via hole exposes at least a portion of the source / drain electrode.

[0016] In an exemplary embodiment, at least a portion of the connecting electrode covers a side wall and a bottom wall of the second via hole.

[0017] In an exemplary embodiment, orthographic projections of the pixel electrode and the connection electrode on the substrate do not overlap.

[0018] In an exemplary embodiment, the second contact region overlaps with an orthographic projection of the source / drain electrode on the substrate.

[0019] In an exemplary embodiment, a light shielding layer is further included, and the light shielding layer is disposed on a side of the channel region of the active layer close to the substrate, and overlaps with an orthographic projection of the channel region of the active layer on the substrate.

[0020] In an exemplary embodiment, the material of the active layer is metal oxide.

[0021] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising the display substrate described above.

[0022] In a third aspect, the present disclosure also provides a method for preparing a display substrate, comprising:

[0023] forming source / drain electrodes on a substrate;

[0024] An active layer is formed on a side of the source / drain electrode away from the substrate, wherein the active layer includes a channel region and a first contact region and a second contact region;

[0025] forming a gate on a side of the active layer away from the substrate, wherein at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0026] Conducting the first contact area and the second contact area;

[0027] A conductive film is formed on the side of the gate away from the substrate, so that the conductive film forms a pixel electrode and a connecting electrode, the pixel electrode is in direct contact with the first contact area, and the connecting electrode connects the second contact area with the source / drain electrode.

[0028] In a fourth aspect, the present disclosure also provides a method for preparing a display substrate, comprising:

[0029] forming source / drain electrodes on a substrate;

[0030] forming a first inorganic dielectric layer on a side of the source / drain electrode away from the substrate;

[0031] An active layer is formed on a side of the first inorganic dielectric layer away from the substrate, wherein the active layer includes a channel region and a first contact region and a second contact region;

[0032] forming a gate on a side of the active layer away from the substrate, wherein at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0033] Conducting the first contact area and the second contact area;

[0034] forming a second inorganic dielectric layer on a side of the gate away from the substrate;

[0035] forming an organic dielectric layer on a side of the second inorganic dielectric layer away from the substrate;

[0036] forming a first via hole and a second via hole penetrating the organic dielectric layer, wherein at least a portion of the first via hole overlaps with an orthographic projection of the first contact area on the substrate, and at least a portion of the second via hole overlaps with an orthographic projection of the second contact area and the source / drain electrode on the substrate;

[0037] forming a third inorganic dielectric layer covering the first via hole and the second via hole on a side of the organic dielectric layer away from the substrate;

[0038] The second inorganic dielectric layer and the third inorganic dielectric layer in the first via hole are etched away to expose at least a portion of the first contact area; the first inorganic dielectric layer, the second inorganic dielectric layer and the third inorganic dielectric layer in the second via hole are etched away to expose at least a portion of the first contact area and at least a portion of the source / drain electrode;

[0039] A conductive film is formed on the side of the third inorganic dielectric layer away from the substrate, so that the conductive film forms a pixel electrode and a connecting electrode, the pixel electrode is in direct contact with the exposed first contact area, and the connecting electrode connects the exposed second contact area with the exposed source / drain electrode.

[0040] The display substrate of the disclosed embodiment makes the connecting electrode and the pixel electrode located in the same film layer. During the preparation of the display substrate, the contact area of ​​the active layer is firstly conductive, and then the connecting electrode is formed to avoid the connecting electrode blocking the contact area, thereby making the contact area fully conductive, reducing the contact impedance, and increasing the on-state current, which is conducive to the realization of high refresh rate and high PPI products.

[0041] In the embodiment of the present disclosure, the second inorganic insulating film and the third inorganic insulating film on the first contact region are etched simultaneously to expose the first contact region, thereby simplifying the preparation process and reducing the production cost.

[0042] The embodiment of the present disclosure simultaneously etches the first inorganic insulating film, the second inorganic insulating film and the third inorganic insulating film on the second contact region to expose the second contact region, thereby simplifying the preparation process and reducing the production cost.

[0043] The disclosed embodiment displays a substrate that shields the channel region of the active layer through a shielding layer to prevent light from directly irradiating the channel region, thereby reducing the negative bias of the transistor gate threshold voltage (Vth) caused by light, solving the leakage problem of the display substrate, and ensuring the negative bias temperature illumination stress (nbtis) stability, thereby increasing the life of the display substrate.

[0044] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0046] Figure 1 is a schematic diagram of a cross-sectional structure of a display substrate of a related technology;

[0047] Figure 2a A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0048] Figure 2b for Figure 2a A cross-sectional view along the A-A' direction;

[0049] Figure 3a It is a schematic plan view of a display substrate preparation process after forming a light shielding layer and a source / drain electrode according to an exemplary embodiment of the present disclosure;

[0050] Figure 3b for Figure 3a A cross-sectional view along the A-A' direction;

[0051] Figure 4a It is a schematic plan view of an exemplary embodiment of the present disclosure after an active layer is formed in a display substrate preparation process;

[0052] Figure 4b for Figure 4a A cross-sectional view along the A-A' direction;

[0053] Figure 5a It is a schematic plan view of an exemplary embodiment of the present disclosure after a gate is formed in a display substrate preparation process;

[0054] Figure 5b for Figure 5a A cross-sectional view along the A-A' direction;

[0055] Figure 6 It is a cross-sectional schematic diagram of an exemplary embodiment of the present disclosure after a second inorganic dielectric layer is formed in a display substrate preparation process;

[0056] Figure 7a It is a schematic plan view of an exemplary embodiment of the present disclosure after an organic dielectric layer, a first via hole and a second via hole are formed in a display substrate preparation process;

[0057] Figure 7b for Figure 7a A cross-sectional view along the A-A' direction;

[0058] Figure 8a It is a schematic plan view of an exemplary embodiment of the present disclosure after a common electrode, a third via hole and a fourth via hole are formed in a display substrate preparation process;

[0059] Figure 8b for Figure 8a A cross-sectional view along the A-A' direction;

[0060] Figure 9a It is a schematic plan view of an exemplary embodiment of the present disclosure after a third inorganic dielectric layer, a fifth via hole and a sixth via hole are formed in a display substrate preparation process;

[0061] Figure 9b for Figure 9a A cross-sectional view along the A-A' direction;

[0062] Fig.10 A simulation curve diagram of a display substrate of the related art;

[0063] Fig.11a It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0064] Fig.11b for Fig.11a A cross-sectional view along the A-A' direction;

[0065] Fig.12 A simulation graph of a substrate is shown for an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0067] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0068] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0069] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0070] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0071] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0072] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0073] In this specification, "connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0074] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0075] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0076] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0077] The inventors of the present disclosure have found through research that the bottom-gate thin-film transistor adopts the back channel etching (BCE) process. The back channel etching is easy to affect the channel device due to over-etching, which is not conducive to the performance of the thin-film transistor. Although an etching protection layer (ES) can be used to solve this problem, the use of the etching protection layer will increase the complexity of the process. The bottom-gate thin-film transistor is not easy to achieve self-alignment, and the back exposure technology has compatibility issues with the current process. The traditional manufacturing method will cause a large overlap area in the bottom-gate thin-film transistor, resulting in a large overlap capacitance, which is not conducive to reducing the channel size. The large overlap capacitance will also reduce the operating speed of the driving circuit, making it difficult to drive a high-resolution active matrix organic light-emitting diode (AMOLED) display.

[0078] The top-gate thin-film transistor can solve the problems and shortcomings of the bottom-gate thin-film transistor. The top-gate thin-film transistor does not have the problem of over-etching damage. The gate dielectric layer in the top-gate thin-film transistor can protect the active layer above the active layer. The top-gate structure has the advantage of achieving self-alignment, and the process is relatively simple. The contact area of ​​the active layer can be plasma treated, and hydrogen can be added to the contact area to increase the conductivity of the contact area. The self-aligned structure can avoid overlapping areas, and there is no overlapping capacitance. The channel size of the thin-film transistor can be controlled more accurately, and a shorter channel can be achieved.

[0079] Figure 1FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate of a related art. Figure 1 As shown, the display substrate of the related art includes a substrate 101', a source / drain electrode 14' disposed on the substrate 101', an active layer 11' disposed on a side of the source / drain electrode 14' away from the substrate 101', and a gate 13' and a source / drain connection electrode 15' disposed on a side of the active layer 11' away from the substrate 101', wherein the source / drain connection electrode 15' connects the source / drain electrode 14' to a contact area of ​​the active layer 11'. The orthographic projections of the source / drain connection electrode 15' and the contact area of ​​the active layer 11' on the substrate 101' overlap.

[0080] In the method for preparing a display substrate of the related art, a source / drain electrode 14' and an active layer 11' are first formed, and then a metal film is formed on the side of the active layer 11' away from the substrate 101'. The metal film is formed into a gate 13' and a source / drain connection electrode 15' through an etching process. Finally, the contact area of ​​the active layer 11' is conductive.

[0081] Since the orthographic projections of the source / drain connection electrode 15' and the contact area of ​​the active layer 11' overlap on the substrate 101', when the contact area of ​​the active layer 11' is conductive, part of the contact area will be blocked by the source / drain connection electrode 15' and cannot be effectively conductive, resulting in a large impedance of the contact area, which reduces the on-state current of the thin film transistor. Figure 1 The contact impedance between the source / drain electrode and the active layer 11 ′ of the display substrate of the related art is tested, and the contact impedance between the source / drain electrode and the active layer 11 ′ reaches 20000Ω.

[0082] An exemplary embodiment of the present disclosure provides a display substrate, including:

[0083] A source / drain electrode is disposed on one side of the substrate;

[0084] An active layer is arranged on a side of the source / drain electrode away from the substrate, the active layer comprising a channel region and a first contact region and a second contact region;

[0085] A gate is arranged on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0086] A pixel electrode is arranged on a side of the gate away from the substrate; the pixel electrode is in direct contact with the first contact area;

[0087] A connecting electrode connects the second contact area to the source / drain electrode, and the connecting electrode and the pixel electrode are located in the same film layer and include the same conductive material.

[0088] The solution of this embodiment is described below by means of some examples.

[0089] In the following, the display substrate of this embodiment is used for a liquid crystal display (LCD) as an example, but the display substrate of this embodiment is not limited thereto. In another embodiment, the display substrate can be used for an organic light emitting diode (OLED) display device or a quantum dot light emitting diode (QLED) display device, etc.

[0090] Figure 2a A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure; Figure 2b Schematic diagram of a cross-sectional structure of a display substrate according to an exemplary embodiment of the present disclosure, wherein: Figure 2b for Figure 2a A cross-sectional view in the direction of AA'. In an exemplary embodiment, as Figure 2a and Figure 2b As shown, in a plane perpendicular to the display substrate, the display substrate at least includes a light shielding layer 21 and a source / drain electrode 14 sequentially arranged on a substrate 101, a first inorganic dielectric layer 41 arranged on a side of the light shielding layer 21 and the source / drain electrode 14 away from the substrate 101, an active layer 11 arranged on a side of the first inorganic dielectric layer 41 away from the substrate 101, a gate insulating layer 31 arranged on a side of the active layer 11 away from the substrate, a gate 13 arranged on a side of the gate insulating layer 31 away from the substrate 101, a second inorganic dielectric layer 42 arranged on a side of the gate 13 away from the substrate 101, an organic dielectric layer 43 arranged on a side of the second inorganic dielectric layer 42 away from the substrate 101, a common electrode 15 arranged on a side of the organic dielectric layer 43 away from the substrate 101, a third inorganic dielectric layer 44 arranged on a side of the common electrode 15 away from the substrate 101, and a pixel electrode 16 and a connecting electrode 17 arranged on a side of the third inorganic dielectric layer 44 away from the substrate 101.

[0091] In an exemplary embodiment, the active layer 11 includes a channel region 111 and a first contact region 112 and a second contact region 113. The first contact region 112 and the second contact region 113 are located at opposite sides of the channel region 111, and the first contact region 112 and the second contact region 113 can be connected to the channel region 111. The channel region 111 of the active layer 11 overlaps with the orthographic projection of the gate 13 on the substrate. The first contact region 112 and the second contact region 113 do not overlap with the orthographic projection of the gate 13 on the substrate.

[0092] In an exemplary embodiment, the channel region 111 of the active layer 11 overlaps with the orthographic projection of the light-shielding layer 21 on the substrate 101. In an exemplary embodiment, the orthographic projection of the channel region 111 of the active layer 11 on the substrate 101 is located in the orthographic projection of the light-shielding layer 21 on the substrate 101, so that the light-shielding layer 21 can completely block the channel region 111 of the active layer 11.

[0093] The disclosed embodiment displays a substrate that shields the channel region of the active layer through a shielding layer to prevent light from directly irradiating the channel region, thereby reducing the negative bias of the transistor gate threshold voltage (Vth) caused by light, solving the leakage problem of the display substrate, and ensuring the negative bias temperature illumination stress (nbtis) stability, thereby increasing the life of the display substrate.

[0094] In an exemplary embodiment, the pixel electrode 16 and the connecting electrode 17 are located in the same film layer and include the same conductive material. The pixel electrode 16 and the connecting electrode 17 are made of the same conductive film using the same etching process. The orthographic projections of the pixel electrode 16 and the connecting electrode 17 on the substrate do not overlap, and the pixel electrode 16 and the connecting electrode 17 are physically disconnected from each other.

[0095] The display substrate of the disclosed embodiment makes the connecting electrode and the pixel electrode located in the same film layer. During the preparation of the display substrate, the contact area of ​​the active layer is firstly conductive, and then the connecting electrode is formed to avoid the connecting electrode blocking the contact area, thereby making the contact area fully conductive, reducing the contact impedance, and increasing the on-state current, which is conducive to the realization of high refresh rate and high PPI products.

[0096] In an exemplary embodiment, the pixel electrode 16 is in direct contact with the first contact area 112 , and the pixel electrode 16 overlaps with the orthographic projection of the first contact area 112 on the substrate. For example, the orthographic projection of the first contact area 112 on the substrate is located in the orthographic projection of the pixel electrode 16 on the substrate.

[0097] In an exemplary embodiment, the connecting electrode 17 connects the second contact region 113 to the source / drain electrode 14, and the connecting electrode 17 overlaps with the orthographic projections of the second contact region 113 and the source / drain electrode 14 on the substrate, and the second contact region 113 overlaps with the orthographic projections of the source / drain electrode 14 on the substrate.

[0098] In an exemplary embodiment, the display substrate further includes a first hole 61 and a second via hole 62 disposed on the base 101 and extending in a direction perpendicular to the base, and the orthographic projections of the first hole 61 and the second via hole 62 on the base do not overlap.

[0099] In an exemplary embodiment, the first hole 61 overlaps with the orthographic projection of the first contact area 112 of the active layer 11 on the substrate. The first hole 61 extends from the surface of the third inorganic layer 44 away from the substrate, penetrates the third inorganic layer 44, the organic medium layer 43 and the second inorganic medium layer 42 in sequence, and extends to the first contact area 112 of the active layer 11, exposing at least a portion of the first contact area 112 of the active layer 11, and at least a portion of the pixel electrode 16 is in direct contact with the exposed first contact area 112 through the first hole 61.

[0100] In an exemplary embodiment, at least a portion of the pixel electrode 16 covers the sidewalls and the bottom wall of the first hole 61 , wherein the bottom wall of the first hole 61 is the surface of the first contact region 112 .

[0101] In an exemplary embodiment, the second via holes 62 overlap with the orthographic projections of the second contact area 113 and the source / drain electrode 14 on the substrate. The second via holes 62 extend from the surface of the third inorganic layer 44 away from the substrate, and sequentially penetrate the third inorganic layer 44, the organic dielectric layer 43, the second inorganic dielectric layer 42 and the first inorganic dielectric layer 41 to the source / drain electrode 14. The side walls of the second via holes 62 expose at least a portion of the second contact area 113, and the bottom walls of the second via holes 62 expose at least a portion of the source / drain electrode 14. At least a portion of the connecting electrode 17 connects the exposed second contact area 113 to the exposed source / drain electrode 14 through the second via holes 62.

[0102] In an exemplary embodiment, at least a portion of the connection electrode 17 covers the sidewalls and the bottom wall of the second hole 62 , wherein the bottom wall of the second hole 62 is the surface of the source / drain electrode 14 .

[0103] In an exemplary embodiment, the material of the active layer may include at least one of amorphous silicon, polycrystalline silicon and oxide. For example, the material of the active layer may be a metal oxide, and the metal oxide may include indium tin oxide (ITO), aluminum zinc oxide (AZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), a metal oxide containing In and / or Sn, etc. The metal oxide active layer has a large mobility, good uniformity, low process temperature, high light transmittance in the visible light region, and is suitable for flexible display.

[0104] right Figure 2bThe contact impedance between the source / drain electrode and the active layer of the display substrate of the present disclosure is tested, and the contact impedance between the source / drain electrode and the active layer reaches 7000Ω. It can be seen that the display substrate of the present disclosure connects the second contact area to the source / drain electrode through the connecting electrode. In the process of preparing the display substrate, the connecting electrode can avoid blocking the second contact area, making the second contact area fully conductive, reducing the contact impedance, thereby increasing the on-state current, which is conducive to the realization of high refresh rate and high PPI products.

[0105] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0106] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0107] (11) Forming a light shielding layer and source / drain electrodes. In an exemplary embodiment, forming the light shielding layer and the source / drain electrodes may include: depositing a first conductive film on the substrate 101, patterning the first conductive film by a patterning process, forming the light shielding layer 21 and the source / drain electrodes 14, such as Figure 3a and Figure 3b shown.

[0108] In an exemplary embodiment, on a plane parallel to the display substrate, the light shielding layer 21 has a rhombus shape, and the light shielding layer 21 is located on a side of the source / drain electrode 14 in the opposite direction to the first direction D1 .

[0109] In an exemplary embodiment, the source / drain electrode 14 is in a strip shape, extends along the second direction D2, and is located on the first direction D1 side of the light shielding layer 21. The first direction D1 and the second direction D2 are both parallel to the plane of the display substrate, and the first direction D1 and the second direction D2 intersect, and for example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0110] In an exemplary embodiment, the first conductive film may be made of a metal material, for example, at least one of titanium, copper, molybdenum-niobium alloy, and molybdenum-aluminum-titanium alloy.

[0111] (12) Forming an active layer. In an exemplary embodiment, forming the active layer may include: on the substrate on which the aforementioned pattern is formed, sequentially depositing a first inorganic insulating film and a semiconductor film on the substrate 101, patterning the first inorganic insulating film and the semiconductor film by a patterning process to form a first inorganic dielectric layer 41 covering the light shielding layer 21 and the source / drain electrode 14, and an active layer 11 disposed on the first inorganic dielectric layer 41, such as Figure 4a and Figure 4b shown.

[0112] In an exemplary embodiment, on a plane parallel to the display substrate, the active layer 11 includes a channel region 111 and a first contact region 112 and a second contact region 113, wherein the first contact region 112 and the second contact region 113 are located on both sides of the channel region 111 in the first direction D1, and the first contact region 112 and the second contact region 113 are connected through the channel region 111.

[0113] In an exemplary embodiment, the shape of the channel region 111 includes a stripe shape intersecting both the first direction D1 and the second direction D2 , and an orthographic projection of the channel region 111 on the substrate is located in an orthographic projection of the light shielding layer 21 on the substrate.

[0114] In an exemplary embodiment, the shape of the first contact region 112 includes a rectangle, which overlaps with the orthographic projection of the light shielding layer 21 on the substrate.

[0115] In an exemplary embodiment, the second contact region 113 has a strip shape extending along the first direction D1 , and the second contact region 113 overlaps with an orthographic projection of the source / drain electrode 14 on the substrate.

[0116] In an exemplary embodiment, the first inorganic dielectric layer 41 may be made of silicon oxide (SiO), silicon nitride (SiN), or a composite film layer of silicon nitride (SiN) and silicon oxide (SiO), and the thickness of the first inorganic dielectric layer 41 may be 200 nm to 500 nm.

[0117] (13) Forming a gate. In an exemplary embodiment, forming the gate may include: depositing a gate insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process, and forming a gate 13 disposed on the gate insulating film, wherein the gate 13 overlaps with an orthographic projection of the channel region 111 of the active layer 11 on the substrate 101;

[0118] Subsequently, the gate 13 is used as a mask to pattern-etch the gate insulating film, so that the gate insulating film forms a gate insulating layer 31 disposed on the active layer 11, and the gate insulating layer 31 overlaps with the orthographic projection of the channel region of the active layer 11 on the substrate 101, and the gate insulating layer 31 exposes the first contact region 112 and the second contact region 113 of the active layer 11; Figure 5a and Figure 5b shown.

[0119] In an exemplary embodiment, the orthographic projections of the gate 13 and the channel region 111 of the active layer 11 on the substrate 101 are both located in the orthographic projection of the light shielding layer 21 on the substrate 101 , so that the light shielding layer 21 can completely shield the channel region of the active layer 11 .

[0120] In an exemplary embodiment, the gate insulating layer 31 may be made of silicon oxide, and the thickness of the gate insulating layer 31 may be 10 nm to 30 nm.

[0121] In an exemplary embodiment, the second conductive film may be made of a metal material, for example, at least one of titanium, copper, molybdenum-niobium alloy, and molybdenum-aluminum-titanium alloy.

[0122] (14) Conducting the Active Layer In an exemplary embodiment, conducting the active layer may include: on the substrate on which the aforementioned pattern is formed, conducting the first contact region 112 and the second contact region 113 of the exposed active layer by a plasma process.

[0123] In an exemplary embodiment, the exposed first contact region 112 and the second contact region 113 of the active layer may be conductively treated by a plasma process using one or a mixture of helium (He), argon (Ar), hydrogen, and methane.

[0124] (15) Forming a second inorganic dielectric layer. In an exemplary embodiment, forming the second inorganic dielectric layer may include: depositing a second inorganic insulating film on the substrate having the aforementioned pattern, forming a second inorganic dielectric layer 42 covering the gate 13, the first contact region 112, and the second contact region 113, such as Figure 6 shown.

[0125] In an exemplary embodiment, the second inorganic dielectric layer 42 may be made of silicon oxide (SiO), or a composite film layer of silicon nitride (SiN) and silicon oxide (SiO), and the thickness of the first inorganic dielectric layer 41 may be 300 nm to 600 nm.

[0126] (16) Forming an organic dielectric layer, a first via hole, and a second via hole. In an exemplary embodiment, forming the organic dielectric layer, the first via hole, and the second via hole may include: first depositing an organic insulating film on the substrate formed with the aforementioned pattern, patterning the organic insulating film through a patterning process, so that the organic insulating film forms an organic dielectric layer 43 disposed on the second inorganic dielectric layer 42; then, performing an etching process on the organic dielectric layer 43 to form the first via hole 51 and the second via hole 52, such as Figure 7a and Figure 7b shown.

[0127] In an exemplary embodiment, the thickness of the organic medium layer is greater than or equal to 2 micrometers and less than or equal to 3 micrometers.

[0128] In the exemplary embodiment, the first via hole 51 and the second via hole 52 are both formed from the surface of the organic dielectric layer 43, penetrate the organic dielectric layer 43, and extend to the surface of the second inorganic dielectric layer 42, exposing the surface of the second inorganic dielectric layer 42. The first via hole 51 overlaps with the orthographic projection of the first contact area 112 of the active layer on the substrate, and the second via hole 52 overlaps with the orthographic projection of the second contact area 113 and the source / drain electrode 14 on the substrate.

[0129] In an exemplary embodiment, the orthographic projections of the first via hole 51 and the second via hole 52 on the substrate may be rectangular. The length of the first via hole 51 and the second via hole 52 may be greater than or equal to 4 microns and less than or equal to 6 microns, and the width of the first via hole 51 and the second via hole 52 may be greater than or equal to 4 microns and less than or equal to 6 microns.

[0130] In some embodiments, the orthographic projections of the first via hole and the second via hole on the substrate may include shapes such as circle, ellipse, triangle, rhombus, trapezoid, pentagon, hexagon, etc., which will not be described in detail in the present disclosure.

[0131] (17) Forming a common electrode, a third via hole, and a fourth via hole. In an exemplary embodiment, forming the common electrode, the third via hole, and the fourth via hole may include: first depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process, so that the third conductive film forms a common electrode 15 disposed on the organic dielectric layer 43; then, performing an etching process on the common electrode 15 to form a third via hole 53 and a fourth via hole 54 penetrating the common electrode 15, wherein the common electrode 15 in the third via hole 53 and the fourth via hole 54 is etched away, and the second inorganic dielectric layer 42 in the third via hole 53 and the fourth via hole 54 is not etched away, as shown in FIG. Figure 8a and Figure 8b shown.

[0132] In an exemplary embodiment, the orthographic projections of the third via hole 53 and the first via hole 51 on the substrate overlap, and the third via hole 53 is connected to the first via hole 51. For example, the orthographic projection of the first via hole 51 on the substrate is located in the orthographic projection of the third via hole 53 on the substrate. The common electrode 15 in the first via hole 51 is etched away to expose the second inorganic dielectric layer 42 on the first contact area 112.

[0133] In an exemplary embodiment, the orthographic projections of the fourth via hole 54 and the second via hole 52 on the substrate overlap, and the fourth via hole 54 is connected to the second via hole 52. For example, the orthographic projection of the second via hole 52 on the substrate is located in the orthographic projection of the fourth via hole 54 on the substrate. The common electrode 15 in the second via hole 52 is etched away to expose the second inorganic dielectric layer 42 on the second contact area 113.

[0134] In an exemplary embodiment, the orthographic projections of the third via hole 53 and the fourth via hole 54 on the substrate may be rectangular. In some embodiments, the orthographic projections of the third via hole and the fourth via hole on the substrate may include circular, elliptical, triangular, rhombus, trapezoidal, pentagonal, hexagonal, etc., which are not described in detail in this disclosure.

[0135] In an exemplary embodiment, the common electrode 15 may be made of a transparent conductive material such as indium tin oxide (ITO).

[0136] (18) Forming a third inorganic dielectric layer, a fifth via hole, and a sixth via hole. In an exemplary embodiment, forming the third inorganic dielectric layer, the fifth via hole, and the sixth via hole may include: first depositing a third inorganic insulating film on the substrate formed with the aforementioned pattern, patterning the third inorganic insulating film through a patterning process, so that the third inorganic insulating film forms a third inorganic dielectric layer 44 covering the common electrode 15; then, performing an etching process on the third inorganic layer 44 to form a fifth via hole 55 and a sixth via hole 56 penetrating the third inorganic layer 44, as shown in FIG. Figure 9a and Figure 9b shown.

[0137] In an exemplary embodiment, the third inorganic dielectric layer 44 covers the sidewalls of the third via hole and the fourth via hole, and covers the sidewalls of the common electrode 15 corresponding to the third via hole and the fourth via hole.

[0138] In an exemplary embodiment, the fifth via hole 55 overlaps with the orthographic projections of the third via hole 53 and the first via hole 51 on the substrate, and the third via hole 53 is connected to the third via hole 53 and the first via hole 51. For example, the orthographic projection of the first via hole 51 on the substrate is located in the orthographic projection of the fifth via hole 55 on the substrate, and the orthographic projection of the fifth via hole 55 on the substrate is located in the orthographic projection of the third via hole 53 on the substrate. In the process of forming the fifth via hole 55, the third inorganic dielectric layer 44 and the second inorganic dielectric layer 42 in the first via hole 51 are etched away at the same time, that is, the third inorganic layer 44 and the second inorganic dielectric layer 42 on the first contact area 112 are etched away at the same time, and the interconnected parts of the first via hole 51, the third via hole 53 and the fifth via hole 55 form a first hole, and the first hole exposes at least a portion of the first contact area 112.

[0139] In an exemplary embodiment, the sixth via hole 56 overlaps with the orthographic projections of the fourth via hole 54 and the second via hole 52 on the substrate, and the sixth via hole 56 is connected to the fourth via hole 54 and the second via hole 52. For example, the orthographic projection of the second via hole 52 on the substrate is located in the orthographic projection of the sixth via hole 56 on the substrate, and the orthographic projection of the sixth via hole 56 on the substrate is located in the orthographic projection of the fourth via hole 54 on the substrate. In the process of forming the sixth via hole 56, the third inorganic dielectric layer 44, the second inorganic dielectric layer 42 and the first inorganic dielectric layer 41 in the second via hole 52 are etched away at the same time, that is, the third inorganic dielectric layer 44, the second inorganic dielectric layer 42 and the first inorganic dielectric layer 41 on the second contact area 113 are etched away at the same time, and the interconnected portions of the second via hole 52, the fourth via hole 54 and the sixth via hole 56 form a second hole, the sidewall of the second hole exposes at least a portion of the source / drain electrode 14, and the bottom wall of the second hole exposes at least a portion of the second contact area 113.

[0140] In the embodiment of the present disclosure, the second inorganic insulating film and the third inorganic insulating film on the first contact region are etched simultaneously to expose the first contact region, thereby simplifying the preparation process and reducing the production cost.

[0141] The embodiment of the present disclosure simultaneously etches the first inorganic insulating film, the second inorganic insulating film and the third inorganic insulating film on the second contact region to expose the second contact region, thereby simplifying the preparation process and reducing the production cost.

[0142] In an exemplary embodiment, the orthographic projections of the fifth via hole 55 and the sixth via hole 56 on the substrate may be rectangular. In some embodiments, the orthographic projections of the fifth via hole and the sixth via hole on the substrate may include circular, elliptical, triangular, rhombus, trapezoidal, pentagonal, hexagonal, etc., which are not described in detail in this disclosure.

[0143] In an exemplary embodiment, the third inorganic dielectric layer 44 may be formed of silicon oxide (SiO), silicon nitride (SiN), or a composite film layer of silicon nitride (SiN) and silicon oxide (SiO).

[0144] (19) Forming a pixel electrode. The pixel electrode is formed by depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film through a patterning process, and forming a pixel electrode 16 and a connecting electrode 17 disposed on the third inorganic dielectric layer 44, wherein the pixel electrode 16 covers the bottom wall and the side wall of the first hole 61 to a portion thereof, and is in direct contact with the exposed first contact area 112; the connecting electrode 17 covers the bottom wall and the side wall of the second hole 62 to a portion thereof, and the connecting electrode 17 connects the exposed first contact area 113 to the exposed source / drain electrode 14, as shown in FIG. Figure 2a and Figure 2b shown.

[0145] right Figure 1 The display substrate of the related art shown in the figure is subjected to a light simulation test, with a bias voltage of -30V, a backlight brightness of 5000nit, and a time of 1H. Fig.10 As shown, at 0 seconds, the voltage of the active layer is 1.36V; at 3600 seconds, the active layer is approximately a conductor and the transistor threshold voltage is approximately a conductor.

[0146] The inventors of the present invention have discovered through research that in a negative bias illumination test of a top-gate thin-film transistor, backlight will be reflected through the gate metal into the channel region of the active layer, thereby affecting the illumination stability of the thin-film transistor device and easily causing the device characteristics to drift negatively or become a conductor.

[0147] Fig.11a It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure; Fig.11b FIG. 1 is a schematic cross-sectional structure diagram of another display substrate of an exemplary embodiment of the present disclosure. Fig.11b for Fig.11a A-A' sectional view. Fig.11a and Fig.11b As shown, this exemplary embodiment shows the structure of the substrate and Figure 2bThe structure of the display substrate shown is basically the same, except that the display substrate of this exemplary embodiment further includes a photoresist layer 60, which is disposed on the side of the channel region 111 of the gate 13 close to the active layer 11. For example, the photoresist layer 60 is disposed between the gate 13 and the gate insulating layer 31. The orthographic projections of the gate 13 and the photoresist layer 60 on the substrate overlap, and the photoresist layer 60 is configured to absorb light and reduce the light reflected to the active layer 11 through the gate 13. For example, the orthographic projection of the gate 13 on the substrate is located in the orthographic projection of the photoresist layer 60 on the substrate.

[0148] The display substrate of the embodiment of the present disclosure reduces the reflection of light by the gate 13 through the photoresist layer 60, reduces the irradiation of the active layer 11 by the light reflected by the gate 13, and improves the light stability of the thin film transistor in the display substrate.

[0149] In an exemplary embodiment, the photoresist layer 60 may be a black photoresist and has a thickness greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers.

[0150] In an exemplary embodiment, the preparation process of the photoresist layer 60 of the substrate shown in the embodiment of the present disclosure is: first, a gate insulating film is deposited; then, a black photoresist film is coated on the gate insulating film; then, a conductive film is deposited on the black photoresist film; then, the conductive film is patterned and etched to form a gate 13; then, using the gate 13 as a mask, the gate insulating film and the black photoresist film are patterned and etched to form a gate insulating layer 31 from the gate insulating film, and to form a photoresist layer 60 from the black photoresist film.

[0151] right Fig.11b The display substrate shown in the figure is subjected to a light simulation test with a bias voltage of -30V, a backlight brightness of 5000nit, and a time of 1H. Fig.12 As shown, at 0 seconds, the voltage of the active layer is 1.16V; at 3600 seconds, the voltage of the active layer is -3.3, and the transistor threshold voltage is -4.46. It can be seen that the photoresist layer 60 of the display substrate of the embodiment of the present disclosure can reduce the reflection of light by the gate 13, and improve the light stability of the thin film transistor in the display substrate.

[0152] The present disclosure also provides a method for preparing a display substrate, comprising:

[0153] forming source / drain electrodes on a substrate;

[0154] An active layer is formed on a side of the source / drain electrode away from the substrate, wherein the active layer includes a channel region and a first contact region and a second contact region;

[0155] forming a gate on a side of the active layer away from the substrate, wherein at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0156] Conducting the first contact area and the second contact area;

[0157] A conductive film is formed on the side of the gate away from the substrate, so that the conductive film forms a pixel electrode and a connecting electrode, the pixel electrode is in direct contact with the first contact area, and the connecting electrode connects the second contact area with the source / drain electrode.

[0158] The present disclosure also provides a method for preparing a display substrate, comprising:

[0159] forming source / drain electrodes on a substrate;

[0160] forming a first inorganic dielectric layer on a side of the source / drain electrode away from the substrate;

[0161] An active layer is formed on a side of the first inorganic dielectric layer away from the substrate, wherein the active layer includes a channel region and a first contact region and a second contact region;

[0162] forming a gate on a side of the active layer away from the substrate, wherein at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate;

[0163] Conducting the first contact area and the second contact area;

[0164] forming a second inorganic dielectric layer on a side of the gate away from the substrate;

[0165] forming an organic dielectric layer on a side of the second inorganic dielectric layer away from the substrate;

[0166] forming a first via hole and a second via hole penetrating the organic dielectric layer, wherein at least a portion of the first via hole overlaps with an orthographic projection of the first contact area on the substrate, and at least a portion of the second via hole overlaps with an orthographic projection of the second contact area and the source / drain electrode on the substrate;

[0167] forming a third inorganic dielectric layer covering the first via hole and the second via hole on a side of the organic dielectric layer away from the substrate;

[0168] The second inorganic dielectric layer and the third inorganic dielectric layer in the first via hole are etched away to expose at least a portion of the first contact area; the first inorganic dielectric layer, the second inorganic dielectric layer and the third inorganic dielectric layer in the second via hole are etched away to expose at least a portion of the first contact area and at least a portion of the source / drain electrode;

[0169] A conductive film is formed on the side of the third inorganic dielectric layer away from the substrate, so that the conductive film forms a pixel electrode and a connecting electrode, the pixel electrode is in direct contact with the exposed first contact area, and the connecting electrode connects the exposed second contact area with the exposed source / drain electrode.

[0170] The embodiment of the present invention further provides a display device, comprising any of the above-mentioned display substrates. The display device includes a mobile phone, a tablet computer, a smart wearable product (such as a smart watch, a bracelet, etc.), a personal digital assistant (PDA), a car computer, etc. The embodiment of the present disclosure does not impose any special restrictions on the specific form of the above-mentioned foldable display device.

[0171] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0172] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A source / drain electrode is disposed on one side of the substrate; An active layer is arranged on a side of the source / drain electrode away from the substrate, the active layer comprising a channel region and a first contact region and a second contact region; A gate is arranged on a side of the active layer away from the substrate, and at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate; A pixel electrode, arranged on a side of the gate away from the substrate; The pixel electrode is in direct contact with the first contact area; A connecting electrode connects the second contact area to the source / drain electrode, and the connecting electrode and the pixel electrode are located in the same film layer and include the same conductive material.

2. The display substrate according to claim 1, characterized in that: It also includes a first hole disposed on the substrate and extending in a direction perpendicular to the substrate, wherein the first hole exposes at least a portion of the first contact area, and the pixel electrode is in direct contact with the exposed first contact area through the first hole.

3. The display substrate according to claim 2, characterized in that: It also includes a second inorganic dielectric layer, an organic dielectric layer, and a third inorganic dielectric layer, which are arranged in sequence on the side of the gate close to the pixel electrode along a direction away from the substrate. The first hole extends from the surface of the third inorganic dielectric layer away from the substrate, penetrates the third inorganic dielectric layer, the organic dielectric layer and the second inorganic dielectric layer in sequence, and extends to the active layer, exposing at least a portion of the first contact area.

4. The display substrate according to claim 2, characterized in that: At least a portion of the pixel electrode covers the sidewalls and the bottom wall of the first hole.

5. The display substrate according to claim 1, characterized in that: It also includes a second via hole arranged on the substrate and extending in a direction perpendicular to the substrate, the second via hole exposing at least a portion of the source / drain electrode and at least a portion of the second contact area, and the connecting electrode connects the exposed source / drain electrode with the exposed second contact area through the second via hole.

6. The display substrate according to claim 5, characterized in that: It also includes a first inorganic dielectric layer arranged between the source / drain electrode and the active layer, and a second inorganic dielectric layer, an organic dielectric layer, and a third inorganic dielectric layer arranged in sequence on the side of the gate close to the pixel electrode along a direction away from the substrate, wherein the second via hole extends from the surface of the third inorganic dielectric layer away from the substrate, penetrates the third inorganic dielectric layer, the organic dielectric layer, the second inorganic dielectric layer, and the first inorganic dielectric layer in sequence, and extends to the source / drain electrode, the side wall of the second via hole exposes at least a portion of the second contact area, and the bottom wall of the second via hole exposes at least a portion of the source / drain electrode.

7. The display substrate according to claim 5, characterized in that: At least a portion of the connecting electrode covers the sidewall and the bottom wall of the second via hole.

8. The display substrate according to any one of claims 1 to 7, characterized in that: The orthographic projections of the pixel electrode and the connecting electrode on the substrate do not overlap.

9. The display substrate according to any one of claims 1 to 7, characterized in that: The second contact region overlaps with an orthographic projection of the source / drain electrode on the substrate.

10. The display substrate according to any one of claims 1 to 7, characterized in that: It also includes a light shielding layer, which is arranged on a side of the channel region of the active layer close to the substrate and overlaps with the orthographic projection of the channel region of the active layer on the substrate.

11. The display substrate according to any one of claims 1 to 7, characterized in that: The material of the active layer is metal oxide.

12. A display device, characterized in that: The display substrate comprises any one of claims 1 to 11.

13. A method for preparing a display substrate, characterized in that: include: forming source / drain electrodes on a substrate; An active layer is formed on a side of the source / drain electrode away from the substrate, wherein the active layer includes a channel region and a first contact region and a second contact region; forming a gate on a side of the active layer away from the substrate, wherein at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate; Conducting the first contact area and the second contact area; A conductive film is formed on the side of the gate away from the substrate, so that the conductive film forms a pixel electrode and a connecting electrode, the pixel electrode is in direct contact with the first contact area, and the connecting electrode connects the second contact area with the source / drain electrode.

14. A method for preparing a display substrate, characterized in that: include: forming source / drain electrodes on a substrate; forming a first inorganic dielectric layer on a side of the source / drain electrode away from the substrate; An active layer is formed on a side of the first inorganic dielectric layer away from the substrate, wherein the active layer includes a channel region and a first contact region and a second contact region; forming a gate on a side of the active layer away from the substrate, wherein at least a portion of the gate overlaps with an orthographic projection of the channel region on the substrate; Conducting the first contact area and the second contact area; forming a second inorganic dielectric layer on a side of the gate away from the substrate; forming an organic dielectric layer on a side of the second inorganic dielectric layer away from the substrate; forming a first via hole and a second via hole penetrating the organic dielectric layer, wherein at least a portion of the first via hole overlaps with an orthographic projection of the first contact area on the substrate, and at least a portion of the second via hole overlaps with an orthographic projection of the second contact area and the source / drain electrode on the substrate; forming a third inorganic dielectric layer covering the first via hole and the second via hole on a side of the organic dielectric layer away from the substrate; Etching and removing the second inorganic dielectric layer and the third inorganic dielectric layer in the first via hole to expose at least a portion of the first contact area; The first inorganic dielectric layer, the second inorganic dielectric layer and the third inorganic dielectric layer in the second via hole are removed by etching to expose at least a portion of the first contact region and at least a portion of the source / drain electrode; A conductive film is formed on the side of the third inorganic dielectric layer away from the substrate, so that the conductive film forms a pixel electrode and a connecting electrode, the pixel electrode is in direct contact with the exposed first contact area, and the connecting electrode connects the exposed second contact area with the exposed source / drain electrode.

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