Display panel

Abstract

A display panel is provided, the display panel including: a base layer; a unit pixel; comprising a first pixel, a second pixel and a third pixel; a first power line; a sensing line; a scan line; and a first data line, a second data line, and a third data line spaced apart along the first direction, extending along the second direction, and connected to the first pixel, the second pixel, and the third pixel, the first pixel, the second pixel and the third pixel each include a first transistor, a second transistor and a third transistor, a capacitor and a light emitting element over the base layer, and wherein the capacitor of the first pixel is spaced apart from the capacitor of the second pixel along a second direction, and the capacitor of the first pixel and the capacitor of the second pixel are spaced apart from the capacitor of the third pixel along the first direction.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0130220, filed on September 27, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure herein relates to display panels including circuit elements having improved reliability. Background Art

[0003] The display panel includes a plurality of pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) configured to control the plurality of pixels. The plurality of pixels each include a display element and a pixel driving circuit configured to control the display element. The pixel driving circuit may include a plurality of organically connected transistors and at least one capacitor. Summary of the invention

[0004] The present disclosure provides a display panel with improved display quality.

[0005] One or more embodiments of the present disclosure provide a display panel, which includes: a substrate layer; unit pixels, including a first pixel, a second pixel, and a third pixel above the substrate layer, the first pixel, the second pixel, and the third pixel are arranged along a first direction and a second direction intersecting each other, and each includes a first transistor, a second transistor, and a third transistor, a capacitor, and a light-emitting element above the substrate layer; a first power line extending along the first direction; a sensing line extending along the first direction and spaced apart from the first power line along the second direction; a scanning line extending along the first direction and spaced apart from the first power line along the second direction, and the sensing line is between the scanning line and the first power line; and a first data line, a second data line, and a third data line, which are spaced apart along the first direction, extend along the second direction, and are respectively connected to the first pixel, the second pixel, and the third pixel, wherein the capacitor of the first pixel is spaced apart from the capacitor of the second pixel along the second direction, and wherein the capacitor of the first pixel and the capacitor of the second pixel are spaced apart from the capacitor of the third pixel along the first direction.

[0006] The capacitor may be between the sensing line and the scanning line, wherein the sensing line overlaps an upper portion of the capacitor, and wherein the scanning line overlaps a lower portion of the capacitor.

[0007] The first data line may be between the second data line and the third data line, wherein the capacitor is between the first data line and the third data line.

[0008] The capacitors may include upper electrodes, respectively, and include first, second, and third light-blocking patterns over the base layer as corresponding lower electrodes, respectively.

[0009] The display panel may further include a first capacitor pattern overlapping the first light blocking pattern, a second capacitor pattern overlapping the second light blocking pattern, and a third capacitor pattern overlapping the third light blocking pattern as upper electrodes, respectively.

[0010] A portion of the first capacitor pattern that does not overlap with the first light blocking pattern may include an active pattern of a second transistor of the first pixel, wherein a portion of the second capacitor pattern that does not overlap with the second light blocking pattern includes an active pattern of a second transistor of the second pixel, and wherein a portion of the third capacitor pattern that does not overlap with the third light blocking pattern includes an active pattern of a second transistor of the third pixel.

[0011] The scan line may include a first pattern and a second pattern protruding along the second direction and spaced apart along the first direction, the first pattern overlapping the active pattern of the second transistor of the first pixel and the active pattern of the second transistor of the second pixel, and the second pattern overlapping the active pattern of the second transistor of the third pixel.

[0012] Portions of the first and second patterns overlapping the active patterns of the first, second, and third pixels may include gates of second transistors of the first, second, and third pixels.

[0013] The second capacitor pattern may include a 2-1st capacitor pattern and a 2-2nd capacitor pattern spaced apart along the second direction, wherein the active pattern of the first transistor of the second pixel is between the 2-1st capacitor pattern and the 2-2nd capacitor pattern.

[0014] The display panel may further include a gate pattern including a gate of the first transistor of the second pixel overlapping the active pattern of the first transistor of the second pixel, the gate pattern connecting the 2-1st capacitor pattern and the 2-2nd capacitor pattern.

[0015] The display panel may further include: a first insulating layer, which is above the base layer and covers the first data line, the second data line, and the third data line and the first light blocking pattern, the second light blocking pattern, and the third light blocking pattern; a second insulating layer, which is above the first insulating layer and covers the first capacitor pattern, the second capacitor pattern, and the third capacitor pattern; a third insulating layer, which is above the second insulating layer and covers the first power line, the sensing line, and the scan line; and a pixel defining layer, which is above the third insulating layer and defines an opening that exposes at least a portion of the first electrode of the light emitting element.

[0016] Among the openings, the opening corresponding to the first electrode of the first pixel can be defined as a first pixel region, the opening corresponding to the first electrode of the second pixel is defined as a second pixel region, and the opening corresponding to the first electrode of the third pixel is defined as a third pixel region, wherein an area of ​​the second pixel region is smaller than an area of ​​the first pixel region and larger than an area of ​​the third pixel region.

[0017] The second pixel region and the third pixel region may be spaced apart along the first direction, wherein the first pixel region is spaced apart from the second pixel region and the third pixel region in respective inclined directions that are inclined with respect to the first direction and the second direction.

[0018] The display panel may further include a second power line connected to the second electrodes of the first pixel, the second pixel, and the third pixel, the second power line being over the base layer, extending along the second direction, and spaced apart from the second data line along the first direction.

[0019] In one or more embodiments of the present disclosure, the display panel includes: a base layer; a first pixel, a second pixel, and a third pixel, which are above the base layer and each include a first transistor, a second transistor, and a third transistor, a capacitor, and a light-emitting element; a first data line, a second data line, and a third data line, which are spaced apart along a first direction and extend along a second direction intersecting the first direction; a first power line, which extends along the first direction; a sensing line, which extends along the first direction; a scanning line, which extends along the first direction; a second power line, which extends along the second direction; and an initial line, which extends along the second direction, wherein the second power line, the second data line, the first data line, the capacitor of the first pixel, the capacitor of the second pixel, the initial line, the capacitor of the third pixel, and the third data line are arranged sequentially along the first direction.

[0020] The first power line may be spaced apart from the scan line along the second direction, and the sensing line is between the first power line and the scan line, wherein the capacitor of the first pixel, the capacitor of the second pixel, and the capacitor of the third pixel are between the sensing line and the scan line.

[0021] The capacitor of the first pixel may be spaced apart from the capacitor of the second pixel along the second direction, wherein the capacitor of the first pixel and the capacitor of the second pixel are spaced apart from the capacitor of the third pixel along the first direction.

[0022] The initial line may be between the capacitor of the third pixel and the capacitor of the first pixel and the capacitor of the second pixel.

[0023] The display panel may also include: a first insulating layer, which is above the base layer and covers the first data line, the second data line and the third data line, the second power line and the initial line; a second insulating layer, which is above the first insulating layer and covers the active pattern of the first transistor, the second transistor and the third transistor; a third insulating layer, which is above the second insulating layer and covers the first power line, the sensing line and the scan line; and a pixel defining layer, which is above the third insulating layer and defines an opening that exposes at least a portion of the first electrode of the light emitting element defined therein.

[0024] The capacitor may include a lower electrode over the base layer and covered by the first insulating layer, and an upper electrode over the first insulating layer and covered by the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present disclosure and together with the description are used to explain aspects of the present disclosure. In the drawings: Figure 1A is a perspective view of a display panel according to one or more embodiments of the present disclosure; Figure 1B is a perspective view of a curved display panel according to one or more embodiments of the present disclosure; Figure 2A is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure; Figure 2B is a plan view of a display panel according to one or more embodiments of the present disclosure; Figure 3 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure; Figure 4 is a plan view of an enlarged display area according to one or more embodiments of the present disclosure; Figure 5A is a plan view according to a stacking order of conductive patterns included in a unit pixel according to one or more embodiments of the present disclosure; Figure 5B It is along Figure 5A A cross-sectional view of the display panel taken along line II'; and FIG. 6A to FIG. 6G is a plan view of a stacking order of conductive patterns included in a unit pixel divided by layers according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for implementing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0027] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown here. In describing the embodiments, the use of "may", "may" or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and alternatives within the conceptual and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives are technically possible. The various embodiments may be implemented independently of each other, or may be implemented together in association.

[0028] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0029] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the diagrams caused by, for example, manufacturing techniques and / or tolerances are expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structures or functional descriptions disclosed herein are merely exemplary. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes shown for elements, layers, or regions, but will include deviations in shapes caused by, for example, manufacturing.

[0030] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0031] For ease of explanation, spatial relative terms such as "under ...", "below ...", "lower", "under ...", "under ...", "above ...", "upper", "upper side", etc. may be used here to describe the relationship between one element or feature and another (other) element or feature as shown in the figure. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as "under" "under" or "below" other elements or features will then be oriented to be "above" other elements or features. Therefore, the example terms "under ..." and "under ..." can include both upper and lower orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used here should be interpreted accordingly. Similarly, when a first part is described as being arranged "on" a second part, this means that the first part is arranged at the upper or lower side of the second part, and is not limited to the upper side of the second part based on the direction of gravity.

[0032] In addition, the phrase "in a plan view" means when the target portion is observed from above, and the phrase "in a schematic cross-sectional view" means when the schematic cross-section taken by vertically cutting the target portion is observed from the side. The term "superimposed" or "superimposed" means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "superimposed" may include stacking, facing or facing, extending thereon, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-superimposed" may include the meaning of any other suitable equivalent such as "spaced apart from..." or "separated from..." or "deviated from..." and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, although the first object and the second object still face each other, it can be understood as being indirectly opposite to each other.

[0033] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that one or more intermediate elements, layers, regions, or components may be present. Additionally, this may collectively represent direct or indirect coupling or connection, as well as integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or one or more intermediate layers, regions, or components may be present. One or more intermediate components may include switches, resistors and / or capacitors, etc. When describing the embodiments, unless explicitly described as directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on" means that one component is directly connected or directly coupled to another component, or is directly on another component without intermediate components.

[0034] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly below" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components (such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to...") can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0035] For the purposes of this disclosure, when a statement such as "at least one of..." or "any one of..." or "one or more of..." is located after a list of elements, the entire list of elements is modified without modifying the individual elements in the list. For example, "at least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the statement "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. For example, the statement "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0036] It will be understood that, although the terms "first", "second", "third", etc. can be used here to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, component or part from another element, member, component, region, area, layer, component or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below can be referred to as the second element, component, region, layer or part. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used here to distinguish between different categories or groups of elements. For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0037] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0038] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "one (kind / person)" are also intended to include plural forms, and the plural forms are also intended to include singular forms. It will also be understood that when the terms "including", "having", "comprising" and their variations are used in this specification, the stated features, wholes, steps, operations, elements and / or components are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups are not excluded.

[0039] As used herein, the terms "substantially", "approximately", "approximately" and similar terms are used as approximate terms, not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values ​​that one of ordinary skill in the art would recognize. For example, "substantially" may include a range of + / - 5% of the corresponding value. As used herein, "approximately" or "approximately" includes the stated value and means: within an acceptable range of deviations of a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0041] Figure 1A is a perspective view of a display panel according to one or more embodiments of the present disclosure. Figure 1B is a perspective view of a curved display panel according to one or more embodiments of the present disclosure. Figure 2A is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure. Figure 2B is a plan view of a display panel according to one or more embodiments of the present disclosure. Figure 3 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure. Figure 4 is a plan view of an enlarged display area according to one or more embodiments of the present disclosure.

[0042] Figure 1A and Figure 1B The display panels DP and DP-1 shown in the figure are light-emitting display panels, and may be any one of a liquid crystal display panel, an electrophoretic display panel, a micro-electromechanical system (MEMS) display panel, an electrowetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel, and a quantum dot display panel. In addition, the display panels DP and DP-1 according to one or more embodiments of the present disclosure may include ultra-small light-emitting elements. For example, the display panels DP and DP-1 may include micro-LED elements and / or nano-LED elements, but are not particularly limited thereto.

[0043] Reference Figure 1A , the display panel DP may display an image through the display surface DP-IS. The upper surface of the member disposed on the uppermost side of the display panel DP may be defined as the display surface DP-IS. According to one or more embodiments of the present disclosure, Figure 2A An upper surface of the window panel WD shown in FIG. 4 may be provided as a display surface DP-IS of the display panel DP.

[0044] The display surface DP-IS may be parallel to a plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DP-IS (i.e., the thickness direction of the display panel DP) is indicated by a third direction DR3. The front surface (or upper surface) and the rear surface (or lower surface) of each layer or unit to be described below are separated by the third direction DR3.

[0045] The display panel DP may include a display area DA and a non-display area NDA. Figure 2B ) in the emission layer EML (see Figure 5B ) is disposed in the display area DA, including an emission layer EML in the pixel PXnm (see Figure 5B ) is not set in the non-display area NDA. The non-display area NDA is defined along the edge of the display surface DP-IS. The non-display area NDA may surround the display area DA. In one or more embodiments of the present disclosure, the non-display area NDA may not be set, or the non-display area NDA may be set only on one side of the display area DA.

[0046] Reference Figure 1B According to one or more embodiments, the display panel DP-1 may be bent along the first direction DR1 relative to a virtual axis AX extending in the second direction DR2. However, the present disclosure is not limited thereto, and the axis may extend in the first direction DR1, or the display panel DP-1 may be bent relative to a plurality of axes extending in different directions.

[0047] According to one or more embodiments, the display panels DP and DP-1 may be rollable display panels, foldable display panels, or slidable display panels. In this case, the display panels DP and DP-1 have flexible characteristics and may be folded or rolled when installed in a display device. Therefore, the display panels DP and DP-1 may include a curved display surface DP-IS or a three-dimensional display surface DP-IS. The three-dimensional display surface DP-IS may include a plurality of display areas indicating different directions.

[0048] The unit pixel PXU is shown as being arranged at Figure 1A and Figure 1B The unit pixel PXU may include at least two pixels for providing different lights. For example, the unit pixel PXU may be a region in which a pixel providing source light is disposed. The light emitting region, shape, and arrangement of each of the pixels included in the unit pixel PXU are not limited to any one. For example, the light emitting region of each of the pixels included in the unit pixel PXU may be different. In addition, when viewed on a plane (e.g., in a plan view), each of the light emitting regions may have a circular shape or a polygonal shape.

[0049] Reference Figure 2A and Figure 2B , the display panel DP according to one or more embodiments of the present disclosure includes a base layer BS, a circuit element layer DP-CL positioned on the base layer BS, a display element layer DP-OLED, an encapsulation layer TFE, a light control layer OSL and a window panel WD. The display panel DP may also include a functional layer such as an anti-reflection layer or a refractive index control layer. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. Hereinafter, the insulating layer may include an organic layer and / or an inorganic layer.

[0050] The base layer BS may include a synthetic resin film. The synthetic resin layer may include a thermosetting resin. For example, the synthetic resin layer may include at least any one of acrylic resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. In addition, the base layer BS may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0051] The circuit element layer DP-CL can form an insulating layer, a semiconductor layer, and a conductive layer by a process such as coating or deposition. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned by photolithography and etching. Through this process, a semiconductor pattern, a conductive pattern, a signal line, etc. are formed. A pattern positioned at the same layer is formed by the same process.

[0052] The circuit element layer DP-CL includes a driving circuit or a signal line constituting a pixel PX. The display element layer DP-OLED may include a pixel definition layer PDL (see Figure 5B ) and a light-emitting element OLED included in the pixel PX.

[0053] The encapsulation layer TFE may be positioned on the display element layer DP-OLED to protect the light emitting element OLED. The encapsulation layer TFE may include an inorganic layer and an organic layer positioned between the inorganic layers. The inorganic layer may protect the light emitting element OLED from moisture and oxygen, and the organic layer may protect the light emitting element OLED from foreign matter such as dust particles.

[0054] The light control layer OSL may include a light control pattern that may change the optical characteristics of the source light generated from the light emitting element. The light control pattern may include quantum dots, and may include a color filter pattern that selectively transmits light passing through the light control pattern.

[0055] The window panel WD may be positioned above the display element layer DP-OLED, and may transmit an image provided from the display element layer DP-OLED to the outside. Figure 1A As shown in , the window panel WD may separate a display area DA and a non-display area NDA of the display surface DP-IS. A boundary between the display area DA and the non-display area NDA may be defined by a bezel pattern positioned under the window panel WD and absorbing light.

[0056] The window panel WD may include a base layer and a functional layer positioned on the base layer. The functional layer may include a protective layer, an anti-fingerprint layer, etc. The base layer of the window panel WD may be formed of glass, sapphire, or plastic.

[0057] Figure 2B A planar arrangement relationship of signal lines SL1 to SLn and DL1 to DLm and pixels PX11 to PXnm included in the display panel DP is shown. The signal lines SL1 to SLn and DL1 to DLm may include a plurality of scan lines SL1 to SLn and a plurality of data lines DL1 to DLm.

[0058] The pixels PX11 to PXnm may be positioned in the display area DA. The pixels PX11 to PXnm are each connected to a corresponding scan line among a plurality of scan lines SL1 to SLn and a corresponding data line among a plurality of data lines DL1 to DLm. The pixels PX11 to PXnm may each include a pixel driving circuit and a light emitting element. According to the configuration of the pixel driving circuit of the pixels PX11 to PXnm, more various types of signal lines may be provided in the display panel DP.

[0059] The gate driving circuit GDC may be positioned in the non-display area NDA. The gate driving circuit GDC may be integrated on the display panel DP through an oxide silicon gate (OSG) driving circuit process or an amorphous silicon gate (ASG) driving circuit process.

[0060] Figure 3 A circuit diagram of one pixel PXij among the pixels PX11 to PXnm is shown.

[0061] The pixel PXij may include a pixel circuit PC and a light emitting element OLED. The pixel circuit PC may include a plurality of transistors T1, T2 and T3 and a capacitor Cst.

[0062] According to one or more embodiments of the present disclosure, any one pixel PXij may include dual capacitors that are spaced apart from each other and connected through a conductive pattern. A description thereof will be provided later.

[0063] The plurality of transistors T1, T2, and T3 may be formed by a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process. Each of the first transistor T1, the second transistor T2, and the third transistor T3 may include any one of a silicon semiconductor and an oxide semiconductor. In this case, the oxide semiconductor may include a crystalline oxide semiconductor or an amorphous oxide semiconductor, and the silicon semiconductor may include amorphous silicon or polycrystalline silicon, etc., but the present disclosure is not limited to any one embodiment.

[0064] Hereinafter, the first transistor T1, the second transistor T2, and the third transistor T3 are described as N-type, but not limited thereto, and each of the first transistor T1, the second transistor T2, and the third transistor T3 may be a P-type transistor or an N-type transistor according to an applied signal. In this case, the source and the drain of the P-type transistor may correspond to the drain and the source of the N-type transistor, respectively.

[0065] Figure 3 A pixel PXij connected to an i-th scan line SCLi, an i-th sensing line SSLi, a j-th data line DLj, and a j-th initial line ILj is shown as an example.

[0066] The pixel circuit PC may include a first transistor T1 (driving transistor), a second transistor T2 (switching transistor), a third transistor T3 (sensing transistor), and a capacitor Cst. However, the pixel circuit PC may also include additional transistors and / or additional capacitors and is not limited to any one embodiment.

[0067] The light emitting element OLED may be an organic light emitting element or an inorganic light emitting element including an anode (first electrode) and a cathode (second electrode). The anode of the light emitting element OLED may receive a first voltage ELVDD through a first transistor T1, and the cathode of the light emitting element OLED may receive a second voltage ELVSS. The light emitting element OLED may receive the first voltage ELVDD and the second voltage ELVSS to emit light.

[0068] The first transistor T1 may include a drain D1 for receiving a first voltage ELVDD, a source S1 connected to an anode of the light emitting element OLED, and a gate G1 connected to the capacitor Cst. The first transistor T1 may control a driving current flowing from the first voltage ELVDD through the light emitting element OLED in response to a voltage value stored in the capacitor Cst.

[0069] The second transistor T2 may include a drain D2 connected to the jth data line DLj, a source S2 connected to the capacitor Cst, and a gate G2 for receiving the i-th first scan signal SCi. The second transistor T2 supplies the data voltage Vd to the first transistor T1 in response to the i-th first scan signal SCi.

[0070] The third transistor T3 may include a source S3 connected to the jth initial line ILj, a drain D3 connected to the anode of the light emitting element OLED, and a gate G3 receiving the i-th second scan signal SSi. The jth initial line ILj may receive the initial voltage Vintit.

[0071] The capacitor Cst may store a voltage difference of various values ​​according to an input signal. For example, the capacitor Cst may store a voltage corresponding to a difference between a voltage output from the second transistor T2 and the first voltage ELVDD.

[0072] like Figure 4 As shown in FIG. 1 , light formed in the first pixel PX-G may be provided to the first pixel region PXA-G, light formed in the second pixel PX-R may be provided to the second pixel region PXA-R, and light formed in the third pixel PX-B may be provided to the third pixel region PXA-B. The first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B may correspond to the opening PDL-OP defined in the pixel defining layer PDL, which will be Figure 5B Described in.

[0073] The peripheral area NPXA is positioned between the first pixel area PXA-G, the second pixel area PXA-R, and the third pixel area PXA-B. The peripheral area NPXA is disposed at a boundary between the first pixel area PXA-G, the second pixel area PXA-R, and the third pixel area PXA-B to reduce or prevent color mixing between the first pixel area PXA-G, the second pixel area PXA-R, and the third pixel area PXA-B.

[0074] The first pixel PX-G, the second pixel PX-R, and the third pixel PX-B may each include a light emitting element OLED (eg, Figure 5B In the OLED-G in FIG, the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B can generate source light of the same color. However, the light emitting areas of the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B can be the same or different.

[0075] Source light generated from the light emitting elements OLED of the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B can be generated by Figure 2A The light control pattern in the light control layer OSL described in the embodiment is converted into any one of red, green and blue. The converted light may be emitted through the first pixel area PXA-G, the second pixel area PXA-R and the third pixel area PXA-B.

[0076] Reference Figure 4 , the second pixel region PXA-R and the third pixel region PXA-B are positioned in the same row, and the first pixel region PXA-G is positioned in a row different from the row of the second pixel region PXA-R and the third pixel region PXA-B. For example, the second pixel region PXA-R and the third pixel region PXA-B may be arranged to be spaced apart along the first direction DR1, and the first pixel region PXA-G may be arranged to be spaced apart from the second pixel region PXA-R and the third pixel region PXA-B in a corresponding oblique direction oblique to each of the first direction DR1 and the second direction DR2.

[0077] According to one or more embodiments, the first pixel region PXA-G may have a larger area than the second pixel region PXA-R, and may have a larger area than the third pixel region PXA-B.

[0078] The first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B have a square shape, but the arrangement form and area of ​​the pixel regions are not limited thereto.

[0079] exist Figure 4The arrangement structure of the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B in the unit pixel PXU shown in the figure is presented only as an example, and the present disclosure is not limited thereto. In one or more embodiments of the present disclosure, the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B may be arranged along the first direction DR1 and positioned in the same row. In addition, the arrangement of the first pixel region PXA-G, the second pixel region PXA-R, and the third pixel region PXA-B in each of the unit pixels PXU does not have to be the same.

[0080] Figure 5A is a plan view according to a stacking order of conductive patterns included in a unit pixel according to one or more embodiments of the present disclosure. Figure 5B It is along Figure 5A A cross-sectional view of the display panel taken along line II'. Figure 5A The stacked structure of the conductive patterns in the Figure 3 The components in the pixel circuit PC and the light emitting element OLED described in FIG. 1 correspond to each other. Therefore, the same / similar reference numerals are used as in FIG. Figure 3 The same / similar components as those described in Figure 5A In, not set Figure 2A The light control layer OSL and the window panel WD described in.

[0081] Reference Figure 5A , the unit pixel PXU may include a first pixel PX-G, a second pixel PX-R, and a third pixel PX-B. The first pixel PX-G, the second pixel PX-R, and the third pixel PX-B may all be included Figure 3 The pixel circuit PC and the light-emitting element OLED described in.

[0082] For example, the first pixel PX-G may include a first light-emitting element OLED-G, a first transistor T1-G, a second transistor T2-G, a third transistor T3-G, and a first capacitor Cst-G, the second pixel PX-R may include a second light-emitting element OLED-R, a first transistor T1-R, a second transistor T2-R, a third transistor T3-R, and a second capacitor Cst-R, and the third pixel PX-B may include a third light-emitting element OLED-B, a first transistor T1-B, a second transistor T2-B, a third transistor T3-B, and a third capacitor Cst-B.

[0083] exist Figure 5A For convenience of description, the first electrode AE ​​(see FIG. 2 ) included in each of the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B is Figure 5B) is shown as replacing the light-emitting elements OLED-R, OLED-G and OLED-B.

[0084] The source light generated from the first pixel PX-G may be provided to the first pixel region PXA-G. The source light generated from the second pixel PX-R may be provided to the second pixel region PXA-R. The source light generated in the third pixel PX-B may be provided to the third pixel region PXA-B.

[0085] The first pixel PX-G, the second pixel PX-R, and the third pixel PX-B are each connected to the first power line ED, the second power line EL, the initial line IL, the scan line SCL, and the sense line SSL. In addition, the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B can be connected to the corresponding data lines DL-G, DL-R, and DL-B. The first power line ED can provide a first voltage ELVDD (see Figure 3 ), the second power line EL can provide a second voltage ELVSS lower than the first voltage ELVDD (see Figure 3 ).

[0086] According to one or more embodiments, the data lines DL-G, DL-R, and DL-B, the initial lines IL, and the second power lines EL may be spaced apart along the first direction DR1 and may each extend along the second direction DR2. The first power lines ED, the scan lines SCL, and the sensing lines SSL may be spaced apart along the second direction DR2 and may each extend along the first direction DR1.

[0087] According to one or more embodiments of the present disclosure, when viewed on a plane, the capacitors Cst-G, Cst-R, and Cst-B included in the first pixel PX-G, the second pixel PX-R, and the third pixel PX-B may be spaced apart. The first capacitor Cst-G may be spaced apart from the second capacitor Cst-R along the second direction DR2. The first capacitor Cst-G and the second capacitor Cst-R may be spaced apart from the third capacitor Cst-B along the first direction DR1.

[0088] When viewed on a plane, the capacitors Cst-G, Cst-R, and Cst-B may be positioned between the sensing line SSL and the scanning line SCL. According to one or more embodiments of the present disclosure, when viewed on a plane, the sensing line SSL may be positioned above the capacitors Cst-G, Cst-R, and Cst-B (e.g., may overlap with the upper portions of the capacitors Cst-G, Cst-R, and Cst-B), and the scanning line SCL may be positioned below the capacitors Cst-G, Cst-R, and Cst-B (e.g., may overlap with the lower portions of the capacitors Cst-G, Cst-R, and Cst-B).

[0089] According to one or more embodiments of the present disclosure, the first capacitor Cst-G included in the first pixel PX-G is spaced apart from the second capacitor Cst-R included in the second pixel PX-R along the second direction DR2, and thus, even when the first pixel region PXA-G of the first pixel PX-G is biased toward the second power line EL, the area of ​​the second capacitor Cst-R can be ensured. Therefore, a display panel DP having improved driving characteristics of the second pixel PX-R can be provided.

[0090] Reference Figure 5A and Figure 5B , the display panel DP according to one or more embodiments may include a base layer BS, insulating layers 10, 20, and 30 positioned on the base layer BS, a pixel defining layer PDL having an opening PDL-OP defined therein, an encapsulation layer TFE, and a first light emitting element OLED-G of a first pixel PX-G. The description of the first light emitting element OLED-G may also be applied to the second light emitting element OLED-R included in the second pixel PX-R and the third light emitting element OLED-B included in the third pixel PX-B.

[0091] The base layer BS may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. For example, the synthetic resin layer may include at least any one of acrylic resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. In addition, the base layer BS may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0092] The first data line DL-G and the first light blocking pattern BML-G may be positioned on the base layer BS. The first light blocking pattern BML-G may be connected to the source of the first transistor T1-G included in the first pixel PX-G, and may receive a signal applied to the source to form a synchronization structure at the lower portion of the semiconductor pattern. The first light blocking pattern BML-G may be connected to the first active pattern A1-G (see Figure 6B ) to receive a bias voltage. The first light blocking pattern BML-G may receive a first voltage ELVDD (see Figure 3 ).

[0093] The first light blocking pattern BML-G may block the potential caused by polarization from affecting the first transistor T1-G. In addition, the first light blocking pattern BML-G may block external light from reaching the first transistor T1-G. In one or more embodiments of the present disclosure, the first light blocking pattern BML-G may be a floating electrode in a form isolated from other electrodes or lines.

[0094] The first data line DL-G may be spaced apart from the first light blocking pattern BML-G. The first data line DL-G may be formed by the same process as the first light blocking pattern BML-G, and the first data line DL-G and the first light blocking pattern BML-G may include the same material.

[0095] The first insulating layer 10 may be positioned on the base layer BS, and may cover the first data line DL-G and the first light-blocking pattern BML-G.

[0096] The first capacitor pattern CG of the first pixel PX-G may be positioned on the first insulating layer 10. The first capacitor pattern CG may overlap the first light blocking pattern BML-G to form a first capacitor Cst-G of the first pixel PX-G.

[0097] The second insulating layer 20 may be positioned on the first insulating layer 10 and may cover the first capacitor pattern CG. According to one or more embodiments, the first insulating layer 10 and the second insulating layer 20 may include an inorganic layer. For example, the inorganic layer may include a silicon oxide layer and a silicon nitride layer. Each of the first insulating layer 10 and the second insulating layer 20 may be provided as a multilayer, and the silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0098] The first gate pattern C-P1 may be positioned on the second insulating layer 20. The first gate pattern C-P1 may be connected to the first capacitor pattern CG through a contact hole defined in the second insulating layer 20. Figure 6B In the embodiment, a region of the first active pattern A1-G, which will be described later, overlapping the first gate pattern C-P1 may be defined as an active region of the first transistor T1-G.

[0099] The third insulating layer 30 may be positioned on the second insulating layer 20 and may cover the first gate pattern C-P1. The third insulating layer 30 may be an organic layer.

[0100] The pixel defining layer PDL and the first light emitting element OLED-G of the first pixel PX-G may be positioned on the third insulating layer 30 .

[0101] The opening PDL-OP may be defined in the pixel defining layer PDL. The opening PDL-OP may expose at least a portion of the first electrode AE. The opening PDL-OP may be provided in plurality. The opening PDL-OP may be provided in the pixel defining layer PDL. Figure 4 The first pixel area PXA-G, the second pixel area PXA-R and the third pixel area PXA-B described in FIG.

[0102] According to one or more embodiments, the pixel defining layer PDL may have light absorption characteristics, for example, the pixel defining layer PDL may be black. The pixel defining layer PDL may include a black colorant. The black colorant may include a black dye and a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining layer PDL may correspond to a light blocking pattern having a light blocking characteristic.

[0103] The first electrode AE ​​of the first light emitting element OLED-G may be positioned on the third insulating layer 30. The second electrode CE may be positioned on the first electrode AE ​​(as used herein, "on" may mean "above"). The emission layer EML may be positioned between the first electrode AE ​​and the second electrode CE. The first light emitting element OLED-G according to one or more embodiments may further include a hole control layer and an electron control layer. The hole control layer may be positioned between the first electrode AE ​​and the emission layer EML. The electron control layer may be positioned between the emission layer EML and the second electrode CE. The hole control layer may include a hole transport layer and a hole injection layer. The electron control layer may include an electron transport layer and an electron injection layer. According to one or more embodiments, the hole control layer, the emission layer, the electron control layer and the second electrode may be a common layer commonly formed in the first pixel PX-G, the second pixel PX-R and the third pixel PX-B.

[0104] The encapsulation layer TFE may cover the first light emitting element OLED-G. The encapsulation layer TFE may include a first inorganic layer, an organic layer, and a second inorganic layer stacked in sequence. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The inorganic layers may each have a multilayer structure. The organic layer may include an acryl organic layer, but is not limited thereto. The inorganic layer may protect the first light emitting element OLED-G from moisture and oxygen, and the organic layer may protect the first light emitting element OLED-G from foreign matter such as dust particles.

[0105] FIG. 6A to FIG. 6G is Figure 5A A plan view of the stacking order of the conductive patterns described in FIG. 1 divided by layers.

[0106] Reference Figure 5A , Figure 5B and Fig. 6A , the first conductive layer MSL1 may be positioned on the base layer BS and covered by the first insulating layer 10 .

[0107] The first conductive layer MSL1 may include a second power line EL, first, second, and third data lines DL-G, DL-R, and DL-B, first, second, and third light blocking patterns BML-G, BML-R, and BML-B, a power line EBR, and an initial line IL.

[0108] The second power line EL according to one or more embodiments of the present disclosure may extend in the second direction DR2. The second power line EL may be spaced apart from the second data line DL-R along the first direction DR1.

[0109] The first data line DL-G and the second data line DL-R may each extend in the second direction DR2. The second data line DL-R may be positioned between the second power line EL and the first data line DL-G. The first data line DL-G may be spaced apart from the second power line EL in the first direction DR1, and the second data line DL-R is between the first data line DL-G and the second power line EL.

[0110] The first and second light blocking patterns BML-G and BML-R may be spaced apart along the second direction DR2. The first and second light blocking patterns BML-G and BML-R may be positioned between the first data line DL-G and the power line EBR. The third light blocking pattern BML-B may be positioned between the initial line IL and the third data line DL-B.

[0111] The first light blocking pattern BML-G, the second light blocking pattern BML-R, and the third light blocking pattern BML-B may each correspond to a lower electrode of a capacitor included in a corresponding pixel.

[0112] The power supply line EBR may extend in the second direction DR2. The power supply line EBR may be positioned between the first and second light blocking patterns BML-G and BML-R and the preliminary line IL.

[0113] The preliminary line IL may extend along the second direction DR2. The preliminary line IL may be positioned between the power supply line EBR and the third light-blocking pattern BML-B.

[0114] The third light-blocking pattern BML-B may be positioned between the initial line IL and the third data line DL-B.

[0115] The third data line DL-B may extend along the second direction DR2. The third data line DL-B may be positioned between the third light blocking pattern BML-B and the adjacent unit pixel PXU (see FIG. Figure 4 ) between the second power lines in the .

[0116] Reference Figure 5A , Figure 5B and Figure 6B , the second conductive layer MSL2 may be positioned on the first insulating layer 10 and may be covered by the second insulating layer 20 .

[0117] The second conductive layer MSL2 may include a first active pattern A1-G, a second active pattern A2-G, a third active pattern A3-G, and a first capacitor pattern CG included in the first pixel PX-G, a first active pattern A1-R, a second active pattern A2-R, a third active pattern A3-R, and a second capacitor pattern C-R1 and C-R2 included in the second pixel PX-R, and a first active pattern A1-B, a second active pattern A2-B, a third active pattern A3-B, and a third capacitor pattern CB included in the third pixel PX-B.

[0118] The first capacitor pattern CG (upper electrode of the first capacitor Cst-G) may overlap the first blocking pattern BML-G to define the first capacitor Cst-G of the first pixel PX-G. The second capacitor patterns C-R1 and C-R2 (upper electrode of the second capacitor Cst-R) may overlap the second light-blocking pattern BML-R to define the second capacitor Cst-R of the second pixel PX-R. The third capacitor pattern CB (upper electrode of the third capacitor Cst-B) may overlap the third light-blocking pattern BML-B to define the third capacitor Cst-B of the third pixel PX-B.

[0119] The first light blocking pattern BML-G, the second light blocking pattern BML-R, and the third light blocking pattern BML-B may each correspond to a lower electrode of a capacitor included in a corresponding pixel.

[0120] A portion of the first capacitor pattern CG may be defined as a second active pattern A2-G, and a portion of the 2-2nd capacitor pattern C-R2 may be defined as a second active pattern A2-R. The third capacitor pattern CB may be spaced apart from the second active pattern A2-B along the second direction DR2, with the first active pattern A1-B between the third capacitor pattern CB and the second active pattern A2-B.

[0121] A portion of each of the first capacitor pattern CG and the first active pattern A1-G may overlap the first light-blocking pattern BML-G, and a portion of the first capacitor pattern CG (e.g., the second active pattern A2-G) may not overlap the first light-blocking pattern BML-G. The third active pattern A3-G may extend in the first direction DR1 and may be positioned between the first blocking pattern BML-G and the initial line IL when viewed on a plane.

[0122] A portion of each of the 2-1st capacitor pattern C-R1, the 2-2nd capacitor pattern C-R2, and the first active pattern A1-R may overlap the second light-blocking pattern BML-R, and a portion of the second active pattern A2-R of the 2-2nd capacitor pattern C-R2 may not overlap the second light-blocking pattern BML-R. The third active pattern A3-R may extend in the first direction DR1 and may be positioned between the second light-blocking pattern BML-R and the initial line IL when viewed on a plane.

[0123] A portion of each of the third capacitor pattern CB, the first active pattern A1-B, and the second active pattern A2-B may overlap the third light-blocking pattern BML-B, and another portion of the second active pattern A2-B may not overlap the third light-blocking pattern BML-B. The third active pattern A3-B may not overlap the third light-blocking pattern BML-B, and when viewed on a plane, the third active pattern A3-B may extend in the first direction DR1 to be positioned between the initial line IL and the third data line DL-B.

[0124] Figure 6C Shown in Figure 5B The contact holes CNT1 and CNT2 are defined in at least one of the first insulating layer 10 and the second insulating layer 20 described in the drawings.

[0125] The first contact hole CNT1 may be defined by the first insulating layer 10 and the second insulating layer 20. The first contact hole CNT1 may overlap the conductive pattern included in the first conductive layer MSL1. Therefore, the conductive patterns located on different layers and overlapping the first contact hole CNT1 may be connected to each other through the first contact hole CNT1.

[0126] The second contact hole CNT2 may be defined by the second insulating layer 20. The second contact hole CNT2 may overlap the conductive pattern included in the second conductive layer MSL2. Therefore, the conductive patterns located on different layers and overlapping the second contact hole CNT2 may be connected to each other through the second contact hole CNT2.

[0127] exist Figure 6C In the figure, for the convenience of description, the first contact hole CNT1 is shown as a relatively small square, and the second contact hole CNT2 is shown as a relatively large rectangle.

[0128] Reference Figure 5A , Figure 5B and Fig.6D , the third conductive layer MSL3 may be disposed on the second insulating layer 20 and may be covered by the third insulating layer 30 .

[0129] The third conductive layer MSL3 may include a first power line ED, a sensing line SSL, a scan line SCL, a first power pattern ED-P1 and ED-P2, a second power pattern EL-P1 and EL-P2, a data pattern D1-P, D2-P and D3-P, an electrode pattern A-P11, A-P12, A-P2 and A-P3, a bridge pattern B-P1, B-P2 and B-P3, a gate pattern C-P1, C-P2 and C-P3 and an initial pattern IL-P.

[0130] The first power line ED may extend along the first direction DR1. The first power line ED may be connected to the power line EBR through the first contact hole CNT1. Figure 3 The first voltage ELVDD described in is supplied to the first power line ED.

[0131] The sensing line SSL may extend along the first direction DR1. According to one or more embodiments of the present disclosure, the sensing line SSL may be positioned below the first power line ED when viewed on a plane. A portion of the sensing line SSL may include a first pattern SP protruding along the second direction DR2. A portion of the first pattern SP overlapping the third active patterns A1-B and A2-B may be defined as a third transistor T3 (see Figure 3 ) of the gate.

[0132] The scan line SCL may extend along the first direction DR1. According to one or more embodiments of the present disclosure, when viewed on a plane, the scan line SCL may be spaced apart from the sensing line SSL along the second direction DR2. When viewed on a plane, a conductive pattern other than the first power line ED among the conductive patterns included in the third conductive layer MSL3 may be positioned between the scan line SCL and the sensing line SSL.

[0133] A portion of the scan line SCL may include second patterns L-P1 and L-P2 protruding along the second direction DR2. A portion of the 2-1st pattern L-P1 overlapping the second active patterns A2-G and A2-R may be defined as a second transistor T2 (see Figure 3 ) of the gate electrode. A portion of the 2-2 pattern L-P2 overlapping the second active pattern A2-B may be defined as a second transistor T2 (see Figure 3 ) of the gate.

[0134] According to one or more embodiments of the present disclosure, when viewed on a plane, the sensing line SSL including the first pattern SP protruding downward is arranged above the scanning line SCL including the 2-1st pattern L-P1 protruding upward, so even when the first pixel PX-G is arranged on the left side of the first pattern SP, the areas of the first capacitor Cst-G and the second capacitor Cst-R can be ensured.

[0135] The first power patterns ED-P1 and ED-P2 may overlap with the power line EBR. The first power patterns ED-P1 and ED-P2 may be connected to the power line EBR through the first contact hole CNT1. The first power patterns ED-P1 and ED-P2 may be spaced apart along the second direction DR2. The 1-1st power pattern ED-P1 may overlap with a portion of the first active pattern A1-G. A portion of the 1-2nd power pattern ED-P2 may protrude along the first direction DR1 and thus overlap with the first active pattern A1-R, and another portion of the 1-2nd power pattern ED-P2 may protrude along the first direction DR1 and thus overlap with the first active pattern A1-B.

[0136] The second power patterns EL-P1 and EL-P2 may overlap the second power line EL. The second power patterns EL-P1 and EL-P2 may be connected to the second power line EL through the first contact hole CNT1. Figure 3 The second voltage ELVSS described in is supplied to the second power line EL. The second power patterns EL-P1 and EL-P2 may be spaced apart along the second direction DR2.

[0137] Among the data patterns D1-P, D2-P and D3-P, a portion of the first data pattern D1-P may be connected to the first data line DL-G through the first contact hole CNT1, and another portion of the first data pattern D1-P may be connected to the second active pattern A2-G through the second contact hole CNT2.

[0138] A portion of the second data pattern D2 -P may be connected to the second data line DL-R through the first contact hole CNT1 , and another portion of the second data pattern D2 -P may be connected to the second active pattern A2 -R through the second contact hole CNT2 .

[0139] A portion of the third data pattern D3 -P may be connected to the third data line DL-B through the first contact hole CNT1 , and another portion of the third data pattern D3 -P may be connected to the second active pattern A2 -B through the second contact hole CNT2 .

[0140] Among the electrode patterns A-P11, A-P12, A-P2, and A-P3, a portion of the 1-1st electrode pattern A-P11 may be connected to the first light-blocking pattern BML-G through the first contact hole CNT1, and another portion of the 1-1st electrode pattern A-P11 may be connected to the third active pattern A3-G through the second contact hole CNT2. A portion of the 1-2nd electrode pattern A-P12 may be connected to the first light-blocking pattern BML-G through the first contact hole CNT1. Another portion of the 1-2nd electrode pattern A-P12 may be connected to the first light-blocking pattern BML-G through the third contact hole CNT3 defined in the third insulating layer 30 (see FIG. 2 ). Fig. 6E ) is connected to the second electrode CE (see Figure 5B ).

[0141] A portion of the second electrode pattern A-P2 may be connected to the second light-blocking pattern BML-R through the first contact hole CNT1, and another portion of the second electrode pattern A-P2 may be connected to the third active pattern A3-R through the second contact hole CNT2. The other portion of the second electrode pattern A-P2 may be connected to the third light-blocking pattern BML-R through the third contact hole CNT3 defined in the third insulating layer 30 (see FIG. Fig. 6E ) is connected to the second electrode CE (see Figure 5B ).

[0142] A portion of the third electrode pattern A-P3 may be connected to the third light-blocking pattern BML-B through the first contact hole CNT1, and another portion of the third electrode pattern A-P3 may be connected to the third active pattern A3-B through the second contact hole CNT2. The other portion of the third electrode pattern A-P3 may be connected to the third light-blocking pattern BML-B through the first contact hole CNT1. Fig. 6E ) is connected to the second electrode CE (see Figure 5B ).

[0143] Among the bridge patterns B-P1, B-P2, and B-P3, a portion of the first bridge pattern B-P1 may be connected to the first light blocking pattern BML-G through a first contact hole CNT1, and another portion of the first bridge pattern B-P1 may be connected to the first active pattern A1-G through a second contact hole CNT2.

[0144] A portion of the second bridge pattern BP2 may be connected to the second light-blocking pattern BML-R through the first contact hole CNT1, and another portion of the second bridge pattern BP2 may be connected to the first active pattern A1-R through the second contact hole CNT2.

[0145] A portion of the third bridge pattern BP3 may be connected to the third light-blocking pattern BML-B through the first contact hole CNT1, and another portion of the second bridge pattern BP2 may be connected to the first active pattern A1-B through the second contact hole CNT2.

[0146] Among the gate patterns C-P1, C-P2, and C-P3, a portion of the first gate pattern C-P1 may be connected to the first capacitor pattern CG through the second contact hole CNT2. When viewed on a plane, the first gate pattern C-P1 overlapped with the first active pattern A1-G may be defined as a first transistor T1 (see Figure 3 ) of the gate.

[0147] A portion of the second gate pattern C-P2 may be connected to the 2-1st capacitor pattern C-R1 through the second contact hole CNT2. Another portion of the second gate pattern C-P2 may be connected to the 2-2nd capacitor pattern C-R2 through the second contact hole CNT2. When viewed on a plane, the second gate pattern C-P2 overlapping the first active pattern A1-R may be defined as the first transistor T1 (see Figure 3 ) of the gate.

[0148] A portion of the third gate pattern C-P3 may be connected to the third capacitor pattern CB through the second contact hole CNT2. When viewed on a plane, the third gate pattern C-P3 overlapping the first active pattern A1-B may be defined as the first transistor T1 (see Figure 3 ) of the gate.

[0149] When viewed on a plane, the preliminary pattern IL-P may overlap the preliminary line IL and may be connected to the preliminary line IL through the first contact hole CNT1. The preliminary voltage Vintit (see Figure 3 ) is provided to the initial line IL.

[0150] A portion of the preliminary pattern IL-P may be connected to the third active patterns A3-G and A3-R through the second contact hole CNT2, and another portion of the preliminary pattern IL-P may be connected to the third active pattern A3-B through the second contact hole CNT2.

[0151] Fig. 6E Shown in Figure 5B The third contact hole CNT3 is defined by the third insulating layer 30 described in the embodiment of the present invention. The third contact hole CNT3 may overlap any one of the conductive patterns included in the third conductive layer MSL3. For example, the third contact hole CNT3 may overlap the 2-1st power pattern EL-P1, the 1-2nd electrode pattern A-P12, the second electrode pattern A-P2, and the third electrode pattern A-P3.

[0152] Reference Figure 5A , Figure 5B and Fig. 6F , the fourth conductive layer MSL4 may be disposed on the third insulating layer 30 and may be covered by the pixel defining layer PDL.

[0153] The fourth conductive layer MSL4 may include a power pattern EL-P and first, second, and third first electrodes AE-G, AE-R, and AE-B. The first, second, and third first electrodes AE-G, AE-R, and AE-B may be connected to the power pattern EL-P. Figure 5A Corresponding to the first electrode AE ​​described in .

[0154] The power pattern EL-P may be supplied with the second voltage ELVSS (see FIG. 1 ) through the second power line EL and the 2-1 th power pattern EL-P1. Figure 3 ). The power pattern EL-P can be connected to the Figure 5A The second electrode CE described in .

[0155] The first electrode AE-G of the first pixel PX-G may be connected to the 1-2 electrode pattern A-P12 through the third contact hole CNT3. The first electrode AE-R of the second pixel PX-R may be connected to the second electrode pattern A-P2 through the third contact hole CNT3. The first electrode AE-B of the third pixel PX-B may be connected to the third electrode pattern A-P3 through the third contact hole CNT3.

[0156] According to one or more embodiments of the present disclosure, when viewed on a plane, even when the first electrode AE-G of the first pixel PX-G is biased to the left, the first electrode AE-G may not overlap with the second capacitor Cst-R of the second pixel PX-R. The first capacitor Cst-G of the first pixel PX-G may overlap only with the first electrode AE-G of the first pixel PX-G, and the second capacitor Cst-R of the second pixel PX-R may overlap only with the first electrode AE-R of the second pixel PX-R. In addition, when viewed in the first direction DR1, the second capacitor Cst-R of the second pixel PX-R may not overlap with the first electrode AE-G of the first pixel PX-G.

[0157] According to one or more embodiments of the present disclosure, a region in which the second capacitor Cst-R of the second pixel PX-R is disposed may be ensured. Therefore, a display panel DP having improved driving characteristics of pixels may be provided.

[0158] Reference Figure 5A , Figure 5B and Figure 6G , the pixel defining layer PDL may be positioned on the fourth conductive layer MSL4. The first opening PXA-G, the second opening PXA-R, the third opening PXA-B, and the power supply opening may be defined in the pixel defining layer PDL. The first opening PXA-G, the second opening PXA-R, and the third opening PXA-B may be located on the fourth conductive layer MSL4. Figure 4 The first pixel area PXA-G, the second pixel area PXA-R and the third pixel area PXA-B described in correspondence.

[0159] The first opening PXA-G may overlap with the first electrode AE-G, and thus may expose at least a portion of the first electrode AE-G. The second opening PXA-R may overlap with the first electrode AE-R, and thus may expose at least a portion of the first electrode AE-R. The third opening PXA-B may overlap with the first electrode AE-B, and thus may expose at least a portion of the first electrode AE-B.

[0160] According to one or more embodiments, the area of ​​the second opening PXA-R may be smaller than the area of ​​the first opening PXA-G, and may be larger than the area of ​​the third opening PXA-B. The second opening PXA-R and the third opening PXA-B may be positioned in the same row, and the first opening PXA-G may be positioned in a row different from the second opening PXA-R and the third opening PXA-B. For example, the second opening PXA-R and the third opening PXA-B may be arranged to be spaced apart along the first direction DR1, and the first opening PXA-G may be arranged to be spaced apart from the second opening PXA-R and the third opening PXA-B in an inclined direction relative to each of the first direction DR1 and the second direction DR2.

[0161] According to one or more embodiments of the present disclosure, by optimizing the arrangement order of the patterns included in the conductive layer, the electrodes included in the capacitor can be arranged in a wide area. Therefore, the function of the capacitor is improved, and thus a display panel including pixels with enhanced driving characteristics can be provided.

[0162] Although the present disclosure has been described with reference to various embodiments, it will be understood that the present disclosure should not be limited to these embodiments, but various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the detailed description in the specification, but should only be determined by reference to the claims which include functional equivalents of the claims.

Claims

1. A display panel, comprising: Base layer; A unit pixel, comprising a first pixel, a second pixel and a third pixel above the base layer, wherein the first pixel, the second pixel and the third pixel are arranged along a first direction and a second direction intersecting each other, and each comprises a first transistor, a second transistor and a third transistor above the base layer, a capacitor and a light emitting element; A first power line extending along the first direction; a sensing line extending along the first direction and spaced apart from the first power line along the second direction; a scan line extending along the first direction and spaced apart from the first power line along the second direction, and the sensing line is between the scan line and the first power line; as well as A first data line, a second data line, and a third data line are spaced apart along the first direction, extend along the second direction, and are connected to the first pixel, the second pixel, and the third pixel, respectively. wherein the capacitor of the first pixel is spaced apart from the capacitor of the second pixel along the second direction, and The capacitor of the first pixel and the capacitor of the second pixel are spaced apart from the capacitor of the third pixel along the first direction.

2. The display panel according to claim 1, wherein: The capacitor is between the sensing line and the scanning line, wherein the sensing line overlaps the upper portion of the capacitor, and The scanning line overlaps with the lower part of the capacitor.

3. The display panel according to claim 1, wherein: The first data line is between the second data line and the third data line, and Wherein, the capacitor is between the first data line and the third data line.

4. The display panel according to claim 1, wherein: The capacitors respectively include upper electrodes, and respectively include first, second, and third light-blocking patterns over the base layer as corresponding lower electrodes.

5. The display panel of claim 4, further comprising a first capacitor pattern overlapping the first light blocking pattern, a second capacitor pattern overlapping the second light blocking pattern, and a third capacitor pattern overlapping the third light blocking pattern as the upper electrodes, respectively.

6. The display panel according to claim 5, wherein: A portion of the first capacitor pattern not overlapping the first light-blocking pattern includes an active pattern of the second transistor of the first pixel, wherein a portion of the second capacitor pattern not overlapping the second light-blocking pattern includes an active pattern of the second transistor of the second pixel, and Wherein, a portion of the third capacitor pattern not overlapping the third light-blocking pattern includes an active pattern of the second transistor of the third pixel.

7. The display panel according to claim 6, wherein: The scan line includes a first pattern and a second pattern protruding along the second direction and spaced apart along the first direction, the first pattern overlapping the active pattern of the second transistor of the first pixel and the active pattern of the second transistor of the second pixel, and the second pattern overlapping the active pattern of the second transistor of the third pixel.

8. The display panel according to claim 7, wherein: Portions of the first and second patterns overlapping the active patterns of the first, second, and third pixels include gates of the second transistors of the first, second, and third pixels.

9. The display panel according to claim 7, wherein: The second capacitor pattern includes a 2-1 capacitor pattern and a 2-2 capacitor pattern spaced apart along the second direction, and The active pattern of the first transistor of the second pixel is between the 2-1 capacitor pattern and the 2-2 capacitor pattern.

10. The display panel according to claim 9, further comprising a gate pattern, the gate pattern including a gate of the first transistor of the second pixel, the gate overlapping the active pattern of the first transistor of the second pixel, the gate pattern connecting the 2-1 capacitor pattern and the 2-2 capacitor pattern.

11. The display panel according to claim 5, further comprising: a first insulating layer over the base layer and covering the first, second and third data lines and the first, second and third light-blocking patterns; a second insulating layer over the first insulating layer and covering the first capacitor pattern, the second capacitor pattern, and the third capacitor pattern; a third insulating layer, above the second insulating layer and covering the first power line, the sensing line and the scanning line; as well as A pixel defining layer is above the third insulating layer and defines an opening exposing at least a portion of the first electrode of the light emitting element.

12. The display panel according to claim 11, wherein: Among the openings, an opening corresponding to the first electrode of the first pixel is defined as a first pixel region, an opening corresponding to the first electrode of the second pixel is defined as a second pixel region, and an opening corresponding to the first electrode of the third pixel is defined as a third pixel region, and The area of ​​the second pixel region is smaller than that of the first pixel region, and larger than that of the third pixel region.

13. The display panel according to claim 12, wherein: The second pixel region and the third pixel region are spaced apart along the first direction, and The first pixel region is spaced apart from the second pixel region and the third pixel region in respective inclined directions inclined relative to the first direction and the second direction.

14. The display panel according to claim 11, further comprising a second power line connected to second electrodes of the first pixel, the second pixel and the third pixel, extending along the second direction above the base layer, and spaced apart from the second data line along the first direction.

15. A display panel, comprising: Base layer; A first pixel, a second pixel, and a third pixel are above the base layer and each include a first transistor, a second transistor, and a third transistor, a capacitor, and a light emitting element; A first data line, a second data line, and a third data line are spaced apart along a first direction and extend along a second direction crossing the first direction; A first power line extending along the first direction; A sensing line extending along the first direction; A scanning line extending along the first direction; A second power line extending along the second direction; as well as an initial line extending along said second direction, The second power line, the second data line, the first data line, the capacitor of the first pixel, the capacitor of the second pixel, the initial line, the capacitor of the third pixel and the third data line are sequentially arranged along the first direction.

16. The display panel according to claim 15, wherein: The first power line is spaced apart from the scan line along the second direction, and the sensing line is between the first power line and the scan line, and The capacitor of the first pixel, the capacitor of the second pixel, and the capacitor of the third pixel are between the sensing line and the scanning line.

17. The display panel according to claim 16, wherein: The capacitor of the first pixel is spaced apart from the capacitor of the second pixel along the second direction, and The capacitor of the first pixel and the capacitor of the second pixel are spaced apart from the capacitor of the third pixel along the first direction.

18. The display panel according to claim 17, wherein: The initial line is between the capacitor of the third pixel and the capacitor of the first pixel and the capacitor of the second pixel.

19. The display panel according to claim 15, further comprising: a first insulating layer, above the base layer, and covering the first data line, the second data line, the third data line, the second power line, and the initial line; a second insulating layer, over the first insulating layer and covering active patterns of the first transistor, the second transistor and the third transistor; a third insulating layer, above the second insulating layer and covering the first power line, the sensing line and the scanning line; as well as A pixel defining layer is above the third insulating layer and defines an opening exposing at least a portion of the first electrode of the light emitting element defined therein.

20. The display panel according to claim 19, wherein: The capacitor includes a lower electrode over the base layer and covered by the first insulating layer, and an upper electrode over the first insulating layer and covered by the second insulating layer.

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