Global navigation satellite system receiver

Abstract

A navigation receiver including a navigation system (200) includes a plurality of radio frequency paths configured to receive global navigation satellite system (GNSS) signals from an antenna and to transmit the GNSS signals within a frequency range to digitize the GNSS signals. The navigation system comprises: a plurality of analog-to-digital converters (101); a plurality of signal processors (102) forming a plurality of signal paths; a requantizer (103); a navigation channel (104); and a time controller (105) that transmits a ticking signal (S106). The navigation receiver further comprises a central processing unit (CPU) system (110), the central processing unit (CPU) system (110) comprising a CPU (107), a bus (data bus) (108), and a memory (109), the CPU receiving a data ready flag signal (Si11). The navigation system and the CPU system are connected through the interface block (202) and the interface block (203). According to the invention, the navigation data can be processed at an increased speed.

Description

Technical Field

[0001] The presently disclosed subject matter relates generally to navigation receivers, and in particular to receivers for processing satellite navigation signals received from satellites of different Global Navigation Satellite Systems (GNSS), such as GPS, GLONASS, etc. Background Art

[0002] A global navigation satellite system receiver receives and processes signals from GNSS satellites to determine the receiver's position. Various techniques have been developed for processing these signals, but these techniques require significant processing power, which is costly and time consuming. A low-cost receiver that uses techniques for rapidly processing GNSS satellite signals is needed. Summary of the invention

[0003] The navigation receiver includes a plurality of RF paths configured to receive GNSS signals from an antenna and transmit the GNSS signals within a frequency range to digitize the GNSS signals. The navigation receiver also includes a navigation system and a CPU system. In one embodiment, the navigation system is configured to process GNSS signals based on a clock CLKnav, and the navigation system includes: multiple analog-to-digital converters (ADCs), the multiple analog-to-digital converters are configured to digitize signals from multiple RF paths; multiple signal processors, the multiple signal processors are configured to process the digitized signals; multiple requantizers, the multiple requantizers are configured to convert the digitized signals into low-bit data; multiple navigation system to CPU system (NS2CS) interface blocks, the multiple navigation system to CPU system (NS2CS) interface blocks are configured to generate packets; multiple CPU system to navigation system (СS2NS) interface blocks, the multiple CPU system to navigation system (СS2NS) interface blocks are configured to convert packets into data; a MUX interconnect device, the MUX interconnect device is configured to distribute data streams; a time controller, the time controller is configured to generate a tick signal; and an asynchronous first-in-first-out device (AFIFO), the asynchronous first-in-first-out device (AFIFO) is configured to send low-bit data and tick signals via multiple channels. In one embodiment, the CPU system is configured to process packets based on a clock CLKcpu, and the CPU system includes: a memory configured to store data and packets; multiple hardware accelerator units, multiple hardware accelerator units configured to process packets; a navigation direct memory access (DMA), the navigation direct memory access (DMA) configured to convert packets into data for multiple channels, the multiple channels are configured to process data from one of the navigation DMA or AFIFO, and a CPU, the CPU is configured to control the navigation system and the CPU system, and the CPU is configured to read the results of GNSS signal processing from the multiple channels configured to process data from one of the navigation DMA or AFIFO and process the results of GNSS signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG1 shows a prior art Global Navigation Satellite System (GNSS) receiver;

[0005] Figure 2A A GNSS receiver according to one embodiment is shown;

[0006] Figure 2B A GNSS receiver according to one embodiment is shown;

[0007] Figure 3A navigation system to CPU system (NS2CS) interface block connecting a navigation system and a CPU system is shown according to one embodiment;

[0008] Figure 4A According to one embodiment, Figure 3 Signal diagram of the NS2CS interface block operating in single packet mode;

[0009] Figure 4B According to one embodiment, Figure 3 Signal diagram of the NS2CS interface block operating in multi-packet mode;

[0010] Figure 5 shows a CPU system to navigation system (CS2NS) interface block connecting a CPU system and a navigation system according to an embodiment;

[0011] Fig. 6A According to one embodiment, Figure 2A , Figure 2B and Figure 3 Components for navigating DMA transfer signals;

[0012] Figure 6B shows a data processing chain according to one embodiment;

[0013] Figure 7 shows a timing diagram of a clock signal for extraction according to one embodiment;

[0014] Figure 8 According to the embodiment, Figure 2A Navigation channel for communication between navigation DMA, NS2CS and CPU system;

[0015] Fig.9A shows the steps of packet processing according to one embodiment;

[0016] Fig. 9B According to one embodiment, Figure 2A , Figure 2B , Figure 3 and Figure 4A Figure 1 shows the Navigation DMA operating in single packet operation mode.

[0017] Fig. 9C According to one embodiment, Figure 2A , Figure 2B , Figure 3 and Figure 4B A diagram of the Navigation DMA operating in a multi-packet mode of operation; and

[0018] Fig.10A high-level block diagram of a computer for performing the operations of the components described herein is shown according to one embodiment. DETAILED DESCRIPTION

[0019] FIG1 shows a schematic diagram of a navigation receiver (e.g., a GNSS receiver) of the prior art including a navigation system 100, which includes "A" analog-to-digital converters (ADCs) shown as ADCs 101(1)...101(A). ADCs 101(1)...101(A) will be collectively referred to as ADC 101. Navigation system 100 also includes a plurality of signal processors, a plurality of which form a plurality of signal paths. A signal path including "S" signal processors is shown by signal processors 102(1,1)...102(S,1). There are "P" signal paths, as shown by signal processors 102(1,1)...102(1,P). Thus, the first path is shown by signal processors 102(1,1)...102(S,1), and the last path is shown by signal processors 102(1,P)...102(S,P). A plurality of signal processors including signal processors 102(1,1)...102(1,P) and signal processors 102(S,1)...102(S,P) will be collectively referred to as signal processors 102. The navigation receiver also includes "Q" requantizers, as shown by requantizers 103(1)...103(Q). Requantizers 103(1)...103(Q) will be collectively referred to as requantizers 103. The navigation receiver shown in FIG. 1 also includes a navigation channel 104, a time controller 105, and a CPU system 110, the time controller 105 transmitting a tick signal S106, the CPU system 110 including a CPU 107, a bus 108, and a memory 109, and the CPU system 110 receives a data ready flag signal S111.

[0020] The GNSS signal received by the antenna is transmitted to one or more RF paths of the plurality of RF paths, which are connected to the input of the ADC 101. In one embodiment, the RF path is configured to transmit GNSS signals within a specific frequency range for digitization. In one embodiment, each ADC 101 in the ADC 101 receives a signal from a corresponding one of the plurality of RF paths. In one embodiment, a plurality or all of the ADCs 101 may receive a signal from a single RF path. The digitized signal from the output of the ADC 101 is input to the signal processor 102 which processes the signal.

[0021] One or more components may be used as the signal processor 102 , for example, the signal processor 102 may be a filter, a noise suppressor, an equalizer, and / or a decimator, etc.

[0022] The signals output from the signal processors 102(S, 1) ... 102(S, P) are input to the requantizers 103(1) ... 103(Q), which requantize the received data into low-bit data. The low-bit data output from the requantizers 103(1) ... 103(Q) are input to the navigation channel 104, which processes the low-bit data.

[0023] The navigation channel 104 transmits a data ready flag signal S111 to the CPU 107. The data ready flag signal S111 indicates that the data in the navigation channel 104 is ready.

[0024] The time controller 105 generates a tick signal S106, which in one embodiment is a time scale. The period of the tick signal S106 is equal to the number of clock cycles of CLKnav, which is set by the CPU 107 before operation (see Figure 7 ). The tick signal S106 is input to: the signal processor 102, the requantizer 103, the navigation channel 104, and the CPU 107. A CPU clock (not shown) called CLKcpu is input to the CPU 107, the bus 108, and the memory 109. The clocks CLKnav and CLKcpu are typically asynchronous, and the CLKcpu rate is usually substantially higher than the CLKnav rate.

[0025] The CPU 107, the memory 109, and all the components of the navigation system 100 are respectively connected to the bus 108, thereby allowing communication between the CPU 107, the memory 109, and all the components of the navigation system 100. When the tick signal S106 occurs, the CPU 107 receives data via the bus 108 and controls the navigation system 100 based on the received data. The memory 109 is used for data storage.

[0026] Figure 2AA schematic diagram of a GNSS receiver is shown, the receiver including a navigation system 200, a CPU system 210. The GNSS receiver also includes a MUX interconnect 201 and "N" navigation system to CPU system (NS2CS) interface blocks, shown as NS2CS interface blocks 202(1)...202(N), which convert data received from the navigation system 200 and then transmit the data to the CPU system 210. The navigation system 200 also includes: "C" CPU system to navigation system (CS2NS) interface blocks, "H" hardware accelerators, and navigation direct memory access (DMA) 205. The "C" CPU system to navigation system (CS2NS) interface blocks are shown as CS2NS interface blocks 203 (1) ... 203 (C), which convert data received from the CPU system 210 and then transmit the data to the navigation system 200. The "H" hardware accelerators are shown as hardware accelerators 204 (1) ... 204 (H). The NS2CS interface blocks 202 (1) ... 202 (N) will be collectively referred to as NS2CS interface blocks. The CS2NS interface blocks 203 (1) ... 203 (C) will be collectively referred to as CS2NS interface blocks 203. The hardware accelerators 204 (1) ... 204 (H) will be collectively referred to as hardware accelerators 204. Figure 2A An interrupt request signal (IRQ) S206 output from the navigation DMA 205 and input to the CPU 107 is shown.

[0027] The GNSS signals received by the antenna are transmitted to one or more RF paths connected to the input of the ADC 101. The digitized signals output from the ADC 101 are input to the signal processor 102, where they are processed. The output of the signal processor 102 is input to the requantizer 103, where the signals are requantized into low-bit data.

[0028] The outputs of the requantizer 103, ADC 101, and signal processor 102 are input to a MUX interconnect 201. The MUX interconnect 201 transmits the outputs of the requantizer 103, ADC 101, and signal processor 102 to the inputs of NS2CS interface blocks 202(1) ... 202(N), where the signals may be further processed.

[0029] The signal output from the CS2NS interface block 203 is input to the MUX interconnection device 201. The signal output from the CS2NS interface block 203 is input to any one of the navigation system 200, the requantizer 103, and the signal processor 102 using the MUX interconnection device 201, and the signal is processed in any one of the navigation system 200, the requantizer 103, and the signal processor 102 to which it is input.

[0030] The time controller 105 generates a tick signal S106 which is used to control various components and is input to: the signal processor 102 , the requantizer 103 , the CPU 107 , the NS2CS interface block 202 , and / or the CS2NS interface block 203 .

[0031] The CPU 107 uses the tick signal S106 to synchronize control between the signal processor 102 , the requantizer 103 , the NS2CS interface block 202 , the CS2NS interface block 203 , and / or the hardware accelerators 204 , 205 .

[0032] CLKnav and CLKcpu clocks are usually asynchronous, and the CLKcpu frequency is significantly higher than the CLKnav frequency. In one embodiment, the frequency of CPU 107 is synchronous and significantly higher than CLKcpu. In one embodiment, the navigation system 200 operates based on the clock CLKnav, and the navigation system includes: ADC 101, signal processor 102, requantizer 103, time controller 105, MUX interconnect device 201, NS2CS interface block 202, CS2NS interface block 203. In one embodiment, the CPU system 210 operates based on the clock CLKcpu, and the CPU system includes: navigation DMA 205, navigation channel 104, CPU 107, bus 108, memory 109, NS2CS interface block 202, CS2NS interface block 203, hardware accelerator 204.

[0033] In one embodiment, the frequency of CPU 107 is synchronized and much higher than CLKcpu. In another embodiment, the operating frequency of navigation channel 104 and navigation DMA 205 is synchronized and significantly higher than CLKcpu.

[0034] In one embodiment, the following components are connected to the bus 108 : navigation DMA 205 , CPU 107 , memory 109 , navigation system 200 , NS2CS interface block 202 , CS2NS interface block 203 , hardware accelerator 204 , and navigation channel 104 .

[0035] The CPU 107 controls the following components via the bus 108 : the navigation DMA 205 , the navigation system 200 , the NS2CS interface block 202 , the CS2NS interface block 203 , the hardware accelerator 204 , and the navigation channel 104 .

[0036] In one embodiment, the CPU 107 is configured to write data to the memory 109 and the hardware accelerator 204 via the bus 108. In one embodiment, the memory 109 is used to store data.

[0037] The following components may serve as data sources: ADC 101 , signal processor 102 , requantizer 103 , hardware accelerator 204 , NS2CS interface block 202 , CS2NS interface block 203 , and CPU 107 .

[0038] After processing, each requantizer in the requantizer 103 forms the same number of samples in a period of time. The output of each requantizer 103 is collected into a stream and transmitted to the input of a NS2CS interface block 202 via the MUX interconnect device 201 for further processing. In one embodiment, one NS2CS interface block 202 is allocated for further processing.

[0039] In one embodiment, the output of the requantizer 103 is input to the NS2CS interface block 202. In one embodiment, the NS2CS interface block 202 writes data from the navigation system 200 via the bus 108 to the memory 109, the hardware accelerator 204, and / or the CPU 107.

[0040] In one embodiment, the CS2NS interface block 203 transfers the data from the memory 109 to the navigation system 200 via the bus 108. When the transfer operation is completed, the CS2NS interface block 202 interrupts the operation of the CPU 107.

[0041] One of the hardware accelerators 204 writes the result of the data processing via the bus 108 to the memory 109 , a different one of the hardware accelerators 204 , and / or the CPU 107 .

[0042] The hardware accelerator 204 may be a coarse-grained reconfigurable architecture (CGRA), a field programmable gate array (FPGA), the coarse-grained reconfigurable architecture (CGRA) may be built into an application-specific integrated circuit (ASIC), the field programmable gate array (FPGA) may be embedded in an ASIC, a spectrum analyzer, or other devices. When data is processed, the hardware accelerator 204 generates an interrupt request (IRQ) transmitted to the CPU 107 and a signal S707 transmitted to the navigation DMA 205.

[0043] The navigation DMA 205 reads data from the memory 109 via the bus 108. The navigation DMA 205 transfers the data from the memory 109 to the navigation channel 104, where the data is processed. After the operation is completed, the navigation DMA 205 outputs an IRQ signal S206 to the CPU 107.

[0044] CPU 107 uses tick signal S106 and IRQs (eg, IRQ S206 ) from navigation DMA 205 , NS2CS interface block 202 , CS2NS interface block 203 , and hardware accelerator 204 to control data flow among: navigation DMA 205 , NS2CS interface block 202 , CS2NS interface block 203 , and hardware accelerator 204 .

[0045] Figure 2B Shown with Figure 2A The GNSS receiver shown in Figure 1 is similar to the GNSS receiver shown in Figure 2. However, Figure 2B An additional component is included, namely an asynchronous first-in, first-out buffer (AFIFO) 214. In one embodiment, the output of the requantizer 103 and the tick signal 106 are connected to the input of the AFIFO 214 via the MUX interconnect 201. Each clock pulse of the CLKnav sample from the requantizer 103 and each clock pulse of the tick signal S106 are input to the AFIFO 214.

[0046] After being resynchronized to the clock CLKcpu, the samples are output from the requantizer 103 to the navigation channel 104, where the samples are processed. After being resynchronized to the clock CLKcpu, the tick signal S106 is input to the navigation channel 104, where the navigation channel 104 is used to process the samples from the requantizer 103.

[0047] The data from the AFIFO 214 to the navigation channel 104 (ie, to the internal logic of the navigation channel 104) is transmitted based on the clock CLKcpu. The AFIFO 214 implements the resynchronization of the data from the clock CLKnav to the clock CLKcpu.

[0048] When the navigation channel 104 operates with data from the AFIFO 214 (samples from the requantizer 103 and the tick signal S106 ), the navigation receiver operates in an operating mode equivalent to that of a standard GNSS receiver and the navigation DMA 205 need not be used.

[0049] Figure 32 shows a schematic diagram of the NS2CS interface block 202 and signal transmission from the navigation system 200 to the CPU system 210. The NS2CS interface block 202 includes: an NS2CS controller 300, an extractor NS2CS 301, a multiplexer 302, a preparation data and requantizer 303, an asymmetric asynchronous first-in first-out (AAFIFO) 304, and a packet manager 309. Figure 3 A plurality of signals are shown, including an IRQ signal S305 from the NS2CS controller 300 of the NS2CS interface block 202, an output signal S306 of the NS2CS interface block 202, a RUN signal S307, and a continuous data stream S308 from the MUX interconnect device 201.

[0050] In one embodiment, before starting CPU 107, NS2CS controller 300 configures: decimator NS2CS 301 (if needed), multiplexer 302, prepare data and requantizer 303, AAFIFO 304, and packet manager 309. In one embodiment, prepare data and requantizer 303 converts samples from digitized multi-level signals into 2-level signals. In summary, bus 108 accommodates many 2-level samples. NS2CS 202 performs data pre-processing and converts data from MUX interconnect 201 into the format required to navigate DMA 205, CPU 107, memory 109, or hardware accelerator 204. In one embodiment, the data stream output from NS2CS 202 is packets.

[0051] In one embodiment, a packet is a number of samples assigned or set by the CPU 107. A sample is data within one clock cycle. If necessary, service information or additional information can be added to the packet from the NS2CS controller 300 to control the hardware accelerator 204. In one embodiment, the NS2CS interface block 202 generates the packet based on the tick signal S106. In one embodiment, the NS2CS interface block 202 generates the packet and then stores it in the memory 109.

[0052] In various embodiments, packet data may be processed in the signal processor 102 using the CS2NS interface block 203 , the requantizer 103 using the CS2NS interface block 203 , the navigation channel 104 using the navigation DMA 205 , the CPU 107 , and / or the hardware accelerator 204 .

[0053] In various embodiments, packets may be generated in: the CPU 107, the NS2CS interface block 202, and / or the hardware accelerator 204. The continuous data stream S308 from the MUX interconnect 201 is input to the decimator NS2CS 301, and if necessary, the signal is decimated using different decimation coefficients and input to the prepare data and requantizer 303. The prepare data and requantizer 303 prepares the data and, if necessary, requantizes the data to lower bit data. If decimation is not used, the continuous data stream S308 from the MUX interconnect 201 enters the input of the multiplexer 302 and further enters the prepare data and requantizer 303. The output data from the prepare data and requantizer 303 passes through the AAFIFO 304 and is input to the packet manager 309, where the data is converted into packets with a given number of samples. The AAFIFO 304 resynchronizes the data from the clock CLKnav to the clock CLKcpu.

[0054] In one embodiment, during operation, the NS2CS interface block 202 stacks data at a given address and generates an IRQ signal S305 to the CPU 107. Data will be written cyclically if necessary. In another embodiment, the extractor NS2CS 301 is removed to reduce the NS2CS interface block 202 space in the ASIC.

[0055] NS2CS interface block 202 operates in two modes: single packet mode and multi-packet mode.

[0056] Figure 4A A signal diagram is shown for the NS2CS interface block 202 operating in single packet mode. During one tick period signal S106, a packet is formed. When a packet is formed, an IRQ signal S305 is generated and input to the CPU 107. In this mode, the CPU 107 uses the tick signal S106 and the IRQ signals from the NS2CS interface block 202, the CS2NS interface block 203, and the hardware accelerators 204, 205 to control the data flow. In one embodiment, the navigation DMA 205 forms a multi-bit data signal S501 for the navigation channel 104.

[0057] Figure 4B1 shows a signal diagram of the NS2CS interface block 202 operating in a multi-packet mode. The time controller 105 generates a tick signal S106, based on which data processing is started. During one cycle of the tick signal S106, U packets are formed. When the first packet has been formed and written to the memory 109, a signal S305 is generated. After each packet is completed, a RUN signal S307 is generated. In one embodiment, Packet 1...Packet U has the same size. In another embodiment, Packet 1...Packet U has different sizes. The navigation DMA 205 reads the packet from the memory 109 based on the signal S307 and forms a multi-bit data signal S501 for the navigation channel 104. When necessary, additional operations on the packet are performed, specifically, the NS2CS interface block generates the S305 and S307 signals at any time after the packet is written to the memory 109.

[0058] Figure 5 The schematic diagram shows the CS2NS interface block 203 and the signal transmission from the navigation system 200 to the CPU system 210. The CS2NS interface block 203 includes: a CS2NS controller 400, a CS2NS prepare data 402, and a CS2NS asynchronous asymmetric FIFO (CS2NS AAFIFO) 401. Figure 5 An IRQ signal S303 output from the CS2NS controller 400 is also shown.

[0059] In one embodiment, before operation, CPU 107 adjusts the following: CS2NS preparation data 402 and CS2NS AAFIFO 401. After the operation starts, NS2CS interface block 203 reads part of the packet from memory 109 before the tick signal S106 is received. NS2CS interface block 203 starts sending samples after the tick signal S106 is received. The entire packet is transmitted to MUX interconnect device 201 based on clock CLKnav (not shown, but used to synchronize packet transmission).

[0060] After the NS2CS interface block 203 starts operating, data from the bus 108 is input to the CS2NS prepare data 402 which processes the data. Data output from the CS2NS prepare data 402 is input to the CS2NS AAFIFO 401. Before the tick signal S106 occurs, data from the CS2NS AAFIFO 401 is input to the MUX interconnection device 201 until the packet transfer is completed.

[0061] In one embodiment, after the entire packet has been read from memory 109, the next packet is read if necessary to ensure continuous data flow processed on CLKnav. CS2NS203 generates IRQ signal S303 at the end of outputting the packet to CS2NS AAFIFO 401. CS2NS AAFIFO 401 resynchronizes the data from clock CLKcpu to clock CLKnav.

[0062] Fig. 6A 204(1) ... 204(H)). The signals received by the navigation DMA 205 include "H" RUN signals, as shown by RUN signals S707(1) ... S707(H) from the outputs of the "H" hardware accelerators (as shown by hardware accelerators 204(1) ... 204(H)). The signals received by the navigation DMA 205 also include "N" signals from the output of the NS2CS interface block, as shown by signals S307(1) ... S307(N). The signals received by the navigation DMA 205 are used to try the automatic mode for the first time.

[0063] In one embodiment, the navigation DMA 205 receives signal S707 from the hardware accelerator 204. Signal S707 is transmitted at the end of writing a packet to the memory 109. The navigation DMA 205 uses signal S707 in a similar manner to signal S307, and signal S707 is also used for the first attempt at automatic mode.

[0064] In one embodiment, the navigation DMA 205 uses signals S307 and S707 to read packets from the memory 109 and generates signal S501 (see FIG. 1 ) based on different data sources NS2CS interface block 202 and / or hardware accelerator 204. Figure 4A and Figure 4B ).

[0065] The NS2CS interface block 202 , the CS2NS interface block 203 and the hardware accelerators 204 , 205 may be arranged in a data processing chain. During operation of the data processing chain, data is transferred from one module to another without the involvement of the CPU 107 .

[0066] In such Figure 6BIn one embodiment shown in , data is processed in a chained manner, the chain starting with a packet from the output of the NS2CS interface block 202(1) being input to the hardware accelerator 204(1), where the packet is processed. The result of the processing of the packet by the hardware accelerator 204(1) is input to the hardware accelerator 204(2). The result of the processing of the packet by the hardware accelerator 204(2) is written to the memory 109. After processing the packet, the hardware accelerator 204(2) generates a signal S707(2). Based on the signal S707(2), the navigation DMA 205 sends the data (signal S501) to the navigation channel 104.

[0067] In the navigation system 200 (as shown in FIG. 2 , Figure 3 and Figure 5 ), the signal is decimated by a signal processor 102 (a decimator in this example).

[0068] Figure 7 One of several possible variations for clock generation of a clock signal, referred to as a clock for decimation, is shown. The tick signal S106 has a specific tick period. The tick signal S106 includes a plurality of ClkNavs. The clock divider 2 signal shows the ClkNav clock divided by 2. Similarly, the clock divider 3 signal shows the ClkNav clock divided by 3, and the clock divider 4 signal shows the ClkNav clock divided by 4. In one embodiment, the signal is input to the signal processor 102 (decimator in this variation) to control decimation. In one embodiment, the tick signal S106 is used for all components (for all clock divisions) simultaneously (for all decimation factors).

[0069] When decimation is used, the number of samples at the input of the NS2CS interface block 202 is reduced, thereby reducing the packet size. In one embodiment, the NS2CS interface block converts the received digitized signal into packets of a preset or specified size.

[0070] Figure 8 According to the embodiment, Figure 5 The CS2NS CPU system communicates with the navigation channel 104. Figure 8As shown in , in one embodiment, the navigation channel 104 includes: channel 500, "D" signals from the navigation DMA 205 (as shown by signals S501(1)...S501(D)), code rate NCO (CRNCO) 503, code rate signal S504, code phase signal S505, code generator 506, code signal S507, selection generator 508, selection signal S509, integration period counter 510, integration period (IP) signal S511, intermediate frequency NCO (IFNCO) 512, cosine signal S513, sine signal S514, correlator 515, commutator 516, and output signal from commutator S517.

[0071] In one implementation, the navigation channel 104 includes a plurality of channels 500 . Figure 8 Channel 500 is shown, which is one of the multiple channels. In one embodiment, a packet may contain data from one or more data sources. Data from different sources may be combined into a packet with the same number of samples over a period of time. Figure 2A , Figure 2B and Figure 3 The lower order data received at the output of the NS2CS interface block 202 (shown in FIG. 1 ) is multiplexed into a single multi-bit word and input to the assigned NS2CS interface block 202 to generate a common packet, which is transmitted to the memory 109 where it is stored. The navigation DMA 205 reads the packet from the memory 109 and converts it (the data from the requantizers 103(1)...103(Q)) into "D" signals, as shown by signals S501(1)...S501(D). The data from each of the requantizers 103(1)...103(Q) is transmitted as signals S501(1)...S501(D), respectively.

[0072] The navigation DMA 205 sends a packet to the navigation channel 104 during the generation of the next packet. The CPU 107 controls the navigation DMA 205 via the bus 108. Prior to operation, the CPU 107 adjusts the navigation DMA 205 to operate in one of several modes.

[0073] The Navigation DMA 205 can operate in the following modes: CPU fully controlled mode and first attempt automatic mode.

[0074] In the CPU fully controlled mode according to one embodiment, the CPU 107 controls the navigation DMA 205 and the channel 500. In one embodiment, the CPU fully controlled mode is used only when the NS2CS interface block 202 operates in the single packet mode. The time controller 105 generates a tick signal S106, which runs the data processing. The NS2CS interface block 202 operates in the single packet mode. When a packet is formed, a signal S305 is generated. According to the signal S305, the CPU 107 writes a control command in the navigation channel 104, and then, according to the command from the CPU 107, the navigation DMA 205 sends the packet. When sending the packet, the navigation DMA 205 generates a signal S206. Based on the signal S206, the CPU 107 reads data from the navigation channel 104. The advantage of this mode is more flexible data chain processing, because the CPU 107 can determine by itself which block to send the data to.

[0075] In the first attempt automatic mode according to one embodiment, the CPU 107 controls 205 and channel 500, wherein the navigation DMA 205 itself uses signals S307 and S707 to send packets via channel 500. In one embodiment, the first attempt automatic mode is used only when the NS2CS interface block 202 operates in multiple data packet mode. The time controller 105 generates a tick signal S106, which runs data processing. After the first packet is sent, a signal S305 is generated. According to the signal S305, the CPU 107 sends a control command to the navigation channel 104, and further, according to the command of the CPU, the navigation DMA 205 sends the packet. At the end of each packet, according to the RUN signal S307, the navigation DMA 205 is run and the packet is sent to the navigation channel 104. After the last packet, based on the current tick signal S106, the navigation DMA 205 generates a signal S206. According to the signal S206, the CPU 107 reads data from the navigation channel 104. The advantage of this mode is that smaller packets require less memory. In addition, since this mode requires less CPU control, power consumption is lower.

[0076] When a packet is ready, the navigation DMA 205 reads the packet from the memory 109 and generates a multi-bit data signal S501. When the data signal S501(1) is sent via the commutator 516, the signal S501 for each clock is sent to the processing logic in the channel 500. When the data S501(D) is sent via the commutator 516, the signal S501 for each clock is sent to the processing logic in the channel 500.

[0077] The navigation DMA 205 in the CPU full controlled mode generates an IRQ signal S206 at the end of a packet after data is sent to the channel 500 , and the IRQ signal S206 corresponds to the cycle of the tick signal S106 .

[0078] The navigation DMA 205 in the first attempt automatic mode generates an IRQ signal S206 once for certain packets at the end of data transmission to the channel 500, and the IRQ signal S206 corresponds to the cycle of the tick signal S106.

[0079] Signals S501(1) ... S501(D) are transmitted from the navigation DMA 205 to the input of the inverter 516. The CPU 107, working in conjunction with the inverter 516, connects the channel 500 to the signal S501(i), where i is any number from 1 to D.

[0080] When the navigation DMA 205 is reading packets from the memory 109, if there is not enough data to form the signal S501 (ie, the navigation DMA 205 does not have time to read data from the memory), the channel 500 stops processing data during this time.

[0081] The navigation channel 104 includes a set of channels 500. The CPU 107 controls and retrieves data from the channels 500 via the bus 108. In the channels 500, each sample from a packet is processed within one clock cycle of CLKcpu.

[0082] In one implementation, the period of the tick signal S106 is smaller than the period of the integrated period signal S511 .

[0083] The configuration for the current channel 500 is a set of settings defined for the selected GNSS signal processing mode. For example, these parameters are the selected S501 (i) and the configuration of the code generator 506.

[0084] In one embodiment, when the navigation DMA 205 is not sending data signals S501, the CPU 107 configures, controls, and retrieves data from the channel 500. Prior to operation, the CPU 107 sets the current configuration of the components and parameters of the channel 500 as follows: the code frequency and initial code phase in the code rate NCO 503, the code generator 506, the strobe generator 508, the duration of the integration period signal S511 in the integration period counter 510, the intermediate frequency and initial code phase in the intermediate frequency NCO 512, and the commutator 516.

[0085] In one embodiment, channel 500 processes input signal S501 ( i ) from the beginning to the end of a packet.

[0086] The CRNCO 503 generates a code frequency signal S504, which is input to the code generator 506 and the integration period counter 510. The code generator 506 generates a code signal S507 at the rate of the signal S504. The code signal S507 is input to the gate generator 508 and the correlator 515. The CRNCO 503 generates a code phase signal S505, which is input to the gate generator 508. The gate generator 508 generates a gate signal S509 using the signals S507 and S505, which is input to the correlator 515. The IFNCO 512 generates a cosine (Cos) signal S513 and a sine (Sin) signal S514 having an intermediate frequency. The signals S513 and S514 are input to the correlator 515. The signal S517 from the commutator 516 is input to the correlator 515. Based on the code rate signal S504, the integration period counter 510 generates an integration period signal S511. The integration period signal S511 is input to the correlator 515 and the navigation DMA 205. In one embodiment, the signal S517 is the signal S501(i). The navigation DMA 205 locks on the signal S511 during the tick period S106.

[0087] In the correlator 515, the signal S517 is multiplied by the cosine signal S513 and the code signal S507, and the result of the multiplication is accumulated on the integration period signal S511. According to the integration period signal S511, the accumulated value (component I shown below) is stored in the buffer register 1, and if necessary, the CPU 107 takes the value and clears the accumulated value.

[0088]

[0089] In the correlator 515, the signal S517 is multiplied by the sinusoidal signal S514 and the code signal S507, and the result of the multiplication is accumulated on the integration period signal S511. According to the signal S511, the accumulated value (component Q shown below) is stored in the buffer register 2, and if necessary, the CPU 107 takes the value and clears the accumulated value.

[0090]

[0091] In the correlator 515, the signal S517 is multiplied by the cosine signal S513 and the selection signal S509, and the multiplication result is accumulated on the integration period signal S511. According to the signal S511, the accumulated value (component dI shown below) is stored in the buffer register 3, and if necessary, the CPU 107 takes the value and clears the accumulated value.

[0092]

[0093] In the correlator 515, the signal S517 is multiplied by the sinusoidal signal S514 and the selection signal S509, and the multiplication result is accumulated on the integration period signal S511. According to the signal S511, the accumulated value (component dQ shown below) is stored in the buffer register 4, and if necessary, the CPU 107 takes the value and clears the accumulated value.

[0094]

[0095] Based on signal S206, if signal S511 is locked and available in navigation DMA 205, CPU 107 reads ready data from channel 500, including values ​​(component I, component Q, component dI, component dQ) from buffer registers 1 to 4. Note that the code phase CRNCO 503, the intermediate frequency phase in IFNCO 512, and the status of the integration cycle counter 510 can also be read.

[0096] Before processing according to signal S501(i), CPU 107 can control / modify parameters of channel 500, including changing the code frequency in CRNCO 503, setting the code phase shift in CRNCO 503, changing the intermediate frequency in IFNCO 512, setting the intermediate frequency phase shift in IFNCO 512, etc.

[0097] The operation of gate generator 508 is described in US 7,764,226 Bl, the disclosure of which is incorporated herein by reference in its entirety.

[0098] Fig.9A The packet processing steps are shown and are described as follows.

[0099] Signals S305, S307, and S707 indicate to the navigation DMA 205 that there is a new packet in the memory 109. The CPU 107 uses a combination of signals S106, S206, S307, and S707 to control the GNSS signals processed in the channel 500. Packet processing using the navigation DMA 205 includes the following steps. The following table describes the packet processing steps. The name column of the table indicates Fig.9A The last digit of the label is associated with a particular step (ie, labels 9112, 9212, and 9312 are each associated with a configuration step, labels 9113, 9213, and 9313 are each associated with a control step, and so on).

[0100]

[0101] In one embodiment, during the formation of a new packet, all steps required for each current channel configuration must be completed.

[0102] In the CPU fully controlled mode, the configuration and control steps are controlled by the CPU 107. During the configuration and control steps, the CPU 107 controls the channel 500 before the packet is sent to the channel 500. The reading step is controlled by the CPU 107. At the reading step, the CPU 107 reads ready data from the channel 500 after processing the packet in the channel 500. The navigation DMA 205 generates an IRQ signal S206 after processing the packet (after the processing step).

[0103] In the first attempt automatic mode, the configuration and control steps are controlled by the CPU 107. During the configuration and control steps, the CPU 107 controls the channel 500 before the first packet formed during the cycle of the tick signal S106 is sent to the channel 500. The reading step is controlled by the CPU 107. In the reading step, after the channel 500 has processed the last packet generated during the cycle of the tick signal S106, the CPU 107 reads the ready data from the channel 500. The navigation DMA 205 generates the IRQ signal S206 after processing the last packet generated during the cycle of the tick signal S106 in the channel 500 (after the processing step).

[0104] In one embodiment, the following steps are performed in the order shown:

[0105] Configuration steps:

[0106] The configuration steps can be used one after another for multiple channels 500. If a new GNSS signal processing needs to be run, the channel 500 will set a new configuration. If necessary, the channel 500 can also stop the GNSS signal processing.

[0107] Control steps:

[0108] The control steps are used one after another for multiple channels 500. If necessary, a control command is sent to the channel 500.

[0109] Processing steps:

[0110] The processing steps are applied simultaneously (in parallel) to all lanes 500. Packets (represented by signal S501) are sent simultaneously to all lanes 500. Each lane 500 processes its own packet received as signal S501(i).

[0111] Reading steps:

[0112] For multiple channels 500, the read steps are used sequentially if necessary. If the signal S511 is available in the navigation DMA 205, the ready data from the channel 500 is retrieved.

[0113] In one embodiment, if necessary, CPU 107 may read data from channel 500 without using navigation DMA 205, thereby temporarily stopping the operation of 205 after signal S206.

[0114] In one embodiment, if channel 500 does not process the previously configured current configuration and CPU 107 will not set one or more new current configurations for channel 500, navigation DMA 205 will not send a packet to channel 500 (ie, navigation DMA 205 skips all steps) and generates signal S206.

[0115] In both CPU fully controlled mode and first attempt automatic mode, using the CPU 107 for the configuration and control steps will ensure synchronization of control for all channels 500 .

[0116] exist Fig.9A In the example, the steps with shaded background are inactive (i.e., not used). In one embodiment, the time for packet generation is equal to the period of the tick signal S106 (see Figure 7 ).

[0117] In one embodiment, channel 500(1) processes signal S501(i) in its current configuration (Config 1). In Config 1, data packets are processed in the same manner as the operation of channel 500 in a typical GNSS receiver (shown in FIG. 1 ) in pipeline mode.

[0118] In one embodiment, Config 1 configuration is performed as follows: at Tick 1 9100 - the current configuration is set, the GNSS signal is processed, and data is read if necessary; and at Tick 2 9200 and Tick 3 9300 - control steps are used, GNSS signal processing continues, and data is read if necessary.

[0119] exist Fig.9A In one embodiment shown in , the steps are performed in the following order:

[0120] Once tick signal S106 number 1 (ie, Tick 1 9100 ) occurs, the following steps will be performed: Config 9112 sets the following: Config 1; Process 9114; and Read 9115.

[0121] Once tick signal S106 number 2 (ie, Tick 2 9200 ) occurs, the following steps will be performed: Use control 9213 for: Config 1 ; Process 9214 ; and Read 9215 .

[0122] Once tick signal S106 number 3 (ie, Tick 3 9300 ) occurs, the following steps will be performed: Control 9313 is used for the following: Config 1; Process 9314; and CPU Read 9315.

[0123] It should be noted that, in one embodiment, in the single GNSS signal processing mode, the channel 500 always operates in the current configuration corresponding to Config 1.

[0124] Fig. 9B A diagram showing the navigation DMA 205 operating in a CPU fully controlled mode.

[0125] The packet corresponds to the periodic tick signal S106. In the CPU fully controlled mode, the CPU 107 uses the tick signals S106, S305 and S206, and uses the navigation DMA 205 to fully control the GNSS signal processing to control the Config step, the control step, and the reading step. According to the tick signal S106, the NS2CS interface block 202 starts to form a packet. The CPU 107 receives the signal S305 and performs the Config step and the control step. In the processing step, the navigation DMA 205 transmits the packet to the navigation channel 104 by the command of the CPU 107. The navigation DMA 205 completes the packet transmission and generates the signal S206. The CPU 107 receives the signal S206 and performs the reading step. Then all steps are repeated cyclically.

[0126] Fig. 9C The diagram shows the navigation DMA 205 operating in first attempt automatic (where 4 packets are formed per tick period) mode.

[0127] Within the periodic tick signal S106, four packets are formed (e.g., in multi-packet mode). In the first attempt automatic mode, the processing of packets 2 and 3 does not require any control from the CPU 107. After processing packet 4, the CPU 107 receives the signal S206 and reads the ready data from the channel 500. The NS2CS 202 starts to form a data packet through the tick signal S106. The CPU 107 receives the signal S305 and performs the Config step and the Control step. In the Processing step, the Navigation DMA 205 transmits packet 1 to the Navigation channel 104 through the command of the CPU 107. In the Processing step, the Navigation DMA 205 transmits packet 2, packet 3, and packet 4 to the Navigation channel 104 through the signal S307. The Navigation DMA 205 ends with the transmission of packet 4 and generates the signal S206. The CPU 107 receives the signal S206 and performs the Reading step. All steps are then repeated cyclically.

[0128] The navigation system 200 processes the GNSS signals in pipeline mode using CLKnav and generates packets using the NS2CS block 202, thereby providing greater flexibility in GNSS signal processing. The formation of packets is associated with the tick signal S106. The packets are further processed in the CPU system 210 based on the clock CLKcpu.

[0129] The samples from all requantizers 103 are combined in one NS2CS interface block 202 and then formed into a packet and written to the memory 109. The packet is input to the navigation channel 104 via the navigation DMA 205, where it is processed based on the clock CLKcpu. The NS2CS interface block 202 generates packets one by one, thereby providing pipeline processing of GNSS signals in the navigation channel 104. In one embodiment, the NS2CS interface block 202 generates packets one by one without losing any data. The control of the data from the navigation channel 104 and the reading of the data from the navigation channel 104 by the CPU 107 are implemented between the packet processing.

[0130] Packets in the navigation channel 104 may be processed in two modes: a CPU fully controlled mode and a first attempt automatic mode.

[0131] In one embodiment, in the CPU fully controlled mode: the CPU 107 controls all processes and the packet is equal to the period of the tick signal S106.

[0132] In one embodiment, in the first attempt automatic mode: the CPU 107 controls and reads data from the navigation channel 104 between packets of each tick signal S106 cycle. In this mode, the size of the packet is reduced several times, and a smaller size of the memory 109 is used. The navigation DMA 205 transfers the first packet of the packets formed in each tick signal S106 cycle to the navigation channel 104 according to the command of the CPU 107. Next, the packet is formed by the packets in each tick signal S106 cycle, and the NS2CS interface block 202 automatically notifies the navigation DMA 205 about the readiness of the new packet, and it allows the partial packet to be automatically transferred to the navigation channel 104. The navigation DMA 205 reads the packet from the memory 109 and transfers it to the navigation channel 104.

[0133] In one embodiment, in the operation of the interference suppressor (e.g., signal processor 102), it is necessary to detect interference in the navigation system 200. For this purpose, a spectrum analyzer (e.g., hardware accelerator 204) located in the CPU system is used. The packets formed by the NS2CS interface block 202 are processed in the spectrum analyzer. The CPU 107 analyzes the results and controls the interference suppressor.

[0134] In another embodiment, after the ASIC is produced, additional filters may be needed in the navigation system. The hardware accelerator 204 can be used as such a filter (e.g., embedded in the ASIC: using FPGA or CGRA). In this case, there is a chain that provides pipeline processing of GNSS signals in the navigation channel 104. The samples from the output of the signal processor 102 are input to the NS2CS interface block 202, which forms packets. The packets of the NS2CS interface block 202 are synchronized with the tick signal S106 and processed in the hardware accelerator 204. The hardware accelerator 204 forms packets and writes the packets to the memory 109. The CS2NS interface block 203 retrieves the packets from the memory 109 and sends the data back to the signal processing chain in the navigation system 200. The data from the CS2NS interface block 203 is synchronized with the tick signal S106, which allows signal delays to be considered during signal processing in the navigation channel 104.

[0135] In one embodiment, the packet may be processed by the CPU 107 to provide flexibility. The packet is recorded and stored in the memory 109 for further processing.

[0136] The NS2CS interface block 202 has a built-in decimator NS2CS 301 which can reduce the number of samples in a packet if necessary. This makes it possible to reduce the data processing time in the CPU 107 or the hardware accelerator 204.

[0137] In one embodiment, when the navigation channel 104 operates with data from the AFIFO 214 (e.g. samples and tick signal S106 from 103), the navigation DMA 205 is not used, then we obtain a mode of operation similar to that of a standard GNSS receiver, and all possibilities for additional processing of the GNSS signals are preserved.

[0138] In one embodiment, a computer is used to perform the operations described herein and, for example, Figure 2A , Figure 2B , Figure 3 , Figure 5 , Fig. 6A , Figure 6B and Figure 8 These components may be, for example, ADCs, signal processors, requantizers, etc. Fig.10 A high-level block diagram of such a computer is shown in . Computer 1002 includes a processor 1004, which controls the overall operation of computer 1002 by executing computer program instructions that define such operation. The computer program instructions can be stored in a storage device 1012 or other computer-readable medium (e.g., a disk, CD ROM, etc.), and loaded into memory 1010 when the computer program instructions need to be executed. Therefore, the method steps described herein can be defined by the computer program instructions stored in memory 1010 and / or storage device 1012 and the method steps described herein can be controlled by the processor 1004 executing the computer program instructions. For example, the computer program instructions can be implemented as a computer executable code written by a person skilled in the art to perform an algorithm defined by one of the various methods described herein. Therefore, by executing the computer program instructions, the processor 1004 performs the algorithm defined by the components and formulas described herein, such as Figure 2A , Figure 2B , Figure 3 , Figure 5 , Fig. 6A , Figure 6B and Figure 8The computer 1002 also includes one or more network interfaces 1006 for communicating with other devices via a network. The computer 1002 also includes input / output devices 1008 (e.g., a display, keyboard, mouse, speakers, buttons, etc.) that enable a user to interact with the computer 1002. Those skilled in the art will recognize that the actual computer implementation may also include other components, and Fig.10 is a high-level representation of some of the components of such a computer for purposes of illustration.

[0139] The foregoing detailed description should be understood to be illustrative and exemplary in all respects, rather than restrictive, and the scope of the inventive concept disclosed herein should be interpreted in accordance with the full scope permitted by patent law. It should be understood that the embodiments shown and described herein are only illustrative of the principles of the inventive concept, and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the inventive concept. Various other feature combinations may be implemented by those skilled in the art without departing from the scope and spirit of the inventive concept.

Claims

1. A navigation receiver, comprising: a plurality of RF paths, the plurality of RF paths being configured to receive GNSS signals from an antenna and transmit the GNSS signals within a frequency range to digitize the GNSS signals; A navigation system, wherein the navigation system is configured to process the GNSS signal based on a clock CLKnav, and the navigation system comprises: a plurality of analog-to-digital converters (ADCs), the plurality of said analog-to-digital converters being configured to digitize signals from a plurality of said RF paths; a plurality of signal processors, the plurality of signal processors being configured to process the digitized signals; a plurality of requantizers, the plurality of requantizers being configured to convert the digitized signals into low-bit data; a plurality of NS2CS interface blocks, the plurality of said NS2CS interface blocks being configured to generate packets; a plurality of С2N interface blocks, wherein the plurality of С2N interface blocks are configured to convert the packets into data; a MUX interconnection device configured to distribute the data from the outputs of the plurality of the ADCs, the signal processors and the requantizers to the input of the NS2CS interface block, and the MUX interconnection device configured to distribute the data from the output of the CS2NS interface block to the plurality of the signal processors and the plurality of the requantizers; a time controller configured to adjust a time scale to generate a tick signal; an asynchronous first-in-first-out device (AFIFO) configured to send the lower-order data and the tick signal to a plurality of the channels for processing; and A CPU system is configured to process the packet based on a clock CLKcpu, and the CPU system comprises: a memory configured to store the data and the packet; a plurality of hardware accelerators, wherein the plurality of hardware accelerators are configured to process the packets; a navigation DMA configured to convert the packet into data for a plurality of channels; a commutator configured to select data from the navigation DMA; and The CPU is configured to synchronize the control between a plurality of signal processors, a plurality of requantizers, an NS2CS interface block, a CS2NS interface block, a plurality of hardware accelerators and a navigation DMA based on the tick signal, and the CPU is configured to synchronize the control between the navigation system and the The CPU system controls; and reads the results of GNSS signal processing from the plurality of channels that process data from the navigation DMA or AFIFO and processes the results of GNSS signal processing; The operating frequencies of the navigation DMA and the plurality of channels are synchronized, and the operating frequencies of the navigation DMA and the plurality of channels are equal to or greater than the clock CLKcpu.

2. The navigation receiver according to claim 1, wherein: The NS2CS interface block converts the digitized signal into packets of a preset size and resynchronizes the data from the clock CLKnav to the clock CLKcpu.

3. The navigation receiver according to claim 1, wherein: The NS2CS interface block writes the packet into a memory and generates a RUN signal transmitted to the navigation DMA and an interrupt request signal transmitted to the CPU.

4. The navigation receiver according to claim 1, wherein: The NS2CS interface block receives low-order data from several of the plurality of requantizers and converts the low-order data into a packet of a specified size for transmission to a memory for use by the navigation DMA.

5. The navigation receiver according to claim 1, wherein: The NS2CS interface block is configured to extract the digitized signal and re-quantize the extracted signal into low-bit data.

6. The navigation receiver according to claim 1, wherein: The NS2CS interface block is configured to form the packets according to the tick signal and generate packets one after another without losing any data.

7. The navigation receiver according to claim 1, wherein: The NS2CS interface block is configured to generate one or more packets within a period of the tick signal.

8. The navigation receiver according to claim 3, wherein: The navigation DMA reads packets from the memory based on one of the RUN signals or commands received from the CPU.

9. The navigation receiver according to claim 1, wherein: The navigation DMA locks data ready states in the plurality of the channels according to the integration period signal, and the CPU reads signals from the plurality of the channels after data processing.

10. The navigation receiver according to claim 8, wherein: After processing the last packet during the current period of the tick signal, the navigation DMA generates an interrupt request that is transmitted to the CPU.

11. The navigation receiver according to claim 8, wherein: The CPU reads ready data from the plurality of channels and sends current channel configuration and control to the plurality of channels between processing packets.

12. The navigation receiver according to claim 1, wherein: In response to a command from the CPU, one of the plurality of hardware accelerators reads the packet from a memory or receives the packet from an NS2CS interface block, processes the packet, and then generates an interrupt request that is transmitted to the CPU.

13. The navigation receiver according to claim 12, wherein: The one of the plurality of hardware accelerators receives a packet, processes the packet, and converts the processing result into a packet written into the memory or into a different one of the plurality of hardware accelerators, and then generates an interrupt request transmitted to the CPU.

14. The navigation receiver according to claim 1, wherein: The CS2NS interface block reads packets from the memory and transmits the data to one of a plurality of signal processors or to one of a plurality of requantizers via a MUX interconnect, and the CS2NS interface block resynchronizes the data from the clock CLKcpu to the clock CLKnav.

15. The navigation receiver according to claim 14, wherein: The CS2NS interface block starts transmitting data based on a tick signal, and when receiving data is finished, the CS2NS interface block generates an interrupt request that is transmitted to the CPU.

16. The navigation receiver according to claim 1, wherein: The CPU reads a packet from a memory, processes the packet, and converts the processing result into a packet and writes the packet into the memory.

17. The navigation receiver according to claim 3, wherein: The CPU processes an interrupt request from one of the following: NS2CS interface block, CS2NS interface block, hardware accelerator, and navigation DMA.

18. The navigation receiver according to claim 1, wherein: The channel uses a tick signal from the output of the AFIFO to process low-order data from the AFIFO.

19. The navigation receiver of claim 1, wherein: The signal processing chain can be assembled from any combination of the following components: CPU, signal processor, NS2CS interface block, СS2NS interface block, requantizer, hardware accelerator, AFIFO, navigation DMA, and navigation channel.

Images