Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, and relates to the technical field of display. A plurality of first patterns are designed on one side of a row driving area of the array substrate, so that sufficient etching liquid is ensured to etch sources and drains of thin film transistors in the row driving area and a display area, and material residues of source and drain film layers caused by less etching liquid in the row driving area and the display area are avoided; the channel of the thin film transistor is prevented from being conducted due to the residual material of the source and drain electrode film layer above the active layer, the active layer of the thin film transistor is prevented from being converted into a conductor, the characteristics of the thin film transistor are ensured, and the yield of the array substrate and the display effect of the display panel are improved.

Description

Array substrate and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Thin film transistors (TFTs) are widely used in flexible display panels due to their advantages such as fewer process steps, high mobility, good bending performance and low process temperature.

[0003] Summary of the Invention

[0004] The present application provides an array substrate, and the technical solution is as follows:

[0005] In one aspect, an array substrate is provided, comprising:

[0006] a substrate having a display area and a peripheral area surrounding the display area, wherein the peripheral area at least includes a row driving area extending along a first direction;

[0007] a plurality of thin film transistors disposed in the row drive region;

[0008] and a plurality of first patterns, the plurality of first patterns being located on at least one side of the row driving region, the plurality of first patterns being spaced apart from the row driving region along the first direction, and the plurality of first patterns being located on the same side of the row driving region being arranged in an array;

[0009] In which, the thin film transistor includes: a gate, a gate insulation layer, an active layer and a source-drain layer stacked in sequence in a direction away from the substrate, the source-drain layer includes a source and a drain arranged at intervals; the multiple first patterns are located in the same layer as at least one of the source and the drain.

[0010] Optionally, the shape of the orthographic projection of the first pattern on the substrate is a rectangle.

[0011] Optionally, the shape of the orthographic projection of the first pattern on the substrate is a square.

[0012] Optionally, one of the two vertical boundaries in the first pattern is parallel to the first direction, and the other boundary is parallel to the second direction;

[0013] The second direction is parallel to an arrangement direction of the display area and the row driving area, and the first direction and the second direction intersect.

[0014] Optionally, the length of the first pattern along the first direction is m1, the distance between any two adjacent first patterns along the first direction is n1, and the ratio of m1 / n1 ranges from 0.9 to 1.9; the length of the first pattern along the second direction is m2, the distance between any two adjacent first patterns along the second direction is n2, and the ratio of m2 / n2 ranges from 0.9 to 1.9.

[0015] Optionally, the minimum distance between the orthographic projections of the plurality of first patterns on the substrate and the orthographic projections of other structures in the array substrate on the substrate ranges from 15 micrometers to 30 micrometers.

[0016] Optionally, the peripheral area includes two row drive areas extending along the first direction, and the two row drive areas are respectively located on both sides of the display area;

[0017] The plurality of first patterns are located on both sides of each row driving region.

[0018] Optionally, the peripheral area further includes a fan-out area extending along a second direction, where the second direction is parallel to an arrangement direction of the row drive area and the display area; and the array substrate further includes:

[0019] a plurality of second patterns, the plurality of second patterns being located on at least one side of the fan-out region, and the plurality of second patterns being spaced apart from the fan-out region along the second direction, the plurality of second patterns being arranged in an array on the same side of the fan-out region, and the second patterns being different from the first patterns in at least one of shape and size;

[0020] The plurality of second patterns include: a plurality of first-type second patterns and a plurality of second-type second patterns, the plurality of first-type second patterns and the gate are located in the same layer, and the plurality of second-type second patterns and the source and the drain are located in the same layer.

[0021] Optionally, the orthographic projections of the plurality of first-type second patterns on the substrate do not overlap with the orthographic projections of the plurality of second-type second patterns on the substrate.

[0022] Optionally, the orthographic projections of the plurality of first-type second patterns on the substrate and the orthographic projections of the plurality of second-type second patterns on the substrate are arranged alternately in the second direction.

[0023] Optionally, the plurality of first-type second patterns and the plurality of second-type second patterns are the same in number and correspond one to one;

[0024] The orthographic projection of each first-type second pattern on the substrate overlaps with the orthographic projection of a corresponding second-type second pattern on the substrate.

[0025] Optionally, the orthographic projection of the second pattern on the substrate is a rectangle, and the length of the second pattern along the first direction is greater than the length along the second direction.

[0026] Optionally, one of the two perpendicular boundaries in the second pattern is parallel to the first direction, and the other boundary is parallel to the second direction.

[0027] Optionally, the length of the second pattern along the first direction is r1, the distance between any two adjacent second patterns along the first direction is s1, and the ratio of r1 / s1 ranges from 0.9 to 1.9;

[0028] The length of the second pattern along the second direction is r2, the distance between any two adjacent second patterns along the second direction is s2, and the ratio of r2 / s2 ranges from 0.9 to 1.9.

[0029] Optionally, a minimum distance between an orthographic projection of the second pattern on the substrate and an orthographic projection of other structures in the array substrate on the substrate is in a range of 75 micrometers to 100 micrometers.

[0030] Optionally, the multiple second patterns are located on both sides of the fan-out area.

[0031] Optionally, the plurality of thin film transistors located in the row driving region constitute a plurality of cascaded shift register units, and each shift register unit includes 18 thin film transistors and a storage capacitor.

[0032] Optionally, the active layer of the thin film transistor is made of metal oxide material.

[0033] On the other hand, a display panel is provided, characterized in that the display panel includes a plurality of pixel units and the array substrate according to the above aspect;

[0034] Wherein, the plurality of pixel units are located in the display area of ​​the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can derive other drawings based on these drawings without inventive effort. This application is described using an oxide thin film transistor as an example.

[0036] FIG1 is a graph showing the relationship between resistance and voltage of an active layer of a thin film transistor before and after being conductively converted according to an embodiment of the present application;

[0037] FIG2 is a schematic diagram of a display effect after an active layer of a thin film transistor in an array substrate provided by an embodiment of the present application is converted into a conductor;

[0038] FIG3 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0039] FIG4 is a top view of a substrate provided in an embodiment of the present application;

[0040] FIG5 is a partial schematic diagram of the array substrate provided in an embodiment of the present application in area A of FIG4 ;

[0041] FIG6 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present application;

[0042] FIG7 is a top view of a first pattern provided in an embodiment of the present application;

[0043] FIG8 is a partial schematic diagram of the array substrate provided in an embodiment of the present application in area B of FIG4 ;

[0044] FIG9 is a partial schematic diagram of the array substrate provided in an embodiment of the present application in area C of FIG4 ;

[0045] FIG10 is a schematic cross-sectional view of FIG9 along the DD direction;

[0046] FIG11 is a cross-sectional scanning electron microscope (SEM) image of FIG9 along the DD direction;

[0047] FIG12 is a cross-sectional schematic diagram of a second pattern provided in an embodiment of the present application;

[0048] FIG13 is a top view of a second pattern provided in an embodiment of the present application;

[0049] FIG14 is a circuit structure diagram of a shift register unit provided in an embodiment of the present application;

[0050] FIG15 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0051] FIG16 is a schematic structural diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0053] In related art, a thin film transistor includes: a gate, a gate insulating layer, an active layer, and a source / drain electrode layer stacked in sequence in a direction away from a substrate. The source / drain electrode layer includes a source electrode and a drain electrode spaced apart.

[0054] However, since the active layer of the thin film transistor is easily conductive during the preparation process, it is easy to cause abnormal characteristics of the thin film transistor, thereby resulting in a low yield rate of the array substrate and poor display effect of the display panel.

[0055] The process steps for oxide thin-film transistors are far fewer than those for low-temperature polysilicon thin-film transistors, and their mobility is much higher than that of amorphous silicon thin-film transistors. Oxide thin-film transistors also have good bending properties and low process temperatures, making them suitable for the manufacture of flexible substrates. Therefore, oxide thin-film transistors have good development prospects in future flexible displays.

[0056] However, compared to amorphous silicon thin-film transistors, oxide thin-film transistors are more susceptible to conductorization during the array substrate fabrication process, resulting in abnormal characteristics of the oxide thin-film transistors and, consequently, display panel abnormalities, significantly impacting the yield and low-cost advantages of oxide display panels. The term "oxide display panel" can be used to indicate that the thin-film transistors in the display panel are oxide thin-film transistors.

[0057] After testing, it was found that in the oxide display panel, due to the large blank area on one side of the row drive area, the active layer of the thin film transistor in the row drive area is easily conductive. Referring to Figure 1, before the active layer of a thin film transistor is conductive, the resistance is 10 10 Ω (ohm), and as the voltage increases, the resistance gradually decreases until the thin film transistor is turned on. However, after the active layer of the thin film transistor is conductive, the resistance is 10 4 Ω, the resistance does not change with the increase of voltage, which leads to the failure of the thin film transistor. Therefore, referring to FIG2 , the display effect of the display panel is poor, and horizontal stripes appear (weak dark lines appear every four rows).

[0058] In Figure 1, 1.00E+01 is used to represent 10 1 , 1.00E+02 is used to represent 10 2 , 1.00E+3 is used to represent 10 3 , and so on, I will not go into details.

[0059] FIG3 is a schematic diagram of the structure of an array substrate provided in an embodiment of the present application. Referring to FIG3 , it can be seen that the array substrate 10 may include a substrate 101 , a plurality of thin film transistors 102 , and a plurality of first patterns 103 .

[0060] Figure 4 is a top view of a substrate provided in an embodiment of the present application. Referring to Figures 3 and 4, the substrate 101 further includes a display area 101a and a peripheral area 101b surrounding the display area 101a. The peripheral area 101b includes at least a row drive region 101b1 extending along a first direction X. Thin-film transistors 102 are located at least in the row drive region 101b1. Alternatively, thin-film transistors 102 may be located in the display area 101a.

[0061] The thin film transistors 102 located in the row driving region 101b1 may constitute the gate driven on array (GOA) circuit of the array substrate 10. The thin film transistors 102 located in the display region 101a may constitute the driving circuit for driving the light emitting units in the array substrate 10 to emit light.

[0062] Figure 5 is a partial schematic diagram of the array substrate provided in an embodiment of the present application, shown in area A of Figure 4. In conjunction with Figures 4 and 5 , multiple first patterns 103 are located on at least one side of the row drive region 101b1. The multiple first patterns 103 are spaced apart from the row drive region 101b1 along the first direction X, and are arranged in an array with the multiple first patterns 103 on the same side of the row drive region 101b1.

[0063] Figure 6 is a schematic diagram of the structure of a thin-film transistor provided in an embodiment of the present application. Referring to Figure 6 , the thin-film transistor 102 includes: a gate 1021, a gate insulating layer 1022, an active layer 1023, and a source / drain layer 1024, stacked sequentially in a direction away from the substrate 101. The source / drain layer 1024 includes a source electrode 10241 and a drain electrode 10242 spaced apart from each other. The array substrate 10 includes multiple first patterns 103 located on the same layer as at least one of the source electrode 10241 and the drain electrode 10242 of the thin-film transistor 102. The multiple first patterns 103 being located on the same layer as at least one of the source electrode 10241 and the drain electrode 10242 can mean that the multiple first patterns 103 and at least one of the source electrode 10241 and the drain electrode 10242 are made of the same material and fabricated using the same patterning process. Typically, the source electrode 10241 and the drain electrode 10242 are made of the same material and fabricated using the same patterning process.

[0064] In the array substrate 10, there is usually a large blank area on one side of the row driving region 101b1 (i.e., an area where no wiring and thin film transistors are set). Therefore, designing multiple first patterns 103 on one side of the row driving region 101b1 can reduce the consumption of etching solution when etching the source and drain film layer to form the source 10241 and drain 10242 of the thin film transistor 102. This can avoid large-area etching and the consumption of a large amount of etching solution, ensuring that there is sufficient etching solution to etch the source 10241 and drain 10242 of the thin-film transistor 102 in the row driving area 101b1 and the display area 101a, thereby avoiding the residual material of the source and drain film layer due to the small amount of etching solution in the row driving area 101b1 and the display area 101a, avoiding the channel of the thin-film transistor 102 from being turned on due to the source and drain film material remaining above the active layer 1023, and avoiding the active layer 1023 of the thin-film transistor 102 from being conductive, thereby ensuring the characteristics of the thin-film transistor 102, and improving the yield of the array substrate 10 and the display effect of the display panel.

[0065] Furthermore, by designing a plurality of first patterns 103 on one side of the row driving region 101b1, the pattern of the source and drain film layer on one side of the row driving region 101b1 can be more uniform with the pattern of the source and drain film layer above the active layer in the display region.

[0066] In summary, an embodiment of the present application provides an array substrate, wherein a plurality of first patterns are designed on one side of a row driving region of the array substrate, thereby ensuring that there is sufficient etching solution to etch the source and drain electrodes of the thin-film transistors in the row driving region and the display region, thereby avoiding residual material of the source and drain film layers due to less etching solution in the row driving region and the display region, avoiding the channel of the thin-film transistor being turned on due to the residual material of the source and drain film layers above the active layer, avoiding the active layer of the thin-film transistor being conductive, ensuring the characteristics of the thin-film transistor, and improving the yield of the array substrate and the display effect of the display panel.

[0067] In the related art, to avoid the influence of static electricity, an electrostatic discharge (ESD) unit is designed on one side of the row drive region 101b1. This application removes the ESD unit in this area and designs multiple first patterns 103. The ESD unit is designed in the peripheral region 101b, located above the display region 101a (on the side of the display region 101a away from the fan-out region 101b2). For example, removing the ESD unit can be used to adjust the mask without increasing the cost of the mask or the difficulty of the process.

[0068] In the embodiment of the present application, the active layer of the thin film transistor 102 may be made of a metal oxide material, that is, the thin film transistor 102 may be an oxide thin film transistor.

[0069] In an embodiment of the present application, the source and drain film layers may include a first film layer, a second film layer, and a third film layer stacked in sequence. The first film layer and the third film layer may be made of a molybdenum-niobium alloy (MoNb), and the second film layer may be made of copper (Cu). In other words, the source and drain film layers may have a stacked structure of MoNb / Cu / MoNb.

[0070] Optionally, the orthographic projection of the first pattern 103 on the substrate 101 is a rectangle. The rectangle may be a right-angled rectangle, a chamfered rectangle, or a rounded rectangle. For example, the orthographic projection of the first pattern 103 on the substrate 101 is a square. That is, the orthographic projection of the first pattern 103 on the substrate 101 includes at least two perpendicular boundaries of equal length.

[0071] Referring to FIG. 5 , it can be seen that one of the two perpendicular boundaries of the first pattern 103 is parallel to the first direction X, and the other is parallel to the second direction Y. The second direction Y is parallel to the arrangement direction of the display area 101a and the row drive area 101b1. The first direction X and the second direction Y intersect, for example, perpendicularly. Multiple first patterns 103 are arranged in an array along the first direction X and the second direction Y.

[0072] Optionally, referring to FIG7 , the length of the first pattern 103 along the first direction X is m1, the distance between any two adjacent first patterns 103 along the first direction X is n1, and the ratio of m1 / n1 ranges from 0.9 to 1.9. The length of the first pattern 103 along the second direction Y is m2, the distance between any two adjacent first patterns 103 along the second direction Y is n2, and the ratio of m2 / n2 ranges from 0.9 to 1.9.

[0073] For example, the length m1 of the first pattern 103 along the first direction X and the length m2 along the second direction Y are both in the range of 12 μm (micrometers) to 15 μm. The distance n1 between any two adjacent first patterns 103 along the first direction X and the distance n2 between any two adjacent first patterns 103 along the second direction Y are both in the range of 8 μm to 13 μm. Referring to FIG7 , the orthographic projection of the first pattern 103 on the substrate 101 can be a rectangular shape with four chamfered corners, that is, the orthographic projection of the first pattern 103 on the substrate 101 is a chamfered rectangle.

[0074] Optionally, the minimum distance between the orthographic projections of the multiple first patterns 103 on the substrate 101 and the orthographic projections of other structures in the array substrate 10 on the substrate 101 ranges from 15 μm to 30 μm. In other words, the distance between the multiple first patterns 103 and other structures in the array substrate 10 can be larger to prevent the multiple first patterns 103 from affecting other structures in the array substrate 10. These other structures can be traces in the array substrate 10 for transmitting signals, or they can be thin-film transistors.

[0075] Referring to Figures 3 and 4 , the peripheral region 101b may include two row drive regions 101b1 extending along the first direction X, with the two row drive regions 101b1 located on either side of the display region 101a. Multiple first patterns 103 are located on either side of each row drive region 101b1. That is, the multiple first patterns 103 may include multiple first patterns 103 located in the first region, multiple first patterns 103 located in the second region, multiple first patterns 103 located in the third region, and multiple first patterns 103 located in the fourth region. For example, referring to Figure 8 , the multiple first patterns 103 located in the first region are arranged in an array in the upper left corner of the substrate 101. Additionally, the multiple first patterns 103 located in the second region are arranged in an array in the lower left corner of the substrate 101, the multiple first patterns 103 located in the third region are arranged in an array in the upper right corner of the substrate 101, and the multiple first patterns 103 located in the fourth region are arranged in an array in the lower right corner of the substrate 101.

[0076] With reference to FIG4 , it can be seen that the peripheral area 101b may further include a fan-out area 101b2 extending along the second direction Y. FIG9 is a partial schematic diagram of the array substrate provided in the C area of ​​FIG4 in an embodiment of the present application. With reference to FIG4 and FIG9 , the array substrate 10 further includes: a plurality of second patterns 104. The plurality of second patterns 104 are located on at least one side of the fan-out area 101b2, and the plurality of second patterns 104 are spaced apart from the fan-out area 101b2 along the second direction Y, and the plurality of second patterns 104 located on the same side of the fan-out area 101b2 are arranged in an array. The second pattern 104 is different from the first pattern 103 in at least one of the shape and size. Optionally, the shape of the orthographic projection of the second pattern 104 on the substrate 101 may be a rectangle.

[0077] Figure 10 is a cross-sectional view along the DD direction of Figure 9. Figure 11 is a schematic electron microscope view along the DD direction of Figure 9. Referring to Figures 10 and 11, the plurality of second patterns 104 include a plurality of first-type second patterns 104a and a plurality of second-type second patterns 104b. The plurality of first-type second patterns 104a are located on the same layer as the gate 1021, and the plurality of second-type second patterns 104b are located on the same layer as the source 10241 and drain 10242.

[0078] The plurality of first-type second patterns 104a being located in the same layer as the gate 1021 may mean that the plurality of first-type second patterns 104a and the gate 1021 are made of the same material and are produced by the same patterning process. The plurality of second-type second patterns 104b being located in the same layer as the source 10241 and the drain 10242 may mean that the plurality of second-type second patterns 104b and the source 10241 and the drain 10242 are made of the same material and are produced by the same patterning process.

[0079] In the embodiment of the present application, multiple second patterns 104 are designed in the fan-out area 101b2, which can also reduce the consumption of etching solution, thereby avoiding the residual material of the source and drain film layer due to the small amount of etching solution in the row driving area 101b1 and the display area 101a, preventing the channel of the thin film transistor 102 from being turned on due to the residual source and drain film material above the active layer 1023, and preventing the active layer 1023 of the thin film transistor 102 from being conductive, thereby ensuring the characteristics of the thin film transistor 102 and improving the display effect and yield of the array substrate.

[0080] Furthermore, the fan-out region 101b2 of the array substrate 10 is typically designed with multiple signal lines, and a portion of at least one of the multiple signal lines may be located on the same layer as the gate 1021, while another portion of the portion is located on the same layer as the source 10241 and the drain 10242. Therefore, by locating the multiple first-type second patterns 104a and the multiple second-type second patterns 104b in the multiple second patterns 104 on the same layer as the gate 1021 and the source 10241 (or the drain 10242), respectively, the design of the multiple second patterns 104 can be ensured to have good pattern uniformity with the design of the patterns (signal lines) in the fan-out region 101b2, thereby improving the yield of the array substrate 10.

[0081] Referring to Figure 10, the orthographic projections of multiple first-type second patterns 104a on the substrate 101 do not overlap with the orthographic projections of multiple second-type second patterns 104b on the substrate 101, which can avoid mutual influence between the multiple first-type second patterns 104a and the multiple second-type second patterns 104b, thereby ensuring the yield of the array substrate 10.

[0082] Optionally, referring to FIG. 10 , orthographic projections of a plurality of first-type second patterns 104 a on the substrate 101 and orthographic projections of a plurality of second-type second patterns 104 b on the substrate 101 are alternately arranged in the second direction Y.

[0083] Optionally, referring to FIG11 , an angle α between a connecting line between a first-type second pattern 104a and a second-type second pattern 104b closest to the first-type second pattern 104a and the supporting surface of the base substrate 101 may range from 25 degrees to 60 degrees.

[0084] In addition, the angle β between the boundary slope surface of each second pattern 104 and the supporting surface of the base substrate 101 ranges from 25 degrees to 60 degrees.

[0085] Alternatively, referring to Figure 12, the number of the plurality of first-type second patterns 104a and the plurality of second-type second patterns 104b are the same and correspond one to one. The orthographic projection of each first-type second pattern 104a on the substrate 101 overlaps with the orthographic projection of a corresponding second-type second pattern 104b on the substrate 101.

[0086] In the embodiment of the present application, the orthographic projection of the second pattern 104 on the substrate 101 is a rectangle, and the length of the second pattern 104 along the first direction X may be greater than the length along the second direction Y. For example, the second pattern 104 may be a strip-shaped structure extending along the first direction X.

[0087] Optionally, one of the two vertical boundaries of the first pattern 103 is parallel to the first direction X, and the other is parallel to the second direction Y. The second direction Y is parallel to the arrangement direction of the display area 101a and the row drive area 101b1. That is, the plurality of first patterns 103 are arranged in an array in the first direction X and the second direction Y.

[0088] Optionally, referring to FIG13 , the length of the second pattern 104 along the first direction X is r1, the distance between any two adjacent second patterns 104 along the first direction X is s1, and the ratio r1 / s1 ranges from 0.9 to 1.9. The length of the second pattern 104 along the second direction X is r2, the distance between any two adjacent second patterns 102 along the second direction Y is s2, and the ratio r2 / s2 ranges from 0.9 to 1.9.

[0089] Optionally, a length r1 of the second pattern 104 along the first direction X ranges from 50 μm to 100 μm, and a length r2 of the second pattern 104 along the second direction Y ranges from 2 μm to 10 μm. The length r1 of the second pattern 104 along the first direction X is not too large (the second pattern 104 may be a short rod-shaped structure), thereby preventing charge accumulation in the second pattern 104 due to the second pattern 104 being too long, thereby avoiding the risk of electrostatic discharge.

[0090] In addition, a distance s1 between any two second patterns 104 adjacent along the first direction X ranges from 50 μm to 100 μm, and a distance s2 between any two second patterns 104 adjacent along the second direction Y ranges from 3 μm to 10 μm.

[0091] 13 , the orthographic projection of the second pattern 104 on the substrate 101 may be a rectangle with four chamfered corners, that is, the orthographic projection of the second pattern 104 on the substrate 101 may be a chamfered rectangle.

[0092] Optionally, the minimum distance between the orthographic projections of the plurality of second patterns 104 on the substrate 101 and the orthographic projections of other structures in the array substrate 10 on the substrate 101 ranges from 75 μm to 100 μm. In other words, the distance between the plurality of second patterns 104 and other structures in the array substrate 10 can be greater to prevent the plurality of second patterns 104 from affecting other structures in the array substrate 10. These other structures can be traces in the array substrate 10 for transmitting signals, or they can be thin-film transistors.

[0093] In the embodiment of the present application, the plurality of second patterns 104 may be located on both sides of the fan-out region 101b2. For example, the plurality of second patterns 104 may include a plurality of second patterns 104 located in the fifth region and a plurality of second patterns 104 located in the sixth region. The fifth region and the sixth region are located on both sides of the fan-out region 101b2, respectively.

[0094] In the embodiment of the present application, the multiple thin film transistors 102 located in the row drive region 101b1 can form multiple cascaded shift register units. Each shift register unit can include 18 thin film transistors 102 and a storage capacitor. Of course, the shift register unit can also have other structures, which are not limited in the embodiment of the present application.

[0095] Figure 14 is a circuit diagram of a shift register unit provided in an embodiment of the present application. Referring to Figure 14 , it can be seen that the shift register unit 01 may include: an input circuit 011, a first reset circuit 012, an output circuit 013, a second reset circuit 014, a first pull control circuit 015, a first pull circuit 016, a second pull control circuit 017, a second pull circuit 018, and a storage capacitor C.

[0096] The input circuit 011 includes a first transistor M1 , wherein a gate electrode and a first electrode of the first transistor M1 are connected to the signal input terminal INPUT, and a second electrode of the first transistor M1 is connected to a pull-up node PU.

[0097] The first reset circuit 012 includes a second transistor M2 and a third transistor M4. The gate of the second transistor M2 is connected to the first reset signal terminal RES1, the first electrode of the second transistor M2 is connected to the pull-up node PU, and the second electrode of the second transistor M2 is connected to the first fixed voltage terminal LVGL. The gate of the third transistor M4 is connected to the first reset signal terminal RES1, the first electrode of the third transistor M4 is connected to the first signal output terminal OUT1, and the second electrode of the third transistor M4 is connected to the second fixed voltage terminal VGL.

[0098] The output circuit 013 includes a first output transistor M3 and a second output transistor M11. The gate of the first output transistor M3 is connected to the pull-up node PU, the first electrode of the first output transistor M3 is connected to the clock signal terminal CLK, and the second electrode of the first output transistor M3 is connected to the first signal output terminal OUT1. The gate of the second output transistor M11 is connected to the pull-up node PU, the first electrode of the second output transistor M11 is connected to the clock signal terminal CLK, and the second electrode of the second output transistor M11 is connected to the second signal output terminal OUT2.

[0099] The second reset circuit 014 includes: a fourth transistor M15, wherein a gate of the fourth transistor M15 is connected to the second reset signal terminal RES2, a first electrode of the fourth transistor M15 is connected to the pull-up node PU, and a second electrode of the fourth transistor M15 is connected to the first fixed voltage terminal LVGL;

[0100] The first pull-up control circuit 015 includes a fifth transistor M5A, a sixth transistor M6A, and a seventh transistor M7A. The gate and first electrode of the fifth transistor M5A are connected to the first control terminal VDDo, and the second electrode of the fifth transistor M5A is connected to the first pull-down node PD1. The gate of the sixth transistor M6A is connected to the pull-up node PU, the first electrode of the sixth transistor M6A is connected to the first pull-down node PD1, and the second electrode of the sixth transistor M6A is connected to the first fixed voltage terminal LVGL. The gate of the seventh transistor M7A is connected to the signal input terminal INPUT, the first electrode of the seventh transistor M7A is connected to the first pull-down node PD1, and the second electrode of the seventh transistor M7A is connected to the first fixed voltage terminal LVGL.

[0101] The first pull-up circuit 016 includes an eighth transistor M8A, a ninth transistor M12A, and a tenth transistor M13A. The gate of the eighth transistor M8A is connected to the first pull-down node PD1, the first electrode of the eighth transistor M8A is connected to the pull-up node PU, and the second electrode of the eighth transistor M8A is connected to the first fixed voltage terminal LVGL. The gate of the ninth transistor M12A is connected to the first pull-down node PD1, the first electrode of the ninth transistor M12A is connected to the second signal output terminal OUT2, and the second electrode of the ninth transistor M12A is connected to the first fixed voltage terminal LVGL. The gate of the tenth transistor M13A is connected to the first pull-down node PD1, the first electrode of the tenth transistor M13A is connected to the first signal output terminal OUT1, and the second electrode of the tenth transistor M13A is connected to the second fixed voltage terminal VGL.

[0102] The second pull-up control circuit 017 includes an eleventh transistor M5B, a twelfth transistor M6B, and a thirteenth transistor M7B. The gate and first electrode of the eleventh transistor M5B are connected to the second control terminal VDDe, and the second electrode of the fifth transistor M5A is connected to the second pull-down node PD2. The gate of the twelfth transistor M6B is connected to the pull-up node PU, the first electrode of the twelfth transistor M6B is connected to the second pull-down node PD2, and the second electrode of the twelfth transistor M6B is connected to the first fixed voltage terminal LVGL. The gate of the thirteenth transistor M7B is connected to the signal input terminal INPUT, the first electrode of the thirteenth transistor M7B is connected to the second pull-down node PD2, and the second electrode of the thirteenth transistor M7B is connected to the first fixed voltage terminal LVGL.

[0103] The second pull-up circuit 018 includes a fourteenth transistor M8B, a fifteenth transistor M12B, and a sixteenth transistor M13B. The gate of the fourteenth transistor M8B is connected to the second pull-down node PD2, the first electrode of the fourteenth transistor M8B is connected to the pull-up node PU, and the second electrode of the fourteenth transistor M8B is connected to the first fixed voltage terminal LVGL. The gate of the fifteenth transistor M12B is connected to the second pull-down node PD2, the first electrode of the fifteenth transistor M12B is connected to the second signal output terminal OUT2, and the second electrode of the fifteenth transistor M12B is connected to the first fixed voltage terminal LVGL. The gate of the sixteenth transistor M13B is connected to the second pull-down node PD2, the first electrode of the sixteenth transistor M13B is connected to the first signal output terminal OUT1, and the second electrode of the sixteenth transistor M13B is connected to the second fixed voltage terminal VGL.

[0104] A first electrode of the storage capacitor C is connected to the pull-up node PU, and a second electrode of the storage capacitor C is connected to the first signal output terminal OUT1.

[0105] Among them, one of the first electrode and the second electrode of each transistor is a source electrode, and the other is a drain electrode.

[0106] In the embodiment of the present application, the thickness of the source and drain layer 1024 can be 350 nm (nanometers), and the thickness of the gate 1021 can be 345 nm. Of course, the thickness of the source and drain layer 1024 and the thickness of the gate 1021 can also be other thicknesses, which are not limited in the embodiment of the present application.

[0107] In summary, an embodiment of the present application provides an array substrate, wherein a plurality of first patterns are designed on one side of a row driving region of the array substrate, thereby ensuring that there is sufficient etching solution to etch the source and drain electrodes of the thin-film transistors in the row driving region and the display region, thereby avoiding residual material of the source and drain film layers due to less etching solution in the row driving region and the display region, avoiding the channel of the thin-film transistor being turned on due to the residual material of the source and drain film layers above the active layer, avoiding the active layer of the thin-film transistor being conductive, ensuring the characteristics of the thin-film transistor, and improving the yield of the array substrate and the display effect of the display panel.

[0108] Figure 15 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Referring to Figure 15 , it can be seen that the display panel 01 may include multiple light-emitting units 20 and an array substrate 10 as provided in the above embodiment. The multiple light-emitting units 20 may be located in the display area 101a of the array substrate 10. The light-emitting units 20 shown in Figure 15 are merely intended to indicate that the light-emitting units 20 are located in the display area 101a and do not represent the actual shape of the light-emitting units 20.

[0109] FIG16 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Referring to FIG16 , the display device may include: a power supply component 02 and a display panel 01 provided in the above embodiment. The power supply component 02 may be used to supply power to the display panel 01.

[0110] Optionally, the display device can be: a liquid crystal display (LCD), an organic light-emitting diode (OLED) display device, electronic paper, a low temperature polycrystalline silicon (LTPS) display device, a low temperature polycrystalline oxide (LTPO) display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0111] The transistors in all embodiments of the present application can be thin film transistors. According to the role in the circuit, the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present application, the source is referred to as the first level and the drain is referred to as the second level. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiments of the present application may include any one of an N-type switching transistor and a P-type switching transistor, wherein the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level, and the P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level.

[0112] It will be understood that although the terms first, second, etc. may be used to describe various elements, components, areas, layers and / or parts in this article, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer or part from another area, layer or part. Therefore, the first element, component, area, layer or part discussed above can be referred to as the second element, component, area, layer or part without departing from the teachings of the present disclosure.

[0113] Spatially relative terms such as "row," "column," "under," "above," "left," "right," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is flipped, the element described as "under other elements or features" will be oriented as "above other elements or features." Thus, the exemplary term "under" can encompass both orientations of above and below. The device can be oriented otherwise (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between two layers," it can be the only layer between the two layers, or one or more intermediate layers may also be present.

[0114] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the existence of the features, integral bodies, steps, operations, elements and / or parts when used in this specification, but do not exclude the existence of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups or add one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In this specification, the specific features, structures, materials or characteristics of description can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples without contradicting each other.

[0115] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0116] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: The array substrate (10) comprises: A substrate (101), the substrate (101) having a display area (101a) and a peripheral area (101b) surrounding the display area (101a), the peripheral area (101b) at least including a row driving area (101b1) extending along a first direction (X); A plurality of thin film transistors (102), wherein the plurality of thin film transistors (102) are at least located in the row driving region (101b1); and, a plurality of first patterns (103), the plurality of first patterns (103) being located at least on one side of the row drive region (101b1), and the plurality of first patterns (103) and the row drive region (101b1) being arranged at intervals along the first direction (X), and the plurality of first patterns (103) located on the same side of the row drive region (101b1) being arranged in an array; The thin film transistor (102) comprises: a gate electrode (1021), a gate insulating layer (1022), an active layer (1023), and a source-drain electrode layer (1024) stacked in sequence in a direction away from the substrate (101); the source-drain electrode layer (1024) comprises a source electrode (10241) and a drain electrode (10242) arranged at intervals; and the plurality of first patterns (103) are located in the same layer as at least one of the source electrode (10241) and the drain electrode (10242).

2. The array substrate according to claim 1, wherein: The shape of the orthographic projection of the first pattern (103) on the substrate (101) is a rectangle.

3. The array substrate according to claim 2, wherein: The shape of the orthographic projection of the first pattern (103) on the substrate (101) is a square.

4. The array substrate according to claim 3, wherein: One of the two vertical boundaries in the first pattern (103) is parallel to the first direction (X), and the other boundary is parallel to the second direction (Y); The second direction (Y) is parallel to the arrangement direction of the display area (101a) and the row drive area (101b1), and the first direction (X) and the second direction (Y) intersect.

5. The array substrate according to claim 4, wherein: The length of the first pattern (103) along the first direction (X) is m1, the distance between any two adjacent first patterns (103) along the first direction (X) is n1, and the ratio of m1 / n1 ranges from 0.9 to 1.9; The length of the first pattern (103) along the second direction (Y) is m2, the distance between any two adjacent first patterns (103) along the second direction (Y) is n2, and the ratio of m2 / n2 ranges from 0.9 to 1.

9.

6. The array substrate according to any one of claims 1 to 5, characterized in that: The minimum distance between the orthographic projections of the plurality of first patterns (103) on the substrate (101) and the orthographic projections of other structures in the array substrate (10) on the substrate (101) ranges from 15 micrometers to 30 micrometers.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The peripheral area (101b) comprises two row drive areas (101b1) extending along the first direction (X), and the two row drive areas (101b1) are respectively located on both sides of the display area (101a); The plurality of first patterns (103) are located on both sides of each row driving region (101b1).

8. The array substrate according to any one of claims 1 to 7, wherein: The peripheral area (101b) further includes a fan-out area (101b2) extending along a second direction (Y), wherein the second direction (Y) is parallel to the arrangement direction of the row drive area (101b1) and the display area (101a); the array substrate (10) further includes: a plurality of second patterns (104), the plurality of second patterns (104) being located at least on one side of the fan-out region (101b2), and the plurality of second patterns (104) and the fan-out region (101b2) being arranged at intervals along the second direction (Y), the plurality of second patterns (104) located on the same side of the fan-out region (101b2) being arranged in an array, and the second patterns (104) being different from the first patterns (103) in at least one of shape and size; The plurality of second patterns (104) include: a plurality of first-type second patterns (104a) and a plurality of second-type second patterns (104b); the plurality of first-type second patterns (104a) and the gate (1021) are located in the same layer; and the plurality of second-type second patterns (104b) and the source (10241) and the drain (10242) are located in the same layer.

9. The array substrate according to claim 8, wherein: The orthographic projections of the plurality of first-type second patterns (104a) on the substrate (101) do not overlap with the orthographic projections of the plurality of second-type second patterns (104b) on the substrate (101).

10. The array substrate according to claim 9, wherein: The orthographic projections of the plurality of first-type second patterns (104a) on the substrate (101) and the orthographic projections of the plurality of second-type second patterns (104b) on the substrate (101) are arranged alternately in the second direction (Y).

11. The array substrate according to claim 8, wherein: The plurality of first-type second patterns (104a) and the plurality of second-type second patterns (104b) are the same in number and correspond one to one; The orthographic projection of each first-type second pattern (104a) on the substrate (101) overlaps with the orthographic projection of a corresponding second-type second pattern (104b) on the substrate (101).

12. The array substrate according to any one of claims 8 to 11, characterized in that: The shape of the orthographic projection of the second pattern (104) on the substrate (101) is a rectangle, and the length of the second pattern (104) along the first direction (X) is greater than the length along the second direction (Y).

13. The array substrate according to claim 12, wherein: One of the two vertical boundaries in the second pattern (104) is parallel to the first direction (X), and the other boundary is parallel to the second direction (Y).

14. The array substrate according to claim 13, wherein: The length of the second pattern (104) along the first direction (X) is r1, the distance between any two adjacent second patterns (104) along the first direction (X) is s1, and the ratio of r1 / s1 ranges from 0.9 to 1.9; The length of the second pattern (104) along the second direction (Y) is r2, the distance between any two adjacent second patterns (104) along the second direction (Y) is s2, and the ratio of r2 / s2 ranges from 0.9 to 1.

9.

15. The array substrate according to any one of claims 8 to 14, characterized in that: The minimum distance between the orthographic projection of the second pattern (104) on the substrate (101) and the orthographic projection of other structures in the array substrate (10) on the substrate (101) ranges from 75 micrometers to 100 micrometers.

16. The array substrate according to any one of claims 8 to 15, characterized in that: The plurality of second patterns (104) are located on both sides of the fan-out area (101b2).

17. The array substrate according to any one of claims 1 to 16, characterized in that: The plurality of thin film transistors (102) located in the row drive region (101b1) constitute a plurality of cascaded shift register units, and each shift register unit includes 18 thin film transistors (102) and a storage capacitor.

18. The array substrate according to any one of claims 1 to 17, characterized in that: The active layer of the thin film transistor (102) is made of metal oxide material.

19. A display panel, characterized in that: The display panel comprises a plurality of light-emitting units (20) and an array substrate (10) according to any one of claims 1 to 18; Wherein, the plurality of light-emitting units (20) are located in the display area (101a) of the array substrate (10).

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