Display substrate and display device

Abstract

The invention provides a display substrate and a display device.The display substrate comprises a substrate body, a plurality of pixel units and a plurality of data lines; at least one sub-pixel comprises a common electrode, and the common electrode comprises a dark area electrode part and a light-transmitting area electrode part; a plurality of slits are formed in the common electrode, the end of at least one slit comprises a first part, a second part and a third part, the second part is located between the first part and the third part, and the first part and the adjacent dark area electrode part are arranged side by side in the first direction; the second part and one part of the adjacent light-transmitting area electrode part are arranged side by side along the first direction, and the third part and the other part of the adjacent light-transmitting area electrode part are arranged side by side along the first direction; the inclination degree of the second part of at least one end of the at least one slit is larger than that of the third part, and the inclination degree of the second part is smaller than that of the first part.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the development of touch technology, more and more display devices use touch for human-computer interaction. In addition to being able to be operated with fingers, touch display devices can also be operated with styluses, which include active pens and passive pens.

[0003] Taking an active pen as an example, when in use, an active pen signal emitted by the active pen is transmitted to a touch integrated circuit via the touch panel, and processed by the touch integrated circuit to obtain the precise coordinates of the active pen on the touch panel.

[0004] Touch display devices can be categorized by their structure into add-on touch panels (add-on mode touch panels), on-cell touch panels, and in-cell touch panels. With the increasing popularity of active pens in products like notebook computers (NBs), tablet PCs (Tablet PCs), and mobile phones, in-cell touch panels have attracted widespread attention due to their numerous advantages, including high compatibility, excellent touch performance, low cost, and thinness. However, the transmittance of current in-cell touch panels is limited by numerous factors, making further improvement difficult.

[0005] Summary of the Invention

[0006] In view of the above problems, the present disclosure provides a display substrate and a display device.

[0007] A first aspect of the present disclosure provides a display substrate, comprising:

[0008] substrate;

[0009] A plurality of pixel units are provided on the substrate, wherein the plurality of pixel units are arranged in an array along a first direction and a second direction;

[0010] A plurality of data lines are provided on the base substrate, and the plurality of data lines are arranged along the first direction;

[0011] in,

[0012] At least one of the pixel units includes a plurality of sub-pixels, and at least one of the sub-pixels includes a common electrode;

[0013] In at least one of the sub-pixels, the common electrode includes a dark region electrode portion and a light-transmitting region electrode portion arranged along the second direction;

[0014] The common electrode is provided with a plurality of slits, at least one of the slits includes at least one end portion, and the at least one end portion includes a first portion, a second portion, and a third portion arranged along a second direction, the second portion is located between the first portion and the third portion, the first portion and an adjacent dark-area electrode portion are arranged side by side along the first direction, the second portion and a portion of an adjacent light-transmitting area electrode portion are arranged side by side along the first direction, and the third portion and another portion of the adjacent light-transmitting area electrode portion are arranged side by side along the first direction; and

[0015] The orthographic projection of at least one end of at least one of the slits on the base substrate is tilted relative to the second direction, and the inclination of the second part in the end is greater than the inclination of the third part, and the inclination of the second part is less than the inclination of the first part.

[0016] According to an embodiment of the present disclosure, at least one of the sub-pixels further includes a thin film transistor, and in the sub-pixel, the dark-area electrode portion on the common electrode includes a first dark-area electrode portion, and at least one end portion of at least one of the slits includes a first end portion;

[0017] The orthographic projection of the first dark-area electrode portion on the base substrate is located on a side of the orthographic projection of the light-transmitting-area electrode portion on the base substrate that is away from the orthographic projection of the thin film transistor for driving the at least one sub-pixel on the base substrate;

[0018] The first end portion and the adjacent first dark-sector electrode portion are arranged side by side along a first direction.

[0019] According to an embodiment of the present disclosure, in at least one of the sub-pixels, the dark-area electrode portion of the common electrode further includes a second dark-area electrode portion, and in the second direction, an orthographic projection of the second dark-area electrode portion on the base substrate is located on a side of the orthographic projection of the light-transmitting-area electrode portion on the base substrate that is close to an orthographic projection of a thin film transistor for driving the at least one sub-pixel on the base substrate;

[0020] At least one end portion of at least one of the slits further includes a second end portion, and a first portion of the second end portion and an adjacent second dark-sector electrode portion are arranged side by side along the first direction.

[0021] According to an embodiment of the present disclosure, at least one of the sub-pixels further includes a thin film transistor, and in the sub-pixel, the dark-area electrode portion on the common electrode includes a second dark-area electrode portion, and at least one end portion of at least one of the slits includes a second end portion;

[0022] The orthographic projection of the second dark-area electrode portion on the base substrate is located on a side of the orthographic projection of the light-transmitting-area electrode portion on the base substrate close to the orthographic projection of the thin film transistor for driving the at least one sub-pixel on the base substrate;

[0023] The second end portion and the adjacent second dark-sector electrode portion are arranged side by side along the first direction.

[0024] According to an embodiment of the present disclosure, in at least one of the sub-pixels, one end of the plurality of slits on the common electrode close to the thin film transistor is a second end, and the plurality of slits include a first slit and a second slit;

[0025] In the second direction, an orthographic projection of the second end portion of the first slit on the base substrate protrudes beyond an orthographic projection of the second end portion of the second slit on the base substrate.

[0026] According to an embodiment of the present disclosure, in at least one of the sub-pixels, in the second direction, the orthographic projection of the second portion of the second end portion of the first slit on the base substrate at least partially protrudes beyond the orthographic projection of the first portion of the second end portion of the second slit on the base substrate.

[0027] According to an embodiment of the present disclosure, in at least one of the sub-pixels, the orthographic projection of the second portion of the second end portion of the first slit on the base substrate at least partially overlaps with the orthographic projection of the thin film transistor for driving the sub-pixel on the base substrate in the first direction.

[0028] According to an embodiment of the present disclosure, at least one of the slits includes a first end and a second end, and extension directions of the third portion of the first end and the third portion of the second end are intersecting or parallel to each other.

[0029] According to an embodiment of the present disclosure, in at least one end portion of at least one of the slits, the orthographic projection of the first portion on the substrate is tilted at a first tilt angle relative to the second direction, and the orthographic projection of the second portion on the substrate is tilted at a second tilt angle relative to the second direction, and both the first tilt angle and the second tilt angle are acute angles; the angle ratio of the second tilt angle to the first tilt angle is between 0.1:1 and 0.3:1.

[0030] According to an embodiment of the present disclosure, in at least one end of at least one of the slits, the orthographic projection of the third part on the substrate is tilted at a third inclination angle relative to the second direction, and the third inclination angle is an acute angle; the angle ratio of the third inclination angle to the second inclination angle is between 0.5:1 and 0.9:1.

[0031] According to an embodiment of the present disclosure, in at least one end portion of at least one of the slits, a ratio of a size of the second portion in the second direction to a size of the first portion in the second direction is between 2.7:1 and 3.3:1.

[0032] According to an embodiment of the present disclosure, the display substrate further includes a plurality of touch lines disposed on the base substrate, at least one of the sub-pixels further includes a pixel electrode, and the plurality of touch lines are arranged along the first direction;

[0033] The multiple slits on the common electrode of at least one of the sub-pixels also include a third slit. For the pixel electrode in at least one of the sub-pixels and the touch line closest to the pixel electrode in the first direction, the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the touch line on the base substrate at least partially overlap with the orthographic projection of the third slit in the sub-pixel on the base substrate, and the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the touch line on the base substrate are spaced apart.

[0034] According to an embodiment of the present disclosure, in at least one of the sub-pixels, in the first direction, the orthographic projection of the third slit on the base substrate is located on a side of the orthographic projection of the first slit on the base substrate away from the orthographic projection of the second slit on the base substrate.

[0035] According to an embodiment of the present disclosure, the display substrate further includes a plurality of shielding electrodes located in the common electrode layer, and an orthographic projection of at least one of the shielding electrodes on the base substrate covers an orthographic projection of at least one of the data lines on the base substrate.

[0036] According to an embodiment of the present disclosure, the plurality of touch lines and the plurality of data lines are provided in the same layer and with the same material, and the touch lines and the common electrodes in the common electrode layer are loaded with the same electrical signal.

[0037] According to an embodiment of the present disclosure, in at least one of the sub-pixels, in the second direction, an orthographic projection of the second end of the third slit on the base substrate protrudes beyond an orthographic projection of the second end of the second slit on the base substrate.

[0038] According to an embodiment of the present disclosure, in at least one of the sub-pixels, in the second direction, an orthographic projection of the second end of the first slit on the base substrate protrudes beyond an orthographic projection of the second end of the third slit on the base substrate.

[0039] According to an embodiment of the present disclosure, in at least one of the sub-pixels, a ratio of the slit widths of the third slit to the first slit is between 2:1 and 3:1.

[0040] According to an embodiment of the present disclosure, in at least one of the sub-pixels, the orthographic projection of the first portion of the second end portion of the third slit on the base substrate at least partially overlaps with the orthographic projection of the thin film transistor for driving the sub-pixel on the base substrate in the first direction.

[0041] According to an embodiment of the present disclosure, at least one of the touch lines includes a touch line body and a transition portion arranged along the second direction, a portion where the touch line body is connected to the transition portion is provided with a bending structure, and an orthographic projection of the second end portion of the third slit in at least one of the sub-pixels on the base substrate at least partially overlaps with an orthographic projection of the bending structure on the base substrate.

[0042] According to an embodiment of the present disclosure, at least one of the sub-pixels includes a light-transmitting area and a dark area at least partially surrounding the light-transmitting area, and the transmittance of the dark area is lower than the transmittance of the light-transmitting area;

[0043] In at least one of the sub-pixels, the orthographic projection of the dark area electrode portion on the common electrode on the base substrate is located within the range of the orthographic projection of the dark area on the base substrate, and the orthographic projection of the light-transmitting area electrode portion on the base substrate is located within the range of the orthographic projection of the light-transmitting area on the base substrate.

[0044] According to an embodiment of the present disclosure, a size of the dark space electrode portion in the second direction is set between 2 μm and 3 μm.

[0045] A second aspect of the present disclosure provides a display device, comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0047] FIG1A schematically shows a schematic diagram of an in-cell touch panel using 1P1T in one example;

[0048] FIG1B schematically shows a schematic diagram of an in-cell touch panel using 1P3T in an example;

[0049] FIG2 schematically shows a schematic diagram of a display substrate in an embodiment of the present disclosure;

[0050] FIG3 schematically shows a superposition of some film layers in a display substrate according to an embodiment of the present disclosure;

[0051] FIG4 schematically shows a schematic diagram of two sub-pixels arranged along a first direction in an embodiment of the present disclosure;

[0052] FIG5 is an enlarged view of position M in FIG4 ;

[0053] FIG6 schematically shows a schematic diagram of a sub-pixel light-emitting area in an embodiment of the present disclosure;

[0054] FIG7 schematically shows the inclination angles of various parts on the first end portion in an embodiment of the present disclosure;

[0055] FIG8 schematically shows a schematic diagram of the division of the inclination degree of the slits on the common electrode;

[0056] FIG9 shows an enlarged view of position N in FIG4 ;

[0057] FIG10 schematically shows the dimensions of each slit in an embodiment of the present disclosure;

[0058] FIG11 schematically shows a diagram of forming an electric field for driving liquid crystal deflection in a pair of ratios;

[0059] FIG12 schematically shows a schematic diagram of forming an electric field for driving liquid crystal deflection in an embodiment of the present disclosure;

[0060] FIG13 schematically shows a comparison diagram of the sub-pixel light-emitting area in a ratio and the sub-pixel light-emitting area in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0062] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0063] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0064] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0065] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0066] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0067] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0068] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0069] Currently, embedded touch panels can adopt pixel designs such as 1P1T, 1P2T or 1P3T, among which 1P1T refers to the corresponding setting of one pixel unit and one touch line, 1P2T refers to the corresponding setting of one pixel unit and two touch lines, and 1P3T refers to the corresponding setting of one pixel unit and three touch lines.

[0070] For example, FIG1A schematically illustrates an example of an in-cell touch panel using 1P1T, and FIG1B schematically illustrates an example of an in-cell touch panel using 1P3T. Referring to FIG1A , in an in-cell touch panel using 1P1T, one pixel unit P' is corresponding to one touch line Tx'. For example, one pixel unit P' includes multiple sub-pixels Px' of different colors, and the touch line Tx' is located to the left of the leftmost sub-pixel Px' in the corresponding pixel unit P'. Referring to FIG1B , in an in-cell touch panel using 1P3T, one pixel unit P' is corresponding to three touch lines Tx'. For example, the three touch lines Tx' are located to the left of each sub-pixel Px' in the corresponding pixel unit P'.

[0071] For example, the embedded touch panel in a mobile phone can adopt a 1P1T pixel design. Compared with a mobile phone, the display panel in a laptop computer is larger in size, and more touch lines need to be laid out to ensure the touch effect. Therefore, a 1P3T pixel design can be adopted.

[0072] Continuing with Figures 1A and 1B, in the examples shown in these two figures, to save costs, the touch line Tx' and the data line DL' are arranged in the same layer and material. The touch line Tx' and the adjacent data line DL' are roughly parallel. However, while this approach can reduce costs, it also has certain drawbacks. Specifically, because the touch line Tx' and the adjacent data line DL' are arranged in the same layer and parallel, the touch line Tx' encroaches on the light-emitting area of ​​the sub-pixel Px', thereby affecting the product's luminous efficiency. Moreover, this problem increases significantly with the number of touch lines Tx'. For example, in a display panel using 1P3T, the number of touch lines Tx' is approximately three times the number of touch lines Tx' in a display panel using 1P1T. This exacerbates the situation in which the touch line Tx' encroaches on the light-emitting area of ​​the sub-pixel Px' in the 1P3T display panel, resulting in lower transmittance for the in-cell touch panel using 1P3T. Therefore, how to improve the transmittance of this product has become a technical problem that needs to be solved urgently.

[0073] In view of this, an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, a plurality of pixel units disposed on the base substrate, a plurality of data lines disposed on the base substrate, a common electrode layer disposed on the base substrate, and a thin-film transistor layer disposed on the base substrate. The plurality of pixel units are arranged in an array along a first direction and a second direction. The plurality of data lines are arranged along the first direction. At least one pixel unit includes a plurality of sub-pixels, and at least one sub-pixel includes a common electrode disposed in the common electrode layer and a thin-film transistor disposed in the thin-film transistor layer. In at least one sub-pixel, the common electrode includes a dark-sector electrode portion and a light-transmitting electrode portion disposed along the second direction. The common electrode is provided with a plurality of slits, and at least one slit includes at least one end portion, and at least one end portion includes a first portion, a second portion, and a third portion disposed along the second direction, the second portion being located between the first portion and the third portion, the first portion being arranged side by side with an adjacent dark-sector electrode portion along the first direction, the second portion being arranged side by side with a portion of an adjacent light-transmitting electrode portion along the first direction, and the third portion being arranged side by side with another portion of an adjacent light-transmitting electrode portion along the first direction. Furthermore, the orthographic projection of at least one end of at least one slit on the substrate is tilted relative to the second direction, and the inclination of the second part of the end is greater than the inclination of the third part, and the inclination of the second part is less than the inclination of the first part.

[0074] In the embodiments of the present disclosure, the first portion of the slit, or what may also be called a corner structure, can improve trace mura. However, the first portion has a large inclination, which results in a positive correlation between the size of the first portion in the second direction and the area of ​​the dark region. Therefore, in the embodiments of the present disclosure, a second portion is added between the first and third portions of the slit, and the inclination of the second portion is made between the first and third portions. In this way, the second and first portions can jointly improve trace mura, but the size of the first portion in the second direction is reduced. In this way, the dark region area can be reduced, thereby improving transmittance.

[0075] The display substrate according to the embodiment of the present disclosure is described in detail below.

[0076] FIG2 schematically shows a schematic diagram of a display substrate in an embodiment of the present disclosure. Referring to FIG2 , the display substrate in this embodiment includes a display area AA and a peripheral area NA at least partially surrounding the display area AA.

[0077] The display substrate may further include a gate drive circuit 11 and a drive chip 12 located in the peripheral area NA. For example, the gate drive circuit 11 may be located on at least one side of the display area AA. In the embodiment shown in FIG2 , the gate drive circuit 11 is respectively located on the left and right sides of the display area AA. It should be noted that the left and right sides may be the left and right sides of the display substrate (screen) viewed by the human eye during display. For example, the drive chip 12 may be located on at least one side of the display area AA. In the embodiment shown in FIG2 , the drive chip 12 is located on the lower side of the display area AA. It should be noted that the lower side may be the lower side of the display substrate (screen) viewed by the human eye during display.

[0078] The gate drive circuit 11 may be implemented by a shift register and may provide scan signals to each gate line (not shown) on the display substrate. The driver chip 12 may include a data drive circuit and may provide data signals to each data signal line DL on the display substrate.

[0079] It should be noted that although Figure 2 shows that the gate drive circuit 11 is located on the left and right sides of the display area AA and the drive chip 12 is located on the lower side of the display area AA, the embodiments of the present disclosure are not limited to this. The gate drive circuit 11 and the drive chip 12 can be located at any suitable position in the peripheral area NA.

[0080] For example, the gate driver circuit 11 can adopt GOA technology, i.e., Gate Driver on Array (GDA). In GOA technology, the gate driver circuit 11 is directly provided on the array substrate, replacing an external chip. Each GOA unit acts as a shift register, and each shift register is connected to a gate line. The shift registers at each level sequentially output scanning signals in turn to achieve row-by-row scanning of the pixel units. In some embodiments, each shift register can also be connected to multiple gate lines. This can adapt to the development trend of high-resolution and narrow-frame display substrates.

[0081] The display substrate may further include a base substrate 100 and a plurality of pixel units P disposed on the base substrate 100 and located in the display area AA. The plurality of pixel units P are arranged in an array along a first direction X and a second direction, where the first direction X intersects the second direction Y. For example, the first direction X is the horizontal direction in FIG. 2 , and the second direction Y is the vertical direction in FIG. 2 , that is, the first direction X and the second direction Y are perpendicular to each other.

[0082] At least one pixel unit P includes multiple sub-pixels Px, and the multiple sub-pixels Px can display different colors through corresponding color filters. For example, the multiple sub-pixels Px in a pixel unit P may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel can be matched with a red color filter to display red light, the second sub-pixel can be matched with a green color filter to display green light, and the third sub-pixel can be matched with a blue color filter to display blue light.

[0083] It should be noted that FIG2 exemplarily shows that the orthographic projection of the sub-pixel on the substrate is a rectangle, but the embodiments of the present disclosure are not limited thereto. Moreover, the arrangement of the three sub-pixels in a pixel unit P is not limited to that shown in FIG2 .

[0084] The display substrate may further include a plurality of data lines DL disposed on the base substrate 100 and located in the display area AA. As shown in FIG. 2 , at least one of the plurality of data lines DL may extend from the upper end of the display area AA to the lower end of the display area AA, thereby being electrically connected to the driver chip 12 located at the lower end of the display area AA.

[0085] In an embodiment of the present disclosure, a plurality of data lines DL are arranged along a first direction X, and at least one data line DL is electrically connected to a plurality of sub-pixels Px arranged along a second direction.

[0086] As shown in FIG2 , a plurality of sub-pixels Px on a display substrate may be arranged in an array along a first direction X and a second direction Y. At least a portion of the sub-pixels Px in each column may be electrically connected to the same data line DL. For example, for a column of sub-pixels Px, all sub-pixels Px in the column of sub-pixels Px are electrically connected to the same data line DL; alternatively, sub-pixels Px in odd-numbered rows of the column of sub-pixels Px are electrically connected to the same data line, while sub-pixels Px in even-numbered rows are electrically connected to another data line DL.

[0087] FIG3 schematically shows a diagram of the stacking of some film layers in a display substrate in an embodiment of the present disclosure. It should be noted that, for clarity, FIG3 only shows the base substrate 100, the common electrode layer 110, the pixel electrode 120, the liquid crystal layer 140, the second conductive layer 150, and the insulating layer 160 located between the conductive film layers. Other film layers, such as the gate layer, are hidden. Referring to FIG3 , the display substrate may further include a common electrode layer 110 and a pixel electrode layer 120 disposed on the base substrate 100. At least one sub-pixel Px may include a common electrode 111 located in the common electrode layer 110 and a pixel electrode 121 located in the pixel electrode layer 120. Optionally, the pixel electrode layer 120 is located between the common electrode layer 110 and the base substrate 100.

[0088] The display substrate disclosed herein can be applied to a liquid crystal display panel. In an embodiment of the present disclosure, the orthographic projection of the pixel electrode 121 of the sub-pixel Px on the substrate 100 is tilted relative to the second direction Y. For example, FIG4 schematically shows a schematic diagram of two sub-pixels arranged along the first direction in an embodiment of the present disclosure. As shown in FIG4 , the pixel electrode 121 in the sub-pixel Px may include two parts, one of which is arranged toward the third direction and the other is arranged toward the fourth direction, and the third direction, the fourth direction, and the second direction Y intersect with each other. The orthographic projection of the common electrode 111 in the sub-pixel Px on the substrate 100 is tilted relative to the second direction Y. For example, as shown in FIG4 , the common electrode 111 in the sub-pixel Px includes two parts, one of which is arranged toward the third direction and the other is arranged toward the fourth direction. In this way, a dual-domain electric field can be formed between the pixel electrode 121 and the common electrode 111, which can improve the color shift problem of the liquid crystal display panel and increase the viewing angle.

[0089] In addition, the orthographic projection of the signal line adjacent to the sub-pixel Px in the first direction X on the substrate 100 may also be arranged obliquely relative to the second direction Y. For example, as shown in FIG. 4 , the data line DL may also be divided into two parts, with the two parts being arranged obliquely toward the third direction and the fourth direction, respectively. It should be noted that a signal line adjacent to a sub-pixel Px may specifically mean that there are no other signal lines of the same type between the two. For example, a data line DL adjacent to a sub-pixel Px may specifically mean that there are no other data lines DL between the two.

[0090] 5 is an enlarged view of a position M in FIG. 4 . Referring to FIG. 4 and FIG. 5 , in at least one sub-pixel Px, the common electrode 111 includes a dark region electrode portion 1111 and a light-transmitting region electrode portion 1112 arranged along the second direction Y. FIG.

[0091] In the embodiments of the present disclosure, the display substrate may be a display substrate used in a liquid crystal display panel. As shown in FIG3 , the display substrate further includes a liquid crystal layer 140, and at least one subpixel Px further includes a light adjustment portion 141 located in the liquid crystal layer 140. When the liquid crystal display panel is displaying, a driving voltage is applied to the pixel electrode 121 and the common electrode 111 of the subpixel Px that needs to emit light, thereby forming an electric field between the common electrode 111 and the pixel electrode 121 of the subpixel Px. The liquid crystal in the light adjustment portion 141 of the subpixel Px is driven by the electric field and deflected, thereby achieving light control.

[0092] Figure 6 schematically shows a schematic diagram of the sub-pixel light-emitting area in an embodiment of the present disclosure. As shown in Figure 6, for a sub-pixel Px, the sub-pixel may include a light-transmitting area TE and a dark area DE at least partially surrounding the light-transmitting area TE. When a driving voltage is applied to the sub-pixel Px to drive the sub-pixel Px to emit light, the light-transmitting area TE is used to emit light to achieve a display function, and the dark area DE emits less or even no light, thereby visually appearing in a dark state, so it is called a dark area DE.

[0093] It should be noted that FIG6 only shows the relative positions of the light-transmitting area TE and the dark area DE, and this does not constitute a limitation on their specific morphologies.

[0094] In some specific embodiments, the orthographic projection of the dark area electrode portion 1111 on the base substrate 100 is located within the range of the orthographic projection of the dark area DE on the base substrate 100. In the embodiments of the present disclosure, the dark area DE and the light-transmitting area TE are arranged along the second direction Y. For example, in some specific embodiments, the dark area DE includes a first dark area Dea, which is closer to the previous row of sub-pixels Px than the light-transmitting area TE. For another example, in some specific embodiments, the dark area DE includes a second dark area Deb, which is closer to the next row of sub-pixels Px than the light-transmitting area TE. For another example, in some specific embodiments, the dark area DE includes at least two portions arranged along the second direction Y, the two portions being separated by the light-transmitting area TE, one portion being closer to the previous row of sub-pixels Px, and this portion can be referred to as the first dark area DEa, and the other portion being closer to the next row of sub-pixels Px, and this portion can be referred to as the second dark area Deb.

[0095] Correspondingly, the dark-area electrode portion 1111 may also include one dark-area electrode portion or two dark-area electrode portions. For example, in some specific embodiments, the dark-area electrode portion 1111 includes a first dark-area electrode portion 1111a, and the first dark-area electrode portion 1111a is located in the first dark area DEa. For another example, in some specific embodiments, the dark-area electrode portion 1111 includes a second dark-area electrode portion 1111b, and the second dark-area electrode portion 1111b is located in the second dark area DEa. For another example, in some specific embodiments, the dark-area electrode portion 1111 includes a first dark-area electrode portion 1111a and a second dark-area electrode portion 1111b, and the first dark-area electrode portion 1111a is located in the first dark area DEa, and the second dark-area electrode portion 1111b is located in the second dark area DEb. For the sake of clarity, the following description will be given by taking the dark area electrode portion 1111 including the first dark area electrode portion 1111a and the second dark area electrode portion 1111b as an example, but it should be understood that this does not exclude that in some embodiments of the present disclosure, the dark area electrode portion 1111 only includes the first dark area electrode portion 1111a or only includes the second dark area electrode portion 1111b.

[0096] 5 , the first dark area electrode portion 1111 a may specifically refer to a portion of the common electrode 111 arranged side by side with the first portion S11 of the first end portion S1 of the slit S along the first direction X. Optionally, in the second direction Y, the size of the first dark area electrode portion 1111 a may be set between 2 μm and 3 μm.

[0097] Optionally, the orthographic projection of the light-transmitting region electrode portion 1112 on the base substrate 100 is located within the range of the orthographic projection of the light-transmitting region TE on the base substrate 100 .

[0098] As shown in FIG4 , at least one sub-pixel further includes a thin-film transistor 131. Specifically, the data line DL and the sub-pixel Px are electrically connected by the thin-film transistor 131 to the pixel electrode 121 in the sub-pixel Px. Furthermore, the thin-film transistor 131 controls whether the data signal on the data line DL is transmitted to the pixel electrode 121 of the corresponding sub-pixel Px. In other words, the thin-film transistor 131 drives the sub-pixel Px to transmit light to achieve display. The thin-film transistor 131 can be either an N-type transistor or a P-type transistor, depending on actual needs and is not limited here.

[0099] In the second direction Y, the positive projection of the first dark area electrode portion 1111a on the base substrate 100 is located on a side away from the positive projection of the light-transmitting area electrode portion 1112 on the base substrate 100 and away from the positive projection of the thin film transistor 131 for driving the at least one sub-pixel Px on the base substrate 100.

[0100] For example, in combination with reference to Figures 4 and 5, taking a sub-pixel Px as an example, in the second direction Y, the first dark area electrode portion 1111a is the portion of the common electrode 111 located above the dotted line X1, the transparent area electrode portion 1112 is the portion of the common electrode 111 located between the dotted line X1 and the dotted line X2, the first dark area electrode portion 1111a is located above the transparent area electrode portion 1112, and the thin film transistor 131 that drives the sub-pixel Px is located below the transparent area electrode portion 1112.

[0101] The common electrode 111 is provided with a plurality of slits S. At least one slit S includes at least one end SD. For example, each slit S has two end SDs: a first end S1 located near the sub-pixels Px in the previous row and a second end S2 located near the sub-pixels Px in the next row. In other words, of the two end SDs of at least one slit S, the end SD located near the thin film transistor 131 is the second end S2.

[0102] The first end S1 of the slit S may specifically refer to a portion of the slit S that extends a certain length from an edge of the slit S close to the sub-pixels Px in the previous row toward the center of the slit S. The second end S2 of the slit S may specifically refer to a portion of the slit S that extends a certain length from an edge of the slit S close to the sub-pixels Px in the next row toward the center of the slit S.

[0103] It should be noted that the length of the extension can be determined according to actual needs. However, no matter how much the extension is, the defined end portion SD should be able to be divided into at least three parts along the second direction Y.

[0104] The first end portion S1 in the embodiment of the present disclosure will be described below.

[0105] The first end portion S1 includes a first portion S11, a second portion S12, and a third portion S13 arranged along the second direction Y. The second portion S12 is located between the first portion S11 and the third portion S13. The first portion S11 is arranged side by side with the adjacent first dark-sector electrode portion 1111a along the first direction X, the second portion S12 is arranged side by side with a portion of the adjacent light-transmitting-sector electrode portion 1112 along the first direction X, and the third portion S13 is arranged side by side with another portion of the adjacent light-transmitting-sector electrode portion 1112 along the first direction X.

[0106] For example, as shown in Figure 5, in the first end S1 of the slit S, the first part S11 is the part of the first end S1 located above the dotted line X1, the second part S12 is the part of the first end S1 located between the dotted line X1 and the dotted line X3, and the third part S13 is the part of the first end S1 located below the dotted line X3.

[0107] For the first end S1 of a slit S, the first dark area electrode portion 1111a is located on the left and right sides of the first portion S11; a portion of the transparent area electrode portion 1112 is located on the left and right sides of the second portion S12; and another portion of the transparent area electrode portion 1112 is located on the left and right sides of the third portion S13.

[0108] Optionally, the slit S may include a main portion S3 located between the first end portion S1 and the second end portion S2. The main portion S3 may include a first main portion S31 extending along the third direction and a second main portion S32 extending along the fourth direction. The first main portion S31 is located between the second main portion S32 and the third portion S13. The third portion S13 of the first end portion S1 may extend in the same direction as the first main portion S31. In other words, the third portion S13 of the first end portion S1 may also be considered an extension of the first main portion S31.

[0109] Optionally, the slit S may include a main portion S3 located between the first end S1 and the second end S2. The main portion S3 may extend along the third direction or along the fourth direction. The third portion S13 of the first end S1 may extend in the same direction as the first main portion S31. In other words, the third portion S13 of the first end S1 may be considered an extension of the first main portion S31. Optionally, for two adjacent sub-pixels Px along the second direction Y, the main portion S3 of one may extend along the third direction, while the main portion S3 of the other may extend along the fourth direction.

[0110] The orthographic projection of the first end S1 of at least one slit S on the base substrate 100 is tilted relative to the second direction Y, the tilt of the second portion S12 is greater than that of the third portion S13, and the tilt of the second portion S12 is less than that of the first portion S11.

[0111] FIG7 schematically illustrates the inclination angles of various portions on a first end portion in an embodiment of the present disclosure. Referring to FIG7 , in a first end portion S1 of at least one slit S, the orthographic projection of a first portion S11 on the substrate 100 is tilted at a first inclination angle θ1 relative to the second direction Y, the orthographic projection of a second portion S12 on the substrate 100 is tilted at a second inclination angle θ2 relative to the second direction Y, and the orthographic projection of a third portion S13 on the substrate 100 is tilted at a third inclination angle θ3 relative to the second direction Y. The second inclination angle θ2 is smaller than the first inclination angle θ1, and the second inclination angle θ2 is greater than the third inclination angle θ3.

[0112] In the embodiment of the present disclosure, the first portion S11 is mainly used to improve Trace Mura. The larger the size of the first portion S11 in the second direction Y, the better the improvement effect. Due to the large inclination of the first portion S11, the size of the first portion S11 in the second direction Y has an impact on the area of ​​the first dark area DEa. Specifically, the pattern of the common electrode 111 defined by the first portion S11 (including the dark area electrode portion 1111 and the edge extending along the first direction, etc.) is difficult to form a uniform electric field, and the non-uniform electric field cannot drive the liquid crystals in the liquid crystal layer 140 to be arranged in a regular pattern, thereby presenting a dark area during display. Moreover, the larger the size of the first portion S11 in the second direction Y, the larger the size of the corresponding dark area electrode portion 1111 in the second direction Y, which makes the size of the dark area in the second direction Y also larger.

[0113] Specifically, with respect to the first end S1 of the slit S, as the size of the first portion S11 in the second direction Y increases, the size of the first dark zone electrode portion 1111a in the second direction Y also increases, which in turn increases the size of the first dark zone DEa in the second direction Y. In the embodiment of the present disclosure, a second portion S12 is added between the first portion S11 and the third portion S13 of the first end S1. Because the inclination of the second portion S12 is between that of the first portion S11 and the third portion S13, the second portion S12 can improve trace mura to a certain extent. The embodiment of the present disclosure utilizes the second portion S12 and the first portion S11 to jointly improve trace mura, thereby minimizing the size of the first portion S11 in the second direction Y without exacerbating trace mura. This reduces the area of ​​the first dark zone electrode portion 1111a, and consequently, the area of ​​the first dark zone DEa, thereby increasing the area of ​​the light-transmitting region and, consequently, the transmittance of the sub-pixel Px.

[0114] For example, Figure 8 schematically shows a schematic diagram of the division of the inclination degree of the slit on the common electrode, wherein the left figure in Figure 8 schematically shows a schematic diagram of the division of the inclination degree of the slit on the common electrode in a pair of proportions, and the right figure in Figure 8 schematically shows a schematic diagram of the division of the inclination degree of the slit on the common electrode in an embodiment of the present disclosure, wherein area A is the area of ​​the third part S13 of the first end S1 on the common electrode 111, area B is the area of ​​the second part S12 of the first end S1 on the common electrode 111, and area C is the area of ​​the first part S11 of the first end S1 on the common electrode 111, that is, in the left figure of Figure 8, the second part S12 is not set on the slit S, and in the right figure of Figure 8, the second part S12 is set on the slit S. As shown in the left figure of FIG8 , to achieve a better Trace Mura improvement effect, the area where the first portion S11 of the common electrode 111 is located (i.e., area C in the left figure of FIG8 ) is approximately 4 μm to 6 μm in the second direction Y. As shown in the right figure of FIG8 , after providing the second portion S12, the area where the first portion S11 of the common electrode 111 is located (i.e., area C in the right figure of FIG8 ) can be reduced to 2.7 μm to 3.3 μm in the second direction Y. Thus, the embodiment of the present disclosure, by providing the second portion S12 as a transition structure in the first end portion S1, can reduce the size of the first portion S11 in the second direction Y while achieving a better Trace Mura improvement effect, thereby reducing the area of ​​the first dark area DEa, thereby improving the transmittance of the sub-pixel Px.

[0115] The second end portion S2 in the embodiment of the present disclosure is described below. It should be noted that, unless otherwise specified, the structures described below all belong to the same sub-pixel Px.

[0116] FIG9 shows an enlarged view of position N in FIG4 . With reference to FIG4 and FIG9 , in some specific embodiments, in at least one sub-pixel Px, the dark area electrode portion 1111 of the common electrode 111 further includes a second dark area electrode portion 1111 b .

[0117] In the embodiment of the present disclosure, the portion of the dark area DE close to the next row of sub-pixels Px is called the second dark area DEb, and the orthographic projection of the second dark area electrode portion 1111b on the base substrate 100 at least partially overlaps with the orthographic projection of the second dark area DEb on the base substrate 100.

[0118] In the second direction Y, the orthographic projection of the second dark-area electrode portion 1111b on the base substrate 100 is located on a side of the orthographic projection of the light-transmitting-area electrode portion 1112 on the base substrate 100 that is close to the orthographic projection of the thin-film transistor 131 for driving the at least one sub-pixel Px on the base substrate 100. For example, referring to FIG. 9 , taking a sub-pixel Px as an example, the second dark-area electrode portion 1111b is the portion of the common electrode 111 below the dotted line X2, and the second dark-area electrode portion 1111b is located below the light-transmitting-area electrode portion 1112.

[0119] At least one end SD of at least one slit S further includes a second end S2. As described above, the second end S2 of the slit S specifically refers to a portion of the slit S defined by extending a certain length from the edge of the slit S adjacent to the next row of sub-pixels Px toward the center of the slit S. It should be noted that the length of the extension can be determined based on actual needs; however, regardless of the extent of the extension, the defined second end S2 should be able to be divided into at least three portions along the second direction Y.

[0120] For example, the second end portion S2 includes a first portion S21, a second portion S22, and a third portion S23 arranged along the second direction Y. The third portion S23 is arranged side by side with a portion of the adjacent light-transmitting area electrode portion 1112 along the first direction X, the second portion S22 is arranged side by side with another portion of the adjacent light-transmitting area electrode portion 1112 along the first direction X, and the first portion S21 is arranged side by side with the adjacent second dark-area electrode portion 1111 b along the first direction X.

[0121] For example, as shown in Figure 9, the third portion S23 is the portion where the second end portion S2 is located above the dotted line X4, the second portion S22 is the portion where the second end portion S2 is located between the dotted line X2 and the dotted line X4, and the first portion S21 is the portion where the second end portion S2 is located below the dotted line X2.

[0122] For example, as shown in Figure 9, for the second end S2 of a slit S, the second dark area electrode portion 1111b is located on the left and right sides of the first part S21 of the second end S2; a part of the light-transmitting area electrode portion 1112 is located on the left and right sides of the second part S22 of the second end S2; and another part of the light-transmitting area electrode portion 1112 is located on the left and right sides of the third part S23 of the second end S2.

[0123] The size of the first portion S21 of the second end portion S2 in the second direction Y can be set with reference to the first end portion S1 , and thus will not be described in detail here.

[0124] The orthographic projection of the second end portion S2 of at least one slit S on the base substrate 100 is tilted relative to the second direction Y, and the tilt of the second portion S22 is greater than that of the third portion S23, and the tilt of the second portion S22 is less than that of the first portion S21.

[0125] For example, in the second end portion S2 of at least one slit S, the orthographic projection of the third portion S23 on the substrate 100 is tilted at a fourth angle relative to the second direction Y, the orthographic projection of the second portion S22 on the substrate 100 is tilted at a fifth angle relative to the second direction Y, and the orthographic projection of the first portion S21 on the substrate 100 is tilted at a sixth angle relative to the second direction Y. The fifth angle is smaller than the sixth angle, and the fifth angle is greater than the fourth angle. Alternatively, the fourth angle may be the same as the third angle, the fifth angle may be the same as the second angle, and the sixth angle may be the same as the first angle.

[0126] In some specific embodiments, the third portion S23 of the second end portion S2 and the third portion S13 of the first end portion S1 extend in directions that intersect with each other. Alternatively, the third portion S23 of the second end portion S2 can extend in the same direction as the second main portion S32 described above. In other words, the third portion S23 of the second end portion S2 can also be considered an extension of the second main portion S32.

[0127] The first portion S21 of the second end portion S2 is also primarily used to improve Trace Mura. Based on a principle similar to the provision of the second portion S12 in the first end portion S1 described above, the embodiments of the present disclosure provide a second portion S22 in the second end portion S2 having an inclination between the third portion S23 and the first portion S21. This can reduce the size of the first portion S21 of the second end portion S2 in the second direction Y without aggravating Trace Mura. This can thereby reduce the area of ​​the second dark-zone electrode portion 1111b, and thereby reduce the area of ​​the second dark zone DEb, thereby further reducing the area of ​​the dark zone DE of the dimming unit.

[0128] Therefore, in the embodiment of the present disclosure, by providing the second portion S12 in the first end portion S1 and the second portion S22 in the second end portion S2, the dark area DE can be reduced without aggravating Trace Mura, thereby improving the transmittance of the sub-pixel Px.

[0129] 4 to 9 , the multiple slits S on the common electrode 111 may have different sizes in the second direction Y. Specifically, in at least one sub-pixel Px, the multiple slits S on the common electrode 111 include a first slit SA and a second slit SB, and the size of the first slit SA in the second direction Y is greater than the size of the second slit SB in the second direction Y.

[0130] In one sub-pixel Px, the orthographic projections of the first end portions S1 of the first slit SA and the second slit SB on the base substrate 100 may be arranged side by side along the first direction X. Unlike the first end portions S1, in the second direction Y, the orthographic projection of the second end portion S2 of the first slit SA on the base substrate 100 protrudes beyond the orthographic projection of the second end portion S2 of the second slit SB on the base substrate 100.

[0131] In the embodiment of the present disclosure, the common electrode 111 is divided into a plurality of strip-shaped portions by slits S thereon. Specifically, the common electrode 111 forms an electric field for driving liquid crystal deflection through these strip-shaped portions and the pixel electrode 121. The slits S arranged in this manner can maximize the area occupied by the strip-shaped portions on the common electrode 111, thereby increasing the light-emitting area of ​​the sub-pixel Px.

[0132] Optionally, the width of the strip portion may be set to between 2 μm and 3 μm, for example, the width of the strip portion may be set to 2.24 μm. The width of the strip portion may refer to an average distance between two side edges of the strip portion arranged along the first direction X, or the width of the strip portion may refer to a distance between two side edges of the strip portion arranged along the first direction X in the first direction X.

[0133] Optionally, in a sub-pixel Px, in the first direction X, the orthographic projection of the second slit SB on the base substrate 100 is located on a side of the orthographic projection of the first slit SA on the base substrate 100 that is close to the orthographic projection of the data line DL electrically connected to the sub-pixel Px on the base substrate 100. As shown in FIG. 4 , for a sub-pixel Px, the data line DL electrically connected to the sub-pixel Px is located on the right side of the sub-pixel Px, and the second slit SB is located on the right side of the first slit SA.

[0134] In some specific embodiments, in at least one sub-pixel Px, in the second direction Y, the orthographic projection of the second portion S22 of the second end portion S2 of the first slit SA on the base substrate 100 at least partially protrudes beyond the orthographic projection of the first portion S21 of the second end portion S2 of the second slit SB on the base substrate 100, so that the first portion S21 of the second end portion S2 of the first slit SA is as close as possible to the next row of sub-pixels Px, so that the second dark area DE of the dimming part can be as close as possible to the next row of sub-pixels, thereby making the size of the transparent area TE of the dimming part in the second direction Y as long as possible.

[0135] Optionally, the first slit SA and the second slit SB have substantially the same slit width. In at least one subpixel Px, on the common electrode 111, the first end S1 of the first slit SA and the second portion S12 of the second slit SB are horizontally aligned along the first direction X. The slit width may refer to the average distance between two side edges of the slit S aligned along the first direction X.

[0136] In the embodiment of the present disclosure, the display substrate further includes a gate layer and a first conductive layer (not shown) disposed on the base substrate 100. As shown in FIG9 , the thin film transistor 131 includes a gate located in the gate layer and a first electrode 1311 and a second electrode 1312 located in the first conductive layer. The positional relationship between the gate layer and the first conductive layer in the thickness direction of the display substrate can be determined based on actual needs, and the embodiment of the present disclosure does not impose any restrictions on this. For example, when the thin film transistor 131 on the display substrate has a bottom-gate structure, the gate layer can be located between the first conductive layer and the base substrate 100.

[0137] In some specific embodiments, a plurality of gate lines GL are provided on the display substrate, and at least one gate line GL is electrically connected to at least one sub-pixel Px. Optionally, at least one gate line GL is electrically connected to at least a portion of the sub-pixels Px in a row, for example, one gate line GL is electrically connected to all the sub-pixels Px in a row of sub-pixels Px.

[0138] In the embodiment of the present disclosure, the gate line GL is electrically connected to the sub-pixel Px, specifically, the gate line GL is electrically connected to the gate of the thin film transistor 131 for driving the sub-pixel Px.

[0139] For example, the gate of thin-film transistor 131 is electrically connected to a gate line GL. The gate driver circuit can provide a scanning signal to the gate of thin-film transistor 131 via the gate line GL to control the turning on and off of thin-film transistor 131. A first electrode 1311 of thin-film transistor 131 is electrically connected to a data line DL and also to the active layer of thin-film transistor 131. A second electrode 1312 of thin-film transistor 131 is electrically connected to pixel electrode 121 in sub-pixel Px and also to the active layer of thin-film transistor 131. When an active level signal is provided on gate line GL, thin-film transistor 131 is turned on, and the first electrode 1311 and the second electrode 1312 of thin-film transistor 131 are conductively connected through the active layer. The data signal on data line DL can be transmitted to pixel electrode 121. Consequently, an electric field can be formed between pixel electrode 121 and common electrode 111 to drive the liquid crystal in dimming unit 141 to deflect.

[0140] Optionally, the orthographic projection of the first electrode 1311 of the thin film transistor 131 on the base substrate 100 is approximately U-shaped, and the opening of the U-shaped portion is disposed away from the data line DL electrically connected to the first electrode 1311. The orthographic projection of the second electrode 1312 of the thin film transistor 131 on the base substrate 100 is approximately I-shaped, and the second electrode 1312 of the thin film transistor 131 extends approximately along the first direction X.

[0141] In some specific embodiments, in at least one sub-pixel Px, the orthographic projection of the second portion S22 of the second end portion S2 of the first slit SA on the base substrate 100 at least partially overlaps with the orthographic projection of the thin film transistor 131 for driving the sub-pixel Px on the base substrate 100 in the first direction X.

[0142] For example, in at least one subpixel Px, the orthographic projection of the second portion S22 of the second end portion S2 of the first slit SA on the substrate 100 defines a first pattern, the orthographic projection of the thin film transistor 131 for driving the subpixel Px on the substrate 100 defines a second pattern, and the orthographic projection of the gate line GL electrically connected to the subpixel Px on the substrate 100 defines a third pattern. The second pattern includes a first edge and a second edge arranged opposite to each other along the second direction Y, the second edge at least partially overlapping the third pattern, and the distance between the first edge and the third pattern is greater than the distance between the first pattern and the third pattern.

[0143] In the embodiments of the present disclosure, the first pattern defined by the orthographic projection of the second portion S22 on the substrate 100 may refer to a pattern defined by the outermost edge of the orthographic projection of the second portion S22 on the substrate 100 as a boundary. The second pattern defined by the orthographic projection of the thin film transistor 131 on the substrate 100 may refer to a pattern defined by the outermost edge of the orthographic projection of the thin film transistor 131 on the substrate 100 as a boundary. The third pattern defined by the orthographic projection of the gate line GL on the substrate 100 may refer to a pattern defined by the outermost edge of the orthographic projection of the gate line GL on the substrate 100 as a boundary.

[0144] In an embodiment of the present disclosure, the distance between the first edge and the third pattern may refer to the minimum distance between the first edge and the third pattern, and the distance between the first pattern and the third pattern may refer to the minimum distance between the first edge and the third pattern.

[0145] As shown in FIG7 , in some specific embodiments, at at least one end SD (e.g., first end S1) of at least one slit S, the orthographic projection of the first portion S11 on the substrate 100 is tilted at a first tilt angle θ1 relative to the second direction Y, and the orthographic projection of the second portion S12 on the substrate 100 is tilted at a second tilt angle θ2 relative to the second direction Y. Both the first tilt angle θ1 and the second tilt angle θ2 are acute angles. The ratio of the second tilt angle θ2 to the first tilt angle θ1 is between 0.1:1 and 0.3:1. For example, the ratio of the second tilt angle θ2 to the first tilt angle θ1 is 7:40. For example, if the second tilt angle θ2 is set to 7°, then the first tilt angle θ1 is set to 40°.

[0146] In some specific embodiments, at at least one end SD (e.g., the first end S1) of at least one slit S, the orthographic projection of the third portion S13 on the substrate 100 is tilted at a third tilt angle θ3 relative to the second direction Y. The third tilt angle θ3 is an acute angle. The ratio of the third tilt angle θ3 to the second tilt angle θ2 is between 0.5:1 and 0.9:1. For example, the ratio of the third tilt angle θ3 to the second tilt angle θ2 is 5:7. For example, if the third tilt angle θ3 is set to 5°, then the second tilt angle θ2 is set to 7°.

[0147] Optionally, the second inclination angle θ2 may be set between 7° and 8°, and the third inclination angle θ3 may be set between 5° and 6°.

[0148] In some specific embodiments, at at least one end SD (e.g., the first end S1) of at least one slit S, a ratio of a dimension D2 of the second portion S12 in the second direction Y to a dimension D1 of the first portion S11 in the second direction Y is between 2.7:1 and 3.3:1. For example, the ratio of the dimension D2 of the second portion S12 in the second direction Y to the dimension D1 of the first portion S11 in the second direction Y is 3:1. For example, the dimension D2 of the second portion S12 in the second direction Y is set to 7.5 μm, and the dimension D1 of the first portion S11 in the second direction Y is set to 2.5 μm.

[0149] Optionally, a dimension D1 of the first portion S11 in the second direction Y may be set between 2 μm and 3 μm, and a dimension D1 of the second portion S12 in the second direction Y may be set between 6 μm and 8 μm.

[0150] By using the display substrate according to the embodiment of the present disclosure, the light emitting area can be increased by 1-2%, thereby increasing the light emitting efficiency by 1-2%.

[0151] In some specific embodiments, the display substrate further includes a plurality of touch lines Tx disposed on the base substrate 100 , and the plurality of touch lines Tx are arranged along the first direction X.

[0152] In the embodiment of the present disclosure, the display substrate adopts a 1P3T design, that is, three touch lines Tx are correspondingly arranged for one pixel unit. The specific arrangement can be referred to the above embodiment and will not be repeated here.

[0153] The plurality of touch lines Tx and the plurality of data lines DL are provided in the same layer and with the same material, and at least one touch line Tx is provided in parallel with the data line DL closest to it in the first direction X. For example, as shown in FIG3 , the touch line Tx is provided in parallel with the data line DL on its left side. That is, when the data line DL includes two portions extending in the third direction and the fourth direction, the touch line Tx also includes two portions, one of which extends in the third direction and the other extends in the fourth direction.

[0154] The multiple slits S on the common electrode 111 of at least one subpixel Px further include a third slit SC, the orthographic projection of the third slit SC on the base substrate 100 at least partially overlaps with the orthographic projection of at least one touch line Tx on the base substrate 100, thereby exposing at least part of the touch line Tx.

[0155] In the embodiment of the present disclosure, three touch lines Tx are provided corresponding to one pixel unit P, and one touch line Tx is provided corresponding to each sub-pixel Px in the pixel unit P. For example, as shown in FIG3 , three touch lines Tx pass through one pixel unit P, and one touch line Tx is provided on the left side of each sub-pixel Px. The touch line Tx can be exposed by the third slit SC of the sub-pixel Px on its right side.

[0156] FIG10 schematically illustrates the dimensions of various slits in an embodiment of the present disclosure. Referring to FIG4 and FIG10 , the slit width D3 of the third slit SC is optionally greater than or equal to the line width D4 of the touch line Tx. The slit width D3 of the third slit SC may refer to the average distance between two sides of the third slit SC arranged along the second direction Y. The line width D4 of the touch line Tx may refer to the average distance between two sides of the touch line Tx arranged along the second direction Y.

[0157] In some specific embodiments, in at least one sub-pixel Px, the ratio of the slit widths of the third slit SC to the first slit SA is between 2:1 and 3:1. For example, the ratio of the slit width D3 of the third slit SC to the slit width D5 of the first slit SA is 2.5:1. The slit width D5 of the first slit SA may refer to the average distance between two sides of the first slit SA arranged along the second direction Y.

[0158] Optionally, the size of the third slit SC in the first direction X may be set between 12 μm and 14 μm. The size of the third slit SC in the first direction X may specifically refer to the distance between two points horizontally arranged along the first direction X on a side of the third slit SC.

[0159] In some specific embodiments, in at least one sub-pixel Px, a ratio of a distance D6 between an edge of the third slit SC near the first slit SA (e.g., the right edge) and an edge of the touch line Tx exposed thereby near the first slit SA (e.g., the right edge) to the slit width D5 of the first slit SA is between 1:1 and 2:1. For example, a ratio of a distance D6 between an edge of the third slit SC near the first slit SA (e.g., the right edge) and an edge of the touch line Tx exposed thereby near the first slit SA (e.g., the right edge) to the slit width D5 of the first slit SA is 1.5:1.

[0160] For example, the right edge of the third slit SC and the right edge of the touch line Tx exposed thereby may have a size between 7 μm and 9 μm in the first direction X. Specifically, the size of the two in the first direction X refers to the distance between two points horizontally disposed along the first direction X.

[0161] Exemplarily, the third slit SC includes a first side and a second side arranged in sequence along the second direction Y, the touch line Tx includes a third side and a fourth side arranged in sequence along the second direction Y, the orthographic projection of the first side on the base substrate 100 is located on the side where the orthographic projection of the third side on the substrate base is away from the orthographic projection of the fourth side on the base substrate 100, and the second side is located on the side where the orthographic projection of the fourth side on the base substrate 100 is away from the orthographic projection of the third side on the base substrate 100.

[0162] For example, the left side of the third slit SC is located to the left of the left side of the touch line Tx, and the right side of the third slit SC is located to the right of the right side of the touch line Tx. In this way, the touch line Tx can be exposed to a greater extent.

[0163] In the embodiment of the present disclosure, the third slit SC not only exposes the touch line Tx, but also may expose the pixel electrode 121 closest to the touch line Tx in the first direction X.

[0164] In some specific embodiments, the display substrate further includes a pixel electrode layer 120, and the at least one sub-pixel Px further includes a pixel electrode 121 located in the pixel electrode layer 120. For the pixel electrode 121 in the at least one sub-pixel Px and the touch line Tx closest to the pixel electrode 121 in the first direction X, the orthographic projection of the pixel electrode 121 on the base substrate 100 and the orthographic projection of the touch line Tx on the base substrate 100 at least partially overlap with the orthographic projection of the third slit SC in the sub-pixel Px on the base substrate 100, and the orthographic projection of the pixel electrode 121 on the base substrate 100 and the orthographic projection of the touch line Tx on the base substrate 100 are spaced apart.

[0165] Exemplarily, for a sub-pixel Px, the pixel electrode 121 includes a fifth side and a sixth side arranged in sequence along the second direction Y, and the orthographic projection of the fifth side on the base substrate 100 is located on the side where the orthographic projection of the second side on the base substrate 100 is close to the orthographic projection of the first side on the base substrate 100.

[0166] For example, the right side of the third slit SC is located to the right of the left side of the pixel electrode 121 .

[0167] In some specific embodiments, the touch line Tx and the common electrode 111 in the common electrode layer 110 are loaded with the same electrical signal. In this way, the touch line Tx and the pixel electrode 121 exposed by the third slit SC can form an electric field at the edge of the sub-pixel Px to which the pixel electrode 121 belongs, which is used to drive liquid crystal deflection. Compared with traditional solutions, this electric field can increase the size of the light-transmitting area TE of the dimming unit in the first direction X, thereby increasing the light-emitting area of ​​the sub-pixel Px.

[0168] For example, FIG11 schematically illustrates a schematic diagram of an electric field formed to drive liquid crystal deflection in a comparative example, and FIG12 schematically illustrates a schematic diagram of an electric field formed to drive liquid crystal deflection in an embodiment of the present disclosure. FIG11 illustrates an electric field formed by the pixel electrode 112' and the common electrode 1111' in a comparative example to drive liquid crystal deflection. Because the common electrode 1111' is located between the touch line Tx' and the pixel electrode 112', no electric field is formed between the two. Referring to FIG11 and FIG12 , in the comparative example, the common electrode 111 is located between the pixel electrode 121 and the touch line Tx closest to the pixel electrode 112' in the first direction X. These three electrodes can form a third electric field at the edge of the sub-pixel Px, as shown in FIG11 . In the embodiment of the present disclosure, the common electrode 111 located between the pixel electrode 121 and the touch line Tx is removed to form a third slit SC. The left side of the pixel electrode 121 and the touch line Tx located to the left of the pixel electrode 121 are exposed through the third slit SC. Since there is no common electrode 111 between the exposed pixel electrode 121 and the touch line Tx, and the touch line Tx is loaded with the same telecommunication signal as the common electrode 111, the exposed pixel electrode 121 and the touch line Tx can form a fourth electric field as shown in Figure 12. As can be clearly seen from the figure, in the first direction X, the range of the fourth electric field is greater than the range of the third electric field. As a result, the light-transmitting area TE of the dimming unit can extend in the first direction X. Figure 13 schematically shows a comparison diagram of the luminous area of ​​the sub-pixel in a comparative example and the luminous area of ​​the sub-pixel in an embodiment of the present disclosure, wherein TEB is the luminous area of ​​the sub-pixel in the comparative example, and TEA is the luminous area of ​​the sub-pixel in the embodiment of the present disclosure that is enlarged relative to the sub-pixel in the comparative example. Referring to Figure 13, the embodiment of the present disclosure extends the light-transmitting area TE to the left, so that the size of the light-transmitting area TE in the first direction X is increased, thereby increasing the luminous area of ​​the sub-pixel Px.

[0169] In some specific embodiments, in at least one sub-pixel Px, in the first direction X, the orthographic projection of the third slit SC on the base substrate 100 is located on a side of the orthographic projection of the first slit SA on the base substrate 100 that is away from the orthographic projection of the second slit SB on the base substrate 100. For example, as shown in FIG. 4 , for a sub-pixel Px, the second slit SB is located to the right of the first slit SA, and the third slit SC is located to the left of the first slit SA.

[0170] In some specific embodiments, in at least one sub-pixel Px, in the second direction Y, the orthographic projection of the second end S2 of the third slit SC on the base substrate 100 protrudes beyond the orthographic projection of the second end S2 of the second slit SB on the base substrate 100, thereby exposing as much of the touch line Tx as possible, which is beneficial to increasing the light-emitting area of ​​the sub-pixel Px.

[0171] In an embodiment of the present disclosure, in at least one sub-pixel Px, in the second direction Y, the orthographic projection of the second portion S22 of the second end portion S2 of the third slit SC on the base substrate 100 at least partially protrudes beyond the orthographic projection of the second end portion S2 of the second slit SB on the base substrate 100, thereby making the first portion S21 of the second end portion S2 of the third slit SC as close as possible to the next row of sub-pixels Px.

[0172] As shown in Figure 4, in some specific embodiments, at least one touch line Tx includes a touch line body Tx1 and a transition portion Tx2 arranged along the second direction Y, a portion where the touch line body Tx1 and the transition portion Tx2 are connected is provided with a bending structure Tx3, and an orthographic projection of a second end portion S2 of at least one third slit SC on the base substrate 100 at least partially overlaps with an orthographic projection of the bending structure Tx3 on the base substrate 100.

[0173] In an embodiment of the present disclosure, the display substrate further includes a touch electrode layer disposed on a base substrate 100. The touch electrode layer includes a plurality of touch blocks (not shown in the figure). Touch wires Tx and data lines DL are located in a first conductive layer. The touch electrode layer may be located on a side of the first conductive layer facing away from the base substrate 100. The touch wire body Tx1 may be electrically connected to the touch blocks in the touch electrode layer via a transition portion Tx2, thereby transmitting touch signals generated by the touch blocks.

[0174] The touch cable body Tx1 may include two portions extending along the third direction and the fourth direction, and the bending structure Tx3 may be located between the portion extending along the fourth direction and the transition portion Tx2.

[0175] In some specific embodiments, in at least one sub-pixel Px, in the second direction Y, the orthographic projection of the second end S2 of the first slit SA on the base substrate 100 protrudes beyond the orthographic projection of the second end S2 of the third slit SC on the base substrate 100. In this way, the size of the third slit SC in the second direction Y can be as large as possible without affecting the setting of the transition portion Tx2.

[0176] In some specific embodiments, in at least one sub-pixel Px, the orthographic projection of the first portion S21 of the second end of the third slit SC on the base substrate 100 at least partially overlaps with the orthographic projection of the thin film transistor 131 for driving the sub-pixel Px on the base substrate 100 in the first direction X.

[0177] For example, in at least one sub-pixel Px, the orthographic projection of the first portion S21 of the second end of the third slit SC on the substrate 100 defines a fourth pattern, the orthographic projection of the thin film transistor 131 for driving the sub-pixel Px on the substrate 100 defines a second pattern, and the orthographic projection of the gate line GL electrically connected to the sub-pixel Px on the substrate 100 defines a third pattern. The second pattern includes a first edge and a second edge oppositely disposed along the second direction Y, the second edge at least partially overlapping the third pattern, and the distance between the first edge and the third pattern is greater than the distance between the fourth pattern and the third pattern.

[0178] In the embodiment of the present disclosure, the fourth pattern defined by the orthographic projection of the first portion S21 of the third slit SC on the base substrate 100 may refer to a pattern defined by the outermost edge of the orthographic projection of the second portion S22 of the third slit SC on the base substrate 100 as a boundary.

[0179] In an embodiment of the present disclosure, the distance between the first edge and the fourth pattern may refer to the minimum distance between the first edge and the fourth pattern, and the distance between the first pattern and the fourth pattern may refer to the minimum distance between the first edge and the fourth pattern.

[0180] In some specific embodiments, the display substrate further includes a plurality of shielding electrodes 112 located in the common electrode layer 110. The orthographic projection of at least one shielding electrode 112 on the base substrate 100 covers the orthographic projection of at least one data line DL on the base substrate 100. The shielding electrodes 112 can prevent interference with the electrical signals on the data lines DL.

[0181] In an embodiment of the present disclosure, in the second direction Y, the distance between the left edge of the shielding electrode 112 and the left edge of the data line DL can be set to between 2 μm and 4 μm, and the distance between the right edge of the shielding electrode 112 and the right edge of the data line DL can be set to between 2 μm and 4 μm. For example, both are 3 μm. The distance between the left edge of the shielding electrode 112 and the left edge of the data line DL can refer to the average distance between the two.

[0182] The display substrate of the embodiment of the present disclosure can increase the light emitting area, thereby improving the light emitting efficiency. Specifically, the display substrate of the embodiment of the present disclosure can increase the light emitting efficiency by at least 3-5% compared with the traditional display substrate.

[0183] In some specific embodiments, at least one subpixel Px includes a light-transmitting region and a dark region at least partially surrounding the light-transmitting region, wherein the transmittance of the dark region is lower than that of the light-transmitting region. In the at least one subpixel Px, the orthographic projection of the first dark-region electrode portion 1111a of the common electrode 111 on the base substrate 100 is within the range of the orthographic projection of the dark region on the base substrate 100, and the orthographic projection of the light-transmitting region electrode portion 1112 on the base substrate 100 is within the range of the orthographic projection of the light-transmitting region on the base substrate 100.

[0184] In some specific embodiments, the size of the dark-space electrode portion 1111 in the second direction Y is set to be between 2 μm and 3 μm. Optionally, the size of at least one of the first dark-space electrode portion 1111 a and the second dark-space electrode portion 1111 b in the second direction Y is set to be between 2 μm and 3 μm. For example, the size of the first dark-space electrode portion 1111 a in the second direction Y is set to be 2.5 μm.

[0185] In the embodiment of the present disclosure, the light-transmitting area TE, the dark area DE, the first dark area electrode portion 1111 a and the second dark area electrode portion 1111 b have been described in detail above and will not be repeated here.

[0186] At least some embodiments of the present disclosure further provide a display panel, comprising the display substrate described above, having a display area and a peripheral area and related structures therein. For example, the display panel may be a liquid crystal display panel.

[0187] It should be understood that the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate. Please refer to the above description for details, which will not be repeated here.

[0188] At least some embodiments of the present disclosure further provide a display device, which may include any device or product having a display function. For example, the display device may be a smartphone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0189] It should be understood that the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate. Please refer to the above description for details, which will not be repeated here.

[0190] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: include: substrate; A plurality of pixel units are provided on the substrate, wherein the plurality of pixel units are arranged in an array along a first direction and a second direction; A plurality of data lines are provided on the base substrate, and the plurality of data lines are arranged along the first direction; in, At least one of the pixel units includes a plurality of sub-pixels, and at least one of the sub-pixels includes a common electrode; In at least one of the sub-pixels, the common electrode includes a dark region electrode portion and a light-transmitting region electrode portion arranged along the second direction; The common electrode is provided with a plurality of slits, at least one of the slits includes at least one end portion, and the at least one end portion includes a first portion, a second portion, and a third portion arranged along a second direction, the second portion is located between the first portion and the third portion, the first portion and an adjacent dark-area electrode portion are arranged side by side along the first direction, the second portion and a portion of an adjacent light-transmitting area electrode portion are arranged side by side along the first direction, and the third portion and another portion of the adjacent light-transmitting area electrode portion are arranged side by side along the first direction; and The orthographic projection of at least one end of at least one of the slits on the base substrate is tilted relative to the second direction, and the inclination of the second part in the end is greater than the inclination of the third part, and the inclination of the second part is less than the inclination of the first part.

2. The display substrate according to claim 1, wherein At least one of the sub-pixels further comprises a thin film transistor, and in the sub-pixel, the dark-area electrode portion on the common electrode comprises a first dark-area electrode portion, and at least one end portion of at least one of the slits comprises a first end portion; The orthographic projection of the first dark-area electrode portion on the base substrate is located on a side of the orthographic projection of the light-transmitting-area electrode portion on the base substrate that is away from the orthographic projection of the thin film transistor for driving the at least one sub-pixel on the base substrate; The first end portion and the adjacent first dark-sector electrode portion are arranged side by side along a first direction.

3. The display substrate according to claim 2, wherein: In at least one of the sub-pixels, the dark-area electrode portion of the common electrode further includes a second dark-area electrode portion, and in the second direction, an orthographic projection of the second dark-area electrode portion on the base substrate is located on a side of the orthographic projection of the light-transmitting-area electrode portion on the base substrate that is close to an orthographic projection of a thin film transistor for driving the at least one sub-pixel on the base substrate; At least one end portion of at least one of the slits further includes a second end portion, and a first portion of the second end portion and an adjacent second dark-sector electrode portion are arranged side by side along the first direction.

4. The display substrate according to claim 1, wherein: At least one of the sub-pixels further comprises a thin film transistor, and in the sub-pixel, the dark-area electrode portion on the common electrode comprises a second dark-area electrode portion, and at least one end portion of at least one of the slits comprises a second end portion; The orthographic projection of the second dark-area electrode portion on the base substrate is located on a side of the orthographic projection of the light-transmitting-area electrode portion on the base substrate close to the orthographic projection of the thin film transistor for driving the at least one sub-pixel on the base substrate; The second end portion and the adjacent second dark-sector electrode portion are arranged side by side along the first direction.

5. The display substrate according to any one of claims 2 to 4, wherein: In at least one of the sub-pixels, one end of the plurality of slits on the common electrode close to the thin film transistor is a second end, and the plurality of slits include a first slit and a second slit; In the second direction, an orthographic projection of the second end portion of the first slit on the base substrate protrudes beyond an orthographic projection of the second end portion of the second slit on the base substrate. The display substrate according to claim 5 , wherein: In at least one of the sub-pixels, in the second direction, an orthographic projection of a second portion of the second end portion of the first slit on the base substrate at least partially protrudes beyond an orthographic projection of a first portion of the second end portion of the second slit on the base substrate.

7. The display substrate according to claim 5, wherein: In at least one of the sub-pixels, an orthographic projection of a second portion of the second end portion of the first slit on the base substrate at least partially overlaps with an orthographic projection of a thin film transistor for driving the sub-pixel on the base substrate in the first direction.

8. The display substrate according to any one of claims 1 to 7, wherein: At least one of the slits includes a first end and a second end, and extension directions of the third portion of the first end and the third portion of the second end intersect or are parallel to each other.

9. The display substrate according to any one of claims 1 to 8, wherein: In at least one end of at least one of the slits, the orthographic projection of the first portion on the substrate is tilted at a first tilt angle relative to the second direction, and the orthographic projection of the second portion on the substrate is tilted at a second tilt angle relative to the second direction, and both the first tilt angle and the second tilt angle are acute angles; the ratio of the second tilt angle to the first tilt angle is between 0.1:1 and 0.3:

1.

10. The display substrate according to claim 9, wherein: In at least one end of at least one of the slits, the orthographic projection of the third portion on the substrate is tilted at a third tilt angle relative to the second direction, and the third tilt angle is an acute angle; the ratio of the third tilt angle to the second tilt angle is between 0.5:1 and 0.9:

1.

11. The display substrate according to any one of claims 1 to 10, wherein: In at least one end portion of at least one of the slits, a ratio of a size of the second portion in the second direction to a size of the first portion in the second direction is between 2.7:1 and 3.3:

1.

12. The display substrate according to any one of claims 5 to 11, wherein: The display substrate further includes a plurality of touch lines disposed on the base substrate, at least one of the sub-pixels further includes a pixel electrode, and the plurality of touch lines are arranged along the first direction; The multiple slits on the common electrode of at least one of the sub-pixels also include a third slit. For the pixel electrode in at least one of the sub-pixels and the touch line closest to the pixel electrode in the first direction, the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the touch line on the base substrate at least partially overlap with the orthographic projection of the third slit in the sub-pixel on the base substrate, and the orthographic projection of the pixel electrode on the base substrate and the orthographic projection of the touch line on the base substrate are spaced apart.

13. The display substrate according to claim 12, wherein: In at least one of the sub-pixels, in the first direction, an orthographic projection of the third slit on the base substrate is located on a side of the orthographic projection of the first slit on the base substrate away from an orthographic projection of the second slit on the base substrate.

14. The display substrate according to claim 12, wherein: The display substrate further includes a plurality of shielding electrodes located in the common electrode layer, and an orthographic projection of at least one of the shielding electrodes on the base substrate covers an orthographic projection of at least one of the data lines on the base substrate.

15. The display substrate according to claim 12, wherein: The plurality of touch lines and the plurality of data lines are provided in the same layer and with the same material, and the touch lines and the common electrodes in the common electrode layer are loaded with the same electrical signal.

16. The display substrate according to claim 12, wherein: In at least one of the sub-pixels, in the second direction, an orthographic projection of the second end portion of the third slit on the base substrate protrudes beyond an orthographic projection of the second end portion of the second slit on the base substrate.

17. The display substrate according to claim 12, wherein: In at least one of the sub-pixels, in the second direction, an orthographic projection of the second end portion of the first slit on the base substrate protrudes beyond an orthographic projection of the second end portion of the third slit on the base substrate.

18. The display substrate according to claim 12, wherein: In at least one of the sub-pixels, a ratio of the slit widths of the third slit to the first slit is between 2:1 and 3:

1.

19. The display substrate according to claim 12, wherein: In at least one of the sub-pixels, an orthographic projection of a first portion of the second end portion of the third slit on the base substrate at least partially overlaps with an orthographic projection of a thin film transistor for driving the sub-pixel on the base substrate in the first direction.

20. The display substrate according to claim 12, wherein At least one of the touch lines includes a touch line body and a transition portion arranged along the second direction, a portion where the touch line body is connected to the transition portion is provided with a bending structure, and an orthographic projection of a second end portion of the third slit in at least one of the sub-pixels on the base substrate at least partially overlaps with an orthographic projection of the bending structure on the base substrate.

21. The display substrate according to any one of claims 1 to 20, wherein: At least one of the sub-pixels includes a light-transmitting area and a dark area at least partially surrounding the light-transmitting area, wherein the transmittance of the dark area is lower than the transmittance of the light-transmitting area; In at least one of the sub-pixels, the orthographic projection of the dark area electrode portion on the common electrode on the base substrate is located within the range of the orthographic projection of the dark area on the base substrate, and the orthographic projection of the light-transmitting area electrode portion on the base substrate is located within the range of the orthographic projection of the light-transmitting area on the base substrate.

22. The display substrate according to claim 1, wherein The size of the dark space electrode portion in the second direction is set to be between 2 μm and 3 μm.

23. A display device, wherein: The display substrate comprises the display substrate according to any one of claims 1 to 22.

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