Host rate adjustment using free space values

Abstract

Methods, systems, and apparatus include receiving a current free-space value and a historical delta value. And calculating an increment value by using the current free space value, the target free space value and the historical increment value. A delta region is determined using the delta value. A new host rate is calculated using the determined delta region, the calculated delta value, and the historical delta value. The new host rate is sent to a host device, causing the host device to change a current host rate to the new host rate.

Description

Technical Field

[0001] The present disclosure relates generally to host rate adjustment, and more particularly, to host rate adjustment using free space values. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0004] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0005] Figure 2 An example graph illustrating host rates and delta zones according to some embodiments of the present disclosure.

[0006] Figure 3A , 3B and 3C are flowcharts illustrating an example method for adjusting a host rate using a free space value according to some embodiments of the present disclosure.

[0007] Figure 4 is a flow chart of an example method for adjusting a host rate using a free space value according to some embodiments of the present disclosure.

[0008] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0009] Aspects of the present disclosure relate to adjusting the host rate using the free space value in the memory subsystem. The memory subsystem can be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0010] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. A die in a package may be assigned to one or more channels for communicating with a memory subsystem controller. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane is composed of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0011] Depending on the cell type, a cell can store one or more binary bits of information and have various logic states related to the number of bits stored. The logic state can be represented by a binary value such as "0" and "1" or a combination of such values. There are various types of cells such as single-level cells (SLCs), multi-level cells (MLCs), three-level cells (TLCs), and four-level cells (QLCs). For example, an SLC can store one bit of information and have two logic states.

[0012] Conventional memory systems receive data from a host system to write to memory, including non-volatile memory (e.g., NAND memory devices). NAND memory devices are subdivided into blocks consisting of writable units (e.g., pages). Pages cannot usually be overwritten. Therefore, there must be free space to write to the NAND memory device. In order to create free space, the memory subsystem performs a discarded item collection process, which includes erasing all data in a block or a portion of a block, while writing valid data to a new block. When the memory subsystem enters a steady state, the amount of free space available is determined by the discarded item collection rate (the rate at which space is released) and the host rate (the rate at which space is consumed). When the discarded item collection rate is higher than the host rate, there is a lot of free space, but the files may be more scattered, resulting in a higher number of random write input / output operations per second (IOPS). On the contrary, when the host rate is higher than the discarded item collection rate, there may not be enough free space and the host may have to wait for the discarded item collection to write, thereby degrading performance.

[0013] Aspects of the present disclosure address the above and other deficiencies by adjusting the host rate based on current free space and target free space. The amount of free space can be adjusted by changing the host rate. For example, increasing the host rate will reduce the amount of free space, and vice versa. By adjusting the host rate to achieve the ideal amount of free space, the memory subsystem can obtain optimal random write IOPS while reducing the likelihood that the host will wait for discarded items to be collected and written.

[0014] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0015] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0016] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0017] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0018] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0019] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0020] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0021] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0022] Although nonvolatile memory devices such as NAND-type memory (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of nonvolatile memory cells are described, the memory device 130 may be based on any other type of nonvolatile memory such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0023] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130 and other such operations (e.g., in response to commands dispatched by the controller 115 on a command bus). The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0024] The memory subsystem controller 115 may include a processing device 117 (e.g., a processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0025] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem 110).

[0026] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses). The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0027] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0028] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] The memory subsystem 110 includes a host rate adjuster 113 that can change the host rate based on the amount of free space. In some embodiments, the controller 115 includes at least a portion of the host rate adjuster 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the host rate adjuster 113 is part of the host system 120, an application, or an operating system.

[0030] The host rate adjuster component 113 can adjust the host rate based on the difference between the current free space and the target free space and the difference between the previous free space and the target free space. Further details regarding the operation of the host rate adjuster 113 are described below.

[0031] Figure 2 An example host rate and free space graph 200 is illustrated according to some embodiments of the present disclosure. Host rate graph 200 includes a target free space line 205, a positive ideal free space line 210, a negative ideal free space line 215, a positive fine free space line 220, a negative fine free space line 225, a positive coarse free space line 230, a negative coarse free space line 235, a positive steady state free space line 240, and a negative steady state free space line 245.

[0032] The vertical axis of the host rate and free space graph 200 represents the incremental free space value (ie, incremental value). Figure 1 The host rate adjuster 113 of the present invention determines the increment value using the current free space value, the target free space value and the historical increment value. The current free space value is a value indicating that the memory device (e.g. Figure 1 The host rate adjuster 113 determines the delta value at a given time t by the following equation: DeltaValue(t)=FreeSpace(t)-TargetFreeSpace+HistoricDeltaValue(t), where (t) represents the time of the current host rate adjustment. The historical delta value is a value representing one or more previous delta values ​​from one or more host adjustment iterations performed by the host rate adjuster 113. For example, the historical delta value is the delta value for the previous host rate adjustment and is determined by the following equation: HistoricDeltaValue(t)=FreeSpace(t-1)-TargetFreeSpace+HistoricDeltaValue(t-1), where (t-1) represents the time of the previous host rate adjustment. In some embodiments, the host rate adjuster 113 also tracks the number of stored samples and clears the HistoricDeltaValue when the stored samples reach a sample threshold. The sampling threshold may be predetermined or may be determined based on characteristics of the system (eg, the desired frequency of host rate adjustments).

[0033] Target free space line 205 indicates the memory subsystem (eg Figure 1The target free space line 205 (i.e., the target free space value) is a free space value that indicates a balance between the generation of free space (e.g., as a result of garbage collection) and the consumption of free space (e.g., due to host writes). Each of the positive free space lines 210, 220, 230, and 240 indicates a positive difference (i.e., an increment) between the free space value and the target free space line 205. In other words, the positive free space lines 210, 220, 230, and 240 represent free space values ​​that are greater than the target free space line 205. Conversely, each of the negative free space lines 215, 225, 235, and 245 indicates a negative difference (i.e., an increment) between the free space value and the target free space line 205, which means that the free space value is less than the target free space line 205.

[0034] The actual incremental free space values ​​of the free space lines 210, 215, 220, 225, 230, 235, 240 and 245 are calculated using the relationship to the value of the target free space line 205. Each of the free space line pairs: positive and negative ideal free space lines 210 and 215, positive and negative fine free space lines 220 and 225, positive and negative coarse free space lines 230 and 235, and positive and negative steady state free space lines 240 and 245 have an absolute value equal to the corresponding paired line. The value of the target free space line 205 is denoted by TargetFreeSpace. The remaining free space lines are calculated according to FS target The calculation is as follows: The values ​​of the ideal free space lines 210 and 215 are given by The values ​​of the free space lines 220 and 225 are fine-tuned by The values ​​of the coarse adjustment free space lines 230 and 235 are represented by and the values ​​of the steady-state free-space lines 240 and 245 are given by express.

[0035] Each of the values ​​a, b, c, and d depends on the host system and the memory subsystem (e.g. Figure 1The performance consistency target is measured using the slowest IOPS at a given percentile divided by the average IOPS. For example, performance consistency may be measured using the 99.9th percentile slowest IOPS divided by the average IOPS, resulting in a performance consistency target of 0.1%. However, the corresponding hierarchy of values ​​​​a, b, c, and d remains constant. The maximum value is a, then b, then c, and the minimum value is d. In some embodiments, the difference between the values ​​​​is also kept constant. For example, the maximum difference between consecutive values ​​​​is between a and b, then between b and c, and the minimum difference between consecutive values ​​​​is between c and d. In one such embodiment, a=64, b=16, c=4, and d=2. In this embodiment, the ideal free space lines 210 and 215 are represented by Indicates that the free space lines 220 and 225 are fine-tuned by The coarse adjustment of free space lines 230 and 235 is represented by and the steady-state free-space lines 240 and 245 are represented by express.

[0036] The host rate chart 200 also includes regions between the free space lines, including an ideal region 255, a positive fine region 260, a negative fine region 265, a positive buffer region 270, a negative buffer region 275, a positive coarse region 280, and a negative coarse region 285. Each of the regions indicates a continuous range of incremental free space values ​​between a pair of corresponding free space lines. For example, the ideal region 255 is a range of values ​​between the positive ideal free space line 210 and the negative ideal free space line 215. The positive fine region 260 is a range of values ​​between the positive fine free space line 220 and the positive ideal free space line 210. The positive buffer region 270 is a range of values ​​between the positive coarse free space line 230 and the positive fine free space line 220. The positive coarse region 280 is a range of values ​​between the positive steady-state free space line 240 and the positive coarse free space line 230. The negative fine region 265 is a range of values ​​between the negative fine free space line 225 and the negative ideal free space line 215. Negative buffer zone 275 is the range of values ​​between negative coarse free space line 235 and negative fine free space line 225. Negative coarse zone 285 is the range of values ​​between negative steady state free space line 245 and negative coarse free space line 235.

[0037] As explained above, the maximum value is a, then b, then c, and the minimum value is d. Similarly, in some embodiments, the maximum difference between consecutive values ​​is between a and b, then between b and c, and the minimum difference between consecutive values ​​is between c and d. In such embodiments, ideal region 255 is the minimum region, followed by fine adjustment regions 260 and 265, then buffer regions 270 and 275, and coarse adjustment regions 280 and 285 are the maximum regions.

[0038] Host rate regulator (eg Figure 1The host rate adjuster 113 of the host controller 110 updates the host rate according to the host rate chart 200. In some embodiments, the host rate adjuster 113 updates the discarded item collection rate instead. Because the discarded item collection rate is the inverse of the host rate (i.e., host rate + discarded item collection rate = constant), embodiments using the discarded item collection rate will have a reverse operation (e.g., increasing the discarded item collection rate instead of decreasing the host rate). For the fine adjustment areas 260 and 265, the host rate adjuster 113 increases or decreases the host rate by the fine adjustment value β. The host rate adjuster 113 determines whether to increase or decrease the host rate (i.e., determines the adjustment polarity) based on the incremental value and the historical incremental value. The host rate adjuster 113 compares the polarity of the historical incremental value with the incremental value. When the polarity of the historical incremental value is opposite to that of the incremental value, the incremental free space has moved from one side of the ideal free space line 210 to the fine adjustment area 260 or 265 on the other side. For example, when the historical delta value is negative and the delta value is positive, the incremental free space has moved from below the target free space line 205 to the positive fine adjustment zone 260 above the target free space line 205. Therefore, the host rate adjuster 113 increases the host rate by the fine adjustment value β to allow the host to consume free space at a rate that outperforms the free space released by the waste collection, thereby ultimately causing the incremental free space value to decrease closer to the ideal zone 255 and the target free space line 205. When the polarity of the historical delta value and the delta value are the same, the incremental free space has remained on the same side of the ideal free space line 210. The previous delta value may have been in the coarse adjustment zone 280 and 285, the buffer zone 270 and 275, the fine adjustment zone 260 and 265, or the ideal zone 255. Therefore, the host rate adjuster 113 adjusts the host rate based on the difference between the delta value and the historical delta value. For example, when both the historical delta value and the delta value are positive and the delta value is greater than the historical delta value, the incremental free space has moved away from the target free space line 205. Therefore, the host rate adjuster 113 increases the host rate by the fine tuning value β to consume more free space, which eventually causes the incremental free space value to decrease closer to the ideal zone 255 and the target free space line 205. When both the historical incremental value and the incremental value are positive but the incremental value is less than the historical incremental value, the incremental free space value has moved toward the target free space line 205. To prevent overcorrection, the host rate adjuster 113 decreases the host rate by the fine tuning value β to create more free space.

[0039] The value of the fine-tuning value β is determined based on the performance consistency target. For example, for performance consistency measured by the 99.9th percentile slowest IOPS divided by the average IOPS, the performance consistency target is 0.1%. Therefore, in order to achieve the performance consistency target, any adjustment to the host rate should be less than 0.1%. Therefore, the fine-tuning value β needs to be at least less than the performance consistency target.

[0040] In some embodiments, the host rate adjuster 113 uses hysteresis to prevent rapid host rate switching when the system does not have time to properly calibrate. For example, instead of comparing the incremental value to a historical incremental value, the host rate adjuster 113 compares the incremental value to a historical incremental value. When the increment value is outside this hysteresis buffer area, the host rate adjuster 113 changes the host rate to allow the system time to stabilize. The host rate adjuster 113 may use the following equation and to determine whether to adjust the host rate. The value of e can be preset or determined by several factors, including the natural lag of the system. For example, e depends on the time it takes for the free space to change in response to a change in the host rate or on the time period between changes in the host rate. Therefore, the longer the time it takes for the free space to change in response to a changed host rate, the higher the value of e. In addition, in embodiments with such lag effects, the host rate adjuster 113 does not always update the host rate when it is in the fine adjustment areas 260 and 265. In some embodiments, when the host rate adjuster 113 does not update the host rate, these attempts are tracked and can be represented by NumAttempts. In such embodiments, the host rate adjuster 113 compares the incremental value divided by the number of attempts to the lag buffer. The host rate adjuster 113 can use the following equation and To determine whether to adjust the host rate, NumAttempts=1 for the first attempt and increments by 1 each time. In some embodiments, when the stored samples reach the sample threshold, NumAttempts is set to 0 to prevent the system from being stuck in the fine tuning regions 260 and 265 .

[0041] For ideal zone 255 and buffer zones 270 and 275, host rate adjuster 113 maintains current host rate. For example, host rate adjuster 113 sets host rate to be equal to previous host rate or does not change host rate otherwise. When in ideal zone 255, host rate is already ideal and does not need to change. When in buffer zones 270 and 275, maintain host rate to avoid host rate overcorrection. Therefore, buffer zones 270 and 275 provide free space range where host rate is constant, thereby allowing to see the influence of previous host rate change in available free space. Buffer zones 270 and 275 allow host rate adjuster 113 to slowly adjust host rate to ideal zone 255, thereby avoiding significant overcorrection.

[0042] For coarse adjustment regions 280 and 285, host rate adjuster 113 increases or decreases the host rate by one of the coarse adjustment values ​​α1 or α2. Host rate adjuster 113 determines whether to increase or decrease the host rate (i.e., determines the adjustment polarity) based on the delta value, the current free space value, the historical delta value, and the target free space value. Host rate adjuster 113 determines whether to use the coarse adjustment value α1 or α2 based on a comparison of the historical delta value and the polarity of the delta value.

[0043] When the polarity of the historical incremental value is opposite to that of the incremental value, the incremental free space has moved from one side of the target free space line 205 to the coarse adjustment zone 280 or 285 on the other side. For example, when the historical incremental value is negative and the incremental value is positive, the incremental free space has moved from below the target free space line 205 to the positive coarse adjustment zone 280 above the target free space line 205. The opposite polarity may indicate an inappropriate zone configuration, such as the values ​​of the free space lines 210, 215, 220, 225, 230, 235, 240, and 245 are not suitable for the current application. For example, an inappropriate zone configuration includes a situation where the values ​​of the free space lines cause the size of the zone to be too large or too small. The opposite polarity may also indicate an inappropriate host rate that is too large or too small caused by the host rate adjustment. Therefore, the host rate adjuster 113 adjusts the host rate to a smaller coarse adjustment value α2. The host rate adjuster 113 compares the current free space value with the target free space value to determine whether to increase or decrease the host rate to a smaller coarse adjustment value α2. For example, if the current free space value is greater than the target free space value, then the delta value for the current sample (excluding the previous delta value) is positive, indicating that the free space has increased since the last adjustment. Therefore, the host rate adjuster 113 increases the host rate by a smaller coarse adjustment value α2 to slow down the host rate adjustment and minimize overcorrection.

[0044] When the polarity of the historical incremental value is the same as the incremental value, the incremental free space remains on the same side of the target free space line 205 and the free space is still in the zone farthest from the ideal zone 255. The host rate adjuster 113 determines whether to adjust the host rate to a larger coarse adjustment value α1 or whether to maintain the current host rate. For example, the host rate adjuster 113 compares the magnitude (i.e., absolute value) of the incremental value with the historical incremental value. When the magnitude of the historical incremental value is greater than the magnitude of the incremental value, the incremental free space has moved closer to the target free space line 205. Therefore, the host rate adjuster 113 maintains the current host rate to prevent overcorrection. When the magnitude of the incremental value is greater than the magnitude of the historical incremental value, the incremental free space has moved further away from the ideal free space line 210. Therefore, the host rate adjuster 113 adjusts the host rate to a larger coarse adjustment value α1, thereby ultimately causing the incremental free space value to decrease closer to the ideal zone 255 and the target free space line 205. The host rate adjuster 113 determines whether to increase or decrease the host rate to a larger coarse adjustment value α1 based on the polarity of the incremental value. For example, when the delta value is positive, the delta free space is in the positive coarse adjustment region 280 and the historical delta value is above the target free space line 205. Therefore, the host rate adjuster 113 increases the host rate to a larger coarse adjustment value α1 to occupy more free space, which ultimately causes the delta free space value to decrease closer to the ideal region 255 and the target free space line 205. In some embodiments, since the delta value and the historical delta value have the same polarity, the rate adjuster 113 determines whether to increase or decrease the host rate to a larger coarse adjustment value α1 based on the polarity of the historical delta value.

[0045] Just like the value of the fine-tuning value β, the values ​​of the coarse-tuning values ​​α1 and α2 are determined based on the performance consistency target. For example, for performance consistency measured using the 99.9th percentile slowest IOPS divided by the average IOPS, the performance consistency target is 0.1%. Therefore, in order to achieve the performance consistency target, any adjustment to the host rate should be less than 0.1%. Therefore, the coarse-tuning values ​​α1 and α2 need to be at least less than the performance consistency target. In addition, the coarse-tuning value α1 is greater than the coarse-tuning value α2, which in turn is greater than the fine-tuning value β. Therefore, the following relationship applies to the performance consistency target and adjustment values: PerformanceConsistencyTarget>a1>a2>β. In one embodiment, when the performance consistency target is 0.1%, a1=0.0977%, a2=0.0488% and β=0.0244%.

[0046] Figure 3A , 3B3C illustrate a flow chart of an example method 300 for adjusting a host rate using a free space value according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The host rate adjuster 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0047] At operation 302, the processing device determines whether the device is in a steady state. For example, the host rate adjuster 113 determines whether the memory device or a portion thereof (e.g. Figure 1 In some embodiments, the processing device determines whether the memory device is in a steady state by monitoring performance consistency. For example, the host rate adjuster 113 monitors IOPS and determines performance consistency using the slowest IOPS of a given percentile divided by the average IOPS. When the performance consistency remains within a predetermined threshold for a given time period, the processing device determines that the memory device is in a steady state. In other embodiments, the processing device determines that the memory device is in a steady state after a predetermined time period during which the memory device operates. In yet other embodiments, the processing device uses other metrics to determine whether the memory device is in a steady state, such as monitoring transient behavior of the memory device. When the memory device is in a steady state, the method 300 proceeds to operation 304. When the memory device is not in a steady state, the method 300 returns to operation 302. If the memory device is not in a steady state, there may still be temporary behavior that may cause unforeseen or unexpected changes in free space. Therefore, the method 300 does not continue until the possibility of temporary behavior has been reduced (e.g., the memory device is in a steady state).

[0048] At operation 304, the processing device receives a current free space value and a historical increment value. For example, the host rate adjuster 113 receives the current free space value and the historical increment value based on the free space of the memory device. The current free space value is a value representing the amount of space in the memory device that has no data or no valid data. In some embodiments, the processing device receives the current free space value and the historical increment value from the local memory (e.g., Figure 1The local memory 119 of the memory device receives the current free space value and the historical increment value. In other embodiments, the processing device receives the current free space value as a result of scanning the free space of the memory device.

[0049] At operation 306, the processing device calculates the delta value. For example, the host rate adjuster 113 calculates the delta value using the current free space, the target free space value, and the historical delta value, as described above. The historical delta value may store information from a plurality of previous delta values ​​(e.g., an average, median, mean, sum, or other value determined from a plurality of previous delta values). In other embodiments, the host rate adjuster 113 calculates the delta value using the current free space, the target free space value, and a plurality of historical delta values.

[0050] At operation 308, the processing device determines the region in which the delta value falls. For example, the host rate adjuster 113 determines a delta value range that includes the calculated delta value. The delta value range is predetermined based on the memory device, performance consistency goals, and other metrics, as described above. When the processing device determines that the delta region is an ideal region (e.g., Figure 2 255) or any of the buffers (e.g., Figure 2 270 and 275), the method 300 proceeds to operation 310. When the processing device determines that the incremental area is any of the coarse adjustment areas (e.g., Figure 2 When the processing device determines that the incremental region is any of the fine adjustment regions (e.g., Figure 2 When the fine adjustment area 260 and 265 is selected, the method 300 proceeds to operation 332 through the off-page connector B.

[0051] At operation 310, the processing device sets the host rate to the previous host rate. For example, the host rate adjuster 113 sends the host rate to the host device (e.g. Figure 1 In some embodiments, the processing device may send a new host rate to maintain the host rate at the previous host rate because the updated host rate is the same as the previous host rate.

[0052] At operation 312, the processing device updates the historical increment value. For example, the host rate adjuster 113 updates the historical increment value by adding the increment value to the historical increment value. In some embodiments, the host rate adjuster 113 averages the increment value with the historical increment value. In some embodiments, the processing device also increments the number of historical samples.

[0053] At operation 314, the processing device determines whether the number of historical samples meets a threshold. For example, the host rate adjuster 113 determines whether the number of delta values ​​represented by the historical delta values ​​is greater than a threshold. In some embodiments, the threshold is predetermined based on the speed at which the host rate changes, the speed at which the free space is updated in response to the host rate change, and other variables. When the processing device determines that the number of historical samples is greater than the threshold, the method 300 proceeds to operation 316. When the processing device determines that the number of historical samples is not greater than the threshold, the method 300 returns to operation 304.

[0054] At operation 316, the processing device resets the historical increment value. For example, the host rate adjuster 113 sets the historical increment value to 0 or another number indicating that there are no stored historical increment values. In embodiments using multiple historical increment values, the host rate adjuster 113 removes the oldest historical increment value to make room for the new increment value.

[0055] At operation 318, the processing device determines whether the historical delta value and the delta value have the same polarity. For example, the host rate adjuster 113 determines whether the historical delta value and the calculated delta value have the same polarity. When the processing device determines that the calculated delta value and the historical delta value have the same polarity, the method 300 proceeds to operation 319. When the processing device determines that the calculated delta value and the historical delta value have opposite polarities, the method 300 proceeds to operation 322.

[0056] At operation 319, the processing device determines whether the magnitude of the increment value is greater than the magnitude of the historical increment value. For example, the host rate adjuster 113 determines whether the magnitude (i.e., absolute value) of the calculated increment value is greater than the magnitude (i.e., absolute value) of the historical increment value. When the processing device determines that the magnitude of the increment value is greater than the magnitude of the historical increment value, the method 300 proceeds to the off-page connector D. Figure 3A When the processing device determines that the magnitude of the incremental value is not greater than the magnitude of the historical incremental value, the method 300 proceeds to operation 320.

[0057] At operation 320, the processing device determines whether the polarity of the calculated delta value is positive. For example, the host rate adjuster 113 determines whether the delta value is greater than 0. When the processing device determines that the delta value is positive, the method 300 proceeds to operation 324. When the processing device determines that the delta value is not positive, the method 300 proceeds to operation 326.

[0058] At operation 322, the processing device determines whether the current free space value is greater than the target free space value. For example, the host rate adjuster 113 determines that the free space value of the current sample is greater than the target free space value (i.e., whether only the delta value of the current sample is greater than 0). When the processing device determines that the current free space value is greater than the target free space value, the method 300 proceeds to operation 328. When the processing device determines that the delta value is not positive, the method 300 proceeds to operation 330.

[0059] At operation 324, the processing device increases the host rate by the large coarse adjustment value α1. For example, the host rate adjuster 113 sends the new host rate (i.e., the previous host rate increased by the large coarse adjustment value α1) to the host device, such as Figure 1 of the host system 120. This causes the host device to update its host rate to the new host rate.

[0060] At operation 326, the processing device reduces the host rate by the large coarse adjustment value α1. For example, the host rate adjuster 113 sends the new host rate (i.e., the previous host rate reduced by the large coarse adjustment value α1) to the host device. This causes the host device to update its host rate to the new host rate.

[0061] At operation 328, the processing device increases the host rate by the small coarse adjustment value α2. For example, the host rate adjuster 113 sends the new host rate (i.e., the previous host rate increased by the small coarse adjustment value α2) to the host device. This causes the host device to update its host rate to the new host rate.

[0062] At operation 330, the processing device reduces the host rate by a small coarse adjustment value α2. For example, the host rate adjuster 113 sends a new host rate (i.e., the previous host rate reduced by a small coarse adjustment value α2) to the host device. This causes the host device to update its host rate to the new host rate.

[0063] At operation 332, the processing device determines whether the polarity of the historical delta value is positive. When the processing device determines that the historical delta value is positive, the method 300 proceeds to operation 334. When the processing device determines that the delta value is not positive, the method 300 proceeds to operation 336.

[0064] At operation 334, the processing device determines whether the polarity of the delta value is positive. When the processing device determines that the delta value is positive, the method 300 proceeds to operation 338. When the processing device determines that the delta value is not positive, the method 300 proceeds to operation 342.

[0065] At operation 336, the processing device determines whether the polarity of the delta value is positive. When the processing device determines that the delta value is positive, the method 300 proceeds to operation 344. When the processing device determines that the delta value is not positive, the method 300 proceeds to operation 340.

[0066] At operation 338, the processing device determines whether the delta value is greater than the historical delta value. When the processing device determines that the delta value is greater than the historical delta value, the method 300 proceeds to operation 344. When the processing device determines that the delta value is not greater than the historical delta value, the method 300 proceeds to operation 342.

[0067] In some embodiments, the processing device compares the delta value to a historical delta value, with positive and negative thresholds on either side of the historical delta value. For example, the threshold may be a fraction of the historical delta value (e.g., 1 / e times the historical delta value). In an exemplary embodiment, the value of e is 5 and thus the threshold is 1 / 5 of the historical delta value. In this embodiment, the processing device therefore determines that the delta value is greater than 6 / 5 times the historical delta value (i.e., ) or less than 4 / 5 times the historical increment value (i.e., ). When the processing device determines that the incremental value is greater than 6 / 5 times the historical incremental value, the method 300 proceeds to operation 344. When the processing device determines that the incremental value is less than 4 / 5 times the historical incremental value, the method 300 proceeds to operation 342. When both conditions are not met (i.e., the incremental value is between 4 / 5 times the historical incremental value and 6 / 5 times the historical incremental value), the method 300 returns to the page. Figure 3A Operation 310 (connection not shown). The fraction 1 / e multiplied by the historical increment value may be different. For example, e may depend on the time it takes for the free space to change in response to the host rate change. Therefore, the longer it takes for the free space to change in response to the changed host rate, the higher the value of e.

[0068] In some embodiments, the processing device counts the number of attempts to adjust the host rate (i.e., the number of times the delta value is between 4 / 5 times the historical delta value and 6 / 5 times the historical delta value). In such embodiments, the processing device divides the delta value by the number of attempts when comparing to the historical delta value with positive and negative thresholds as described above.

[0069] At operation 340, the processing device determines whether the delta value is greater than the historical delta value. When the processing device determines that the delta value is greater than the historical delta value, the method 300 proceeds to operation 342. When the processing device determines that the delta value is not greater than the historical delta value, the method 300 proceeds to operation 344.

[0070] At operation 342, the processing device increases the host rate by the fine adjustment value β. For example, the host rate adjuster 113 sends the new host rate (i.e., the previous host rate increased by the fine adjustment value β) to the host device. This causes the host device to update its host rate to the new host rate.

[0071] In some embodiments, the processing device compares the delta value to a historical delta value, with positive and negative thresholds on either side of the historical delta value. For example, the threshold may be a fraction of the historical delta value (e.g., 1 / e times the historical delta value). In an exemplary embodiment, the value of e is 5 and thus the threshold is 1 / 5 of the historical delta value. In this embodiment, the processing device therefore determines that the delta value is greater than 6 / 5 of the historical delta value (i.e., ) times, or less than 4 / 5 of the historical increment value (i.e., ) times. When the processing device determines that the incremental value is greater than 6 / 5 times the historical incremental value, the method 300 proceeds to operation 342. When the processing device determines that the incremental value is less than 4 / 5 times the historical incremental value, the method 300 proceeds to operation 344. When both conditions are not met (i.e., the incremental value is between 4 / 5 times the historical incremental value and 6 / 5 times the historical incremental value), the method 300 returns to the page. Figure 3A Operation 310 (connection not shown). The fraction 1 / e multiplied by the historical increment value may be different. For example, e may depend on the time it takes for the free space to change in response to the host rate change. Therefore, the longer it takes for the free space to change in response to the changed host rate, the higher the value of e.

[0072] In some embodiments, the processing device counts the number of attempts to adjust the host rate (i.e., the number of times the delta value is between 4 / 5 times the historical delta value and 6 / 5 times the historical delta value). In such embodiments, the processing device divides the delta value by the number of attempts when comparing to the historical delta value with positive and negative thresholds.

[0073] At operation 344, the processing device reduces the host rate by the fine-tuning value β. For example, the host rate adjuster 113 sends the new host rate (i.e., the previous host rate reduced by the fine-tuning value β) to the host device. This causes the host device to update its host rate to the new host rate.

[0074] Figure 4 is a flow chart of an example method 400 for adjusting a host rate using a free space value according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1The host rate adjuster 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0075] At operation 405, the processing device receives a current free space value and a historical delta value. For example, the host rate adjuster 113 receives the current free space value and the historical delta value based on the free space of the memory device. The current free space value is a value representing the amount of space in the memory device that has no data or no valid data. In some embodiments, the free space includes obsolete blocks that have no valuable data (e.g., blocks that have failed due to obsolete collection). In other embodiments, the free space includes scanned space for victim blocks (e.g., source blocks to be deleted during obsolete collection). In some embodiments, the processing device scans from local memory (e.g., Figure 1 The local memory 119 of the memory device receives the current free space value and the historical increment value. In other embodiments, the processing device receives the current free space value as a result of scanning the free space of the memory device.

[0076] At operation 410, the processing device calculates the delta value. For example, the host rate adjuster 113 calculates the delta value using the current free space, the target free space value, and the historical delta value. The target free space value is the memory subsystem (e.g. Figure 1 The target free space value is a free space value that indicates a good balance between the generation of free space (e.g., as a result of discarded items collection) and the consumption of free space (e.g., due to host writes). The historical delta value may store information from multiple previous delta values. In other embodiments, the host rate adjuster 113 calculates the delta value using the current free space, the target free space value, and multiple historical delta values.

[0077] At operation 415, the processing device determines a delta region. For example, the host rate adjuster 113 determines a delta value range that includes the calculated delta value. The delta value range is predetermined based on the memory device, performance consistency target, and other metrics.

[0078] At operation 420, the processing device calculates a new host rate. For example, the host rate adjuster 113 calculates the host rate using the calculated increment value, the historical increment value, and the determined increment area. The processing device calculates the host rate according to the operation explained in detail above. For example, when the determined increment area is an ideal area or a buffer area, the processing device may calculate the new host rate as the current host rate, as shown in FIG. Figure 3A When it is determined that the incremental region is a coarse adjustment region, the processing device may calculate a new host rate because the current host rate is increased or decreased by α1 or α2 or is the same as the current host rate, as shown in FIG. Figure 3B When it is determined that the incremental region is a fine adjustment region, the processing device may calculate a new host rate because the current host rate is increased or decreased by β, as described in reference to operations 318, 319, 310, 320 and 322. Figure 3C The process is described as operations 332, 334, 336, 338, and 340.

[0079] At operation 425, the processing device sends the host rate to the host device. For example, the host rate adjuster 113 sends the new host rate to the host device. This causes the host device to update its host rate to the new host rate. In some embodiments, when the updated host rate is the same as the previous host rate, the processing device does not send the new host rate to the host device, causing the host device to keep the host rate the same.

[0080] Figure 5 An example machine illustrating a computer system 500 in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110) or can be used to perform operations of the controller (e.g., execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0081] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0082] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.)), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 518, which communicate with each other via a bus 530.

[0083] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 for communicating over a network 520.

[0084] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 526 or software embodying any one or more of the methodologies or functionality described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or the processing device 502 during execution by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0085] In one embodiment, instructions 526 include instructions for implementing instructions corresponding to a host rate adjuster component (e.g., Figure 1 The machine-readable storage medium 524 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0086] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0087] It should be borne in mind, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0088] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system (e.g., controller 115) may perform computer-implemented methods 300 and 400 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in a memory or other non-transitory machine-readable storage medium. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0089] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of various these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0090] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0091] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: receiving a current free space value and a historical increment value from a memory device; calculating a delta value using the current free space value, a target free space value, and the historical delta value, wherein the target free space value is a preferred amount of free space during steady-state operation of the memory device and wherein the historical delta value is determined using one or more previous delta values; determining a delta zone in a plurality of delta zones using the delta value, wherein each delta zone in the plurality of delta zones comprises a continuous range of delta values ​​and wherein the determined delta zone comprises the calculated delta value; calculating a new host rate using the determined delta region, the calculated delta value, and the historical delta value; and The new host rate is sent to a host device, wherein the host device changes a current host rate to the new host rate in response to receiving the new host rate.

2. The method according to claim 1, further comprising: The historical delta value is updated using the calculated delta value.

3. The method according to claim 2, wherein the plurality of incremental regions include an ideal region, a positive fine adjustment region, a negative fine adjustment region, a positive buffer region, a negative buffer region, a positive coarse adjustment region, and a negative coarse adjustment region, wherein: The ideal region includes the target free space value and is bounded by a positive ideal line and a negative ideal line; The positive fine adjustment area is delimited by the positive ideal line and the positive fine adjustment line; The negative fine adjustment area is delimited by the negative ideal line and the negative fine adjustment line; The positive buffer zone is delimited by the positive fine adjustment line and the positive coarse adjustment line; The negative buffer is delimited by the negative fine adjustment line and the negative coarse adjustment line; The positive coarse adjustment area is delimited by the positive coarse adjustment line and the positive steady state line; The negative coarse adjustment region is bounded by the negative coarse adjustment line and the negative steady state line; and Wherein each of the positive ideal line, the negative ideal line, the positive fine adjustment line, the negative fine adjustment line, the positive coarse adjustment line, the negative coarse adjustment line, the positive steady state line and the negative steady state line is determined by a distance to the target free space value. 4 . The method of claim 3 , wherein calculating the new host rate when the determined delta region is the ideal region, the positive buffer region, or the negative buffer region comprises using the current host rate as the new host rate.

5. The method of claim 3, wherein calculating the new host rate when the determined delta region is the positive or negative coarse adjustment region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; setting the adjustment polarity to said current polarity; comparing the current polarity with the historical polarity; determining a coarse adjustment value using the comparison, wherein the coarse adjustment value when the current polarity is equal to the historical polarity is greater than the coarse adjustment value when the current polarity is opposite to the historical polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and the coarse adjustment value.

6. The method of claim 3, wherein calculating the new host rate when the determined delta region is the positive or negative coarse adjustment region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; determining a sample polarity using the current free space value and the target free space value; setting the adjustment polarity to the sample polarity; comparing the current polarity with the historical polarity; determining a coarse adjustment value using the comparison, wherein the coarse adjustment value when the current polarity is equal to the historical polarity is greater than the coarse adjustment value when the current polarity is opposite to the historical polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and the coarse adjustment value.

7. The method of claim 3, wherein calculating the new host rate when the determined delta region is the positive or negative fine tuning region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; comparing the current polarity with the historical polarity; and In response to the current polarity being opposite to the historical polarity, an adjusted polarity is determined to be the current polarity.

8. The method of claim 3, wherein calculating the new host rate when the determined delta region is the positive or negative fine tuning region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; comparing the current polarity with the historical polarity; In response to the current polarity being equal to the historical polarity, comparing the calculated delta value to the historical delta value; and In response to the calculated delta value being greater than the historical delta value, the adjusted polarity is determined to be the current polarity.

9. The method of claim 3, wherein calculating the new host rate when the determined delta region is the positive or negative fine tuning region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; comparing the current polarity with the historical polarity; In response to the current polarity being equal to the historical polarity, comparing the calculated delta value to the historical delta value; and In response to the calculated delta value being less than the historical delta value, determining the adjusted polarity to be opposite to the current polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and a fine adjustment value.

10. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receiving a current free space value and a historical increment value from a memory device; calculating a delta value using the current free space value, a target free space value, and the historical delta value, wherein the target free space value is a preferred amount of free space during steady-state operation of the memory device and wherein the historical delta value is determined using one or more previous delta values; determining a delta zone in a plurality of delta zones using the delta value, wherein each delta zone in the plurality of delta zones comprises a continuous range of delta values ​​and wherein the determined delta zone comprises the calculated delta value; calculating a new host rate using the determined delta region, the calculated delta value, and the historical delta value; and The new host rate is sent to a host device, wherein the host device changes a current host rate to the new host rate in response to receiving the new host rate.

11. The non-transitory computer-readable storage medium of claim 10, wherein the processing device is further configured to: The historical delta value is updated using the calculated delta value.

12. The non-transitory computer-readable storage medium of claim 11, wherein the plurality of incremental areas include an ideal area, a positive fine adjustment area, a negative fine adjustment area, a positive buffer area, a negative buffer area, a positive coarse adjustment area, and a negative coarse adjustment area, wherein: The ideal region includes the target free space value and is bounded by a positive ideal line and a negative ideal line; The positive fine adjustment area is delimited by the positive ideal line and the positive fine adjustment line; The negative fine adjustment area is delimited by the negative ideal line and the negative fine adjustment line; The positive buffer zone is delimited by the positive fine adjustment line and the positive coarse adjustment line; The negative buffer is delimited by the negative fine adjustment line and the negative coarse adjustment line; The positive coarse adjustment area is delimited by the positive coarse adjustment line and the positive steady state line; The negative coarse adjustment region is bounded by the negative coarse adjustment line and the negative steady state line; and Wherein each of the positive ideal line, the negative ideal line, the positive fine adjustment line, the negative fine adjustment line, the positive coarse adjustment line, the negative coarse adjustment line, the positive steady state line and the negative steady state line is determined by a distance to the target free space value.

13. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined delta region is the ideal region, the positive buffer region, or the negative buffer region comprises using the current host rate as the new host rate.

14. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined delta region is the positive or negative coarse tuning region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; setting the adjustment polarity to said current polarity; comparing the current polarity with the historical polarity; determining a coarse adjustment value using the comparison, wherein the coarse adjustment value when the current polarity is equal to the historical polarity is greater than the coarse adjustment value when the current polarity is opposite to the historical polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and the coarse adjustment value.

15. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined delta region is the positive or negative coarse tuning region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; determining a sample polarity using the current free space value and the target free space value; setting the adjustment polarity to the sample polarity; comparing the current polarity with the historical polarity; determining a coarse adjustment value using the comparison, wherein the coarse adjustment value when the current polarity is equal to the historical polarity is greater than the coarse adjustment value when the current polarity is opposite to the historical polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and the coarse adjustment value.

16. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined delta region is the positive or negative fine tuning region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; comparing the current polarity with the historical polarity; and In response to the current polarity being opposite to the historical polarity, an adjusted polarity is determined to be the current polarity.

17. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined delta region is the positive or negative fine tuning region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; comparing the current polarity with the historical polarity; In response to the current polarity being equal to the historical polarity, comparing the calculated delta value to the historical delta value; and In response to the calculated delta value being greater than the historical delta value, the adjusted polarity is determined to be the current polarity.

18. The non-transitory computer-readable storage medium of claim 12, wherein calculating the new host rate when the determined delta region is the positive or negative fine tuning region comprises: determining a current polarity and a historical polarity, wherein the current polarity is a polarity of the calculated delta value and wherein the historical polarity is a polarity of the historical delta value; comparing the current polarity with the historical polarity; In response to the current polarity being equal to the historical polarity, comparing the calculated delta value to the historical delta value; and In response to the calculated delta value being less than the historical delta value, determining the adjusted polarity to be opposite to the current polarity; and The new host rate is calculated using the current host rate, the adjustment polarity, and a fine adjustment value.

19. A system comprising: a plurality of memory devices; and a processing device operatively coupled to the plurality of memory devices to: receiving a current free space value and a historical delta value from a memory device of the plurality of memory devices; calculating a delta value using the current free space value, a target free space value, and the historical delta value, wherein the target free space value is a preferred amount of free space during steady-state operation of the memory device and wherein the historical delta value is determined using one or more previous delta values; determining a delta zone in a plurality of delta zones using the delta value, wherein each delta zone in the plurality of delta zones comprises a continuous range of delta values ​​and wherein the determined delta zone comprises the calculated delta value; calculating a new host rate using the determined delta region, the calculated delta value, and the historical delta value; and sending the new host rate to a host device, wherein the host device changes a current host rate to the new host rate in response to receiving the new host rate; and The historical delta value is updated using the calculated delta value.

20. The system of claim 19, wherein the plurality of incremental regions include an ideal region, a positive fine adjustment region, a negative fine adjustment region, a positive buffer region, a negative buffer region, a positive coarse adjustment region, and a negative coarse adjustment region, wherein: The ideal region includes the target free space value and is bounded by a positive ideal line and a negative ideal line; The positive fine adjustment area is delimited by the positive ideal line and the positive fine adjustment line; The negative fine adjustment area is delimited by the negative ideal line and the negative fine adjustment line; The positive buffer zone is delimited by the positive fine adjustment line and the positive coarse adjustment line; The negative buffer is delimited by the negative fine adjustment line and the negative coarse adjustment line; The positive coarse adjustment area is delimited by the positive coarse adjustment line and the positive steady state line; The negative coarse adjustment region is bounded by the negative coarse adjustment line and the negative steady state line; and Wherein each of the positive ideal line, the negative ideal line, the positive fine adjustment line, the negative fine adjustment line, the positive coarse adjustment line, the negative coarse adjustment line, the positive steady state line and the negative steady state line is determined by a distance to the target free space value.

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