Inductor structure and filter

Abstract

The invention provides an inductor structure and a filter, and relates to the technical field of passive devices, the inductor structure comprises a dielectric substrate, a first conductive structure and a second conductive structure; the dielectric substrate is provided with a plurality of connecting via holes penetrating in the thickness direction of the dielectric substrate, connecting electrodes are arranged in the connecting via holes, and the first conductive structure and the second conductive structure are electrically connected through the connecting electrodes to form a coil of the inductance structure; one of the first conductive structure and the second conductive structure comprises at least three sub-layers, and the other one comprises at least one sub-layer; orthographic projections of two sub-layers in the first conductive structure and the second conductive structure on the dielectric substrate are at least partially overlapped, and the flowing directions of current are approximately parallel. The inductor structure is used for preparing a high-performance filter.

Description

Inductor structure, filter Technical Field

[0001] The present application relates to the field of display technology, and in particular to an inductor structure and a filter. Background Art

[0002] With the rapid development of electronic communications and the increasing popularity of 5G technology, the frequency range of signal transmission is becoming increasingly wider, greatly increasing the speed of signal transmission between devices and promoting the rapid development of information transmission in society. At the same time, various new process technologies are constantly emerging, and integration technology is rapidly developing. More and more devices are being integrated into small chips, which not only significantly reduces the size of electronic devices, but also enriches the various media functions within devices. Device sizes have iterated from macroscopic centimeters to microscopic micrometers and even nanometers.

[0003] 5G technology expands the range of signal transmission. The significant increase in signal frequency places higher demands on the electronic components within the device. Currently, there is an urgent need to provide an inductor structure with a small size and high inductance value.

[0004] Summary of the Invention

[0005] The embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides an inductor structure, comprising:

[0007] a dielectric substrate having a plurality of connection vias extending through the dielectric substrate along its thickness, wherein connection electrodes are disposed in the connection vias, and further comprising a first surface and a second surface disposed opposite to each other along its thickness direction;

[0008] a first conductive structure, disposed on the first surface;

[0009] a second conductive structure, disposed on the second surface;

[0010] The first conductive structure and the second conductive structure are electrically connected via the connecting electrode to form a coil of the inductor structure; one of the first conductive structure and the second conductive structure includes at least three sublayers, and the other includes at least one sublayer; orthographic projections of two of the sublayers in the first conductive structure and the second conductive structure on the dielectric substrate at least partially overlap, and current flow directions are substantially parallel.

[0011] In at least one embodiment provided in this application, the sublayer in the first conductive structure is referred to as a first conductive sublayer, and the sublayer in the second conductive structure is referred to as a second conductive sublayer;

[0012] Wherein, the first conductive structure includes at least three first conductive sub-layers, and the second conductive structure includes at least three second conductive sub-layers;

[0013] Alternatively, the first conductive structure includes at least three first conductive sub-layers, and the second conductive structure includes one second conductive sub-layer.

[0014] In at least one embodiment provided in the present application, the orthographic projections of at least two of the first conductive sublayers on the dielectric substrate at least partially overlap, and the current flow directions of the two layers are parallel.

[0015] In at least one embodiment provided in the present application, an orthographic projection of at least one of the first conductive sublayers on the dielectric substrate at least partially overlaps with an orthographic projection of the second conductive sublayer on the dielectric substrate, and current flow directions of the two are parallel.

[0016] In at least one embodiment provided in the present application, when the first conductive structure includes at least three first conductive sublayers and the second conductive structure includes one second conductive sublayer,

[0017] The first conductive structure includes an even number of the first conductive sub-layers, and the orthographic projections of at least two of the first conductive sub-layers on the dielectric substrate at least partially overlap, and the current flows in the two sub-layers in the same direction.

[0018] In at least one embodiment provided in the present application, an orthographic projection of at least one of the first conductive sublayers on the dielectric substrate at least partially overlaps with an orthographic projection of the second conductive sublayer on the dielectric substrate, and current flows in the two layers in the same direction.

[0019] In at least one embodiment provided in the present application, when the first conductive structure includes at least three first conductive sublayers and the second conductive structure includes one second conductive sublayer,

[0020] The first conductive structure includes an odd number of the first conductive sub-layers, and the orthographic projections of at least two of the first conductive sub-layers on the dielectric substrate at least partially overlap, and current flows in the two sub-layers in opposite directions.

[0021] In at least one embodiment provided in the present application, an orthographic projection of at least one of the first conductive sublayers on the dielectric substrate at least partially overlaps with an orthographic projection of the second conductive sublayer on the dielectric substrate, and current flows in the two layers in opposite directions.

[0022] In at least one embodiment provided in the present application, the first conductive structure includes a first first conductive sublayer, a second first conductive sublayer, a third first conductive sublayer, and a fourth first conductive sublayer sequentially arranged in a direction away from the dielectric substrate;

[0023] The first first conductive sublayer includes a plurality of first traces extending along a first direction and arranged along a second direction, and the fourth first conductive sublayer includes a plurality of second traces extending along the first direction and arranged along the second direction; the first direction and the second direction intersect; and orthographic projections of the first traces and the second traces on the dielectric substrate at least partially overlap.

[0024] The second first conductive sublayer includes a third trace, the third first conductive sublayer includes a plurality of fourth traces extending along a third direction and arranged along a fourth direction, and the second conductive sublayer includes a plurality of fifth traces extending along the third direction and arranged along the fourth direction; the third direction and the fourth direction intersect; the orthographic projections of the fourth trace and the fifth trace on the dielectric substrate at least partially overlap; and the first direction and the third direction intersect.

[0025] In at least one embodiment provided in the present application, the inductor structure includes N first traces arranged in the same row and N second traces arranged in the same row, where N is a positive integer and N is greater than or equal to 1; the orthographic projections of the Nth first trace and the Nth second trace on the dielectric substrate overlap, and the current flows in the same direction;

[0026] The two connecting electrodes are divided into a group, and the same connecting electrode group is in contact with and connected to the same fifth trace. The same connecting electrode group includes a first connecting electrode and a second connecting electrode. The area where the first connecting electrode is located overlaps with the orthographic projection of the first end of the fourth trace on the dielectric substrate, and the area where the second connecting electrode is located overlaps with the orthographic projection of the second end of the fourth trace on the dielectric substrate. The current flows in opposite directions in the first connecting electrode and the second connecting electrode in the same connecting electrode group.

[0027] In at least one embodiment provided in the present application, the inductor structure further includes N fourth routing lines arranged in the same row and N+1 fifth routing lines arranged in the same row; the orthographic projections of the Nth fourth routing line and the N+1th fifth routing line on the dielectric substrate overlap, and the current flows in the same direction.

[0028] In at least one embodiment provided in the present application, on the first surface, the second end of the first first routing line and the second end of the first second routing line are respectively electrically connected to the first end of the first fourth routing line, and the first end of the second first routing line and the first end of the second second routing line are respectively electrically connected to the second end of the first fourth routing line;

[0029] The second end of the Nth first routing line and the second end of the Nth second routing line are respectively electrically connected to the first end of the Nth fourth routing line, and the first end of the N+1th first routing line and the first end of the N+1th second routing line are respectively electrically connected to the second end of the Nth fourth routing line.

[0030] In at least one embodiment provided herein, the inductor structure includes N+1 connecting electrode groups arranged in the same row, a first end of the third trace is electrically connected to the N+1th second connecting electrode, and a second end of the third trace is electrically connected to the first end of the first first trace and the first end of the first second trace, respectively;

[0031] The first end of the first first routing line and the first end of the first second routing line are electrically connected to the first second connecting electrode respectively, and the first end of the first first routing line and the first end of the first second routing line are electrically connected to the second first connecting electrode respectively; the first end of the Nth first routing line and the first end of the Nth second routing line are electrically connected to the Nth second connecting electrode respectively, and the second end of the Nth first routing line and the second end of the Nth second routing line are electrically connected to the N+1th first connecting electrode respectively.

[0032] In at least one embodiment provided in the present application, the orthographic projection of the third trace except the first end and the second end thereof on the dielectric substrate does not overlap with the area where the connecting electrode group is located.

[0033] In at least one embodiment provided in the present application, the inductor structure further includes N+1 fourth wirings arranged in the same row and N+1 fifth wirings arranged in the same row;

[0034] The orthographic projections of the Nth fourth routing line and the Nth fifth routing line on the dielectric substrate overlap, and the current flows in the same direction.

[0035] In at least one embodiment provided in the present application, on the first surface, the second end of the first fourth routing is electrically connected to the first end of the first first routing and the first end of the first second routing, the first end of the N+1th fourth routing is electrically connected to the second end of the Nth first routing and the second end of the Nth second routing, and the second end of the N+1th fourth routing is electrically connected to the first end of the N+1th first routing and the first end of the N+1th second routing.

[0036] In at least one embodiment provided in the present application, the inductor structure includes N+1 connecting electrode groups arranged in the same row, the first end of the third trace is electrically connected to the N+1th second connecting electrode, and the second end of the third trace is electrically connected to the first end of the first fourth trace.

[0037] In at least one embodiment provided in the present application, orthographic projections of the first routing lines, the second routing lines, the fourth routing lines, and the fifth routing lines on the dielectric substrate overlap with orthographic projections of the third routing lines on the dielectric substrate.

[0038] In at least one embodiment provided in the present application, the first conductive structure includes a first first conductive sublayer, a third first conductive sublayer, and a fourth first conductive sublayer sequentially arranged in a direction away from the dielectric substrate;

[0039] The first first conductive sublayer includes a plurality of first traces extending along a first direction and arranged along a second direction, and the fourth first conductive sublayer includes a plurality of second traces extending along the first direction and arranged along the second direction; the first direction and the second direction intersect; and orthographic projections of the first traces and the second traces on the dielectric substrate at least partially overlap.

[0040] The third first conductive sublayer includes a plurality of fourth traces extending along a third direction and arranged along a fourth direction, and the second conductive sublayer includes a plurality of fifth traces extending along the third direction and arranged along the fourth direction; the third direction and the fourth direction intersect; the orthographic projections of the fourth trace and the fifth trace on the dielectric substrate at least partially overlap; and the first direction and the third direction intersect.

[0041] In at least one embodiment provided in the present application, the inductor structure includes N first traces arranged in the same row, N second traces arranged in the same row, N+1 fourth traces arranged in the same row, and N+1 fifth traces arranged in the same row; wherein N is a positive integer, and N is greater than or equal to 1;

[0042] The orthographic projections of the Nth first routing line and the Nth second routing line on the dielectric substrate overlap, and the current flows in opposite directions; the orthographic projections of the Nth fourth routing line and the Nth fifth routing line on the dielectric substrate overlap, and the current flows in opposite directions;

[0043] The two connecting electrodes are divided into a group, and the same connecting electrode group is in contact with and connected to the same fifth trace. The same connecting electrode group includes a first connecting electrode and a second connecting electrode. The area where the first connecting electrode is located overlaps with the orthographic projection of the first end of the fourth trace on the dielectric substrate, and the area where the second connecting electrode is located overlaps with the orthographic projection of the second end of the fourth trace on the dielectric substrate. The current flows in opposite directions in the first connecting electrode and the second connecting electrode in the same connecting electrode group.

[0044] In at least one embodiment provided in the present application, the first first connecting electrode is electrically connected to the first end of the first fourth routing line and the first end of the first first routing line, the second end of the first fourth routing line is electrically connected to the first second connecting electrode, the second end of the first first routing line is electrically connected to the second second connecting electrode and the first end of the first second routing line, and the second end of the first second routing line is electrically connected to the first end of the first first routing line and the first end of the first fourth routing line.

[0045] The Nth first connecting electrode is electrically connected to the first end of the Nth fourth routing and the first end of the Nth first routing, respectively; the second end of the Nth fourth routing is electrically connected to the Nth second connecting electrode, respectively; the second end of the Nth first routing is electrically connected to the N+1th second connecting electrode and the first end of the Nth second routing, respectively; the second end of the Nth second routing is electrically connected to the first end of the Nth first routing and the first end of the Nth fourth routing, respectively.

[0046] In at least one embodiment provided in the present application, the inductor structure further includes a first insulating layer, a second insulating layer, a third insulating layer, a first protective layer, and a second protective layer;

[0047] The first insulating layer is located between the first first conductive sublayer and the second first conductive sublayer, the second insulating layer is located between the second first conductive sublayer and the third first conductive sublayer, and the third insulating layer is located between the third first conductive sublayer and the fourth first conductive sublayer;

[0048] The first protective layer covers the fourth first conductive sub-layer, and the second protective layer covers the second conductive sub-layer.

[0049] In at least one embodiment provided in the present application, the inductor structure further includes a first insulating layer, a third insulating layer, a first protective layer, and a second protective layer;

[0050] The first insulating layer is located between the first first conductive sub-layer and the third first conductive sub-layer, and the third insulating layer is located between the third first conductive sub-layer and the fourth first conductive sub-layer;

[0051] The first protective layer covers the fourth first conductive sub-layer, and the second protective layer covers the second conductive sub-layer.

[0052] In at least one embodiment provided in the present application, the thickness of the first conductive sublayer and the second conductive sublayer are both in the range of 1 μm to 10 μm.

[0053] In at least one embodiment provided in this application, the connecting electrode comprises a metal material;

[0054] Alternatively, the connection electrode includes resin and a metal material covering the resin.

[0055] In at least one embodiment provided in the present application, at least one of the first routing, the second routing, the fourth routing and the fifth routing includes a plurality of sub-routings arranged in parallel, there is a gap between two adjacent sub-routings, and the line widths of the sub-routings are substantially the same.

[0056] In at least one embodiment provided in the present application, the angle between the first direction and the third direction is an acute angle.

[0057] In at least one embodiment provided in the present application, the third routing includes a plurality of sub-routings arranged in parallel, a gap exists between two adjacent sub-routings, and the line widths of the sub-routings are substantially the same.

[0058] In at least one embodiment provided in the present application, the line width of the third routing line is smaller than the line widths of the first routing line, the second routing line, and the fourth routing line.

[0059] In a second aspect, an embodiment of the present application provides a filter comprising at least one inductor structure as described in any one of the first aspects and at least one capacitor.

[0060] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0062] FIG1 and FIG3 are both schematic structural diagrams of a first inductor structure provided by an embodiment of the present application;

[0063] FIG2 is a schematic diagram of the intermediate structure of the inductor structure of FIG1 when the fourth first conductive sublayer is not provided;

[0064] FIG4 is a right side view of FIG1;

[0065] FIG5 is a top view of the first conductive structure in the inductor structure shown in FIG1 ;

[0066] FIG6 is a top view of FIG1 ;

[0067] FIG7 is a schematic diagram of the intermediate structure of the second inductor structure provided by an embodiment of the present application when the third first conductive sublayer and the fourth first conductive sublayer are not provided;

[0068] FIG8 is a schematic structural diagram of a second inductor structure provided in an embodiment of the present application;

[0069] FIG9 is a right side view of FIG8;

[0070] FIG10 is a top view of the first conductive structure in the inductor structure shown in FIG8 ;

[0071] FIG11 is a schematic diagram of an intermediate structure of the third inductor structure provided by an embodiment of the present application when the fourth first conductive sublayer is not provided;

[0072] FIG12 is a schematic structural diagram of a third inductor structure provided in an embodiment of the present application;

[0073] FIG13 is a top view of the first conductive structure in the inductor structure shown in FIG12;

[0074] FIG14 is a right side view of FIG12;

[0075] FIG15 is a schematic diagram of the structure of a filter;

[0076] 16A-16H are schematic diagrams of intermediate structures during the preparation process of an inductor structure provided in an embodiment of the present application. Specific embodiments

[0077] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0078] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0079] In the embodiments of the present application, the terms "upper" and "lower" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0080] Throughout the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present application. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0081] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0082] The features "parallel," "perpendicular," and "identical" used in the embodiments of the present application include features such as "parallel," "perpendicular," and "identical" in the strict sense, as well as "approximately parallel," "approximately perpendicular," and "approximately identical" that include certain tolerances, taking into account the measurement and tolerances associated with the measurement of a particular quantity (e.g., limitations of the measurement system), and represent within an acceptable range of deviation for a particular value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the stated value.

[0083] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0084] In the embodiments of this application, "same layer" refers to the relationship between multiple film layers formed from the same material after the same step (e.g., a one-step patterning process). "Same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. Polygons in this specification are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and some small deformations due to tolerances may exist.

[0085] With the rapid development of electronic communications and the increasing popularity of 5G technology, the frequency range of signal transmission is becoming increasingly wider, greatly increasing the speed of signal transmission between devices and promoting the rapid development of information transmission in society. At the same time, various new process technologies are constantly emerging, and integration technology is rapidly developing. More and more devices are being integrated into small chips, which not only significantly reduces the size of electronic devices, but also enriches the various media functions within devices. Device sizes have iterated from macroscopic centimeters to microscopic micrometers and even nanometers.

[0086] 5G technology first expands the range of signal transmission. This significant increase in signal frequency places higher demands on the electronic components within devices, especially in common mobile terminals. Secondly, the increase in signal frequency requires electronic components to transmit signals better and faster, further increasing the rated power of devices. Achieving higher performance per unit volume has become a new goal.

[0087] The development of IPD (Integrated Passive Device) technology has greatly improved the integration of devices, becoming a manufacturing method that can match the development requirements of electronic communication technology. This process changes the traditional process dimensions and also places higher demands on the design of passive components. The traditional copper wire coil inductor has been replaced by planar spiral inductors. With the development of substrate processing technology, 3D structure inductors have also been vigorously developed. This type of passive device can be used for both discrete devices and RF modules. Therefore, the improvement of IPD device performance will contribute to the further development of RF technology.

[0088] Based on this, embodiments of the present application provide an inductor structure and filter based on IPD technology, the inductor structure comprising a dielectric substrate, a first conductive structure disposed on a first surface, and a second conductive structure disposed on a second surface; the dielectric substrate having a plurality of connecting vias extending through its thickness, with connecting electrodes disposed within the connecting vias; wherein the first conductive structure and the second conductive structure are electrically connected via the connecting electrodes to form a coil of the inductor structure; one of the first conductive structure and the second conductive structure comprises at least three sublayers, and the other comprises at least one sublayer; orthographic projections of two of the first conductive structure and the second conductive structure on the dielectric substrate at least partially overlap, and the current flow directions are substantially parallel. The inductor structure provided in embodiments of the present application, under existing fabrication process conditions, can, through design changes, significantly improve inductance value, increase inductance density per unit volume, and reduce the size of the inductor structure, thereby enabling the inductor structure to have a wider and more flexible application, while improving the performance of the inductor structure without increasing the fabrication process difficulty and fabrication cost.

[0089] The inductor structure and filter provided in the embodiments of the present application will be specifically introduced and described below with reference to the accompanying drawings.

[0090] An embodiment of the present application provides an inductor structure, as shown in FIG4 , FIG9 and FIG14 , including:

[0091] The dielectric substrate 1 has a plurality of connection vias Via extending through the dielectric substrate 1 along its thickness, wherein connection electrodes DJ are disposed in the connection vias. The dielectric substrate 1 further includes a first surface B1 and a second surface B2 disposed opposite to each other along its thickness direction.

[0092] A first conductive structure 6 is provided on the first surface B1;

[0093] A second conductive structure 7, disposed on the second surface B2;

[0094] The first conductive structure 6 and the second conductive structure 7 are electrically connected via the connecting electrode DJ to form a coil of an inductor structure. One of the first conductive structure 6 and the second conductive structure 7 includes at least three sublayers, and the other includes at least one sublayer (for example, as shown in FIG. 1 and FIG. 4 , the first conductive structure 6 includes sublayers D1-1, D1-2, D1-3, and D1-4; the second conductive structure 7 includes sublayer D2). The orthographic projections of two of the sublayers in the first conductive structure 6 and the second conductive structure 7 on the dielectric substrate 1 at least partially overlap, and the current flow directions are substantially parallel.

[0095] The dielectric substrate 1 is mainly made of insulating material, and the specific material type of the dielectric substrate 1 is not limited here.

[0096] In some embodiments, the main material of the dielectric substrate 1 may be a rigid material.

[0097] Exemplarily, the dielectric substrate 1 may be a standard silicon wafer with embedded chips, a high-resistance silicon substrate, a glass substrate, a ceramic substrate, or a low-K molding material with embedded chips in an eWLB (embedded wafer level ball grid array) packaging process.

[0098] In other embodiments, the main material of the dielectric substrate 1 may be a flexible material.

[0099] Exemplarily, the dielectric substrate 1 may be a polyimide (PI) substrate or a bisbenzocyclobutene (BCB) substrate.

[0100] The size and thickness of the dielectric substrate 1 are not limited here.

[0101] Exemplarily, the thickness of the dielectric substrate 1 may range from 0.2 mm to 0.5 mm, for example, 0.3 mm or 0.4 mm.

[0102] The above-mentioned multiple connection vias Via refer to two or more connection vias Via, wherein the connection vias Via are at least filled with conductive material to form connection electrodes DJ. Therefore, the structure of the connection vias Via is not directly reflected in the drawings provided in the embodiments of the present application.

[0103] The specific number of the above-mentioned connecting vias Via (or connecting electrodes DJ) is not limited here.

[0104] In some embodiments, the number of the connecting vias Via (or connecting electrodes DJ) is an even number, so that a loop is formed between the first conductive structure 6 and the second conductive structure 7 on both sides of the dielectric substrate 101. For example, the number of the connecting vias Via (or connecting electrodes DJ) can be two, four, six, eight, etc.

[0105] The three-dimensional shape of the connecting via is not limited here. For example, the three-dimensional shape of the connecting via can be a column, such as a cylinder or a prism; for example, the three-dimensional shape of the connecting via can be a truncated cone or a prism.

[0106] The cross-sectional shape of the connecting vias Via is not limited herein. For example, the cross-sectional shape of the connecting vias Via can be a quadrilateral, such as a rectangle, a square, or a trapezoid.

[0107] The number and shape of the connection electrodes DJ are related to the number and shape of the connection vias Via, which will not be described in detail here.

[0108] The size of the planar pattern of the connecting vias is not limited here. Exemplarily, the planar pattern of the connecting vias is substantially circular, wherein the diameter of the circle ranges from 30 μm to 100 μm. For example, the diameter of the circle is 33 μm, 35 μm, 40 μm, 43 μm, 45 μm, 48 μm, 55 μm, 60 μm, 63 μm, 65 μm, 68 μm, 70 μm, 75 μm, 78 μm, 80 μm, 86 μm, 88 μm, 90 μm, 93 μm, 95 μm, or 98 μm.

[0109] Exemplarily, when the planar figure connecting the via hole Via is a polygon, the size of the maximum diagonal of the polygon ranges from 30μm to 100μm, for example, the size of the maximum diagonal of the polygon is 33μm, 35μm, 40μm, 43μm, 45μm, 48μm, 55μm, 60μm, 63μm, 65μm, 68μm, 70μm, 75μm, 78μm, 80μm, 86μm, 88μm, 90μm, 93μm, 95μm or 98μm.

[0110] Exemplarily, when the three-dimensional shape of the connecting via Via is a truncated cone or a prism, the sizes of the planar figures of the upper opening and the lower opening of the connecting via Via are different. In this case, the size range of the planar figures of the upper opening and the lower opening is 30μm to 100μm.

[0111] Exemplarily, the three-dimensional shape of the connecting via Via can be a shape (hourglass shape) of two truncated cone or prism-shaped structures spliced ​​together, that is, the three-dimensional shape of the connecting via Via shows that the sizes of the upper opening and the lower opening are both larger than the size of the plane figure of the middle area; it can be understood that at this time, the shape of its cross-sectional figure is a shape formed by two trapezoids spliced ​​together, wherein the upper base of the upper trapezoid and the upper base of the lower trapezoid are spliced ​​together, and the lower bases of the two trapezoids are respectively located on both sides.

[0112] In an exemplary embodiment, the first surface B1 and the second surface B2 may be parallel (substantially parallel) to each other. For example, the first surface B1 and the second surface B2 may both be planes.

[0113] The shapes of the specific conductive patterns of the first conductive structure 6 and the second conductive structure 7 are not limited herein. For example, the orthographic projections of the conductive patterns in the first conductive structure 6 and the conductive patterns in the second conductive structure 7 on the dielectric substrate 1 at least partially overlap, where "at least partially overlap" includes but is not limited to partial overlap and complete overlap.

[0114] There is no limitation on the specific materials of the first conductive structure 6 and the second conductive structure 7. For example, the materials of the first conductive structure 6 and the second conductive structure 7 may include any one of copper, silver, aluminum, nickel, molybdenum and titanium, or a combination of several metals stacked together.

[0115] In an exemplary embodiment, one of the first conductive structure 6 and the second conductive structure 7 includes at least three sublayers, and the other includes at least one sublayer, including but not limited to the following:

[0116] First, the first conductive structure 6 includes at least three sub-layers, and the second conductive structure 7 includes at least one sub-layer.

[0117] For example, the first conductive structure 6 includes at least three sub-layers, and the second conductive structure 7 includes one sub-layer. In this case, the sub-layers in the first conductive structure 6 are electrically connected to each other to serve as first conductive lines.

[0118] For another example, the first conductive structure 6 includes at least three sublayers, and the second conductive structure 7 includes at least three sublayers. In this case, the sublayers in the first conductive structure 6 are electrically connected to each other to serve as first conductive wires; the sublayers in the second conductive structure 7 are electrically connected to each other to serve as second conductive wires. The first conductive wires and the second conductive wires are electrically connected via the connecting electrode DJ to form a conductive loop and a coil of the inductor structure.

[0119] Second, the second conductive structure 7 includes at least three sub-layers, and the first conductive structure 6 includes at least one sub-layer.

[0120] For example, the second conductive structure 7 includes at least three sub-layers, and the first conductive structure 6 includes one sub-layer. In this case, the sub-layers in the second conductive structure 7 are electrically connected to each other to serve as second conductive lines.

[0121] For another example, the second conductive structure 7 includes at least three sublayers, and the first conductive structure 6 includes at least three sublayers. In this case, the sublayers in the first conductive structure 6 are electrically connected to each other to serve as first conductive wires; the sublayers in the second conductive structure 7 are electrically connected to each other to serve as second conductive wires. The first conductive wires and the second conductive wires are electrically connected via the connecting electrode DJ, forming a conductive loop and a coil of the inductor structure.

[0122] Illustratively, the material of the at least one sub-layer may include any one of copper, silver, aluminum, nickel, molybdenum and titanium, or a combination of several metals stacked together.

[0123] In some embodiments, the material of the at least one sublayer may include a molybdenum-nickel-titanium alloy (MoNiTi) layer, a copper metal layer, and a molybdenum-niobium alloy (MoNb) layer stacked in sequence. The molybdenum-nickel-titanium alloy layer may increase the nucleation density of copper metal grains in the electroplating process, and the molybdenum-niobium alloy layer may prevent copper metal oxidation.

[0124] In other embodiments, the at least one sublayer may include a molybdenum-niobium alloy layer, a copper metal layer, and a protective layer stacked in sequence. The protective layer may include any of copper-nickel alloy (CuNi), nickel, or indium tin oxide (ITO). The molybdenum-niobium alloy layer improves the adhesion between the copper metal and the film layer on the side of the dielectric substrate 1, while the protective layer prevents oxidation of the copper metal.

[0125] In some embodiments, the thickness of the at least one sub-layer may be in the range of 0.5-10 μm, for example, the thickness may be 0.5 μm, 1 μm, 1.8 μm, 2.7 μm or 10 μm.

[0126] In other embodiments, the thickness of the at least one sub-layer may be in the range of 1.5 μm to 7 μm, for example, the thickness may be 1.5 μm, 2 μm, 4 μm, 6.5 μm or 7 μm.

[0127] The orthographic projections of two sub-layers in the first conductive structure 6 and the second conductive structure 7 on the dielectric substrate 1 at least partially overlap, and the current flow directions are substantially parallel, including but not limited to the following situations:

[0128] The first type is that the first conductive structure 6 includes at least three sub-layers, and the orthographic projections of two sub-layers in the first conductive structure 6 on the dielectric substrate 1 at least partially overlap, and the current flow directions are substantially parallel.

[0129] The second type is that the second conductive structure 7 includes at least three sub-layers, and the orthographic projections of two sub-layers in the second conductive structure 7 on the dielectric substrate 1 at least partially overlap, and the current flow directions are substantially parallel.

[0130] In a third embodiment, the first conductive structure 6 includes at least three sublayers, and the second conductive structure 7 includes at least one sublayer; or, the first conductive structure 6 includes at least one sublayer, and the second conductive structure 7 includes at least three sublayers. The orthographic projections of one sublayer in the first conductive structure 6 and one sublayer in the second conductive structure 7 on the dielectric substrate 1 at least partially overlap, and the current flows in substantially parallel directions.

[0131] It should be noted that the above-mentioned “at least partially overlap” includes partial overlap or complete overlap.

[0132] The substantially parallel flow directions of the currents may include two situations: the flow directions of the currents are consistent (ie, the same) or the flow directions of the currents are opposite.

[0133] The theoretical calculation formulas for inductance and mutual inductance are provided below:

[0134] Among them, LZ represents the inductance value of the inductor structure, L M It represents the mutual inductance value in the inductor structure. An increase in the mutual inductance value will increase the overall inductance value of the inductor structure.

[0135] In the above formula (1), μ is the magnetic permeability of the material of the dielectric substrate 1. The wire provided in the first conductive structure 6 is referred to as the first wire, the wire provided in the second conductive structure 7 is referred to as the second wire, and the connecting electrode DJ is referred to as the third wire. For the first conductive structure 6 and the second conductive structure 7, L represents the effective length of the wire, W represents the width of the wire, and t represents the thickness of the wire. For the connecting electrode DJ, taking a columnar connecting electrode DJ as an example, W represents the diameter of the circle when the planar figure is a circle, t represents the height of the columnar connecting electrode DJ, and L also represents the diameter of the circle.

[0136] In formula (2), μ represents the magnetic permeability of the material of dielectric substrate 1. The conductor provided in first conductive structure 6 is referred to as the first conductor, the conductor provided in second conductive structure 7 is referred to as the second conductor, and connecting electrode DJ is referred to as the third conductor. L represents the effective length of the conductor, W represents the width of the conductor, t represents the thickness of the conductor, and D represents the spacing between the conductors. For connecting electrode DJ, taking a columnar connecting electrode DJ as an example, W represents the diameter of the circle when the planar shape is circular, t represents the height of the columnar connecting electrode DJ, L also represents the diameter of the circle, and D represents the spacing between connecting electrodes DJ.

[0137] It should be noted that, when the current directions of the two conductive structures are consistent, the larger the area of ​​the overlapping region between the two, the greater the mutual inductance.

[0138] In the inductor structure provided in the embodiments of the present application, referring to FIG. 4 , FIG. 9 , or FIG. 14 , on the one hand, by providing one of the first conductive structure 6 and the second conductive structure 7 with at least three sublayers and the other with at least one sublayer (for example, as shown in FIG. 1 and FIG. 4 , the first conductive structure 6 includes sublayers D1-1, D1-2, D1-3, and D1-4; the second conductive structure 7 includes sublayer D2), the number of conductive layers constituting the wire (coil) is increased, thereby extending the effective length of the coil forming the inductor structure, thereby increasing the inductance density of the inductor structure and improving the inductance value. On the other hand, by providing that the orthographic projections of two of the sublayers in the first conductive structure 6 and the second conductive structure 7 on the dielectric substrate 1 at least partially overlap, when the currents flow in the two structures in the same direction, the mutual inductance of the inductor structure can be effectively increased, further increasing the inductance value of the inductor structure and improving the performance of the inductor structure. While the size of the inductor structure remains substantially unchanged, the application flexibility of the inductor structure is improved, and the application field of the inductor structure is expanded.

[0139] In at least one embodiment provided in the present application, as shown in conjunction with FIG1 and FIG4 , the sublayer in the first conductive structure 6 is referred to as the first conductive sublayer D1 (e.g., sublayer D1-1, sublayer D1-2, sublayer D1-3, and sublayer D1-4), and the sublayer in the second conductive structure 7 is referred to as the second conductive sublayer D2;

[0140] In some embodiments, the first conductive structure 6 includes at least three first conductive sub-layers D1, and the second conductive structure 7 includes at least three second conductive sub-layers D2;

[0141] Alternatively, in other embodiments, as shown in combination with Figures 1 and 4, Figures 8 and 9, or Figures 12 and 14, the first conductive structure 6 includes at least three first conductive sublayers D1, and the second conductive structure 7 includes one second conductive sublayer D2.

[0142] In at least one embodiment provided in the present application, the orthographic projections of at least two first conductive sub-layers D1 on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two layers are parallel.

[0143] For example, there may be two first conductive sub-layers D1 whose orthographic projections on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two layers are parallel.

[0144] For example, the orthographic projections of the two first conductive sub-layers D1 on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two layers are consistent (the same).

[0145] For another example, the orthographic projections of the two first conductive sub-layers D1 on the dielectric substrate 1 at least partially overlap, and the current flows in the two layers are in opposite directions.

[0146] For example, there may be three first conductive sub-layers D1 whose orthographic projections on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two layers are parallel.

[0147] For example, the orthographic projections of the first and second first conductive sublayers D1 on the dielectric substrate 1 at least partially overlap, and the current flows in the two layers in the same (same) direction; and the orthographic projections of the second and third first conductive sublayers D1 on the dielectric substrate 1 at least partially overlap, and the current flows in the two layers in opposite directions.

[0148] For another example, the orthographic projections of the three first conductive sub-layers D1 on the dielectric substrate 1 at least partially overlap, and the current flow directions of the three first conductive sub-layers D1 are the same.

[0149] In at least one embodiment provided in the present application, an orthographic projection of at least one first conductive sublayer D1 on the dielectric substrate 1 at least partially overlaps with an orthographic projection of the second conductive sublayer D2 on the dielectric substrate 1 , and current flows in both directions are parallel.

[0150] For example, there may be an orthographic projection of the first conductive sublayer D1 on the dielectric substrate 1 at least partially overlapping with an orthographic projection of the second conductive sublayer D2 on the dielectric substrate 1 , and the current flow directions of the two layers are parallel.

[0151] For example, an orthographic projection of a first conductive sublayer D1 on the dielectric substrate 1 at least partially overlaps with an orthographic projection of a second conductive sublayer D2 on the dielectric substrate 1 , and current flows in the two layers in the same direction.

[0152] For example, there may be two orthographic projections of the first conductive sublayer D1 on the dielectric substrate 1 and an orthographic projection of the second conductive sublayer D2 on the dielectric substrate 1 , which at least partially overlap, and the current flow directions of the two are parallel.

[0153] For example, the orthographic projection of one of the two first conductive sublayers D1 on the dielectric substrate 1 at least partially overlaps with the orthographic projection of the second conductive sublayer D2 on the dielectric substrate 1, and the current flows in the two layers in the same (same) direction. The orthographic projection of the other first conductive sublayer D1 on the dielectric substrate 1 at least partially overlaps with the orthographic projection of the second conductive sublayer D2 on the dielectric substrate 1, and the current flows in the two layers in opposite directions.

[0154] For another example, the orthographic projections of the two first conductive sub-layers D1 on the dielectric substrate 1 and the orthographic projection of the second conductive sub-layer D2 on the dielectric substrate 1 at least partially overlap, and the current flow directions of the two are the same.

[0155] In at least one embodiment provided in the present application, when the first conductive structure 6 includes at least three first conductive sublayers D1 and the second conductive structure 7 includes one second conductive sublayer D2, when the first conductive structure 6 includes an even number of first conductive sublayers D1,

[0156] In some examples, the orthographic projections of at least two first conductive sublayers D1 on the dielectric substrate 1 at least partially overlap, and the current flows in the two layers in the same direction;

[0157] In other examples, an orthographic projection of at least one first conductive sublayer D1 on the dielectric substrate at least partially overlaps with an orthographic projection of the second conductive sublayer D2 on the dielectric substrate, and current flows in the two layers in the same direction.

[0158] Exemplarily, the first conductive structure 6 includes 4 first conductive sub-layers D1 , 6 first conductive sub-layers D1 , 8 first conductive sub-layers D1 , or 10 first conductive sub-layers D1 .

[0159] In the inductor structure provided in the embodiment of the present application, by setting one of the first conductive structure 6 and the second conductive structure 7 to include at least three sublayers, and the other to include at least one sublayer (for example, as shown in Figures 1 and 4, the first conductive structure 6 includes sublayer D1-1, sublayer D1-2, sublayer D1-3 and sublayer D1-4; the second conductive structure 7 includes sublayer D2), the number of conductive layers constituting the wire (coil) is increased, thereby extending the effective length of the coil forming the inductor structure, thereby increasing the inductance density of the inductor structure and improving the inductance value.

[0160] In addition, when the first conductive structure 6 includes an even number of first conductive sublayers D1, by arranging the orthographic projections of two of the sublayers in the first conductive structure 6 and the second conductive structure 7 on the dielectric substrate 1 to at least partially overlap, when the directions of current flow in the two are the same, the mutual inductance of the inductor structure can be effectively increased, the inductance value of the inductor structure can be further increased, and the performance of the inductor structure can be improved. When the size of the inductor structure remains basically unchanged, the application flexibility of the inductor structure is improved, and the application field of the inductor structure is expanded.

[0161] In at least one embodiment provided in the present application, when the first conductive structure 6 includes at least three first conductive sublayers D1 and the second conductive structure 7 includes one second conductive sublayer D2, when the first conductive structure 6 includes an odd number of first conductive sublayers D1,

[0162] In some examples, the orthographic projections of at least two first conductive sub-layers D1 on the dielectric substrate 1 at least partially overlap, and the current flows in the two layers are in opposite directions.

[0163] In other examples, an orthographic projection of at least one first conductive sublayer D1 on the dielectric substrate 1 at least partially overlaps with an orthographic projection of the second conductive sublayer D2 on the dielectric substrate 1 , and current flows in the two layers are in opposite directions.

[0164] Exemplarily, the first conductive structure 6 includes 3 first conductive sub-layers D1 , 5 first conductive sub-layers D1 , 7 first conductive sub-layers D1 , 9 first conductive sub-layers D1 , or 11 first conductive sub-layers D1 .

[0165] In the inductor structure provided in the embodiment of the present application, when the first conductive structure 6 includes an odd number of first conductive sublayers D1, by setting one of the first conductive structure 6 and the second conductive structure 7 to include at least three sublayers and the other to include at least one sublayer (for example, as shown in combination with Figures 1 and 4, the first conductive structure 6 includes sublayer D1-1, sublayer D1-2, sublayer D1-3 and sublayer D1-4; the second conductive structure 7 includes sublayer D2), the number of conductive layers constituting the wire (coil) is increased, thereby extending the effective length of the coil forming the inductor structure, thereby increasing the inductance density of the inductor structure, improving the inductance value, and improving the performance of the inductor structure; while the size of the inductor structure remains basically unchanged, the application flexibility of the inductor structure is improved, and the application field of the inductor structure is expanded.

[0166] In at least one embodiment provided in the present application, as shown in combination with FIG1 , FIG2 , FIG3 , and FIG4 , or as shown in combination with FIG7 , FIG8 , and FIG9 , the first conductive structure 6 includes a first first conductive sublayer D1-1, a second first conductive sublayer D1-2, a third first conductive sublayer D1-3, and a fourth first conductive sublayer D1-4, which are sequentially arranged in a direction away from the dielectric substrate 1 ;

[0167] It should be noted that Figure 4 is a right side view of the inductor structure shown in Figure 3. Figures 1 and 3 depict the same inductor structure, but to avoid confusion due to excessive markings, the current flow direction of each trace in the inductor structure is marked in Figure 3.

[0168] 1 , 2 , 3 , and 4 , or in combination with FIG. 7 , 8 , and 9 , the first first conductive sublayer D1-1 includes a plurality of first traces L1 extending along a first direction F1 and arranged along a second direction F2, and the fourth first conductive sublayer D1-4 includes a plurality of second traces L2 extending along the first direction and arranged along the second direction; the first direction F1 and the second direction F2 intersect; and the orthographic projections of the first traces L1 and the second traces L2 on the dielectric substrate 1 at least partially overlap.

[0169] The second first conductive sublayer D1-2 includes a third trace L3, the third first conductive sublayer D1-3 includes a plurality of fourth traces L4 extending along the third direction F3 and arranged along the fourth direction F4, and the second conductive sublayer D2 includes a plurality of fifth traces L5 extending along the third direction F3 and arranged along the fourth direction F4; the third direction F3 and the fourth direction F4 intersect; the orthographic projections of the fourth trace L4 and the fifth trace L5 on the dielectric substrate 1 at least partially overlap; and the first direction F1 and the third direction F3 intersect.

[0170] In an exemplary embodiment, the materials of the first first conductive sublayer D1-1, the second first conductive sublayer D1-2, the third first conductive sublayer D1-3 and the fourth first conductive sublayer D1-4 may all include any one of copper, silver, aluminum, nickel, molybdenum and titanium, or a combination of several metals stacked together.

[0171] Exemplarily, the material of at least one of the first conductive sub-layers D1 includes a molybdenum-nickel-titanium alloy (MoNiTi) layer, a copper metal layer, and a molybdenum-niobium alloy (MoNb) layer stacked in sequence. The molybdenum-nickel-titanium alloy layer can increase the nucleation density of copper metal grains in the electroplating process, and the molybdenum-niobium alloy layer prevents copper metal oxidation.

[0172] Illustratively, the material of the at least one first conductive sublayer D1 may include a molybdenum-niobium alloy layer, a copper metal layer, and a protective layer stacked in sequence. The protective layer may include any one of copper-nickel alloy (CuNi), nickel, or indium tin oxide (ITO). The molybdenum-niobium alloy layer improves the adhesion between the copper metal and the film layer on the side of the dielectric substrate 1, while the protective layer prevents oxidation of the copper metal.

[0173] Here, there is no limitation on whether the materials of the first first conductive sublayer D1-1, the second first conductive sublayer D1-2, the third first conductive sublayer D1-3 and the fourth first conductive sublayer D1-4 are the same, which can be determined based on the design requirements of the conductivity of the inductor structure.

[0174] Here, there is no limitation on whether the lengths and widths (also referred to as line widths, Width) of the first line L1 , the second line L2 , the third line L3 , the fourth line L4 and the fifth line are the same.

[0175] In some embodiments, the first trace L1 and the second trace L2 have the same length.

[0176] In some embodiments, the third trace L4 and the fifth trace L5 have the same length.

[0177] In some embodiments, the length of the third line L3 is greater than the lengths of the first line L1 , the second line L2 , the third line L4 , and the fifth line L5 .

[0178] In some examples, the first trace L1 and the second trace L2 have the same width.

[0179] In some examples, the third trace L4 and the fifth trace L5 have the same width.

[0180] In some examples, the line width of the third trace L3 is smaller than the line widths of the first trace L1 , the second trace L2 , the third trace L4 , and the fifth trace L5 .

[0181] Here, there is no limitation on whether the thicknesses of the first line L1 , the second line L2 , the third line L3 , the fourth line L4 and the fifth line are the same.

[0182] In some examples, thicknesses of at least portions of the first trace L1 , the second trace L2 , the third trace L3 , the fourth trace L4 , and the fifth trace are substantially the same.

[0183] In some examples, at least a portion of the first trace L1, the second trace L2, the third trace L3, the fourth trace L4, and the fifth trace may include straight lines;

[0184] Alternatively, at least a portion of the first line L1, the second line L2, the third line L3, the fourth line L4, and the fifth line may include arcs;

[0185] Alternatively, at least a portion of the first line L1, the second line L2, the third line L3, the fourth line L4, and the fifth line may include a broken line segment consisting of a straight line segment;

[0186] Alternatively, at least a portion of the first line L1 , the second line L2 , the third line L3 , the fourth line L4 , and the fifth line may include a combination of straight lines and arcs.

[0187] In at least one embodiment provided herein, as shown in conjunction with FIG. 1 , FIG. 2 , and FIG. 3 , the inductor structure includes N first traces L1 and N second traces L2 arranged in the same row, where N is a positive integer and greater than or equal to 1. As shown in FIG. 5 , the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 overlap, and the current flows in the same direction. The direction indicated by the dashed arrow in FIG. 3 may be the current flow direction.

[0188] It should be noted that, in order to clearly illustrate the positional relationship between the orthographic projections of the Nth first line L1 and the Nth second line L2 on the dielectric substrate 1, Figures 5 and 6 are drawn as an example in which the orthographic projections of the Nth first line L1 and the Nth second line L2 on the dielectric substrate 1 partially overlap. In some embodiments, the orthographic projections of the Nth first line L1 and the Nth second line L2 on the dielectric substrate 1 may completely overlap.

[0189] In an exemplary embodiment, two connection electrodes DJ are grouped together; the same connection electrode group is in contact with and connected to the same fifth trace L5; the same connection electrode group includes a first connection electrode DJ1 and a second connection electrode DJ2; the area where the first connection electrode DJ1 is located overlaps with the orthographic projection of the first end of the fourth trace L4 on the dielectric substrate 1; and the area where the second connection electrode DJ2 is located overlaps with the orthographic projection of the second end of the fourth trace L4 on the dielectric substrate 1; and the current flows in opposite directions in the first connection electrode DJ1 and the second connection electrode DJ2 in the same connection electrode group.

[0190] It should be noted that in this specification, the first and second ends of each trace are named according to the direction of current flow. For example, as shown in Figure 3, the current flows from the first end of the trace to the second end. The first and second ends of the first trace L1, the second trace L2, the third trace L3, the fourth trace L4, and the fifth trace L5 are all named according to this rule and will not be further described below.

[0191] In an exemplary embodiment, as shown in FIG3 , the orthographic projections of the first connection electrode DJ1 and the second connection electrode DJ2 in the same connection electrode group on the film layer where the fifth line L5 is located fall within the region where the same fifth line L5 is located.

[0192] It should be noted that, in this specification, the first connection electrode DJ1 and the second connection electrode DJ2 can be determined based on the projection positions of the first end and the second end of the fourth line L4 relative to the two connection electrodes DJ in the same connection electrode group; wherein, the connection electrode overlapping with the projection of the first end of the fourth line L4 is the first connection electrode DJ1, and the connection electrode overlapping with the projection of the second end of the fourth line L4 is the second connection electrode DJ2, and the first end and the second end of the fourth line L4 are related to the direction of current flow in the fourth line L4; when the direction of current flow in the fourth line L4 is opposite, the first connection electrode DJ1 and the second connection electrode DJ2 swap positions.

[0193] In at least one embodiment provided herein, in combination with FIG. 1 or FIG. 3 , the inductor structure further includes N fourth traces L4 arranged in the same row and N+1 fifth traces L5 arranged in the same row; the orthographic projections of the Nth fourth trace L4 and the N+1th fifth trace L5 on the dielectric substrate 1 overlap, and the current flows in the same direction.

[0194] Exemplarily, the number of the fifth lines L5 is greater than the number of the fourth lines L4 by 1.

[0195] Exemplarily, the orthographic projections of the first fourth line L4 and the second fifth line L5 on the dielectric substrate 1 overlap, and the current flows in the same direction; the orthographic projections of the second fourth line L4 and the third fifth line L5 on the dielectric substrate 1 overlap, and the current flows in the same direction; and the orthographic projections of the third fourth line L4 and the fourth fifth line L5 on the dielectric substrate 1 overlap, and the current flows in the same direction.

[0196] In the embodiment of the present application, as shown in FIG3 , the fourth trace L4 is referred to as the first fourth trace L4 , the second fourth trace L4 , the third fourth trace L4 , etc., starting from the left side of the inductor structure. Other traces such as the first trace L1 , the second trace L2 , and the fifth trace L5 are also sorted starting from the left side of the inductor structure.

[0197] In at least one embodiment provided in the present application, in combination with FIG1 or FIG3 , on the first surface B1, the second end of the first first line L1 (the direction indicated by the arrow is the second end) and the second end of the first second line L1 (the direction indicated by the arrow is the second end) are respectively electrically connected to the first end of the first fourth line L4 (the direction opposite to the arrow is the first end), and the first end of the second first line L1 (the direction opposite to the arrow is the first end) and the first end of the second second line L2 (the direction opposite to the arrow is the first end) are respectively electrically connected to the second end of the first fourth line L4 (the direction indicated by the arrow is the second end);

[0198] The second end of the Nth first routing line L1 and the second end of the Nth second routing line L2 are respectively electrically connected to the first end of the Nth fourth routing line L4, and the first end of the N+1th first routing line L1 and the first end of the N+1th second routing line L2 are respectively electrically connected to the second end of the Nth fourth routing line L4.

[0199] Exemplarily, when N=2, the second end of the second first routing L1 and the second end of the second second routing L2 are respectively electrically connected to the first end of the second fourth routing L4, and the first end of the third first routing L1 and the first end of the third second routing L2 are respectively electrically connected to the second end of the second fourth routing L4.

[0200] Exemplarily, when N=3, the second end of the third first routing L1 and the second end of the third second routing L2 are respectively electrically connected to the first end of the third fourth routing L4, and the first end of the fourth first routing L1 and the first end of the fourth second routing L2 are respectively electrically connected to the second end of the third fourth routing L4.

[0201] Exemplarily, when N=5, the second end of the 5th first routing line L1 and the second end of the 5th second routing line L2 are respectively electrically connected to the first end of the 5th fourth routing line L4, and the first end of the 6th first routing line L1 and the first end of the 6th second routing line L2 are respectively electrically connected to the second end of the 5th fourth routing line L4.

[0202] Exemplarily, when N=6, the second end of the 6th first routing line L1 and the second end of the 6th second routing line L2 are respectively electrically connected to the first end of the 6th fourth routing line L4, and the first end of the 7th first routing line L1 and the first end of the 7th second routing line L2 are respectively electrically connected to the second end of the 6th fourth routing line L4.

[0203] In at least one embodiment provided in the present application, in combination with Figure 1 or Figure 3, the inductor structure includes N+1 connecting electrode groups arranged in the same row, the first end of the third trace L3 (the direction opposite to the arrow is the first end) is electrically connected to the N+1 second connecting electrode DJ2, and the second end of the third trace L3 (the direction opposite to the arrow is the first end) is electrically connected to the first end of the first first trace L1 (the direction opposite to the arrow is the first end) and the first end of the first second trace L2 (the direction opposite to the arrow is the first end); the first end of the first first trace L1 and the first end of the first second trace L2 are electrically connected to the first second connecting electrode DJ2, respectively, and the first end of the first first trace L1 and the first end of the first second trace L2 are electrically connected to the second first connecting electrode DJ1, respectively; the first end of the Nth first trace L1 and the first end of the Nth second trace L2 are electrically connected to the Nth second connecting electrode DJ2, respectively, and the second end of the Nth first trace L1 and the second end of the Nth second trace L2 are electrically connected to the N+1th first connecting electrode DJ1, respectively.

[0204] Exemplarily, when N=2, the first end of the second first routing L1 and the first end of the second second routing L2 are respectively electrically connected to the second second connection electrode DJ2, and the second end of the second first routing L1 and the second end of the second second routing L2 are respectively electrically connected to the third first connection electrode DJ1.

[0205] Exemplarily, when N=3, the first end of the third first routing L1 and the first end of the third second routing L2 are respectively electrically connected to the third second connection electrode DJ2, and the second end of the third first routing L1 and the second end of the third second routing L2 are respectively electrically connected to the fourth first connection electrode DJ1.

[0206] Exemplarily, when N=5, the first end of the 5th first routing L1 and the first end of the 5th second routing L2 are respectively electrically connected to the 5th second connection electrode DJ2, and the second end of the 5th first routing L1 and the second end of the 5th second routing L2 are respectively electrically connected to the 6th first connection electrode DJ1.

[0207] In at least one embodiment provided in the present application, as shown in FIG1-FIG3 and FIG5-FIG6, the orthographic projection of the third trace L3 except the first end and the second end thereof on the dielectric substrate 1 does not overlap with the area where the connection electrode group is located.

[0208] Exemplarily, the rest of the third line L3 except the first end and the second end thereof may be referred to as the main portion of the third line L3 .

[0209] In some examples, the orthographic projection of the main portion of the third line L3 on the dielectric substrate 1 does not overlap with the orthographic projections of the first line L1 , the second line L2 , the fourth line L4 , and the fifth line L5 on the dielectric substrate 1 .

[0210] In the embodiment of the present application, by ensuring that the orthographic projection of the main portion of the third line L3 on the dielectric substrate 1 does not overlap with the orthographic projections of the first line L1, the second line L2, the fourth line L4, and the fifth line L5 on the dielectric substrate 1, the interference of the current in the third line L3 on the mutual inductance between the first line L1 and the second line L2 and the interference of the mutual inductance between the fourth line L4 and the fifth line L5 can be greatly reduced, thereby maximizing the mutual inductance in the inductor structure, further increasing the inductance value of the inductor structure, and improving the performance of the inductor structure. While the size of the inductor structure remains substantially unchanged, the application flexibility of the inductor structure is improved, and the application field of the inductor structure is expanded.

[0211] In at least one embodiment of the present application, as shown in Figures 7 to 9, the inductor structure includes N first traces L1 arranged in the same row and N second traces L2 arranged in the same row, where N is a positive integer and greater than or equal to 1. As shown in Figure 10, the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 overlap, and the current flows in the same direction. The direction indicated by the dotted arrows in Figures 7 and 8 may be the current flow direction, and Figure 9 is a right view of Figure 8.

[0212] It should be noted that, in order to clearly illustrate the positional relationship between the orthographic projections of the Nth first line L1 and the Nth second line L2 on the dielectric substrate 1, FIG10 shows an example in which the orthographic projections of the Nth first line L1 and the Nth second line L2 on the dielectric substrate 1 partially overlap. In some embodiments, the orthographic projections of the Nth first line L1 and the Nth second line L2 on the dielectric substrate 1 may completely overlap.

[0213] In an exemplary embodiment, as shown in Figures 7 and 8, two connection electrodes DJ are divided into a group, and the same connection electrode group is in contact with and connected to the same fifth trace L5. The same connection electrode group includes a first connection electrode DJ1 and a second connection electrode DJ2. The area where the first connection electrode DJ1 is located overlaps with the orthographic projection of the first end of the fourth trace L4 on the dielectric substrate 1, and the area where the second connection electrode DJ2 is located overlaps with the orthographic projection of the second end of the fourth trace L4 on the dielectric substrate 1. The currents of the first connection electrode DJ1 and the second connection electrode DJ2 in the same connection electrode group flow in opposite directions.

[0214] In at least one embodiment provided in the present application, as shown in FIG. 7 and FIG. 8 , the inductor structure further includes N+1 fourth traces L4 arranged in the same row and N+1 fifth traces L5 arranged in the same row; the orthographic projections of the Nth fourth trace L4 and the Nth fifth trace L5 on the dielectric substrate 1 overlap, and the current flows in the same direction.

[0215] In at least one embodiment provided in the present application, in combination with Figures 7 and 8, on the first surface B1, the second end of the first fourth routing L4 (the direction opposite to the arrow is the second end) is electrically connected to the first end of the first first routing L1 (the direction pointed by the arrow is the first end) and the first end of the first second routing L2 (the direction pointed by the arrow is the first end), the first end of the N+1th fourth routing L4 is electrically connected to the second end of the Nth first routing L1 and the second end of the Nth second routing L2, and the second end of the N+1th fourth routing L4 is electrically connected to the first end of the N+1th first routing L1 and the first end of the N+1th second routing L2.

[0216] Exemplarily, when N=3, the first end of the 4th fourth routing line L4 is electrically connected to the second end of the 3rd first routing line L1 and the second end of the 3rd second routing line L2, and the second end of the 4th fourth routing line L4 is electrically connected to the first end of the 4th first routing line L1 and the first end of the 4th second routing line L2.

[0217] Exemplarily, when N=4, the first end of the 5th fourth routing L4 is electrically connected to the second end of the 4th first routing L1 and the second end of the 4th second routing L2, respectively, and the second end of the 5th fourth routing L4 is electrically connected to the first end of the 5th first routing L1 and the first end of the 5th second routing L2, respectively.

[0218] Exemplarily, when N=5, the first end of the 6th fourth routing L4 is electrically connected to the second end of the 5th first routing L1 and the second end of the 5th second routing L2, respectively, and the second end of the 6th fourth routing L4 is electrically connected to the first end of the 6th first routing L1 and the first end of the 6th second routing L2, respectively.

[0219] In at least one embodiment provided in the present application, in combination with Figures 7 and 8, the inductor structure includes N+1 connecting electrode groups arranged in the same row, the first end of the third trace L3 is electrically connected to the N+1 second connecting electrode DJ2, and the second end of the third trace L3 is electrically connected to the first end of the first fourth trace L4.

[0220] In at least one embodiment provided in the present application, as shown in conjunction with FIG. 7 and FIG. 8 , the orthographic projections of each first line L1, each second line L2, each fourth line L4, and each fifth line L5 on the dielectric substrate 1 overlap with the orthographic projection of the third line L3 on the dielectric substrate 1 .

[0221] The orthographic projection of the third line L3 on the dielectric substrate 1 partially overlaps with the orthographic projections of the first lines L1 , the second lines L2 , the fourth lines L4 , and the fifth lines L5 on the dielectric substrate 1 .

[0222] In addition, as shown in FIG7 , FIG8 and FIG10 , the extending direction of the orthographic projection of the third line L3 on the dielectric substrate 1 intersects the extending directions of the orthographic projections of the first lines L1 , the second lines L2 , the fourth lines L4 and the fifth lines L5 on the dielectric substrate 1 .

[0223] In at least one embodiment provided in the present application, as shown in Figures 11, 12, and 14, the first conductive structure 6 includes a first first conductive sublayer D1-1, a third first conductive sublayer D1-3, and a fourth first conductive sublayer D1-4, which are sequentially arranged in a direction away from the dielectric substrate 1; Figure 14 is a right view of Figure 12.

[0224] As shown in Figures 12 and 14 , the first first conductive sublayer D1-1 includes a plurality of first traces L1 extending along a first direction F1 and arranged along a second direction F2, and the fourth first conductive sublayer D1-4 includes a plurality of second traces L2 extending along the first direction F1 and arranged along the second direction F2. The first direction F1 and the second direction F2 intersect. The orthographic projections of the first traces L1 and the second traces L2 on the dielectric substrate 1 at least partially overlap.

[0225] The third first conductive sublayer D1-3 includes a plurality of fourth traces L4 extending along the third direction F3 and arranged along the fourth direction F4. The second conductive sublayer D2 includes a plurality of fifth traces L5 extending along the third direction F3 and arranged along the fourth direction F4. The third direction F3 and the fourth direction F4 intersect. The orthographic projections of the fourth traces L4 and the fifth traces L5 on the dielectric substrate 1 at least partially overlap. The first direction F1 intersects the third direction F3.

[0226] In some examples, the second direction F2 can be substantially parallel to the fourth direction F4.

[0227] The materials of the first first conductive sub-layer D1-1, the third first conductive sub-layer D1-3 and the fourth first conductive sub-layer D1-4 can be referred to the above description and will not be repeated here.

[0228] Here, there is no limitation on whether the lengths and widths (also referred to as line widths, Width) of the first line L1 , the second line L2 , the fourth line L4 and the fifth line are the same.

[0229] In some embodiments, the first trace L1 and the second trace L2 have the same length.

[0230] In some embodiments, the third trace L4 and the fifth trace L5 have the same length.

[0231] In some examples, the first trace L1 and the second trace L2 have the same width.

[0232] In some examples, the third trace L4 and the fifth trace L5 have the same width.

[0233] Here, there is no limitation on whether the thicknesses of the first line L1 , the second line L2 , the third line L3 , the fourth line L4 and the fifth line are the same.

[0234] In some examples, thicknesses of at least portions of the first trace L1 , the second trace L2 , the third trace L3 , the fourth trace L4 , and the fifth trace are substantially the same.

[0235] In some examples, at least part of the first route L1, the second route L2, the third route L3, the fourth route L4, and the fifth route may include straight lines; or, at least part of the first route L1, the second route L2, the third route L3, the fourth route L4, and the fifth route may include arcs; or, at least part of the first route L1, the second route L2, the third route L3, the fourth route L4, and the fifth route may include broken line segments composed of straight line segments; or, at least part of the first route L1, the second route L2, the third route L3, the fourth route L4, and the fifth route may include a combination of straight lines and arcs.

[0236] In at least one embodiment provided herein, as shown in FIG. 11 , FIG. 12 , and FIG. 14 , the inductor structure includes N first traces L1 arranged in the same row, N second traces L2 arranged in the same row, N+1 fourth traces L4 arranged in the same row, and N+1 fifth traces L5 arranged in the same row; wherein N is a positive integer and is greater than or equal to 1;

[0237] Referring to the directions of the arrows marked in FIG11 and FIG12 (the directions of the arrows indicate the directions of current flow), the orthographic projections of the Nth first trace L1 and the Nth second trace L2 on the dielectric substrate 1 overlap, and the current flows in opposite directions. The orthographic projections of the Nth fourth trace L4 and the Nth fifth trace L5 on the dielectric substrate 1 overlap, and the current flows in opposite directions.

[0238] It should be noted that, in order to clearly illustrate the positional relationship between the orthographic projections of the Nth first line L1 and the Nth second line L2 on the dielectric substrate 1, FIG13 is drawn using the example of partial overlap of the orthographic projections of the Nth first line L1 and the Nth second line L2 on the dielectric substrate 1. In some embodiments, the orthographic projections of the Nth first line L1 and the Nth second line L2 on the dielectric substrate 1 may completely overlap.

[0239] The two connection electrodes are divided into a group, and the same connection electrode group is in contact with and connected to the same fifth trace L5. The same connection electrode group includes a first connection electrode DJ1 and a second connection electrode DJ2. The area where the first connection electrode DJ1 is located overlaps with the orthographic projection of the first end of the fourth trace L4 on the dielectric substrate 1, and the area where the second connection electrode DJ2 is located overlaps with the orthographic projection of the second end of the fourth trace L4 on the dielectric substrate 1. The currents of the first connection electrode DJ1 and the second connection electrode DJ2 in the same connection electrode group flow in opposite directions.

[0240] It should be noted that in this specification, the first and second ends of each trace are named according to the direction of current flow, with current flowing from the first end to the second end of the trace. The inductor structure shown in FIG12 differs from the inductor structures shown in FIG3 or FIG8 . Due to the change in current direction, the position of the first end of the fourth trace L4 changes. Therefore, compared to the inductor structures shown in FIG3 or FIG8 , the positions of the first connection electrode DJ1 and the second connection electrode DJ2 in the inductor structure shown in FIG12 are swapped.

[0241] In an exemplary embodiment, as shown in FIG12 , the orthographic projections of the first connection electrode DJ1 and the second connection electrode DJ2 in the same connection electrode group on the film layer where the fifth line L5 is located fall within the region where the same fifth line L5 is located.

[0242] In at least one embodiment provided in the present application, as shown in conjunction with FIG11 and FIG12 , the first first connection electrode DJ1 is electrically connected to the first end of the first fourth line L4 (in the direction opposite to the arrow) and the first end of the first first line L1 (in the direction opposite to the arrow), the second end of the first fourth line L4 (in the direction indicated by the arrow) is electrically connected to the first second connection electrode DJ2, the second end of the first first line L2 is electrically connected to the second second connection electrode DJ2 and the first end of the first second line L2, and the second end of the first second line L2 is electrically connected to the first end of the first first line L1 and the first end of the first fourth line L4.

[0243] The Nth first connecting electrode DJ1 is electrically connected to the first end of the Nth fourth routing L4 and the first end of the Nth first routing L1, respectively; the second end of the Nth fourth routing L4 is electrically connected to the Nth second connecting electrode DJ2, respectively; the second end of the Nth first routing L1 is electrically connected to the N+1th second connecting electrode DJ2 and the first end of the Nth second routing L2, respectively; the second end of the Nth second routing L2 is electrically connected to the first end of the Nth first routing L1 and the first end of the Nth fourth routing L4, respectively.

[0244] Exemplarily, when N=4, the 4th first connecting electrode DJ1 is electrically connected to the first end of the 4th fourth routing L4 and the first end of the 4th first routing L1, respectively, the second end of the 4th fourth routing L4 is electrically connected to the 4th second connecting electrode DJ2, and the second end of the 4th first routing L1 is electrically connected to the 5th second connecting electrode DJ2 and the first end of the 4th second routing L2, respectively; the second end of the 4th second routing L2 is electrically connected to the first end of the 4th first routing L1 and the first end of the 4th fourth routing L4, respectively.

[0245] Exemplarily, when N=5, the 5th first connecting electrode DJ1 is electrically connected to the first end of the 5th fourth routing L4 and the first end of the 5th first routing L1, respectively, the second end of the 5th fourth routing L4 is electrically connected to the 5th second connecting electrode DJ2, and the second end of the 5th first routing L1 is electrically connected to the 6th second connecting electrode DJ2 and the first end of the 5th second routing L2, respectively; the second end of the 5th second routing L2 is electrically connected to the first end of the 5th first routing L1 and the first end of the 5th fourth routing L4, respectively.

[0246] Exemplarily, when N=6, the 6th first connecting electrode DJ1 is electrically connected to the first end of the 6th fourth route L4 and the first end of the 6th first route L1, respectively, the second end of the 6th fourth route L4 is electrically connected to the 6th second connecting electrode DJ2, and the second end of the 6th first route L1 is electrically connected to the 7th second connecting electrode DJ2 and the first end of the 6th second route L2, respectively; the second end of the 6th second route L2 is electrically connected to the first end of the 6th first route L1 and the first end of the 6th fourth route L4, respectively.

[0247] In at least one embodiment provided in the present application, as shown in Figures 4 and 9, the inductor structure also includes a first insulating layer 2, a second insulating layer 3, a third insulating layer 4, a first protective layer 5 and a second protective layer 8; the first insulating layer 2 is located between the first first conductive sublayer D1-1 and the second first conductive sublayer D1-2, the second insulating layer 3 is located between the second first conductive sublayer D1-2 and the third first conductive sublayer D1-3, and the third insulating layer 4 is located between the third first conductive sublayer D1-3 and the fourth first conductive sublayer D1-4; the first protective layer 5 covers the fourth first conductive sublayer D1-4, and the second protective layer 8 covers the second conductive sublayer D2.

[0248] In at least one embodiment provided in the present application, as shown in Figure 14, the inductor structure also includes a first insulating layer 2, a third insulating layer 4, a first protective layer 5 and a second protective layer 8; the first insulating layer 2 is located between the first first conductive sublayer D1-1 and the third first conductive sublayer D1-3, and the third insulating layer 4 is located between the third first conductive sublayer D1-3 and the fourth first conductive sublayer D1-4; the first protective layer 5 covers the fourth first conductive sublayer D1-4, and the second protective layer 8 covers the second conductive sublayer D2.

[0249] The materials of the first insulating layer 2 , the second insulating layer 3 , the third insulating layer 4 , the first protective layer 5 and the second protective layer 8 are all insulating materials; wherein the insulating materials may include organic insulating materials or inorganic insulating materials.

[0250] For example, the organic insulating material may include photoresist, resin, for example, epoxy resin, polyimide, acrylic resin, etc.

[0251] Exemplarily, the inorganic insulating material may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0252] In the embodiments of the present application, description is made by taking as an example that the materials of the first insulating layer 2 , the second insulating layer 3 , the third insulating layer 4 , the first protective layer 5 and the second protective layer 8 are all organic materials.

[0253] In at least one embodiment provided in the present application, the thickness of the first conductive sublayer D1 and the second conductive sublayer D2 are both in the range of 1 μm to 10 μm.

[0254] Exemplarily, the thickness of the first conductive sublayer D1 and the second conductive sublayer D2 are both in the range of 1.5 μm to 7 μm, for example, the thickness may be 1.5 μm, 2 μm, 4 μm, 6.5 μm or 7 μm.

[0255] Here, there is no limitation on whether the thicknesses of the first conductive sublayer D1 and the second conductive sublayer D2 are the same. For example, the thicknesses can be set according to the material and conductivity requirements of the traces provided in the first conductive sublayer D1 and the second conductive sublayer D2.

[0256] In practical applications, when the materials of the first conductive sublayer D1 and the second conductive sublayer D2 both meet the conductivity requirements, the thicknesses of the first conductive sublayer D1 and the second conductive sublayer D2 can be set to be roughly the same to simplify the preparation process and reduce the difficulty of the preparation process.

[0257] In some examples, since the thickness range of the first conductive sublayer D1 and the second conductive sublayer D2 are both 1μm to 10μm, which is relatively thick, in order to improve the stability between two adjacent conductive film layers, the thickness of at least part of the insulating layer can be set to be greater than the thickness of the conductive sublayer.

[0258] For example, the thickness of the first insulating layer 2 is greater than or equal to the thickness of the first first conductive sub-layer D1 - 1 .

[0259] For example, the thickness of the second insulating layer 3 is greater than or equal to the thickness of the second first conductive sub-layer D1 - 2 .

[0260] For example, the thickness of the third insulating layer 4 is greater than or equal to the thickness of the third first conductive sub-layer D1 - 3 .

[0261] For example, the thickness of the first protection layer 5 is greater than or equal to the thickness of the fourth first conductive sub-layer D1 - 4 .

[0262] For example, the thickness of the second protection layer 8 is greater than or equal to the thickness of the second conductive sub-layer D2.

[0263] In at least one embodiment provided in the present application, the connecting electrode DJ comprises a metal material;

[0264] Alternatively, the connection electrode DJ includes a resin and a metal material covering the resin.

[0265] It should be noted that when the connecting via is filled with conductive material using an electroplating process, the conductive material is preferentially deposited on the sidewalls of the connecting via. This may result in incomplete filling of the conductive material at the center of the connecting via, resulting in a gap. In this case, a resin material is used to fill the gap to enhance the mechanical strength of the connecting electrode DJ and its support for other film layers. When the connecting electrode DJ comprises a resin and a metal material encapsulating the resin, the conductive region of the connecting electrode DJ on the side near the first surface B1 and / or the second surface B2 may have a planar shape, such as a circular or polygonal ring.

[0266] In at least one embodiment provided in the present application, at least one of the first route L1, the second route L2, the fourth route L4 and the fifth route L5 includes multiple sub-routes arranged in parallel, with a gap between two adjacent sub-routes, and the line width of each sub-route is approximately the same.

[0267] In an embodiment of the present application, by setting at least one of the first line L1, the second line L2, the fourth line L4 and the fifth line L5 to include multiple sub-lines arranged in parallel, and there is a gap between two adjacent sub-lines, the mutual inductance generated between the sub-lines of the first line L1, the second line L2, the fourth line L4 and the fifth line L5 can be further improved, thereby further improving the inductance density and inductance value of the inductance structure when the size of the inductance structure is fixed.

[0268] In at least one embodiment provided in the present application, the angle between the first direction F1 and the third direction F3 is an acute angle, so that the arrangement space of each trace can be minimized, thereby reducing the spatial size of the inductor structure.

[0269] In at least one embodiment provided in the present application, the third routing L3 includes a plurality of sub-routes arranged in parallel, with a gap between two adjacent sub-routes, and the line widths of the sub-routes are approximately the same. In this way, the mutual inductance generated between the sub-routes can be reduced, thereby further improving the inductance density and inductance value of the inductance structure when the size of the inductance structure is fixed.

[0270] In at least one embodiment provided in the present application, the line width of the third line L3 is smaller than the line widths of the first line L1, the second line L2, and the fourth line L4. In this way, the interference of the current in the third line L3 on the mutual inductance between the first line L1 and the second line L2, and the mutual inductance between the fourth line L4 and the fifth line L5 can be greatly reduced, thereby further improving the inductance density and inductance value of the inductance structure when the size of the inductance structure is fixed.

[0271] An embodiment of the present application provides a filter, as shown in FIG15 , comprising at least one inductor structure L as described above and at least one capacitor C; wherein the insulating medium in capacitor C is labeled JZ. Furthermore, the filter includes solder balls or conductive pillars 9, which are used to electrically connect the filter to other components in the RF module.

[0272] The filter provided in the embodiments of the present application includes a 3D inductor structure. By configuring this inductor structure, on the one hand, one of the first conductive structure 6 and the second conductive structure 7 in the inductor structure includes multiple sublayers, and the other includes at least one sublayer, thereby increasing the number of conductive layers constituting the wire (coil), thereby extending the effective length of the coil forming the inductor structure, thereby increasing the inductance density of the inductor structure and improving the inductance value. On the other hand, the orthographic projections of two of the sublayers in the first conductive structure 6 and the second conductive structure 7 in the inductor structure on the dielectric substrate 1 at least partially overlap. When the currents of the two sublayers flow in the same direction, the mutual inductance of the inductor structure can be effectively increased, further increasing the inductance value of the inductor structure and improving the performance of the inductor structure. While the size of the inductor structure remains essentially unchanged, the application flexibility of the inductor structure is improved, and the application field of the inductor structure is expanded.

[0273] An embodiment of the present application provides a packaging substrate, comprising at least one inductor structure L as described above.

[0274] The package substrate provided in the embodiments of the present application includes a 3D inductor structure. By configuring this inductor structure, on the one hand, one of the first conductive structure 6 and the second conductive structure 7 in the inductor structure includes at least three sublayers, and the other includes at least one sublayer (for example, as shown in Figures 1 and 4, the first conductive structure 6 includes sublayers D1-1, D1-2, D1-3, and D1-4; the second conductive structure 7 includes sublayer D2). This increases the number of conductive layers constituting the wire (coil), thereby extending the effective length of the coil forming the inductor structure, thereby increasing the inductance density of the inductor structure and improving the inductance value. On the other hand, the orthographic projections of two of the sublayers in the first conductive structure 6 and the second conductive structure 7 in the inductor structure on the dielectric substrate 1 at least partially overlap. When the currents flowing in the two structures are in the same direction, the mutual inductance of the inductor structure can be effectively increased, further increasing the inductance value of the inductor structure and improving the performance of the inductor structure. While the size of the inductor structure remains essentially unchanged, the application flexibility of the inductor structure is improved, and the application field of the inductor structure is expanded.

[0275] The embodiment of the present application provides a method for preparing an inductor structure, and the method is described in detail as follows:

[0276] S01. Select a substrate (dielectric substrate 1) as shown in FIG16A , and make through holes (connection vias Via) at reserved holes of the substrate to obtain a structure as shown in FIG16B .

[0277] Illustratively, the thickness of the dielectric substrate 1 is 0.2-0.5 mm.

[0278] Exemplarily, the dielectric substrate 1 may be a glass substrate, a silicon-based substrate, a ceramic substrate, or the like.

[0279] For example, the diameter of the connecting via hole can be 30-100 μm, and the cross-sectional shape of the hole can be columnar or hourglass-shaped according to the through-hole technology.

[0280] S02 . Perform metal filling in the connection via hole to obtain the connection electrode DJ as shown in FIG16C .

[0281] In some embodiments, the metal connection in the hole can be achieved by injecting copper metal into the through-hole through electroplating technology to achieve conduction of the circuit in the hole; it should be noted that when the conductive material is filled in the connecting via by the electroplating process, the conductive material is preferentially deposited on the side wall of the connecting via. There may be incomplete filling of the conductive material and gaps in the center of the connecting via. At this time, the gap is filled with resin material to improve the mechanical strength of the connecting electrode DJ and the support for other film layers.

[0282] S03 . Prepare a conductive structure on the second surface B2 of the dielectric substrate 1 to obtain a second conductive structure 7 as shown in FIG16D . The second conductive structure 7 includes a fifth trace L5 .

[0283] S04 , forming a second protective layer 8 as shown in FIG16D , wherein the second protective layer 8 covers the second conductive structure 7 .

[0284] Exemplarily, the thickness of the second protective layer 8 is greater than or equal to 2 μm.

[0285] S05. On the first surface B1, the first first conductive sub-layer D1-1 (including the first trace L1) and the first insulating layer 2 as shown in Figure 16E, the second first conductive sub-layer D1-2 (including the third trace L3) and the second insulating layer 3 as shown in Figure 16F, the third first conductive sub-layer D1-3 (including the fourth trace L4) and the third insulating layer 4 as shown in Figure 16G, the fourth first conductive sub-layer D1-4 (including the second trace L2) and the first protective layer 5 as shown in Figure 16H are formed in sequence.

[0286] Among them, the first first conductive sublayer D1-1 (including the first trace L1), the second first conductive sublayer D1-2 (including the third trace L3), the third first conductive sublayer D1-3 (including the fourth trace L4), and the fourth first conductive sublayer D1-4 (including the second trace L2) can all be prepared by electroplating process. Specifically, each patterned first conductive sublayer D1 can be formed through the processes of electroplating film formation, photoresist coating, exposure and etching.

[0287] It should be noted that only the preparation process of the structure related to the invention is introduced here. The introduction of the specific components and materials of the inductor structure can be referred to the description in the previous article and will not be repeated here.

[0288] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An inductor structure, wherein: include: A dielectric substrate, wherein the dielectric substrate has a plurality of connection vias extending through the dielectric substrate along the thickness thereof, wherein connection electrodes are disposed in the connection vias, and the dielectric substrate further comprises a first surface and a second surface disposed opposite to each other along the thickness thereof; A first conductive structure, disposed on the first surface; A second conductive structure is disposed on the second surface; The first conductive structure and the second conductive structure are electrically connected through the connecting electrode to form a coil of the inductor structure; one of the first conductive structure and the second conductive structure includes at least three sublayers, and the other includes at least one sublayer; orthographic projections of two of the sublayers in the first conductive structure and the second conductive structure on the dielectric substrate at least partially overlap, and current flow directions are substantially parallel.

2. The inductor structure according to claim 1, wherein: The sublayer in the first conductive structure is called a first conductive sublayer, and the sublayer in the second conductive structure is called a second conductive sublayer; Wherein, the first conductive structure includes at least three first conductive sub-layers, and the second conductive structure includes at least three second conductive sub-layers; Alternatively, the first conductive structure includes at least three first conductive sub-layers, and the second conductive structure includes one second conductive sub-layer.

3. The inductor structure according to claim 2, wherein: Orthographic projections of at least two of the first conductive sublayers on the dielectric substrate at least partially overlap, and current flow directions of the two layers are parallel.

4. The inductor structure according to claim 2, wherein: An orthographic projection of at least one of the first conductive sublayers on the dielectric substrate at least partially overlaps with an orthographic projection of the second conductive sublayer on the dielectric substrate, and current flow directions of the two are parallel.

5. The inductor structure according to claim 2, wherein: In the case where the first conductive structure includes at least three first conductive sub-layers and the second conductive structure includes one second conductive sub-layer, The first conductive structure includes an even number of the first conductive sublayers, at least two of the first conductive sublayers The orthographic projections of a conductive sublayer on the dielectric substrate at least partially overlap, and the current flow directions of the two are the same.

6. The inductor structure according to claim 5, wherein: An orthographic projection of at least one of the first conductive sublayers on the dielectric substrate at least partially overlaps with an orthographic projection of the second conductive sublayer on the dielectric substrate, and current flows in the two layers are in the same direction.

7. The inductor structure according to claim 2, wherein: In the case where the first conductive structure includes at least three first conductive sub-layers and the second conductive structure includes one second conductive sub-layer, The first conductive structure includes an odd number of the first conductive sub-layers, and the orthographic projections of at least two of the first conductive sub-layers on the dielectric substrate at least partially overlap, and the current flows in the two sub-layers in opposite directions.

8. The inductor structure according to claim 7, wherein: An orthographic projection of at least one of the first conductive sublayers on the dielectric substrate at least partially overlaps with an orthographic projection of the second conductive sublayer on the dielectric substrate, and current flows in the two layers are in opposite directions.

9. The inductor structure according to claim 5 or 6, wherein: The first conductive structure comprises a first first conductive sublayer, a second first conductive sublayer, a third first conductive sublayer and a fourth first conductive sublayer which are sequentially arranged in a direction away from the dielectric substrate; The first first conductive sublayer includes a plurality of first traces extending along the first direction and arranged along the second direction, and the fourth first conductive sublayer includes a plurality of second traces extending along the first direction and arranged along the second direction; the first direction and the second direction intersect; and the orthographic projections of the first traces and the second traces on the dielectric substrate at least partially overlap; The second first conductive sublayer includes a third routing line, the third first conductive sublayer includes a plurality of fourth routing lines extending along a third direction and arranged along a fourth direction, and the second conductive sublayer includes a plurality of fifth routing lines extending along the third direction and arranged along the fourth direction; the third direction and the fourth direction intersect; the orthographic projections of the fourth routing line and the fifth routing line on the dielectric substrate at least partially overlap; the first direction and the third direction intersect.

10. The inductor structure according to claim 9, wherein: The inductor structure includes N first routing lines arranged in the same row and N second routing lines arranged in the same row, wherein N is a positive integer and N is greater than or equal to 1; the orthographic projections of the Nth first routing line and the Nth second routing line on the dielectric substrate overlap, and the current flows in the same direction; The two connection electrodes are divided into a group, and the same connection electrode group is in contact with and connected to the same fifth routing line; the same connection electrode group includes a first connection electrode and a second connection electrode, and the area where the first connection electrode is located overlaps with the orthographic projection of the first end of the fourth routing line on the dielectric substrate, and the area where the second connection electrode is located overlaps with the orthographic projection of the second end of the fourth routing line on the dielectric substrate; the current flow directions of the first connection electrode and the second connection electrode in the same connection electrode group are opposite.

11. The inductor structure according to claim 10, wherein: The inductor structure further includes N fourth routing lines arranged in the same row and N+1 fifth routing lines arranged in the same row; the orthographic projections of the Nth fourth routing line and the N+1th fifth routing line on the dielectric substrate overlap, and the current flows in the same direction.

12. The inductor structure according to claim 11, wherein: On the first surface, the second end of the first first routing line and the second end of the first second routing line are respectively electrically connected to the first end of the first fourth routing line, and the first end of the second first routing line and the first end of the second second routing line are respectively electrically connected to the second end of the first fourth routing line; The second end of the Nth first routing line and the second end of the Nth second routing line are respectively electrically connected to the first end of the Nth fourth routing line, and the first end of the N+1th first routing line and the first end of the N+1th second routing line are respectively electrically connected to the second end of the Nth fourth routing line.

13. The inductor structure according to claim 12, wherein: The inductor structure includes N+1 connecting electrode groups arranged in the same row, the first end of the third wiring is electrically connected to the N+1th second connecting electrode, and the second end of the third wiring is electrically connected to the first end of the first first wiring and the first end of the first second wiring respectively; A first end of the first first wiring and a first end of the second second wiring are respectively The first end of the Nth first wiring and the first end of the Nth second wiring are respectively electrically connected to the first second connection electrode, the first end of the first first wiring and the first end of the first second wiring are respectively electrically connected to the second first connection electrode; the first end of the Nth first wiring and the first end of the Nth second wiring are respectively electrically connected to the Nth second connection electrode, and the second end of the Nth first wiring and the second end of the Nth second wiring are respectively electrically connected to the N+1th first connection electrode.

14. The inductor structure according to claim 13, wherein: The orthographic projection of the other regions of the third wiring except the first end and the second end thereof on the dielectric substrate does not overlap with the region where the connecting electrode group is located.

15. The inductor structure according to claim 10, wherein: The inductor structure further includes N+1 fourth wirings arranged in the same row and N+1 fifth wirings arranged in the same row; The orthographic projections of the Nth fourth routing line and the Nth fifth routing line on the dielectric substrate overlap, and the current flows in the same direction.

16. The inductor structure according to claim 15, wherein: On the first surface, the second end of the first fourth routing is electrically connected to the first end of the first first routing and the first end of the first second routing, the first end of the N+1th fourth routing is electrically connected to the second end of the Nth first routing and the second end of the Nth second routing, and the second end of the N+1th fourth routing is electrically connected to the first end of the N+1th first routing and the first end of the N+1th second routing.

17. The inductor structure according to claim 16, wherein: The inductor structure includes N+1 connecting electrode groups arranged in the same row, the first end of the third wiring is electrically connected to the N+1th second connecting electrode, and the second end of the third wiring is electrically connected to the first end of the first fourth wiring.

18. The inductor structure according to claim 17, wherein: The orthographic projections of each of the first routing lines, each of the second routing lines, each of the fourth routing lines, and each of the fifth routing lines on the dielectric substrate overlap with the orthographic projections of the third routing line on the dielectric substrate.

19. The inductor structure according to claim 7 or 8, wherein: The first conductive structure comprises a first first conductive sublayer, a third first conductive sublayer and a fourth first conductive sublayer which are sequentially arranged in a direction away from the dielectric substrate; The first first conductive sublayer includes a plurality of first traces extending along a first direction and arranged along a second direction, and the fourth first conductive sublayer includes a plurality of second traces extending along the first direction and arranged along the second direction; the first direction and the second direction intersect; and the orthographic projections of the first traces and the second traces on the dielectric substrate at least partially overlap; The third first conductive sublayer includes a plurality of fourth routing lines extending along a third direction and arranged along a fourth direction, and the second conductive sublayer includes a plurality of fifth routing lines extending along the third direction and arranged along the fourth direction; the third direction and the fourth direction intersect; the orthographic projections of the fourth routing lines and the fifth routing lines on the dielectric substrate at least partially overlap; the first direction and the third direction intersect.

20. The inductor structure according to claim 19, wherein: The inductor structure includes N first routing lines arranged in the same row, N second routing lines arranged in the same row, N+1 fourth routing lines arranged in the same row, and N+1 fifth routing lines arranged in the same row; wherein N is a positive integer, and N is greater than or equal to 1; The orthographic projections of the Nth first routing line and the Nth second routing line on the dielectric substrate overlap, and the current flows in opposite directions; the orthographic projections of the Nth fourth routing line and the Nth fifth routing line on the dielectric substrate overlap, and the current flows in opposite directions; The two connection electrodes are divided into a group, and the same connection electrode group is in contact with and connected to the same fifth routing line; the same connection electrode group includes a first connection electrode and a second connection electrode, and the area where the first connection electrode is located overlaps with the orthographic projection of the first end of the fourth routing line on the dielectric substrate, and the area where the second connection electrode is located overlaps with the orthographic projection of the second end of the fourth routing line on the dielectric substrate; the current flow directions of the first connection electrode and the second connection electrode in the same connection electrode group are opposite.

21. The inductor structure according to claim 20, wherein: The first first connection electrode is electrically connected to the first end of the first fourth routing line and the first end of the first first routing line respectively, the second end of the first fourth routing line is electrically connected to the first second connection electrode, the second end of the first first routing line is electrically connected to the second second connection electrode and the first end of the first second routing line respectively; the second end of the first second routing line is electrically connected to the first end of the first first routing line and the first end of the first fourth routing line respectively; The Nth first connecting electrode is electrically connected to the first end of the Nth fourth routing and the first end of the Nth first routing, respectively; the second end of the Nth fourth routing is electrically connected to the Nth second connecting electrode, respectively; the second end of the Nth first routing is electrically connected to the first end of the N+1th second connecting electrode and the first end of the Nth second routing, respectively; the second end of the Nth second routing is electrically connected to the first end of the Nth first routing and the first end of the Nth fourth routing, respectively.

22. The inductor structure according to any one of claims 10 to 18, wherein: The inductor structure further includes a first insulating layer, a second insulating layer, a third insulating layer, a first protective layer and a second protective layer; The first insulating layer is located between the first first conductive sublayer and the second first conductive sublayer, the second insulating layer is located between the second first conductive sublayer and the third first conductive sublayer, and the third insulating layer is located between the third first conductive sublayer and the fourth first conductive sublayer; The first protective layer covers the fourth first conductive sublayer, and the second protective layer covers the second conductive sublayer.

23. The inductor structure according to claim 20 or 21, wherein: The inductor structure further includes a first insulating layer, a third insulating layer, a first protective layer and a second protective layer; The first insulating layer is located between the first first conductive sublayer and the third first conductive sublayer, and the third insulating layer is located between the third first conductive sublayer and the fourth first conductive sublayer; The first protective layer covers the fourth first conductive sublayer, and the second protective layer covers the second conductive sublayer.

24. The inductor structure according to any one of claims 2 to 8, 10 to 18, 20 to 21, wherein: The thickness of the first conductive sublayer and the second conductive sublayer are both in the range of 1 μm to 10 μm.

25. The inductor structure according to any one of claims 10 to 18, 20 to 21, wherein: The connecting electrode comprises a metal material; Alternatively, the connection electrode includes resin and a metal material covering the resin.

26. The inductor structure according to any one of claims 10 to 18, 20 to 21, wherein: At least one of the first routing line, the second routing line, the fourth routing line and the fifth routing line includes a plurality of sub-routing lines arranged in parallel, a gap is provided between two adjacent sub-routing lines, and the line widths of the sub-routing lines are substantially the same.

27. The inductor structure according to claim 9, wherein: The angle between the first direction and the third direction is an acute angle.

28. The inductor structure according to claim 9, wherein: The third routing line includes a plurality of sub-routing lines arranged in parallel, a gap is provided between two adjacent sub-routing lines, and the line widths of the sub-routing lines are substantially the same.

29. The inductor structure according to claim 9, wherein: The line width of the third routing line is smaller than the line widths of the first routing line, the second routing line, and the fourth routing line.

30. A filter, wherein: The method comprises at least one inductive structure according to any one of claims 1 to 29 and at least one capacitor.

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