Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of suppressing a decrease in strength against external stress even when the multilayer ceramic capacitor is thinned. A laminated ceramic capacitor (1) is provided with: a laminated body (10) in which a plurality of dielectric layers (20) and a plurality of internal electrode layers (30), each of which includes a ceramic material, are laminated; a plurality of external electrodes (40) disposed on at least the second main surface (TS2) of the laminate (10); and a stress suppression film (50) that suppresses stress applied to the laminate (10) and the plurality of external electrodes (40). The stress suppression film (50) is made of an insulating material and extends along the first main surface (TS1) and both end surfaces (LS1, LS2), or extends along the first main surface (TS1) and both side surfaces so as to cover the laminate (10) and the plurality of external electrodes (40). The end portion of the stress suppression film (50) protrudes further toward the second main surface (TS2) than the outermost surface of the plurality of external electrodes (40).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] A laminated ceramic capacitor having a laminated body in which a plurality of dielectric layers including ceramic materials and a plurality of internal electrode layers are laminated, and external electrodes arranged on end faces or side faces of the laminated body is known. Such a laminated ceramic capacitor is required to be further miniaturized and thinned (for example, see Patent Document 1).

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-42110 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] When a laminated ceramic capacitor is thinned, the strength of the laminate, especially the ceramic layer, is reduced, and the laminated ceramic capacitor may be damaged due to the stress from the mounter during installation. For example, cracks may occur in the ceramic layer of the laminate. If the cracks generated in the ceramic layer progress to the internal electrode layer, for example, water may penetrate the cracks, and the insulation of the laminated ceramic capacitor may be reduced.

[0008] An object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing a decrease in strength against external stress even when the capacitor is reduced in thickness.

[0009] Means used to solve problems

[0010] The multilayer ceramic capacitor of the present invention comprises: a stacked body, in which a plurality of dielectric layers and a plurality of internal electrode layers containing ceramic materials are stacked, the stacked body having a first main surface and a second main surface opposite to each other in a stacking direction, two side surfaces opposite to each other in a width direction intersecting the stacking direction, and two end surfaces opposite to each other in a length direction intersecting the stacking direction and the width direction; a plurality of external electrodes arranged on at least the second main surface of the stacked body; and a stress suppression film for suppressing stress applied to the stacked body and the plurality of external electrodes. The stress suppression film is made of an insulating material and extends along the first main surface and the two end surfaces, or along the first main surface and the two side surfaces so as to cover the stacked body and the plurality of external electrodes. The end of the stress suppression film protrudes further than the outermost surface of the plurality of external electrodes on the second main surface side.

[0011] Effects of the Invention

[0012] According to the present invention, even if a multilayer ceramic capacitor is reduced in thickness, a decrease in strength against external stress can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view showing a multilayer ceramic capacitor according to the present embodiment.

[0014] Figure 2 yes Figure 1 This is a cross-sectional view taken along line II-II (LT cross section) of the multilayer ceramic capacitor shown.

[0015] Figure 3 yes Figure 1 A cross-sectional view (WT cross section) taken along line III-III of the multilayer ceramic capacitor shown.

[0016] Figure 4 It is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment.

[0017] Figure 5 yes Figure 4 The VV line cross-sectional view (LT cross-sectional view) of the multilayer ceramic capacitor shown.

[0018] Figure 6 yes Figure 4 A cross-sectional view (WT cross section) taken along line VI-VI of the multilayer ceramic capacitor shown.

[0019] Figure 7 It is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment.

[0020] Figure 8 yes Figure 7 A cross-sectional view taken along line VIII-VIII (LT cross section) of the multilayer ceramic capacitor shown.

[0021] Fig. 9 yes Figure 7 This is a cross-sectional view (WT cross section) taken along line IX-IX of the multilayer ceramic capacitor shown.

[0022] Fig.10 It is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment.

[0023] Fig.11 It is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment.

[0024] Fig.12 It is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, an example of an embodiment of the present invention will be described with reference to the accompanying drawings. In addition, in each of the drawings, the same reference numerals are given to the same or corresponding parts.

[0026] <Multilayer Ceramic Capacitors>

[0027] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to the present embodiment. Figure 2 yes Figure 1 The II-II line cross-sectional view of the multilayer ceramic capacitor shown in FIG. Figure 3 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line III-III shown in FIG. Figure 1 to Figure 3 The illustrated multilayer ceramic capacitor 1 includes a multilayer body 10 , an external electrode 40 , and a stress suppression film 50 . The external electrode 40 includes a first external electrode 41 and a second external electrode 42 .

[0028] exist Figure 1 to Figure 3 The XYZ orthogonal coordinate system is shown in the drawings described later. The X direction is the length direction L of the laminated ceramic capacitor 1 and the laminated body 10, the Y direction is the width direction W of the laminated ceramic capacitor 1 and the laminated body 10, and the Z direction is the stacking direction T of the laminated ceramic capacitor 1 and the laminated body 10. Thus, Figure 2 The section shown is also called the LT section. Figure 3 The cross section shown is also referred to as the WT cross section.

[0029] In addition, the longitudinal direction L, the width direction W, and the stacking direction T are not necessarily orthogonal to each other, and may be intersecting to each other.

[0030] The stacked body 10 has a substantially rectangular parallelepiped shape and has first and second main surfaces TS1 and TS2 facing each other in the stacking direction T, first and second side surfaces WS1 and WS2 facing each other in the width direction W, and first and second end surfaces LS1 and LS2 facing each other in the longitudinal direction L.

[0031] The corners and ridges of the laminate 10 are preferably rounded. The corners are the portions where three surfaces of the laminate 10 intersect, and the ridges are the portions where two surfaces of the laminate 10 intersect.

[0032] like Figure 2 as well as Figure 3 As shown, the laminate 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 laminated in a lamination direction T. In addition, the laminate 10 includes an inner layer portion 100 in the lamination direction T, and a first outer layer portion 101 and a second outer layer portion 102 disposed to sandwich the inner layer portion 100 .

[0033] The inner layer portion 100 includes a part of the plurality of dielectric layers 20 and the plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are disposed opposite to each other via the dielectric layer 20. The inner layer portion 100 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0034] The first outer layer portion 101 is arranged on the first main surface TS1 side of the stacked body 10, and the second outer layer portion 102 is arranged on the second main surface TS2 side of the stacked body 10. More specifically, the first outer layer portion 101 is arranged between the internal electrode layer 30 closest to the first main surface TS1 among the plurality of internal electrode layers 30 and the first main surface TS1, and the second outer layer portion 102 is arranged between the internal electrode layer 30 closest to the second main surface TS2 among the plurality of internal electrode layers 30 and the second main surface TS2. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, and each include a portion of the plurality of dielectric layers 20 other than a portion used for the inner layer portion 100. The first outer layer portion 101 and the second outer layer portion 102 are portions that function as protective layers for the inner layer portion 100.

[0035] As the material of the dielectric layer 20, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component can be used. In addition, as the material of the dielectric layer 20, Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds can be added as auxiliary components.

[0036] More specifically, the dielectric layer 20 includes a plurality of dielectric particles. The dielectric particles are barium titanate-based ceramics such as perovskite compounds containing Ba and Ti. The dielectric particles may also contain at least one of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y as a minor component.

[0037] The thickness of the dielectric layer 20 is not particularly limited, and may be, for example, 0.30 μm or more and 5.0 μm or less. The number of dielectric layers 20 is not particularly limited, and may be, for example, 5 or more and 2000 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer and the number of dielectric layers in the outer layer.

[0038] like Figure 2 as well as Figure 3 As shown, the plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the stacking direction T of the stacked body 10.

[0039] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312 , and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322 .

[0040] The opposing electrode portion 311 and the opposing electrode portion 321 are opposed to each other via the dielectric layer 20 in the stacking direction T of the stacked body 10. The shapes of the opposing electrode portion 311 and the opposing electrode portion 321 are not particularly limited, and may be, for example, substantially rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are portions (effective regions) that generate electrostatic capacitance and substantially function as capacitors.

[0041] The lead electrode portion 312 extends from the opposing electrode portion 311 toward the first end surface LS1 of the stacked body 10 and is exposed at the first end surface LS1. The lead electrode portion 322 extends from the opposing electrode portion 321 toward the second end surface LS2 of the stacked body 10 and is exposed at the second end surface LS2. The shapes of the lead electrode portions 312 and 322 are not particularly limited and may be, for example, substantially rectangular.

[0042] Thus, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap exists between the first internal electrode layer 31 and the second end surface LS2 of the stack 10, that is, the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap exists between the second internal electrode layer 32 and the first end surface LS1 of the stack 10, that is, the first external electrode 41.

[0043] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. In addition, the first internal electrode layer 31 and the second internal electrode layer 32 may contain at least one selected from metals such as Cu, Ag, Pd or Au, or alloys containing at least one of these metals such as Ag-Pd alloy as a main component, and may also contain the above at least one as a component other than the main component. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may also contain particles of a dielectric having the same composition system as the ceramic contained in the dielectric layer 20 as a component other than the main component. In addition, in this specification, the so-called main component metal is defined as the metal component with the highest weight %.

[0044] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, and may be, for example, 0.30 μm to 1.0 μm. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, and may be, for example, 5 to 2000.

[0045] like Figure 3As shown, the stack 10 has an electrode opposing portion W30 in which the internal electrode layer 30 is opposed in the width direction W, and a first side gap portion WG1 and a second side gap portion WG2 which are configured to sandwich the electrode opposing portion W30. The first side gap portion WG1 is located between the electrode opposing portion W30 and the first side surface WS1, and the second side gap portion WG2 is located between the electrode opposing portion W30 and the second side surface WS2. More specifically, the first side gap portion WG1 is located between the end of the first side surface WS1 side of the internal electrode layer 30 and the first side surface WS1, and the second side gap portion WG2 is located between the end of the second side surface WS2 side of the internal electrode layer 30 and the second side surface WS2. The first side gap portion WG1 and the second side gap portion WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side gap portion WG1 and the second side gap portion WG2 are portions that function as protective layers of the internal electrode layer 30. In addition, the first side gap portion WG1 and the second side gap portion WG2 are also referred to as W gaps.

[0046] like Figure 2 As shown, the stacked body 10 has an electrode opposing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 are opposed to each other in the longitudinal direction L, a first end gap portion LG1, and a second end gap portion LG2. The first end gap portion LG1 is located between the electrode opposing portion L30 and the first end surface LS1, and the second end gap portion LG2 is located between the electrode opposing portion L30 and the second end surface LS2. More specifically, the first end gap portion LG1 is located between the end of the second internal electrode layer 32 on the first end surface LS1 side and the first end surface LS1, and the second end gap portion LG2 is located between the end of the first internal electrode layer 31 on the second end surface LS2 side and the second end surface LS2. The first end gap portion LG1 does not include the second internal electrode layer 32 but includes the first internal electrode layer 31 and the dielectric layer 20, and the second end gap portion LG2 does not include the first internal electrode layer 31 but includes the second internal electrode layer 32 and the dielectric layer 20. The first end gap LG1 is a portion that functions as an electrode portion extending from the first internal electrode layer 31 to the first end surface LS1, and the second end gap LG2 is a portion that functions as an electrode portion extending from the second internal electrode layer 32 to the second end surface LS2. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0047] In addition, the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32 are located at the electrode opposing portion L30. In addition, the lead electrode portion 312 of the first internal electrode layer 31 is located at the first end gap portion LG1, and the lead electrode portion 322 of the second internal electrode layer 32 is located at the second end gap portion LG2.

[0048] The dimensions of the stacked body 10 are not particularly limited, and for example, the length in the longitudinal direction L may be 0.05 mm to 1.00 mm, the width in the width direction W may be 0.10 mm to 0.50 mm, and the thickness in the stacking direction T may be 0.10 mm to 0.50 mm.

[0049] The dimensions of the multilayer ceramic capacitor 1 including the external electrode 40 described later are not particularly limited, and may be, for example, 0.05 mm to 1.00 mm in length direction L, 0.10 mm to 0.50 mm in width direction W, and 0.10 mm to 0.50 mm in thickness in stacking direction T.

[0050] In addition, as a method for measuring the thickness of the dielectric layer 20 and the internal electrode layer 30, for example, a method of observing the LT cross section near the center in the width direction of the laminate exposed by grinding using a scanning electron microscope can be cited. In addition, each value may be an average value of the measured values ​​at multiple locations in the longitudinal direction, and further, may be an average value of the measured values ​​at multiple locations in the stacking direction.

[0051] Similarly, as a method for measuring the thickness of the laminate 10 or the thickness of the laminated ceramic capacitor 1, for example, a method of observing the LT cross section near the center in the width direction of the laminate exposed by grinding, or the WT cross section near the center in the length direction of the laminate or the laminated ceramic capacitor exposed by grinding using a scanning electron microscope can be cited. In addition, each value may be an average value of the measured values ​​at multiple locations in the length direction or the width direction.

[0052] Similarly, as a method for measuring the length of the laminated body 10 or the length of the laminated ceramic capacitor 1, for example, a method of observing the LT cross section near the center in the width direction of the laminated body or the laminated ceramic capacitor exposed by grinding using a scanning electron microscope can be cited. In addition, each value may be an average value of the measured values ​​at multiple locations in the stacking direction.

[0053] Similarly, as a method for measuring the width of the stacked body 10 or the width of the multilayer ceramic capacitor 1, for example, a method of observing the WT cross section near the center of the length direction of the stacked body or the multilayer ceramic capacitor exposed by grinding using a scanning electron microscope can be cited. In addition, each value may be an average value of the measured values ​​at multiple locations in the stacking direction.

[0054] The external electrode 40 includes a first external electrode 41 and a second external electrode 42 .

[0055] The first external electrode 41 is arranged on at least the second main surface TS2 of the stacked body 10, and more specifically, is arranged on a portion of the second main surface TS2 on the first end surface LS1 side. Figure 1 to Figure 3 In the example, the first external electrode 41 is also arranged on the first end surface LS1 of the stack 10 and is connected to the first internal electrode layer 31. That is, the first external electrode 41 is L-shaped in the LT cross section and is arranged along a portion of the first end surface LS1 side of the second main surface TS2 of the stack 10 and the first end surface LS1. Figure 1 to Figure 3 In the example, the first external electrode 41 is not arranged on the first main surface TS1 and the two side surfaces WS1 and WS2.

[0056] The second external electrode 42 is arranged on at least the second main surface TS2 of the stacked body 10, and more specifically, is arranged on a portion of the second main surface TS2 on the second end surface LS2 side. Figure 1 to Figure 3 In the example, the second external electrode 42 is also arranged on the second end surface LS2 of the stack 10 and connected to the second internal electrode layer 32. That is, the second external electrode 42 is L-shaped and arranged along a portion of the second end surface LS2 side of the second main surface TS2 of the stack 10 and the second end surface LS2. Figure 1 to Figure 3 In the example, the second external electrode 42 is not arranged on the first main surface TS1 and the two side surfaces WS1 and WS2.

[0057] The first external electrode 41 includes a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 includes a second base electrode layer 425 and a second plating layer 426. Alternatively, the first external electrode 41 may be composed of only the first plating layer 416, and the second external electrode 42 may be composed of only the second plating layer 426.

[0058] The first base electrode layer 415 and the second base electrode layer 425 may also be sintered layers containing metal and glass. As glass, there may be cited a glass component containing at least one selected from B, Si, Ba, Mg, Al or Li. As a specific example, borosilicate glass may be used. As metal, Cu is included as a main component. In addition, as metal, for example, at least one selected from metals such as Ni, Ag, Pd or Au, or alloys such as Ag-Pd alloys may be included as a main component, and a component other than the above at least one main component may be included.

[0059] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by an impregnation method and firing it. In addition, the fired layer can be fired after the internal electrode layer is fired, or it can be fired at the same time as the internal electrode layer. In addition, the fired layer can also be multilayer.

[0060] Alternatively, the first foundation electrode layer 415 and the second foundation electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-mentioned fired layer, or may be formed directly on the laminate without forming a fired layer.

[0061] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and firing. In addition, the resin layer can be fired after the internal electrode layer is fired, or it can be fired simultaneously with the internal electrode layer. In addition, the resin layer can also be multilayered.

[0062] The thickness of each of the first foundation electrode layer 415 and the second foundation electrode layer 425 which are fired layers or resin layers is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0063] Alternatively, the first foundation electrode layer 415 and the second foundation electrode layer 425 may be thin film layers of 1 μm or less in thickness formed by a thin film forming method such as sputtering or vapor deposition and in which metal particles are deposited.

[0064] The first plating layer 416 covers at least a portion of the first base electrode layer 415, and the second plating layer 426 covers at least a portion of the second base electrode layer 425. The first plating layer 416 and the second plating layer 426 include, for example, at least one selected from a metal such as Cu, Ni, Ag, Pd, or Au, or an alloy such as an Ag-Pd alloy.

[0065] The first plating layer 416 and the second plating layer 426 may each be formed of multiple layers. Preferably, a two-layer structure of Ni plating and Sn plating is used. The Ni plating layer can prevent the base electrode layer from being corroded by the solder when the ceramic electronic component is mounted, and the Sn plating layer improves the wettability of the solder when the ceramic electronic component is mounted, making it easy to mount.

[0066] The thickness of each of the first plating layer 416 and the second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0067] <<Stress Suppression Film>>

[0068] The stress suppression film 50 suppresses stress applied to the stacked body 10 and the external electrode 40 . The stress suppression film 50 extends along the first main surface (upper surface) TS1 and the two end surfaces LS1 , LS2 , and extends along the first main surface TS1 and the two side surfaces WS1 , WS2 to cover the stacked body 10 and the external electrode 40 .

[0069] The end of the stress suppression film 50 protrudes by D1 on the second main surface (bottom surface, mounting surface) TS2 side from the outermost surface (the surface located closest to the bottom surface) of the external electrode 40. The protruding dimension D1 of the end of the stress suppression film 50 may be 5 μm or more and 10 μm or less. If D1 is 5 μm or more, a stress suppression effect is obtained, and if D1 is 10 μm or less, connectivity between the external electrode 40 and the cream solder is obtained.

[0070] In the stress suppression film 50 , a film thickness Da of a main surface portion (first portion) along the first main surface TS1 and a film thickness Db of a side surface portion (second portion) along the two end surfaces LS1 and LS2 and the two side surfaces WS1 and WS2 satisfy the following relational expression.

[0071] 0.8Da≥Db

[0072] The film thickness Da of the main surface portion (first portion) may be 4.5 μm or more and 5.5 μm or less.

[0073] If the film thickness Da of the main surface portion (first portion) is relatively thick, the main surface portion of the stress suppression film 50 along the first main surface TS1 can withstand the suction force applied to the first main surface TS1 side that becomes the upper surface when suction is performed by a mounter, and the suction force applied to the laminated body 10 can be suppressed. On the other hand, if the film thickness Db of the side surface portion (second portion) is relatively thin, the solder pad can be reduced in the mounting substrate, and high-density mounting can be achieved.

[0074] The stress suppression film 50 is made of a material having insulating properties, thereby preventing the external electrodes 40 from being short-circuited.

[0075] The strength of the stress suppression film 50 is preferably higher than the strength of the plurality of dielectric layers 20 of the laminate 10. Specifically, in terms of strength against stress during mounting using a mounter, the strength of the stress suppression film 50 is preferably higher than the strength of the plurality of dielectric layers 20 of the laminate 10. For example, the Young's modulus of the stress suppression film 50 is preferably 400 GPa or more and 1500 GPa or less.

[0076] From the viewpoint of insulation and strength, diamond-like carbon, glass, etc. can be cited as the material of the stress suppression film 50. Among them, diamond-like carbon is preferable as the material of the stress suppression film 50.

[0077] <Manufacturing method>

[0078] Next, a method for manufacturing the above-mentioned multilayer ceramic capacitor 1 is described. First, a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. As the binder and the solvent, known materials can be used.

[0079] Next, the conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. Screen printing, gravure printing, or the like can be used as a method for forming the internal electrode pattern.

[0080] Next, a predetermined number of dielectric sheets for the second outer layer 102 without an internal electrode pattern printed thereon are stacked. Dielectric sheets for the inner layer 100 with an internal electrode pattern printed thereon are sequentially stacked. A predetermined number of dielectric sheets for the first outer layer 101 without an internal electrode pattern printed thereon are stacked. Thus, a laminated sheet is produced.

[0081] Next, the stacked sheets are pressed in the stacking direction by isostatic pressing or the like to produce a stacked block. Next, the stacked block is cut into a given size to cut out stacked small pieces. At this time, dielectric sheets for the first side margin portion W11 and the second side margin portion W12 may also be attached to the sides of the stacked small pieces. In addition, at this time, the corners and ridges of the stacked small pieces are rounded by roller grinding or the like. Next, the stacked small pieces are fired to produce a stacked body 10. The firing temperature also depends on the materials of the dielectric and the internal electrode, but is preferably above 900°C and below 1400°C.

[0082] Next, a conductive paste as an electrode material for a base electrode layer (for the first base electrode layer 415) is applied to the second main surface TS2 and the first end surface LS1 of the stacked body 10 by a coating method. Similarly, a conductive paste as an electrode material for a base electrode layer (for the second base electrode layer 425) is applied to the second main surface TS2 and the second end surface LS2 of the stacked body 10 by a coating method. Then, these conductive pastes are fired to form the first base electrode layer 415 and the second base electrode layer 425 as fired layers. The firing temperature is preferably 600° C. or higher and 900° C. or lower.

[0083] Alternatively, the first foundation electrode layer 415 and the second foundation electrode layer 425 may be formed as thin films by a thin film forming method such as sputtering or vapor deposition.

[0084] In the above, the base electrode layer is formed and fired after the stacked chips are fired, that is, the stacked body and the external electrodes are fired separately. However, the base electrode layer may be formed and fired before the stacked chips are fired, that is, the stacked body and the external electrodes may be fired simultaneously.

[0085] Thereafter, the first plating layer 416 is formed on the surface of the first foundation electrode layer 415 to form the first external electrode 41 , and the second plating layer 426 is formed on the surface of the second foundation electrode layer 425 to form the second external electrode 42 .

[0086] Next, a stress suppression film 50 is formed so as to cover the laminate 10 and the external electrode 40. As a method for forming the stress suppression film 50, a PVD method (Physical Vapor Deposition) method such as a sputtering method or a vapor deposition method can be cited. At this time, by adjusting the height of the mounting fixture, the protruding dimension D1 of the stress suppression film 50 can be adjusted. In addition, Figure 1 and the following Figure 4 , Figure 7 and Figure 10 to Figure 12 The shape of the protruding portion can also be deformed by the mounting fixture.

[0087] Through the above steps, the above-mentioned multilayer ceramic capacitor 1 is obtained.

[0088] Here, in a conventional multilayer ceramic capacitor that does not include a stress suppression film 50, if the multilayer ceramic capacitor is thinned, the strength of the multilayer body 10, especially the ceramic layer (dielectric layer 20), is reduced, and the stress from the mounter during mounting may cause damage to the multilayer ceramic capacitor. For example, when mounting using a mounter, stress is applied to the first main surface TS1 side of the multilayer ceramic capacitor, which becomes the upper surface, and thus stress is applied to the external electrode 40 on the second main surface TS2 of the multilayer ceramic capacitor, which becomes the bottom surface (mounting surface), and damage may occur in the multilayer ceramic capacitor. For example, cracks may occur in the ceramic layer (dielectric layer 20) of the multilayer body 10. If the cracks generated in the ceramic layer (dielectric layer 20) progress to the internal electrode layer 30, for example, water may penetrate into the cracks, and the insulation of the multilayer ceramic capacitor may be reduced.

[0089] In this regard, according to the multilayer ceramic capacitor 1 of the present embodiment, the stress suppression film 50 extends along the first main surface (upper surface) TS1 and the two end surfaces LS1 and LS2, and extends along the first main surface (upper surface) TS1 and the two side surfaces WS1 and WS2 so as to cover the laminated body 10 and the external electrode 40, and the end of the stress suppression film 50 protrudes by D1 on the second main surface (bottom surface, mounting surface) TS2 side from the outermost surface (surface located closest to the bottom surface side) of the external electrode 40. Thus, when mounting is performed using a mounter, the stress applied to the first main surface TS1 side, which becomes the upper surface, can be dispersed from the main surface portion of the stress suppression film 50 along the first main surface TS1 to the end surface portions along the two end surfaces LS1 and LS2 and the side surface portions along the two side surfaces WS1 and WS2, and released to the protruding end portions. Thus, stress applied to the external electrode 40 and the laminate 10 on the second main surface TS2 serving as the bottom surface (mounting surface) can be suppressed, and cracks can be suppressed from occurring in the ceramic layer (dielectric layer 20) of the laminate 10. Thus, according to the laminated ceramic capacitor 1 of this embodiment, even if the thickness is reduced, a decrease in strength against external stress can be suppressed.

[0090] Furthermore, according to the multilayer ceramic capacitor 1 of this embodiment, when being adsorbed by a mounter, the main surface portion of the stress suppression film 50 along the first main surface TS1 can also receive the adsorption force applied to the first main surface TS1 side as the upper surface.

[0091] Furthermore, according to the multilayer ceramic capacitor 1 of this embodiment, the external electrode 40 on the end faces LS1, LS2 or the side faces WS1, WS2 can be covered by the stress suppression film 50, so that the cream solder can be prevented from bulging on the end faces LS1, LS2 or the side faces WS1, WS2. As a result, the solder pad can be reduced in the mounting substrate, and high-density mounting can be achieved.

[0092] In addition, according to the multilayer ceramic capacitor 1 of the present embodiment, since the external electrode 40 is not formed on the first main surface TS1 side, the number of stacked layers in the stacked body 10 can be increased, and the capacitor effective area can be increased. In addition, since the external electrode 40 is not formed on the two side surfaces WS1 and WS2, the area in the stacked body 10 can be increased, and the capacitor effective area can be increased.

[0093] The embodiments of the present invention have been described above, but the present invention is not limited to the above-mentioned embodiments, and various changes and deformations can be made. For example, in the above-mentioned embodiments, the stress suppression film 50 is illustrated as extending along five surfaces, namely, the first main surface (upper surface) TS1, the two end surfaces LS1, LS2, and the two side surfaces WS1, WS2. However, the present invention is not limited to this, and the stress suppression film 50 may also be a mode in which it extends only along the three surfaces of the first main surface (upper surface) TS1 and the two end surfaces LS1, LS2. Alternatively, the stress suppression film 50 may also be a mode in which it extends only along the three surfaces of the first main surface (upper surface) TS1 and the two side surfaces WS1, WS2.

[0094] In addition, in the above-mentioned embodiment, the two external electrodes 40 are arranged on a part of the two end faces LS1, LS2 sides of the second main surface TS2 of the stack 10 and the two end faces LS1, LS2. However, in the present invention, the shape, number and arrangement position of the external electrodes 40 are not limited to this. For example, the present invention can also be applied to a method in which a plurality of external electrodes 40 are arranged on at least a part of the second main surface TS2 of the stack 10. In addition, the present invention can also be applied to a method in which a plurality of external electrodes 40 are arranged on at least a part of the two side faces WS1, WS2 sides of the second main surface TS2. Several examples of the shape, number and arrangement position of the external electrodes 40 are shown below.

[0095] (Variant 1)

[0096] Figure 4 is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment. Figure 5 yes Figure 4 The VV line cross-sectional view of the multilayer ceramic capacitor shown in FIG. Figure 6 yes Figure 4 FIG. 5 is a cross-sectional view of the multilayer ceramic capacitor taken along line VI-VI shown in FIG. Figures 4 to 6 The stacked ceramic capacitor 1 shown with Figure 1 to Figure 3 Compared with the multilayer ceramic capacitor 1 shown, the shape of the external electrode 40 is different.

[0097] The first external electrode 41 is arranged only on the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10, specifically, only on a portion of the second main surface TS2 on the first end surface LS1 side. That is, the first external electrode 41 is not arranged on the first end surface LS1, the first main surface (upper surface) TS1, the first side surface WS1, and the second side surface WS2. In this case, for example, the first external electrode 41 and the first internal electrode layer 31 may be connected by one or more vias 35 extending in the stacking direction T on the first end surface LS1 side of the stacked body 10.

[0098] The second external electrode 42 is arranged only on the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10, specifically, only on a portion of the second main surface TS2 on the second end surface LS2 side. That is, the second external electrode 42 is not arranged on the second end surface LS2, the first main surface (upper surface) TS1, the first side surface WS1, and the second side surface WS2. In this case, for example, the second external electrode 42 and the second internal electrode layer 32 can be connected by one or more vias 35 extending in the stacking direction T on the second end surface LS2 side of the stacked body 10.

[0099] There is no limitation on the method for forming the via hole 35. For example, after the above-mentioned stacking block is prepared and before the stacking pieces are cut out, a plurality of holes arranged along the width direction are formed near the ends of the stacking pieces, and the formed holes are filled with a conductive paste.

[0100] (Variant 2)

[0101] Figure 7 is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment. Figure 8 yes Figure 7 The VIII-VIII line cross-sectional view of the multilayer ceramic capacitor shown in FIG. Fig. 9 yes Figure 7 A cross-sectional view of the multilayer ceramic capacitor taken along line IX-IX shown. Figure 7 to Figure 9 The stacked ceramic capacitor 1 shown with Figure 1 to Figure 3Compared with the multilayer ceramic capacitor 1 shown, the shape of the external electrode 40 is different.

[0102] The first external electrode 41 is disposed on a portion of the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10 on the first end surface LS1 side and on the first end surface LS1, and is connected to the first internal electrode layer 31. Figure 7 to Figure 9 In the example, the first external electrode 41 is also arranged on a portion of the first main surface (upper surface) TS1 on the first end surface LS1 side of the stack 10, is also arranged on a portion of the first side surface WS1 on the first end surface LS1 side of the stack 10, and is also arranged on a portion of the second side surface WS2 on the first end surface LS1 side of the stack 10. That is, the first external electrode 41 is in an Angular U-shape in the LT cross section, and is arranged along a portion of the first end surface LS1 side of the second main surface TS2 of the stack 10, the first end surface LS1, and a portion of the first end surface LS1 side of the first main surface TS1. In addition, the first external electrode 41 is in an Angular U-shape in the LW cross section, and is arranged along a portion of the first side surface WS1 of the stack 10 on the first end surface LS1 side, the first end surface LS1, and a portion of the second side surface WS2 on the first end surface LS1 side.

[0103] The second external electrode 42 is disposed on a portion of the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10 on the second end surface LS2 side and on the second end surface LS2, and is connected to the second internal electrode layer 32. Figure 7 to Figure 9 In the example, the second external electrode 42 is also arranged on a portion of the second end face LS2 side of the first main surface (upper surface) TS1 of the stack 10, is also arranged on a portion of the second end face LS2 side of the first side surface WS1 of the stack 10, and is also arranged on a portion of the second end face LS2 side of the second side surface WS2 of the stack 10. That is, the second external electrode 42 is in an Angular U-shape in the LT cross section, and is arranged along a portion of the second end face LS2 side of the second main surface TS2 of the stack 10, the second end face LS2, and a portion of the second end face LS2 side of the first main surface TS1. In addition, the second external electrode 42 is in an Angular U-shape in the LW cross section, and is arranged along a portion of the second end face LS2 side of the first side surface WS1 of the stack 10, the second end face LS2, and a portion of the second end face LS2 side of the second side surface WS2.

[0104] In this case, a flat-plate-shaped spacing member 55 may be arranged in the portion where the plurality of external electrodes 40 are not arranged on each of the first main surface TS1 and the second main surface TS2. In this case, the stress suppression film 50 may be extended on the first main surface TS1 so as to also cover the spacing member 55. Thus, in the first main surface TS1 which becomes the upper surface, the height difference between the portion where the external electrodes 40 are arranged and the portion where the external electrodes 40 are not arranged can be suppressed, and the adsorption property of the mounting machine can be improved. In addition, since there is no distinction between the upper and lower surfaces in the form before the stress suppression film 50 is formed, the spacing member 55 is preferably arranged on both the first main surface TS1 and the second main surface TS2.

[0105] (Variant 3)

[0106] Fig.10 It is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment. Fig.10 The stacked ceramic capacitor 1 shown with Figure 7 to Figure 9 Compared with the multilayer ceramic capacitor 1 shown, the number of external electrodes 40 is different.

[0107] For example, in Figure 7 to Figure 9 In the multilayer ceramic capacitor 1 shown, the external electrode 40 includes a third external electrode 43 and a fourth external electrode 44 in addition to the first external electrode 41 and the second external electrode 42. In this way, the multilayer ceramic capacitor 1 includes the third external electrode 43 and the fourth external electrode 44 as the third electrode in addition to the first external electrode 41 and the second external electrode 42, and is therefore called a three-terminal multilayer ceramic capacitor. The features of the present invention can also be applied to such a three-terminal multilayer ceramic capacitor.

[0108] The third external electrode 43 is disposed between the first external electrode 41 and the second external electrode 42 on a portion of the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10 on the first side surface WS1 and on the first side surface WS1. Fig.10 In the example, the third external electrode 43 is also arranged on a portion of the first side surface WS1 side of the first principal surface (upper surface) TS1 of the stacked body 10. That is, the third external electrode 43 is in an angular U-shape in the WT cross section, and is arranged along a portion of the first side surface WS1 side of the second principal surface TS2 of the stacked body 10, the first side surface WS1, and a portion of the first side surface WS1 side of the first principal surface TS1.

[0109] The fourth external electrode 44 is disposed between the first external electrode 41 and the second external electrode 42 on a portion of the second main surface (bottom surface, mounting surface) TS2 of the laminate 10 on the second side surface WS2 and on the second side surface WS2. Fig.10In the example, the fourth external electrode 44 is also arranged on a portion of the second side surface WS2 side of the first main surface (upper surface) TS1 of the stacked body 10. That is, the fourth external electrode 44 is a U-shape (Angular U-shape) in the WT cross section, and is arranged along a portion of the second side surface WS2 side of the second main surface TS2 of the stacked body 10, the second side surface WS2, and a portion of the second side surface WS2 side of the first main surface TS1.

[0110] exist Fig.10 The multilayer ceramic capacitor 1 shown in FIG. Figure 7 to Figure 9 Similarly, in the illustrated multilayer ceramic capacitor 1 , a flat-plate spacer 55 is disposed in a portion where the plurality of external electrodes 40 are not disposed on each of the first main surface TS1 and the second main surface TS2 . In this case, the stress suppression film 50 may extend on the first main surface TS1 to also cover the spacer 55 .

[0111] In addition, Fig.10 In the embodiment, as the shape of the external electrode 40, an external electrode 40 having a U-shaped cross section (angular U-shape) is exemplified. However, the features of the present invention are not limited to this, and can also be applied to Fig.10 In the multilayer ceramic capacitor 1 shown in FIG. Figure 1 to Figure 3 The multilayer ceramic capacitor 1 shown is also a multilayer ceramic capacitor 1 having an external electrode 40 with an L-shaped cross section. In this case, the third external electrode 43 is L-shaped in the WT cross section and is arranged along a portion of the first side surface WS1 side of the second main surface TS2 of the multilayer body 10 and the first side surface WS1. In addition, the fourth external electrode 44 is L-shaped in the WT cross section and is arranged along a portion of the second side surface WS2 side of the second main surface TS2 of the multilayer body 10 and the second side surface WS2.

[0112] In addition, the features of the present invention can also be applied to Fig.10 In the multilayer ceramic capacitor 1 shown in FIG. Figures 4 to 6 The illustrated multilayer ceramic capacitor 1 is similarly a multilayer ceramic capacitor 1 of a type including the external electrode 40 only on the second main surface TS2 .

[0113] (Variant 4)

[0114] Fig.11 It is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment. Fig.11 The stacked ceramic capacitor 1 shown with Figure 7 to Figure 9 Compared with the multilayer ceramic capacitor 1 shown, the number and arrangement positions of the external electrodes 40 are different.

[0115] For example, when viewed from the second main surface TS2 side, the external electrode 40 includes a first external electrode 41, a second external electrode 42, a third external electrode 43, and a fourth external electrode 44 at four corners of the laminate 10. Such a laminated ceramic capacitor 1 can include, for example, two laminated ceramic capacitor elements between the first external electrode 41 and the second external electrode 42, and between the third external electrode 43 and the fourth external electrode 44. The features of the present invention can also be applied to such a multi-terminal laminated ceramic capacitor.

[0116] The first external electrode 41 is disposed at a corner portion on the first end surface LS1 side and the first side surface WS1 side of the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10, and at a portion of the first end surface LS1 and a portion of the first side surface WS1. Fig.11 In the example, the first external electrode 41 is also arranged at the corner of the first end face LS1 side and the first side face WS1 side of the first main surface (upper surface) TS1 of the stacked body 10. That is, the first external electrode 41 is in an angular U-shape in the LT cross section, and is arranged along a portion of the first end face LS1 side of the second main surface TS2 of the stacked body 10, the first end face LS1, and a portion of the first end face LS1 side of the first main surface TS1. In addition, the first external electrode 41 is in an angular U-shape in the WT cross section, and is arranged along a portion of the first side face WS1 side of the second main surface TS2 of the stacked body 10, the first side face WS1, and a portion of the first side face WS1 side of the first main surface TS1.

[0117] The second external electrode 42 is arranged at a corner portion on the second end surface LS2 side and the first side surface WS1 side of the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10, and at a portion of the second end surface LS2 and a portion of the first side surface WS1. Fig.11 In the example, the second external electrode 42 is also arranged at the corner of the second end face LS2 side and the first side face WS1 side in the first main surface (upper surface) TS1 of the stack 10. That is, the second external electrode 42 is in an angular U-shape in the LT cross section, and is arranged along a portion of the second end face LS2 side, the second end face LS2, and a portion of the second end face LS2 side in the first main surface TS1 of the stack 10. In addition, the second external electrode 42 is in an angular U-shape in the WT cross section, and is arranged along a portion of the first side face WS1 side, the first side face WS1, and a portion of the first side face WS1 side in the first main surface TS1 of the stack 10.

[0118] The third external electrode 43 is arranged at a corner portion on the first end surface LS1 side and the second side surface WS2 side of the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10, and at a portion of the first end surface LS1 and a portion of the second side surface WS2. Fig.11 In the example, the third external electrode 43 is also arranged at the corner of the first end face LS1 side and the second side face WS2 side in the first main surface (upper surface) TS1 of the stacked body 10. That is, the third external electrode 43 is in an angular U-shape in the LT cross section, and is arranged along a portion of the first end face LS1 side, the first end face LS1, and a portion of the first main surface TS1 on the first end face LS1 side in the second main surface TS2 of the stacked body 10. In addition, the third external electrode 43 is in an angular U-shape in the WT cross section, and is arranged along a portion of the second side face WS2 side, the second side face WS2, and a portion of the second side face WS2 side in the first main surface TS1 of the stacked body 10.

[0119] The fourth external electrode 44 is arranged at a corner portion on the second end surface LS2 side and the second side surface WS2 side of the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10, and at a portion of the second end surface LS2 and a portion of the second side surface WS2. Fig.11 In the example, the fourth external electrode 44 is also arranged at the corner of the second end face LS2 side and the second side face WS2 side in the first main surface (upper surface) TS1 of the stack 10. That is, the fourth external electrode 44 is in an angular U-shape in the LT cross section, and is arranged along a portion of the second end face LS2 side, the second end face LS2, and a portion of the second end face LS2 side in the second main surface TS2 of the stack 10, the second side face WS2, and a portion of the second side face WS2 side in the first main surface TS1. In addition, the fourth external electrode 44 is in an angular U-shape in the WT cross section, and is arranged along a portion of the second side face WS2 side, the second side face WS2, and a portion of the second side face WS2 side in the second main surface TS2 of the stack 10, the second side face WS2, and a portion of the second side face WS2 side in the first main surface TS1.

[0120] exist Fig.11 The multilayer ceramic capacitor 1 shown in FIG. Figure 7 to Figure 9 Similarly, in the illustrated multilayer ceramic capacitor 1 , a flat-plate spacer 55 is disposed in a portion where the plurality of external electrodes 40 are not disposed on each of the first main surface TS1 and the second main surface TS2 . In this case, the stress suppression film 50 may extend on the first main surface TS1 to also cover the spacer 55 .

[0121] In addition, Fig.11In the embodiment, as the shape of the external electrode 40, an external electrode 40 having a U-shaped cross section (angular U-shape) is exemplified. However, the features of the present invention are not limited to this, and can also be applied to Fig.10 In the multilayer ceramic capacitor 1 shown in FIG. Figure 1 to Figure 3 The multilayer ceramic capacitor 1 shown is also a multilayer ceramic capacitor 1 in the form of an external electrode 40 having an L-shaped cross section. In this case, the first external electrode 41 is L-shaped in the LT cross section and is arranged along a portion of the first end face LS1 side of the second main surface TS2 of the stack 10 and the first end face LS1, and is L-shaped in the WT cross section and is arranged along a portion of the first side face WS1 side of the second main surface TS2 of the stack 10 and the first side face WS1. In addition, the second external electrode 42 is L-shaped in the LT cross section and is arranged along a portion of the second end face LS2 side of the second main surface TS2 of the stack 10 and the second end face LS2, and is L-shaped in the WT cross section and is arranged along a portion of the first side face WS1 side of the second main surface TS2 of the stack 10 and the first side face WS1. In addition, the third external electrode 43 is L-shaped in the LT cross section, and is arranged along a portion of the first end face LS1 side of the second main surface TS2 of the stack 10 and the first end face LS1, and is L-shaped in the WT cross section, and is arranged along a portion of the second side face WS2 side of the second main surface TS2 of the stack 10 and the second side face WS2. In addition, the fourth external electrode 44 is L-shaped in the LT cross section, and is arranged along a portion of the second end face LS2 side of the second main surface TS2 of the stack 10 and the second end face LS2, and is L-shaped in the WT cross section, and is arranged along a portion of the second side face WS2 side of the second main surface TS2 of the stack 10 and the second side face WS2.

[0122] In addition, the features of the present invention can also be applied to Fig.11 In the multilayer ceramic capacitor 1 shown in FIG. Figures 4 to 6 The illustrated multilayer ceramic capacitor 1 is similarly a multilayer ceramic capacitor 1 of a type including the external electrode 40 only on the second main surface TS2 .

[0123] (Variant 5)

[0124] Fig.12 It is a perspective view showing a multilayer ceramic capacitor according to a modified example of the present embodiment. Fig.12 The stacked ceramic capacitor 1 shown with Figure 7 to Figure 9 Compared with the multilayer ceramic capacitor 1 shown, the number and arrangement positions of the external electrodes 40 are different.

[0125] For example, the external electrode 40 includes a first external electrode 41, a third external electrode 43, a fifth external electrode 45, and a seventh external electrode 47 on the first side surface WS1 of the stacked body 10, and includes a second external electrode 42, a fourth external electrode 44, a sixth external electrode 46, and an eighth external electrode 48 on the second side surface WS2 of the stacked body 10. Such a stacked ceramic capacitor 1 can, for example, have four stacked ceramic capacitor elements arranged in an array between the first external electrode 41 and the second external electrode 42, between the third external electrode 43 and the fourth external electrode 44, between the fifth external electrode 45 and the sixth external electrode 46, and between the seventh external electrode 47 and the eighth external electrode 48. The features of the present invention can also be applied to such an array-type stacked ceramic capacitor.

[0126] The first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 are each arranged on a portion of the first side surface WS1 of the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10 and on the first side surface WS1. Fig.12 In the example, the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 are each also arranged on a portion of the first side surface WS1 side of the first principal surface (upper surface) TS1 of the stack 10. That is, the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 are each in an angular U-shape in the WT cross section, and are arranged along a portion of the first side surface WS1 side of the second principal surface TS2 of the stack 10, the first side surface WS1, and a portion of the first side surface WS1 side of the first principal surface TS1.

[0127] The second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are arranged on a portion of the second side surface WS2 of the second main surface (bottom surface, mounting surface) TS2 of the stacked body 10 and on the second side surface WS2. Fig.12 In the example, the second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are also arranged on a portion of the second side surface WS2 side of the first main surface (upper surface) TS1 of the stack 10. That is, the second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are U-shaped (Angular U-shape) in the WT cross section, and are arranged along a portion of the second side surface WS2 side of the second main surface TS2 of the stack 10, the second side surface WS2, and a portion of the second side surface WS2 side of the first main surface TS1.

[0128] exist Fig.12 The multilayer ceramic capacitor 1 shown in FIG. Figure 7 to Figure 9 Similarly, in the illustrated multilayer ceramic capacitor 1 , a flat-plate spacer 55 is disposed in a portion where the plurality of external electrodes 40 are not disposed on each of the first main surface TS1 and the second main surface TS2 . In this case, the stress suppression film 50 may extend on the first main surface TS1 to also cover the spacer 55 .

[0129] In addition, Fig.12 In the embodiment, as the shape of the external electrode 40, an external electrode 40 having a U-shaped cross section (angular U-shape) is exemplified. However, the features of the present invention are not limited to this, and can also be applied to Fig.12 In the multilayer ceramic capacitor 1 shown in FIG. Figure 1 to Figure 3 The multilayer ceramic capacitor 1 shown is also a multilayer ceramic capacitor 1 in the form of an external electrode 40 having an L-shaped cross section. In this case, the first external electrode 41, the third external electrode 43, the fifth external electrode 45, and the seventh external electrode 47 are each L-shaped in the WT cross section, and are arranged along a portion of the first side surface WS1 side of the second main surface TS2 of the multilayer body 10 and the first side surface WS1. In addition, the second external electrode 42, the fourth external electrode 44, the sixth external electrode 46, and the eighth external electrode 48 are L-shaped in the WT cross section, and are arranged along a portion of the second side surface WS2 side of the second main surface TS2 of the multilayer body 10 and the second side surface WS2.

[0130] In addition, the features of the present invention can also be applied to Fig.12 In the multilayer ceramic capacitor 1 shown in FIG. Figures 4 to 6 The illustrated multilayer ceramic capacitor 1 is similarly a multilayer ceramic capacitor 1 of a type including the external electrode 40 only on the second main surface TS2 .

[0131] In the above-mentioned Modifications 1 to 5, the stress suppression film 50 is also exemplified as extending along five surfaces, namely, the first main surface (upper surface) TS1, the two end surfaces LS1, TS2, and the two side surfaces WS1, WS2. However, the present invention is not limited thereto, and the stress suppression film 50 may also be extending along three surfaces, namely, the first main surface (upper surface) TS1 and the two end surfaces LS1, LS2. Alternatively, the stress suppression film 50 may also be extending along three surfaces, namely, the first main surface (upper surface) TS1 and the two side surfaces WS1, WS2.

[0132] In addition, the present invention may be implemented in the following aspects.

[0133] <1> A multilayer ceramic capacitor comprising:

[0134] A laminated body in which a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic materials are laminated, the laminated body having a first main surface and a second main surface opposite to each other in a lamination direction, two side surfaces opposite to each other in a width direction intersecting the lamination direction, and two end surfaces opposite to each other in a length direction intersecting the lamination direction and the width direction;

[0135] a plurality of external electrodes disposed on at least the second main surface of the stack; and

[0136] a stress suppression film for suppressing stress applied to the stacked body and the plurality of external electrodes,

[0137] The stress suppression film is made of an insulating material and extends along the first main surface and the two end surfaces, or along the first main surface and the two side surfaces so as to cover the stacked body and the plurality of external electrodes.

[0138] An end portion of the stress suppression film protrudes further than outermost surfaces of the plurality of external electrodes on the second main surface side.

[0139] <2> The multilayer ceramic capacitor according to <1>, wherein

[0140] The stress suppression film extends along the first main surface and the two end surfaces, and extends along the first main surface and the two side surfaces.

[0141] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein:

[0142] The stress suppression film has a strength higher than that of the plurality of dielectric layers of the stacked body.

[0143] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein

[0144] The stress suppression film has a Young's modulus of 400 GPa or more and 1500 GPa or less.

[0145] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein

[0146] The stress suppression film contains diamond-like carbon or glass as a material.

[0147] <6> The multilayer ceramic capacitor according to any one of <1> to <5>, wherein

[0148] In the stress suppression film, a film thickness Da of a first portion along the first main surface and a film thickness Db of a second portion along the two end surfaces or the two side surfaces satisfy the following relationship:

[0149] 0.8Da≥Db.

[0150] <7> The multilayer ceramic capacitor according to <6>, wherein

[0151] The film thickness Da of the first portion is greater than or equal to 4.5 μm and less than or equal to 5.5 μm.

[0152] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein

[0153] Each of the plurality of external electrodes is L-shaped in a cross section along the stacking direction and the longitudinal direction, and is arranged along the second main surface and one of the two end surfaces of the stacked body, or,

[0154] Each of the plurality of external electrodes has an L-shape in a cross section along the stacking direction and the width direction, and is arranged along the second main surface and one of the two side surfaces of the stacked body.

[0155] <9> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein

[0156] Each of the plurality of external electrodes is arranged only along the second main surface of the stacked body,

[0157] The stacked body has a plurality of via holes extending in the stacking direction and connecting the plurality of external electrode layers to different portions of the plurality of internal electrode layers, respectively.

[0158] <10> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein

[0159] Each of the plurality of external electrodes is U-shaped in a cross section along the stacking direction and the longitudinal direction, and is arranged along the second main surface of the stack, one of the two end surfaces, and the first main surface, or,

[0160] Each of the plurality of external electrodes is U-shaped in a cross section along the stacking direction and the width direction, and is arranged along the second main surface of the stack, one of the two side surfaces, and the first main surface,

[0161] A flat-plate-shaped spacer member is disposed in a portion of each of the first main surface and the second main surface where the plurality of external electrodes are not disposed.

[0162] The stress suppression film extends on the first main surface so as to also cover the spacing member.

[0163] Description of Reference Numerals

[0164] 1 Multilayer Ceramic Capacitors

[0165] 10 Laminated body

[0166] 20 Dielectric layer

[0167] 30 Internal electrode layer

[0168] 31 First internal electrode layer

[0169] 311 first opposing electrode portion

[0170] 312 first extraction electrode portion

[0171] 32 Second internal electrode layer

[0172] 321 Second counter electrode portion

[0173] 322 second extraction electrode portion

[0174] 35 Vias

[0175] 40 External electrodes

[0176] 41 first external electrode

[0177] 415 first base electrode layer

[0178] 416 First plating layer

[0179] 42 second external electrode

[0180] 425 second base electrode layer

[0181] 426 Second plating layer

[0182] 50 Stress suppression film

[0183] 55 Spacer

[0184] 100 Inner layer

[0185] 101 First outer layer

[0186] 102 Second outer layer

[0187] L30 Electrode facing part

[0188] LG1 First end gap

[0189] LG2 Second end gap

[0190] W30 Electrode facing part

[0191] WG1 First side clearance

[0192] WG2 Second side clearance

[0193] L Length direction

[0194] T stacking direction

[0195] W Width direction

[0196] LS1 First End

[0197] LS2 Second end face

[0198] TS1 First main surface

[0199] TS2 Second main surface

[0200] WS1 first side

[0201] WS2 Second side.

Claims

1. A multilayer ceramic capacitor comprising: A laminated body in which a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic materials are laminated, the laminated body having a first main surface and a second main surface opposite to each other in a lamination direction, two side surfaces opposite to each other in a width direction intersecting the lamination direction, and two end surfaces opposite to each other in a length direction intersecting the lamination direction and the width direction; a plurality of external electrodes disposed on at least the second main surface of the stack; and a stress suppression film for suppressing stress applied to the stacked body and the plurality of external electrodes, The stress suppression film is made of an insulating material and extends along the first main surface and the two end surfaces, or along the first main surface and the two side surfaces so as to cover the stacked body and the plurality of external electrodes. An end portion of the stress suppression film protrudes further than outermost surfaces of the plurality of external electrodes on the second main surface side.

2. The multilayer ceramic capacitor according to claim 1, wherein The stress suppression film extends along the first main surface and the two end surfaces, and extends along the first main surface and the two side surfaces.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The stress suppression film has a strength higher than that of the plurality of dielectric layers of the stacked body.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The stress suppression film has a Young's modulus of 400 GPa or more and 1500 GPa or less.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein The stress suppression film contains diamond-like carbon or glass as a material.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein In the stress suppression film, a film thickness Da of a first portion along the first main surface and a film thickness Db of a second portion along the two end surfaces or the two side surfaces satisfy the following relationship: 0.8Da≥Db.

7. The multilayer ceramic capacitor according to claim 6, wherein: The film thickness Da of the first portion is greater than or equal to 4.5 μm and less than or equal to 5.5 μm.

8. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein Each of the plurality of external electrodes is L-shaped in a cross section along the stacking direction and the longitudinal direction, and is arranged along the second main surface and one of the two end surfaces of the stacked body, or, Each of the plurality of external electrodes has an L-shape in a cross section along the stacking direction and the width direction, and is arranged along the second main surface and one of the two side surfaces of the stacked body.

9. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein Each of the plurality of external electrodes is arranged only along the second main surface of the stacked body, The stacked body has a plurality of via holes extending in the stacking direction and connecting the plurality of external electrode layers to different portions of the plurality of internal electrode layers, respectively.

10. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein Each of the plurality of external electrodes is U-shaped in a cross section along the stacking direction and the longitudinal direction, and is arranged along the second main surface of the stack, one of the two end surfaces, and the first main surface, or, Each of the plurality of external electrodes is U-shaped in a cross section along the stacking direction and the width direction, and is arranged along the second main surface of the stack, one of the two side surfaces, and the first main surface. A flat-plate-shaped spacer member is disposed in a portion of each of the first main surface and the second main surface where the plurality of external electrodes are not disposed. The stress suppression film extends on the first main surface so as to also cover the spacing member.

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