Electronic device with frequency jitter

Abstract

An electronic device may include an inverter. The inverter may convert direct current (DC) power to alternating current (AC) power. The inverter may output a corresponding AC signal at a given frequency using a clock signal at the given frequency. The inverter may receive a dithered clock signal that is frequency dithered using a modulated signal. The dithered clock signal may have at least three different frequency levels during repetitive cycles of the modulated signal. The at least three different frequency levels may include a fundamental frequency, a first frequency lower than the fundamental frequency, and a second frequency higher than the fundamental frequency. The dithered clock signal may last at the fundamental frequency for fewer total cycles than at the first frequency and for fewer total cycles than at the second frequency during the repetitive cycles of the modulated signal.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 164,291 filed on February 3, 2023 and U.S. Provisional Patent Application No. 63 / 402,242 filed on August 30, 2022, which are hereby incorporated by reference in their entirety. Technical Field

[0002] This document relates generally to electronic devices, and more particularly to electronic devices having inverters. Background Art

[0003] Electronic devices sometimes include an inverter that converts direct current (DC) power to alternating current (AC) power. The inverter can use a clock signal at a given frequency to output a corresponding AC signal. If care is not taken, the operation of the inverter may cause greater electromagnetic interference (EMI) than desired. Summary of the invention

[0004] An electronic device may include: an inverter configured to receive a jittered clock signal and output a corresponding AC signal; and a control circuit configured to obtain the jittered clock signal using a modulation signal and a clock signal. The jittered clock signal may have at least three different frequency levels during a repeated cycle of the modulation signal. The at least three different frequency levels may include a base frequency, a first frequency lower than the base frequency, and a second frequency higher than the base frequency. The jittered clock signal may last at the base frequency for less total cycles than at the first frequency and for less total cycles than at the second frequency during the repeated cycle of the modulation signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a schematic diagram of an illustrative electronic device according to some embodiments.

[0006] Figure 2 is a schematic diagram of an illustrative inverter according to some embodiments.

[0007] Figure 3 is a schematic diagram of an illustrative electronic device including a dithering circuit according to some embodiments.

[0008] Figure 4 is a graph of exemplary modulation waveforms that may be used for frequency dithering in an electronic device according to some embodiments.

[0009] Figure 5 According to some embodiments, the Figure 4 FIG. 4 is a graph of a clock signal with an exemplary modification of a modulation waveform subjected to frequency jitter.

[0010] Figure 6is a graph of an exemplary modulation waveform that may be used for frequency dithering in an electronic device using scaling of a clock signal according to some embodiments.

[0011] Figure 7 According to some embodiments Figure 6 A histogram of the total periods per cycle for various values ​​of the modulation signal.

[0012] Figure 8 According to some embodiments, in the use Figure 6 A histogram of the total cycles per cycle of the modulated waveform with jitter at various frequencies of the modified clock signal. DETAILED DESCRIPTION

[0013] Figure 1 , an exemplary electronic device of the type in which an inverter may be provided is shown. The electronic device 10 may be a computing device such as a laptop computer, a computer monitor including an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic device, a smaller device (such as a wristwatch device, a hanging device, a headset or earpiece device, a device embedded in glasses or other equipment worn on the user's head, or other wearable or micro devices), a display, a computer display including an embedded computer, a computer display not including an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which the electronic equipment is installed in a kiosk or a car), a power adapter, a docking station, or other electronic equipment and / or accessories. The electronic device 10 may be capable of wireless charging (e.g., sending and / or receiving wireless power). Any of the aforementioned electronic devices may include a wireless power transmission coil or a wireless charging coil (as an example) for sending and / or receiving wireless power. As an additional example, the electronic device 10 may be a wireless charging pad or a wireless charging plate, may be equipment that has been incorporated into furniture, a vehicle, or other systems, may be a removable battery box (e.g., for a cellular phone, a tablet computer, earbuds, etc.), or may be other wireless power transmission equipment.

[0014] like Figure 1As shown, the electronic device 10 may include control circuitry 16 for supporting the operation of the device 10. This control circuitry may include processing circuitry associated with a microprocessor, a power management unit, a baseband processor, a digital signal processor, a microcontroller, and / or an application-specific integrated circuit having processing circuitry. The processing circuitry implements desired control and communication features in the electronic device 10. For example, the processing circuitry may be used to process user input, handle negotiations between the electronic device and an external electronic device, transmit and receive data (e.g., in-band data sent or received during wireless power transmission using a wireless charging coil, data sent or received using an antenna, etc.), make measurements, estimate power loss, determine power transmission levels, and otherwise control the operation of the electronic device 10.

[0015] The control circuit in the electronic device 10 may be configured to use hardware (e.g., dedicated hardware or circuitry), firmware, and / or software to perform operations in the electronic device 10. Software code and other data for performing operations in the electronic device 10 are stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) in the control circuit 16. Software code may sometimes be referred to as software, data, program instructions, instructions, or code. A non-transitory computer-readable storage medium may include a non-volatile memory such as a non-volatile random access memory (NVRAM), one or more hard disk drives (e.g., a disk drive or a solid-state drive), one or more removable flash drives, or other removable media, etc. The software stored on the non-transitory computer-readable storage medium may be executed on a processing circuit of the control circuit 16. The processing circuit may include a dedicated integrated circuit having a processing circuit, one or more microprocessors, a central processing unit (CPU), or other processing circuits.

[0016] like Figure 1 As shown, the electronic device further includes an inverter 18. The inverter 18 can convert direct current (DC) power into alternating current (AC) power. The inverter 18 can use a clock signal at a given frequency to output a corresponding AC signal at a given frequency.

[0017] Figure 2 FIG. 1 is a schematic diagram of an exemplary inverter 18 in the electronic device 10. Figure 2 As shown, the inverter 18 may receive a DC voltage Vdc (e.g., from an AC-DC converter, a battery, etc.). The inverter 18 includes transistors T1 and T2. Each transistor (T1 and T2) has a corresponding gate 22. The transistors T1 and T2 are coupled in series between a positive voltage terminal (at a positive power supply voltage Vdc) and a ground voltage terminal (at a ground power supply voltage Vss (sometimes simply referred to as a ground voltage Vss)).

[0018] The control circuit 16 may generate control signals applied to the gate terminals 22 of the inverter transistors T1 and T2. The gates 22 of the transistors T1 and T2 may receive complementary signals such that when the gate of the transistor T2 is low, the gate of the transistor T1 is high, and vice versa. In other words, the transistors T1 and T2 are asserted in a mutually exclusive manner, wherein when T1 is asserted, T2 is deasserted, and vice versa.

[0019] By way of an exemplary configuration, transistors T1 and T2 may be supplied with an AC signal (e.g., a clock signal) at a suitable operating frequency with a desired pulse width (or duty cycle) to control the amount of power being transmitted. Exemplary frequencies include 100kHz-200kHz, 200kHz-300kHz, 300kHz-400kHz, 1.778MHz, 13.56MHz, 6.78GHz, etc. In general, control signals may be applied to T1 and T2 at any desired frequency.

[0020] Component 20 may be coupled between node 24 and a ground power supply terminal Vss. Node 24 is interposed between T1 and T2 and may sometimes be referred to as an output node or output terminal of inverter 18. When a control signal is applied to gates 22 of transistors T1 and T2, the DC voltage Vdc is converted into an AC signal across component 20.

[0021] Component 20 may be a wireless charging coil, a transformer coil, an antenna, or any other desired component. Consider an example where component 20 is a wireless charging coil. When a control signal is applied to gates 22 of transistors T1 and T2, a DC voltage Vdc is converted into an AC signal across wireless charging coil 20, which generates a wireless power signal that can be received by a wireless charging coil in a corresponding electronic device. The wireless charging coil may be connected (e.g., in series between node 24 and a ground power terminal Vss) to a resonant capacitor tuned to a fundamental frequency f0.

[0022] Some electronic devices with inverters may employ signal jittering to improve the electromagnetic emission characteristics of the system (e.g., to reduce conducted emissions and / or radiated emissions). For example, the electronic device 10 may jitter the clock signal used to control the inverter 18. This effectively jitters the frequency of the AC signal output by the inverter 18.

[0023] In this document, various signals (e.g., clock signals) may be referred to as having a corresponding waveform (e.g., the shape of the voltage of the signal over time). A given waveform may have a cyclic shape that repeats at a given frequency (i.e., a given waveform may be periodic). The cyclic shape need not be a regular shape (e.g., a sinusoid). In fact, the cyclic shape may deviate from a sinusoidal shape. However, this type of waveform may still have a frequency associated with the periodic repetition of a non-sinusoidal shape.

[0024] Figure 3 is a diagram of an exemplary electronic device 10 with a dithering circuit. In one possible arrangement, the dithering circuit 32 and the clock modulation circuit 34 may be used to implement a spread spectrum clocking technique (sometimes referred to as clock dithering). In spread spectrum clocking, the clock waveform is intentionally modified so that the spectrum of the signal spreads around a target frequency of the clock signal. This target frequency is sometimes referred to as the fundamental frequency of the clock signal. This reduces EMI associated with the target frequency of the clock signal, such as emissions at harmonics of the target frequency.

[0025] As previously mentioned, a clock signal may be provided to the inverter 18 at a given frequency to cause the transistors in the inverter circuit to switch on and off to form an AC signal (also at a given frequency) across the components.

[0026] The electronic device 10 may include a dithering circuit 32 and a clock modulation circuit 34 for performing a frequency dithering operation. The dithering circuit 32 and the clock modulation circuit 34 may be considered part of the control circuit 16.

[0027] The jitter circuit 32 may determine a modulation waveform 36 for modulating a clock waveform 38 (sometimes referred to as a local clock waveform 38, an initial clock waveform 38, an un-jittered clock waveform 38, a system clock 38, etc.). To mitigate EMI in the electronic device 10, the modulation waveform 36 is applied to the clock waveform 38 by the clock modulation circuit 34. The clock modulation circuit 34 may use the modulation waveform 36 to frequency modulate the clock waveform 38. The resulting modified clock signal 40 is then provided to the inverter 18 to form a frequency-jittered AC signal.

[0028] Figure 4 is a graph of an exemplary modulation signal 36 that may be used for frequency dithering. Figure 4 The frequency of the modulated signal 36 is shown over time. Figure 4 In FIG. 1 , the modulation signal 36 follows a step function with various levels (e.g., at -2Δf, -Δf, 0, Δf, and +2Δf). The modulation signal is used to frequency modulate (jitter) the system clock signal so that the output of the inverter is frequency jittered. For simplicity, Figure 4 The time axis is shown in units of cycles. Each cycle is a single cycle of the clock signal modulated using the modulation signal 36. Figure 4In the example of , the modulated signal 36 has a frequency of -2Δf for three periods of the clock signal, then a frequency of -Δf for two periods of the clock signal, then a frequency of 0 for one period of the clock signal, then a frequency of +Δf for two periods of the clock signal, then a frequency of +2Δf for three periods of the clock signal, then a frequency of +Δf for two periods of the clock signal, then a frequency of 0 for one period of the clock signal, and then a frequency of -Δf for two periods of the clock signal. The modulated signal thus includes a total of 16 periods of the clock signal in a given cycle. The modulated signal may repeat Figure 4 The cycle depicted in .

[0029] The modulation signal 36 may cause the modified clock signal 40 to deviate from the base frequency f0 (e.g., 1.778 MHz). As previously mentioned, components such as a wireless charging coil connected to the output of the inverter may be tuned to the base frequency (e.g., using a capacitor). The waveform of the modified clock signal 40 (when using a signal from Figure 4 The modulation signal 36 after modulation) Figure 5 As shown in Figure 5 As shown, the modified clock signal 40 has a frequency f0-2Δf between t0 and t1 (e.g., for three cycles), the modified clock signal 40 has a frequency f0-Δf between t1 and t2 (e.g., for two cycles), the modified clock signal 40 has a frequency f0 between t2 and t3 (e.g., for one cycle), the modified clock signal 40 has a frequency f0+Δf between t3 and t4 (e.g., for two cycles), the modified clock signal 40 has a frequency f0+2Δf between t4 and t5 (e.g., for three cycles), the modified clock signal 40 has a frequency f0+Δf between t5 and t6 (e.g., for two cycles), the modified clock signal 40 has a frequency f0 between t6 and t7 (e.g., for one cycle), and the modified clock signal 40 has a frequency f0-Δf between t7 and t8 (e.g., for two cycles).

[0030] like Figure 5 In the example of FIG. 1 , the inverter can be operated at a 50% duty cycle. This example is merely illustrative, as the inverter can be operated at various desired duty cycles.

[0031] Figure 4 The modulation waveform 36 in may have a corresponding modulation frequency f m and the total frequency spread. The modulation frequency f m is the frequency of the modulation waveform 36, also known as the dither pattern repetition rate. In other words, the modulating signal is modulated at a modulation frequency or repetition rate f m repeat Figure 4 mode. Figure 4, the modulation frequency is equal to 1 divided by the duration of 16 periods used to complete a cycle of the modulating waveform.

[0032] Generally speaking, the modulation frequency may be less than 1 MHz, less than 0.5 MHz, less than 0.2 MHz, less than 0.1 MHz, less than 0.01 MHz, greater than 1 MHz, greater than 0.5 MHz, greater than 0.2 MHz, greater than 0.1 MHz, greater than 0.01 MHz, between 0.1 MHz and 0.2 MHz, etc.

[0033] The difference between the minimum and maximum frequencies of the modulating signal is sometimes referred to as the total frequency spread or total frequency deviation of the modulating signal. Figure 4 The minimum frequency is -2Δf, and the maximum frequency is + 2Δf. The total frequency spread is therefore 4Δf.

[0034] Generally speaking, the total frequency extension of the modulated signal may be greater than 60kHz, greater than 100kHz, greater than 150kHz, greater than 500kHz, greater than 1MHz, greater than 10MHz, less than 100kHz, less than 150kHz, less than 500kHz, less than 1MHz, less than 10MHz, between 150kHz and 160kHz, etc.

[0035] exist Figure 4 In , the modulating waveform spends a given number of cycles (duration) at each level of the step function. Figure 4 The duration at a given level (before proceeding to the next frequency level) can vary. Figure 4 , the number of cycles at each level is 3, then 2, then 1, then 2, then 3, then 2, then 1, and then 2 in order. The number of cycles at each level may be proportional (but not necessarily proportional) to the difference between the frequency at that level and the fundamental frequency. In other words, at the largest difference from the fundamental frequency (e.g., at -2Δf and +2Δf), the duration is the largest (3 cycles). At the smallest deviation from the fundamental frequency (e.g., at 0, which is equal to the fundamental frequency), the duration is the smallest (1 cycle). At intermediate deviations from the fundamental frequency (e.g., at -Δf and +Δf), intermediate durations (2 cycles) are used.

[0036] exist Figure 4 In , the modulating signal is adjusted between five overall frequencies (sometimes called frequency levels or frequency steps). Figure 4 In the example, there is a uniform difference Δf between each adjacent pair of frequency levels. This example is merely illustrative. In another possible arrangement, there may be a non-uniform difference between adjacent pairs of frequency levels.

[0037] As an example, the clock modulation circuit 34 may modulate the clock signal 38 by dividing the frequency of the clock signal by the variation (based on the modulation waveform 36). As an example, a local clock signal in the electronic device 10 may have a frequency of 80 MHz. The local clock signal may be divided by a predetermined scaling factor to obtain a clock signal for controlling the inverter 18. For example, a scaling factor of 45 may be used to obtain a 1.778 MHz clock signal for controlling the inverter 18 (e.g., 80 MHz / 45=1.778 MHz).

[0038] The modulation signal 36 may be an adjustment to a predetermined scaling factor. The modulation circuit 34 divides the local clock signal frequency by the scaling factor plus the adjustment obtained from the modulation signal 36. In other words, the frequency of the modified clock signal 40 may be equal to 80 MHz / (45+x), where x is the adjustment obtained from the modulation signal 36.

[0039] Figure 6 is a graph of an exemplary modulation signal 36 that may be used for frequency dithering. Figure 6 The value of x of the modulated signal 36 (in the aforementioned scaling scheme) over time is shown. For simplicity, Figure 6 The time axis is shown in units of cycles. Each cycle is a single cycle of the clock signal modulated using the modulation signal 36. Figure 6 In the example of , the modulated signal 36 has a value of 2 for three cycles of the clock signal, then a value of 1 for two cycles of the clock signal, then a value of 0 for one cycle of the clock signal, then a value of -1 for two cycles of the clock signal, then a value of -2 for three cycles of the clock signal, then a value of -1 for two cycles of the clock signal, then a value of 0 for one cycle of the clock signal, and then a value of 1 for two cycles of the clock signal.

[0040] When the modulation signal 36 has a value of 2 for x, the resulting frequency (e.g., of the modified clock signal) is equal to 80 MHz / (45+2)=1.702 MHz (sometimes referred to as f1). When the modulation signal 36 has a value of 1 for x, the resulting frequency is equal to 80 MHz / (45+1)=1.739 MHz (sometimes referred to as f2). When the modulation signal 36 has a value of 0 for x, the resulting frequency is equal to 80 MHz / (45+0)=1.778 MHz (sometimes referred to as f0). When the modulation signal 36 has a value of -1 for x, the resulting frequency is equal to 80 MHz / (45-1)=1.818 MHz (sometimes referred to as f3). When the modulation signal 36 has a value of -2 for x, the resulting frequency is equal to 80 MHz / (45-2)=1.860 MHz (sometimes referred to as f4).

[0041] The magnitudes of f1, f2, f0, f3, and f4 provided above are merely exemplary. Generally speaking, f1, f2, f0, f3, and f4 may have any desired magnitudes. Generally speaking, each of f1, f2, f0, f3, and f4 may have a magnitude between 100kHz and 100MHz. As another specific example, f1 may be between 1.69MHz and 1.72MHz, f2 may be between 1.72MHz and 1.75MHz, f0 may be between 1.76MHz and 1.79MHz, f3 may be between 1.80MHz and 1.83MHz, and f4 may be between 1.84MHz and 1.88MHz. Each of f1, f2, f3, and f4 may be within 15% of f0, within 10% of f0, within 8% of f0, within 5% of f0, within 3% of f0, etc.

[0042] Figure 6 The modulation frequency f of the modulation waveform m It is 0.111MHz. Figure 6 The total frequency spread of the modulated waveform is 0.158 MHz (eg, 1.860 MHz - 1.702 MHz).

[0043] Figure 7 is (e.g., during one cycle of the modulating signal) Figure 6 A histogram of the total number of cycles at each level of the modulation signal. As shown, there are 3 total cycles with a value of 2, 4 total cycles with a value of 1, 2 total cycles with a value of 0, 4 total cycles with a value of -1, and 3 total cycles with a value of -2.

[0044] Figure 8 is used (e.g., during one cycle of the modulating signal) Figure 6 A bar graph of the total number of cycles at each frequency level of the modified clock signal modified by the modulation waveform. As shown, there are 3 total cycles with a frequency of f1, 4 total cycles with a value of f2, 2 total cycles with a value of f0, 4 total cycles with a value of -f3, and 3 total cycles with a value of f4. f4 is greater than f3, f3 is greater than f0, f0 is greater than f2, and f2 is greater than f1.

[0045] like Figure 7 As shown, the value 0 (which corresponds to having Figure 8 The number of cycles at the modified clock signal of the fundamental frequency f0 in is lower than the number of cycles at any other value. Therefore, Figure 4 and Figure 6 The modulated signal 36 in reduces the total time spent at the fundamental frequency (f0). This type of modulation scheme can reduce the conducted emissions (CE) at the fundamental frequency to below the target threshold while also meeting occupied bandwidth (OBW) requirements, jitter requirements, and radiated emissions (RE) requirements.

[0046] With five frequency levels (e.g. Figure 8 The examples of modified clock signals having f1, f2, f0, f3, and f4 in FIG. 1 and FIG. 2 are merely illustrative. If desired, the modulated signal (and, correspondingly, the modified clock signal) may have three frequency levels, more than three frequency levels, more than five frequency levels, more than seven frequency levels, etc. Regardless of the number of frequency levels, the modified clock signal may spend fewer cycles at the base frequency than at other frequencies within a given cycle of the modulated signal.

[0047] According to one embodiment, an electronic device is provided, comprising: an inverter configured to receive a jittered clock signal and output a corresponding AC signal; and a control circuit configured to use a modulation signal and a clock signal to obtain the jittered clock signal, wherein the jittered clock signal has at least three different frequency levels during a repeated cycle of the modulation signal, the at least three different frequency levels comprising a base frequency, a first frequency lower than the base frequency, and a second frequency higher than the base frequency, and the jittered clock signal continues at the base frequency for a total period that is less than that at the first frequency and continues for a total period that is less than that at the second frequency during the repeated cycle of the modulation signal.

[0048] According to another embodiment, the jittered clock signal continues for a respective duration at each frequency level before advancing to a subsequent frequency level, and the durations are different for at least two of the different frequency levels.

[0049] According to another embodiment, the durations for the at least two of the different frequency levels comprise a different number of cycles.

[0050] According to another embodiment, the duration for the frequency level increases with increasing difference relative to the fundamental frequency.

[0051] According to another embodiment, the at least three different frequency levels include at least five different frequency levels.

[0052] According to another embodiment, the at least five different frequency levels include a third frequency between the first frequency and the base frequency and a fourth frequency between the second frequency and the base frequency.

[0053] According to another embodiment, the jittered clock signal lasts for fewer total periods at the base frequency than at the third frequency and for fewer total periods at the fourth frequency during the repeating cycle of the modulated signal.

[0054] According to another embodiment, the jittered clock signal lasts for fewer total periods at the first frequency than at the third frequency during the repeating cycle of the modulated signal.

[0055] According to another embodiment, the jittered clock signal lasts for fewer total periods at the second frequency than at the fourth frequency during the repeating cycle of the modulating signal.

[0056] According to another embodiment, the jittered clock signal continues at the first frequency for three cycles, then at the third frequency for two cycles, then at the base frequency for one cycle, then at the fourth frequency for two cycles, then at the second frequency for three cycles, then at the fourth frequency for two cycles, then at the base frequency for one cycle, and then at the third frequency for two cycles during the repetitive cycle of the modulated signal.

[0057] According to another embodiment, the first frequency is 1.702 MHz, the third frequency is 1.739 MHz, the base frequency is 1.778 MHz, the fourth frequency is 1.818 MHz, and the second frequency is 1.860 MHz.

[0058] According to another embodiment, the repeating cycle of the modulation signal includes 16 periods of the jittered clock signal.

[0059] According to another embodiment, the electronic device includes: a wireless charging coil, which receives the AC signal from the inverter.

[0060] According to one embodiment, a non-transitory computer-readable storage medium storing one or more programs is provided, wherein the one or more programs are configured to be executed by one or more processors of an electronic device including an inverter, wherein the inverter is configured to receive a jittered clock signal and output a corresponding AC signal, wherein the one or more programs include instructions for: using a modulation signal and a clock signal to obtain the jittered clock signal, wherein the jittered clock signal has at least three different frequency levels during a repeated cycle of the modulation signal, the at least three different frequency levels including a base frequency, a first frequency lower than the base frequency, and a second frequency higher than the base frequency, and the jittered clock signal continues at the base frequency for a total period less than at the first frequency and continues for a total period less than at the second frequency during the repeated cycle of the modulation signal.

[0061] According to one embodiment, a method for operating an electronic device is provided, the electronic device comprising: an inverter, the inverter being configured to receive a jittered clock signal and output a corresponding AC signal, the method comprising: using a modulation signal and a clock signal to obtain the jittered clock signal, the jittered clock signal having at least three different frequency levels during a repeated cycle of the modulation signal, the at least three different frequency levels comprising a base frequency, a first frequency lower than the base frequency, and a second frequency higher than the base frequency, and the jittered clock signal continues at the base frequency for a total period that is less than that at the first frequency and continues for a total period that is less than that at the second frequency during the repeated cycle of the modulation signal.

[0062] According to one embodiment, an electronic device is provided, comprising: an inverter configured to receive a jittered clock signal and output a corresponding AC signal; and a control circuit configured to use a modulation signal and a clock signal to obtain the jittered clock signal, wherein the modulation signal comprises during a repeated cycle: a first level, wherein the first level causes the jittered clock signal to have a fundamental frequency; a second level, wherein the second level causes the frequency of the jittered clock signal to decrease relative to the fundamental frequency; and a third level, wherein the third level causes the frequency of the jittered clock signal to increase relative to the fundamental frequency, wherein the modulation signal continues at the first level for a total period that is less than that at the second level and continues for a total period that is less than that at the third level during the repeated cycle.

[0063] According to another embodiment, the modulated signal continues at each level for a respective duration before advancing to a subsequent frequency level, and the duration is different for at least two of the different levels.

[0064] According to another embodiment, the durations for the at least two of the different levels comprise different numbers of cycles for the dithered clock signal.

[0065] According to another embodiment, the duration for the level increases with increasing frequency variation relative to the fundamental frequency caused by the jittered clock signal.

[0066] According to another embodiment, the increase in frequency is a first increase in frequency, the decrease in frequency is a first decrease in frequency, the modulation signal includes a fourth level, the fourth level causes a second decrease in the frequency of the jittered clock signal relative to the base frequency, the second decrease in frequency is less than the first decrease in frequency, and the modulation signal includes a fifth level, the fifth level causes a second increase in the frequency of the jittered clock signal relative to the base frequency, the second increase in frequency is less than the first increase in frequency.

[0067] According to another embodiment, the modulated signal during the repetitive cycle continues at the second level for three cycles, then at the fourth level for two cycles, then at the first level for one cycle, then at the fifth level for two cycles, then at the third level for three cycles, then at the fifth level for two cycles, then at the first level for one cycle, and then at the fourth level for two cycles.

[0068] The foregoing is merely illustrative and various modifications may be made to the embodiments described. The foregoing embodiments may be implemented individually or in any combination.

Claims

1. An electronic device, comprising: an inverter configured to receive the jittered clock signal and output a corresponding AC signal; and A control circuit configured to obtain the jittered clock signal using a modulation signal and a clock signal, wherein: The jittered clock signal has at least three different frequency levels during a repeating cycle of the modulated signal; The at least three different frequency levels include a base frequency, a first frequency lower than the base frequency, and a second frequency higher than the base frequency; and The jittered clock signal lasts at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency during the repeating cycle of the modulated signal.

2. The electronic device of claim 1, wherein the jittered clock signal continues for a respective duration at each frequency level before advancing to a subsequent frequency level, and wherein the duration is different for at least two of the different frequency levels. 3 . The electronic device of claim 2 , wherein the durations for the at least two of the different frequency levels comprise different numbers of cycles. 4 . The electronic device of claim 2 , wherein the duration for the frequency level increases as the difference relative to the fundamental frequency increases. 5 . The electronic device of claim 1 , wherein the at least three different frequency levels include at least five different frequency levels. 6 . The electronic device of claim 5 , wherein the at least five different frequency levels include a third frequency between the first frequency and the base frequency and a fourth frequency between the second frequency and the base frequency.

7. The electronic device of claim 6, wherein the jittered clock signal persists at the base frequency for fewer total cycles than at the third frequency and for fewer total cycles than at the fourth frequency during the repeating cycle of the modulated signal.

8. The electronic device of claim 7, wherein the jittered clock signal lasts for fewer total periods at the first frequency than at the third frequency during the repeating cycle of the modulated signal.

9. The electronic device of claim 7, wherein the jittered clock signal lasts for fewer total periods at the second frequency than at the fourth frequency during the repeating cycle of the modulated signal.

10. An electronic device according to claim 6, wherein the jittered clock signal lasts for three cycles at the first frequency, then for two cycles at the third frequency, then for one cycle at the base frequency, then for two cycles at the fourth frequency, then for three cycles at the second frequency, then for two cycles at the fourth frequency, then for one cycle at the base frequency, and then for two cycles at the third frequency during the repeated cycle of the modulated signal.

11. The electronic device according to claim 6, wherein the first frequency is 1.702 MHz, the third frequency is 1.739 MHz, the base frequency is 1.778 MHz, the fourth frequency is 1.818 MHz, and the second frequency is 1.860 MHz.

12. The electronic device of claim 6, wherein the repeating cycle of the modulated signal comprises 16 periods of the jittered clock signal.

13. The electronic device according to claim 1, further comprising: A wireless charging coil receives the AC signal from the inverter.

14. A non-transitory computer-readable storage medium storing one or more programs, the one or more programs configured to be executed by one or more processors of an electronic device including an inverter, the inverter configured to receive a jittered clock signal and output a corresponding AC signal, the one or more programs comprising instructions for: The jittered clock signal is obtained using a modulation signal and a clock signal, wherein: The jittered clock signal has at least three different frequency levels during a repeating cycle of the modulated signal; The at least three different frequency levels include a base frequency, a first frequency lower than the base frequency, and a second frequency higher than the base frequency; and The jittered clock signal lasts at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency during the repeating cycle of the modulated signal.

15. A method of operating an electronic device comprising an inverter, the inverter being configured to receive a jittered clock signal and output a corresponding AC signal, the method comprising: The jittered clock signal is obtained using a modulation signal and a clock signal, wherein: The jittered clock signal has at least three different frequency levels during a repeating cycle of the modulated signal; The at least three different frequency levels include a base frequency, a first frequency lower than the base frequency, and a second frequency higher than the base frequency; and The jittered clock signal lasts at the fundamental frequency for fewer total periods than at the first frequency and for fewer total periods than at the second frequency during the repeating cycle of the modulated signal.

16. An electronic device comprising: an inverter configured to receive the jittered clock signal and output a corresponding AC signal; and A control circuit configured to obtain the jittered clock signal using a modulation signal and a clock signal, wherein the modulation signal during a repeating cycle comprises: a first level causing the jittered clock signal to have a fundamental frequency; a second level that causes the frequency of the jittered clock signal to decrease relative to the base frequency; and a third level that increases the frequency of the jittered clock signal relative to the base frequency, wherein the modulated signal persists at the first level for fewer total periods than at the second level and for fewer total periods than at the third level during the repeating cycle.

17. The electronic device of claim 16, wherein the modulated signal continues at each level for a respective duration before advancing to a subsequent level, and wherein the duration is different for at least two of the different levels. 18 . The electronic device of claim 17 , wherein the durations for the at least two of the different levels comprise different numbers of cycles for the dithered clock signal.

19. The electronic device of claim 17, wherein the duration for the level increases with an increase in a frequency change relative to the fundamental frequency caused by the jittered clock signal.

20. An electronic device according to claim 16, wherein the increase in frequency is a first increase in frequency, wherein the decrease in frequency is a first decrease in frequency, wherein the modulation signal includes a fourth level, the fourth level causes a second decrease in the frequency of the jittered clock signal relative to the base frequency, the second decrease in frequency is less than the first decrease in frequency, and wherein the modulation signal includes a fifth level, the fifth level causes a second increase in the frequency of the jittered clock signal relative to the base frequency, the second increase in frequency is less than the first increase in frequency.

21. An electronic device according to claim 20, wherein the modulated signal during the repetitive cycle continues at the second level for three cycles, then at the fourth level for two cycles, then at the first level for one cycle, then at the fifth level for two cycles, then at the third level for three cycles, then at the fifth level for two cycles, then at the first level for one cycle, and then at the fourth level for two cycles.

Images