Switching frequency control for integrated resonant half-bridge isolated DC / DC with burst mode operation

Abstract

A system includes a control circuit (408) having a voltage input and a control circuit output. The control circuit (408) generates a control voltage at the control circuit output, the control voltage having a magnitude negatively correlated with a magnitude of an input voltage at the input voltage input. The VCO (430) has a VCO control input and a VCO clock output. The VCO control input is coupled to the control circuit output. The VCO (430) generates a VCO clock on the VCO clock output, the VCO clock having a frequency that varies with the control voltage. A protection circuit (440) has a first clock input, a second clock input, and a protection circuit output. The second clock input is coupled to the VCO clock output. The protection circuit (440) generates a protection circuit output signal at the protection circuit output based on a frequency difference between a clock signal at the first clock input and the VCO clock.

Description

Background Art

[0001] A voltage converter is a circuit (e.g., an integrated circuit "IC") that receives an input voltage at one voltage level and generates an output voltage at a different voltage level. Some voltage converters are isolated converters that include a current barrier between the input and the output. The current isolation barrier lacks a direct electrical connection between the circuit system on one side of the barrier and the circuit system on the other side of the barrier. One type of current isolation barrier is a transformer, which has two inductors-a primary coil for the input side of the converter and a secondary coil for the output side of the converter-and there is no direct electrical connection between the primary coil and the secondary coil. Isolated voltage converters have a wide variety of applications, such as in controller area networks (CAN), power startup bias and gate drivers, isolated sensor interfaces, etc. Summary of the invention

[0002] In one example, a system includes a control circuit having a voltage input and a control circuit output. The control circuit is configured to generate a control voltage at the control circuit output, the control voltage having a magnitude that is negatively correlated to the magnitude of an input voltage at the input voltage input. A voltage controlled oscillator (VCO) has a VCO control input and a VCO clock output. The VCO control input is coupled to the control circuit output. The VCO is configured to generate a VCO clock on the VCO clock output, the VCO clock having a frequency that varies with the control voltage. A protection circuit has a first clock input, a second clock input, and a protection circuit output. The second clock input is coupled to the VCO clock output. The protection circuit is configured to generate a protection circuit output signal at the protection circuit output based on a frequency difference between a clock signal at the first clock input and the VCO clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] To describe various examples in detail, reference is now made to the accompanying drawings, in which:

[0004] Figure 1 is a schematic diagram of a quasi-resonant voltage converter in an example.

[0005] Figure 2 is a timing diagram of the signals used in the quasi-resonant voltage converter in the example.

[0006] Figure 3 is a graph illustrating the relationship between input voltage, switching frequency and maximum output power of the converter in the described embodiment and the benefit of the described example of increasing the maximum output power at lower levels of input voltage and limiting the maximum output power at higher levels of input voltage.

[0007] Figure 4is a schematic diagram of a primary side control and power stage circuit of a quasi-resonant voltage converter including a voltage controlled oscillator control circuit and an over-power protection circuit in the described embodiments.

[0008] Figure 5 In the described embodiment Figure 4 Schematic diagram of the voltage controlled oscillator control circuit.

[0009] Figure 6 In the described embodiment Figure 4 Schematic diagram of the over-power protection circuit.

[0010] Figure 7 is a timing diagram illustrating the operation of the overpower protection circuit in the described embodiment.

[0011] Figure 8 is a graph illustrating another embodiment for providing a suitable switching frequency based on the magnitude of the input voltage. DETAILED DESCRIPTION

[0012] The examples described herein relate to a voltage converter. In one example, the voltage converter is an isolated voltage converter, which includes a transformer that isolates the "primary" side of the converter from the "secondary" side. The isolated voltage converter is configured to use a transformer to convert an input direct current (DC) voltage (VIN) received on the primary side to a different (or the same) DC voltage (VOUT) on the secondary side. The primary side includes a control and power stage, which may include a power stage that receives a DC input voltage and generates a time-varying voltage sent to the primary winding of the transformer. The time-varying voltage on the primary winding of the transformer induces a time-varying current / voltage in the secondary winding of the transformer. The secondary side includes a rectifier to convert the time-varying current / voltage from the secondary winding to an approximately DC output voltage VOUT.

[0013] Figure 1 1 is a block diagram of a system including an isolated voltage converter 100 (e.g., a quasi-resonant voltage converter) in an example. The isolated voltage converter 100 has a primary side 105 and a secondary side 107. The isolated voltage converter 100 includes a transformer 120 that can be used as an isolation transformer to isolate the primary side 105 from the secondary side 107 current. Dashed line 101 delimits the primary side 105 and the secondary side 107. There is no electrical connection between the primary side and the secondary side. The terms "primary" and "secondary" refer to the primary and secondary inductors (also referred to as coils or windings) of the transformer 120.

[0014] The primary side 105 includes a voltage input 111. The DC input voltage provided to the voltage input 111 is VIN. The secondary side 107 includes a voltage output 131. The isolated output voltage from the voltage output 131 is VOUT. The output of the rectifier 130 is coupled to an output capacitor 132 and to a load 133. The primary side 105 includes a primary side control and power stage 110. The secondary side 107 includes a rectifier 130. In one example, the rectifier 130 is a full-bridge rectifier including four diodes, but other embodiments of the rectifier are also possible. The primary side 105 has a ground Vssp. The secondary side 107 has a ground Vsss. The grounds Vssp and Vsss are isolated from each other.

[0015] The transformer 120 has a primary winding 121 and a secondary winding 122. The primary side control and power stage 110 receives Vin, and the switching nodes VP1 and VP2 of the primary side power are coupled to the terminals of the primary winding 121 of the transformer 120, as shown. The rectifier 130 is coupled to the secondary winding 122 of the transformer 120. The rectifier 130 converts the time-varying voltage from the secondary winding 122 of the transformer into a DC output voltage VOUT. The voltages VIN and VOUT do not share the same ground and are galvanically isolated from each other.

[0016] The isolated voltage converter 100 regulates the voltage level of VOUT. In one example, a feedback signal PS_ON is provided from the secondary side 107 to the primary side 105 to turn on and off the power stage within the primary side control and power circuit 110. PS_ON can be transmitted from the secondary side 107 to the primary side 105 through the transformer 120 (or another suitable current isolation data channel). The secondary side 107 may include a sensing circuit 135 to sense, for example, the magnitude of VOUT. In one example, the sensing circuit 135 asserts PS_ON as a first logic state (e.g., logic high) in response to VOUT falling below a lower threshold level, and asserts PS_ON as a second opposite logic state (e.g., logic low) in response to VOUT increasing above an upper threshold level. The voltage difference between the upper threshold level and the lower threshold level represents the output voltage ripple. In response to the assertion of PS_ON (e.g., logic high), the primary side control and power circuit 110 turns on its power stage (described below) to transfer energy to the rectifier 130, the load 133, and the output capacitor 132 through the transformer 120, thereby increasing (e.g., ramping up) VOUT. In one example, in response to the de-assertion of PS_ON (e.g., logic low), the primary side control and power circuit 110 can shut down the power stage to stop the energy transfer to the rectifier 130 through the transformer 120, thereby reducing (e.g., ramping down) VOUT as the output capacitor 132 discharges while supplying power to the load 133. In the examples described herein, even before the PS_ON signal is de-asserted, the primary side control and power circuit 110 shuts down the power stage at a higher voltage level of VIN to reduce the output power level to a safer level.

[0017] Figure 2 An example timing diagram of PS_ON is provided. When PS_ON is low, the primary side control and power circuit 110 shuts down its power stage. When PS_ON is high, the primary side control and power circuit 110 uses its power stage to generate a high frequency switching waveform between switch nodes VP1 and VP2 using a relatively high frequency clock.

[0018] Figure 3 301, 321, and 331 are included. The y-axis is the maximum output power that the converter can produce, and the x-axis is VIN. Assuming that the frequency of the switching waveform between the switching nodes VP1 and VP2 is fixed, curve 301 relates the output power to VIN. Curve 301 shows that as VIN increases, the output power also increases. Curve 301 illustrates a problem with implementations where the switching frequency of the power stage has a fixed frequency, where at lower levels of VIN (e.g., as identified by reference numeral 305), the maximum output power is relatively low. At Figure 3In the example of , at VIN equal to 9 V, the maximum output power is about 0.1 W. Such a low level of output power may not be sufficient to power a load (eg, load 133).

[0019] Curve 321 illustrates the relationship between the maximum output power and VIN of a quasi-resonant voltage converter that varies the switching frequency inversely with respect to VIN. As VIN increases, the switching frequency decreases. With such an implementation, all other conditions being equal, the maximum output power from the converter is greater at any given VIN than with an implementation using a fixed switching frequency (curve 301). The variable switching frequency implementation advantageously produces a higher level of maximum output power at a lower level of VIN (see reference numeral 325, compared to reference numeral 321), thereby providing a sufficient level of available output power even at a lower level of VIN.

[0020] However, a problem with a quasi-resonant converter that varies the switching frequency inversely with respect to VIN over all nominal levels of VIN is that at higher levels of VIN (see reference numeral 328), the maximum output power can be dangerously high in the event of a short circuit in the output of the converter (e.g., VOUT shorted to ground). Figure 3 In the example of , the maximum output power is approximately 7.8 W at VIN equal to 19 V. If VOUT is accidentally shorted to ground, the power delivered through the converter will likely damage the converter and possibly other components mounted on the same circuit board as the converter.

[0021] The examples described herein involve a primary side control and power circuit 110 that produces curve 331. At lower levels of VIN, the primary side control and power circuit 110 changes the switching frequency oppositely with respect to VIN, and thus curve 331 is at lower levels of VIN (e.g., at Figure 3 At VIN levels above 10V (in this example), the primary side control and power circuit 110 includes additional off time each time the primary side turns on its power stage, thereby reducing the duty cycle of the converter and limiting the maximum power (reference numeral 335) as shown by curve 331 above 10V relative to curves 321 and 301.

[0022] Figure 41 is a circuit schematic illustrating an implementation of the primary side control and power circuit 110. The primary side control and power circuit 110 includes a control circuit 408 coupled to a power stage 410 through a level shifter 460. In this example, the control circuit 408 includes a variable controlled oscillator (VCO) control circuit 420, a VCO 430, an over power protection (OPP) circuit 440, and a synchronization (synch) circuit 450. The VCO control circuit 420 receives VIN and generates an output signal CONTROL that is sent to the VCO 430. In the described example, CONTROL is an analog voltage that is inversely proportional to VIN. The VCO 430 receives CONTROL as an input signal and generates an output clock (VCO_CLK) whose frequency is controlled by CONTROL--the larger CONTROL, the higher the frequency of VCO_CLK, and vice versa. Therefore, VCO_CLK is a variable frequency clock signal whose frequency varies inversely with respect to VIN.

[0023] In one example, the components of the control circuit 408, the VCO control circuit 420, the VCO 430, the OPP circuit 440, and the synchronization circuit 450 are fabricated as integrated circuits on a common die. In other examples, some components of the control circuit may be fabricated on different dies. The power stage 410 may be on one of the dies described above, or on a separate die.

[0024] The OPP circuit 440 receives PS_ON, a fixed frequency clock signal (FIXED_CLK) and VCO_CLK as inputs, and generates an output signal PSON_OPP, as described herein. PSON_OPP is a digital signal and is in one of two digital states. For example, at a logic high, PSON_OPP causes the synchronization circuit 450 to use VCO_CLK to generate a gate control signal 451 for a switching transistor within the power stage 410. The switching frequency of the power stage 410 is controlled by the frequency of VCO_CLK. Because the frequency of VCO_CLK is negatively correlated with VIN, the switching frequency is also negatively correlated with VIN.

[0025] The level shifter 460 level shifts the gate control signal 451 to the appropriate voltage to turn on and off their corresponding switching transistors. The power stage 410 includes transistors M1, M2, M3, and M4. In this example, the transistors M1-M4 are n-channel field effect transistors (NFETs), but may be implemented as other types of transistors in other embodiments. The output signals G1, G2, G3, and G4 from the level shifter are the gate voltages for the transistors M1, M2, M3, and M4 within the power stage 410, respectively.

[0026] When the power stage 410 is to be turned on (e.g., PSON_OPP is asserted to a logic high to request the control circuit 408 to turn on the power stage 410), the synchronization circuit 450 responds by generating a gate control signal 451 in the following manner: turning on transistors M1 and M2 simultaneously while transistors M3 and M4 are turned off, and then turning on transistors M3 and M4 while transistors M1 and M2 are turned off. The on and off states of transistors M1-M4 repeat - transistors M1 and M2 are turned on (transistors M3 and M4 are turned off), then transistors M3 and M4 are turned on (transistors M1 and M2 are turned off), then transistors M1 and M2 are turned on again (transistors M3 and M4 are turned off), and so on. By controlling the on / off states of transistors M1-M4 in this manner, a switching voltage waveform is generated on switch nodes VP1 and VP2 that is delivered to the primary winding 121. When PSON is forced low by the secondary side, the synchronization circuit 450 responds by turning on transistors M2 and M4 (and turning off transistors M1 and M3 ) to interrupt the switching waveform and thus interrupt the transfer of energy to the secondary side 107 through the transformer 120 .

[0027] Figure 5 An example implementation of a VCO control circuit 420 is shown. In this example, the VCO control circuit 420 includes a VIN detection circuit 510, a VCO reference circuit 550, and a spread spectrum modulation (SSM) circuit 580. The VIN detection circuit 510 generates a current I4 that can be positive (in the direction of current flow as shown), 0 amperes, or negative (in the opposite direction). The VIN detection circuit 510 generates the current I4 to increase (in the positive direction) as VIN increases. The current I4 is provided to the VCO reference circuit 550, which generates a CONTROL signal to the VCO 430. The SSM circuit 580 is included to reduce electromagnetic interference (EMI).

[0028] The VIN detection circuit 510 includes a resistor R1, a capacitor C1, current sources IREF1 and IREF2 (IREF1 and IREF2 both refer to circuits that generate a reference current and the magnitude of the reference current), current mirrors MIRR1 and MIRR2, a transistor M51 (e.g., a p-channel field effect transistor PFET), and a buffer 512 (e.g., an operational amplifier). Each of the current sources can be trimmed (e.g., by a value written to a register) to generate a fixed current level. One terminal of the resistor R1 is coupled to VIN, and the other terminal of the resistor R1 is coupled to the positive (+) input of the buffer 502, to the capacitor C1, to the current source IREF1, and to the source of the transistor M51. The positive (+) input of the buffer 512 is coupled to a voltage reference (2.5V in this example, but may not be 2.5V). The negative input of the buffer 512 is also 2.5V because there is zero or very small voltage drop between the inputs of the operational amplifier. Therefore, the buffer 512 adjusts the voltage node 515 to 2.5V.

[0029] The current flowing through resistor R1 is divided between IREF1 and transistor M51. Because IREF1 is a fixed current, the current through transistor M51 (current I1) is the difference between the current through resistor R1 and IREF. In other words, current I1 is [(Vin-2.5) / R1]-IREF1. Therefore, as VIN increases, I1 increases, and as VIN decreases, I1 decreases. In one example, IREF1 is trimmed to a value of 6.5 microamperes (μA).

[0030] Current I1 is mirrored by current mirror MIRR1 (e.g., a combination of transistors configured as a current mirror) to current I2. In one example, the current mirror ratio implemented by current MIRR1 is 1:1, which means that current I2 is equal to current I1. Current I2 is then mirrored by current mirror MIRR2 to current I3. The (trimmable) current mirror ratio implemented by current MIRR2 is 1:k, which means that current I3 is equal to k times current I2. In one example, k is equal to 2, which means that current I3 is twice current I2.

[0031] Current I4 is the difference between current I3 and IREF2. In one example, IREF2 is trimmed to a value of 30μA. If I3 is greater than IREF2, current I4 is a positive current (flowing in the direction of the arrow of I4) entering resistor R10 (described below). The magnitude of positive current I4 varies with VIN. As VIN increases, more positive current I4 flows from left to right through resistor R10. If I3 is less than IREF2, current I4 is a negative current. If I3 is equal to IREF2, I4 is equal to 0 amperes, and no current flows through resistor R10. In one example, the value of R1 is 1MΩ, IREF1 and IREF2 are trimmed to 6.5μA and 30μA, respectively, and k is trimmed to a value of 2. With these component values, I4 will be 0A when VIN is equal to 24V. At VIN levels greater than 24V, current I4 will be positive and have a larger positive magnitude at larger values ​​of VIN. For example, at a VIN of 28 V, current I4 will be equal to 8 μA. At VIN levels less than 24 V, current I4 will be negative, with a more negative magnitude at smaller values ​​of VIN. For example, at a VIN of 20 V, current I4 will be equal to -8 μA.

[0032] The VCO reference circuit 550 includes a buffer 552, a capacitor C3, and resistors R2, R3, R4, R5, R6, R7, and R10. Resistors R2-R7 are connected in series between VDD (an internally generated and regulated supply voltage) and ground (AGND). Resistor R7 is trimmable and is trimmed so that when I4 is approximately 0A, the CONTROL signal sent to the VCO 430 is set to a target level for a particular input voltage VIN. The series combination of resistors R2-R7 forms a resistor divider 568 to generate a voltage VSSMHI from resistor R3 and a voltage VSSMLO from resistor R4 for the SSM circuit 580. The SSM circuit 580 generates a spread spectrum voltage ramp 585 that is sent to the positive input of the buffer 552. The negative input of the buffer 552 will also be equal to the voltage ramp 585. Resistor R10 is coupled between the negative input of the buffer 552 and the output of the buffer 552. Depending on the magnitude of VIN, current I4 flows in one direction or in the other direction through resistor R10, as described above. If current I4 is a positive current (flowing in the direction of the arrow of I4), a voltage drop will occur across resistor R10, where the voltage at the output of buffer 552 is less than the voltage at the negative input of the buffer. The magnitude of the voltage drop is equal to the product of I4 and the resistance of resistor R10 (I4×R10). As current I4 becomes more negative, the voltage at the output of buffer 552 becomes larger relative to ground (AGND).

[0033] If current I4 is a negative current (arrow relative to I4), a voltage drop also occurs across resistor R10, where the voltage at the output of buffer 552 is greater than the voltage at the negative input of the buffer. The magnitude of the voltage drop is equal to I4×R10. The more negative the current I4, the greater the voltage at the output of buffer 552 will be. The output voltage of buffer 552 is the CONTROL signal described above, which is provided to VCO 430.

[0034] The SSM circuit 580 generates a spread spectrum voltage ramp 585. In one example, the average level of the spread spectrum voltage ramp is equal to the voltage [(VSSMHI-VSSMLO) / 2+VSSMLO] (divider voltage) from the voltage divider 568, where the peak voltage 586 is approximately 200 mV higher than the divider voltage, and where the valley voltage 587 is approximately 200 mV lower than the divider voltage. By modulating the voltage 585 (which is also the voltage on the left terminal of the resistor R10), the VCO 430 will generate a frequency that will change linearly with the voltage ramp 585, thereby generating less EMI than using a fixed voltage instead of a voltage ramp. The SSM circuit 580 includes switching current sources 581 and 582. When the switching current source 581 is turned on, current flows to charge the capacitor C4, thereby causing the voltage across the capacitor C4 to increase (ramp up) linearly. When the switching current source 582 is turned on, current flows from the capacitor C4, thereby discharging the capacitor C4 and causing the voltage across the capacitor C4 to decrease linearly (ramp down). The voltage across the capacitor C4 is the spread spectrum ramp 585. The comparator 583 outputs a signal to the break-before-make circuit 584 to indicate when the spread spectrum ramp 585 reaches its peak 586 or its valley 587. The break-before-make circuit 584 turns the switching current sources 581 and 582 on and off by first turning off the current source that is currently turned on and then turning on the other current source.

[0035] Figure 6610 . It is an example implementation of the OPP circuit 440. In this example, the OPP circuit 440 includes a down counter 610, an up counter 630, logic circuits 601 and 621, and a synchronizer 620. The logic circuit 601 includes a synchronizer 614, data (D) flip-flops 616 and 618, AND gates 617 and 619, and an OR gate 612. The logic circuit 621 includes a synchronizer 634 and a D flip-flop 632. The PS_ON signal is coupled to the D input of the flip-flop 618, one input of the AND gate 619, and the synchronizer 634 and is coupled to the enable (EN) input of the down counter 610. When the EN input is asserted high, the down converter 610 is caused to count, and when EN is low, the counting function of the down counter is disabled and its "non-zero" output is forced to be low. In another example, the counter 610 can be implemented as an up counter. VCO_CLK is coupled to the clock inputs of synchronizers 620 and 634, up-counter 630, and D flip-flop 632. FIXED_CLK is coupled to the clock inputs of down-counter 610, synchronizer 614, and flip-flops 616 and 618.

[0036] Because there are two separate clock domains in OPP circuit 440, synchronizers 614, 620 and 634 are included. One clock domain is VCO_CLK, and the other clock domain is FIXED_CLK. For example, the D input of synchronizer 614 is generated based on VCO_CLK, but the clock provided to synchronizer 614 is FIXED_CLK. When data generated in a clock domain is locked with clocks in different clock domains, synchronizers prevent metastability problems. In an example, each synchronizer includes two D flip-flops connected in series.

[0037] The Q output of synchronizer 614 (signal DONE_FC) is coupled to the D input of flip-flop 616 and one input of AND gate 617. The NOT-Q output of flip-flop 616 is connected to the other input of AND gate 617, and the output of AND gate 617 (signal DONE_RISE, which pulses high for one FIXED_CLK cycle in response to the rising edge of DONE_FC) is coupled to the input of OR gate 612. The NOT-Q output of flip-flop 618 is connected to the other input of AND gate 619, and the output of AND gate 619 (signal PSON_RISE, which also pulses high for one FIXED_CLK cycle in response to the rising edge of PS_ON) is coupled to the other input of OR gate 612. The output of OR gate 612 (signal LOAD) is coupled to the LOAD all ones input of down counter 610, which is a 5-bit counter in one example. In one example, in response to LOAD being logic high, down counter 610 loads its starting count value as all logic ones. The output of down counter 610 is labeled "non-zero" and is logic high (1) if any count bit is 1. The "non-zero" output becomes logic low (0) if and when down counter 610 reaches 0. The "non-zero" output of down counter 610 is coupled to the D input of synchronizer 620. The Q output of flip-flop 620 is Figure 4 The PSON_OPP signal shown in FIG.

[0038] The Q output (signal PSON_VCO) of synchronizer 634 is coupled to the EN input of up-counter 630. When enabled (PSON_VCO is logic high), up-counter 630 increases its count value after each rising edge of VCO_CLK. Up-counter 630 has an "equal to MAX" output and a "greater than or equal to MAX-3" output. The "equal to MAX" output is logic low until the up-counter reaches its final count value. In one example, the up-counter is a 6-bit counter that counts from 0 to 63 (decimal). After reaching the count value of 63, the "equal to MAX" output changes from 0 to 1. The "equal to MAX" output is coupled to the restart input of the up-counter. When the MAX output is asserted high, up-counter 630 resets its count value to 0 and starts counting again. The "greater than or equal to MAX-3" output (signal DONE) is logic low until the count value of the up-counter reaches its maximum value minus 3, which helps to ensure that the DONE signal from the up-counter is longer than one VCO_CLK pulse. DONE is coupled to the D input of flip-flop 632 , and the Q output of flip-flop 632 (signal DONEVCO) is coupled to the D input of synchronizer 614 .

[0039] During operation, the positive assertion (e.g., high) of PS_ON enables the down counter 610, and the up counter 630 is enabled by the synchronizer 634. In one example, the frequency of FIXED_CLK is higher than half of the variable frequency of VCO_CLK. In one example, the frequency of FIXED_CLK is 32MHz, and the frequency of VCO_CLK ranges from 68MHz for low level VIN to 36MHz for higher level VIN. Because VCO_CLK has a higher frequency than FIXED_CLK, the up counter (which counts the pulses of VCO_CLK) is an n-bit up counter, and the down counter is an m-bit down counter, where n is greater than m. In one example, n is 6 bits, and m is 5 bits. VCO_CLK counts at twice the clock cycle because counter 630 has one more bit than counter 610.

[0040] At low VIN (for example, Figure 3 In the example of VIN being less than 10V, the frequency of VCO_CLK will be high enough so that the up-counter 630 will cause DONE and DONEVCO to be logic 1 before the down-counter 610 reaches its terminal count value (0). DONEVCO, forced high by the D flip-flop 632, is provided to the D input of the synchronizer 614, and the DONE_RISE pulse is high through the D flip-flop 616. The output (LOAD) of the OR gate 612 also pulses high at this time, thereby causing the down-counter 610 to be reloaded. As long as VIN is at a low enough level so that the up-counter 630 reaches its own terminal count before the down-counter reaches its terminal count, the down-counter 610 will not reach its terminal count value. In this case, the "non-zero" output of the down-counter 610 remains logically high, and through the synchronizer 620, PSON_OPP remains logically high.

[0041] At higher levels of VIN (for example, Figure 3When the up-counter 630 reaches its final count value (e.g., 0), the frequency of VCO_CLK becomes low enough so that the down-counter 610 will reach its final count value before the up-counter 630 reaches its final count value. When the down-counter 610 reaches its final count value (e.g., 0), the "non-zero" output changes from a logic high to a logic low. After the next pulse of VCO_CLK, the synchronizer 620 forces PSON_OPP to be low. Then, when the up-counter 630 finally reaches its final value, DONE is forced to be high, which forces DONEVCO to be high through the D flip-flop 632, thereby (through the synchronizer 614, the D flip-flop 616, the "AND" gate 617 and the "OR" gate 612) causing the down-counter to be reloaded, and at this time "non-zero" is forced to be high again. The length of time that PSON_OPP is low varies with the frequency difference between FIXED_CLK and VCO_CLK.

[0042] Figure 7 An example timing diagram is shown including three instances of PS_ON and PSON_OPP 701, 702, and 703. PSON_OPP 701 corresponds to a relatively low VIN (e.g., less than 10V). In this case, PSON_OPP is substantially equivalent to PS_ON. The delay between the edges of PS_ON and PSON_OPP varies with the Figure 6 702 and PSON_OPP 703 are two examples of PSON_OPP under two different levels of VIN for the case where VIN is a higher value, for which an additional off time is added to avoid the large maximum output power capacity of the converter as described above. The VIN of PSON_OPP 703 is higher than the VIN of PSON_OPP 702. In all three cases, the PSON_OPP signal is converted to high (in response to the rising edge 711 of the rising edge 709 of PS_ON). The falling edge 712 of PSON_OPP 702 is caused by the down counter 610 as described above before the falling edge 714 of PS_ON. The timing of the falling edge 712 of PSON_OPP varies indirectly with the magnitude of VIN. Therefore, the off time of the converter is longer than the case where only PS_ON is used to turn on and off the converter. The off time 704 at medium VIN is less than the off time 706 at higher VIN.

[0043] Figure 8 Another example is shown where at VIN below a lower threshold (Vmin), the converter implements a higher switching frequency (Fswmax). Figure 8It is also illustrated that for VIN above an upper threshold (Vmax), the converter implements a lower switching frequency (Fswmin). For VIN between the lower threshold Vmin and the upper threshold Vmax, the converter implements an inverse linear relationship between VIN and switching frequency as shown (e.g., the switching frequency decreases linearly as VIN increases). In one example, the VIN detection circuit 510 implements Figure 8 The current mirror MIRR2 may include a clamp circuit that limits the current I3 to a maximum value when VIN is greater than Vmax, and also limits I3 to a minimum value when VIN is less than Vmin.

[0044] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0045] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or through a combination thereof.

[0046] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnects or their ends between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components.

[0047] Circuits or devices described herein as including certain components may alternatively be adapted to be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0048] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuitry. For example, field effect transistors (FETs) (e.g., NFETs, PFETs), bipolar junction transistors (BJTs—e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0049] Reference herein to a FET being "on" means that there is a conduction channel of the transistor and drain current can flow through the transistor. Reference herein to a FET being "off" means that there is no conduction channel and drain current does not flow through the FET. However, an "off" FET may have current flowing through the body diode of the transistor.

[0050] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the displayed resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0051] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0052] The use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "approximately" or "substantially" before a parameter means within + / -10% of the parameter.

[0053] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A system comprising: a control circuit having a voltage input and a control circuit output, the control circuit being configured to generate a control voltage at the control circuit output having a magnitude that is inversely related to a magnitude of an input voltage at the input voltage input; a voltage controlled oscillator (VCO) having a VCO control input coupled to the control circuit output and a VCO clock output, the VCO control input being configured to generate a VCO clock at the VCO clock output, the VCO clock having a frequency that varies with the control voltage; as well as A protection circuit having a first clock input, a second clock input coupled to the VCO clock output, and a protection circuit output, the second clock input being configured to generate a protection circuit output signal at the protection circuit output based on a frequency difference between a clock signal at the first clock input and the VCO clock.

2. The system of claim 1, wherein the control circuit, VCO, and protection circuit are at least part of a voltage converter, and the protection circuit is configured to inversely change a duty cycle of the voltage converter relative to the input voltage.

3. The system of claim 2, wherein the duty cycle is based on the frequency difference between the clock signal at the first clock input and the VCO clock.

4. The system of claim 1, wherein the protection circuit comprises: a first counter comprising a first clock input coupled to the first clock input; as well as A second counter includes a second clock input coupled to the VCO clock output. 5 . The system of claim 4 , wherein the first counter is one of an up counter or a down counter, and the second counter is the other of an up counter or a down counter.

6. The system of claim 1, wherein the control circuit comprises: an input voltage input detection circuit having a current output, the input voltage input detection circuit being configured to generate an output current at the current output that is proportional to the input voltage; and A VCO reference circuit has a current input coupled to the current output, the VCO reference circuit being configured to generate the control voltage based on the output current.

7. The system of claim 1, wherein the control circuit is configured to: for a range of the input voltage between a first threshold and a second threshold, inversely varying the magnitude of the control voltage; for an input voltage greater than the second threshold, setting the magnitude of the control voltage at a first voltage level; and For input voltages less than the first threshold, the magnitude of the control voltage is set at a second voltage level.

8. The system of claim 7, wherein the first threshold is less than the second threshold, and the first voltage level is less than the second voltage level.

9. A voltage converter, comprising: a control circuit having a voltage input and a control circuit output, the control circuit being configured to generate a control voltage at the control circuit output having a magnitude that is inversely related to a magnitude of an input voltage at the input voltage input; a voltage controlled oscillator (VCO) having a VCO control input coupled to the control circuit output and a VCO clock output, the VCO control input being configured to generate a VCO clock at the VCO clock output, the VCO clock having a frequency that varies with the control voltage; as well as A protection circuit is coupled to the VCO, the protection circuit being configured to change a duty cycle of the voltage converter based on the magnitude of the input voltage.

10. The voltage converter of claim 9, wherein the protection circuit includes a first clock input, and the protection circuit is configured to change the duty cycle based on a frequency difference between a clock signal at the first clock input and the VCO clock.

11. The voltage converter of claim 10, wherein the protection circuit comprises: a first counter comprising a first counter clock input coupled to the first clock input; as well as A second counter includes a second counter clock input coupled to the VCO clock output. 12 . The voltage converter of claim 11 , wherein the first counter is one of an up counter or a down counter, and the second counter is the other of an up counter or a down counter. 13 . The voltage converter of claim 11 , wherein the clock signal at the first clock input is configured to receive a clock signal having a frequency higher than a frequency of the VCO clock.

14. The voltage converter of claim 9, wherein the control circuit comprises: an input voltage input detection circuit having a current output, the input voltage input detection circuit being configured to generate an output current at the current output that is proportional to the input voltage; and A VCO reference circuit has a current input coupled to the current output, the VCO reference circuit being configured to generate the control voltage based on the output current.

15. The voltage converter of claim 9, wherein the control circuit is configured to: for a range of the input voltage between a first threshold and a second threshold, inversely varying the magnitude of the control voltage; for an input voltage greater than the second threshold, setting the magnitude of the control voltage at a first voltage level; and For input voltages less than the first threshold, the magnitude of the control voltage is set at a second voltage level. 16 . The voltage converter of claim 15 , wherein the first threshold is less than the second threshold, and the first voltage level is less than the second voltage level.

17. The voltage converter of claim 9, wherein the voltage converter is an isolated voltage converter.

18. A circuit comprising: a first counter having a first enable input and a first clock input; a second counter having a second enable input and a second clock input; a first logic circuit having a first logic circuit clock input, a first logic circuit control input, and a second logic circuit control input, the first logic circuit being configured to enable the first counter in response to a signal at the first logic circuit control input; as well as a second logic circuit having a second logic circuit clock input and a second logic circuit control output, the second logic circuit control output being coupled to the first control input, the second logic circuit being configured to enable the second counter in response to the signal at the first logic circuit control input, the second logic circuit being configured to generate a control signal at the second logic circuit control output in response to the second counter reaching a terminal count value.

19. The circuit of claim 18, wherein the first counter is one of an up counter or a down counter, and the second counter is the other of an up counter or a down counter.

20. The circuit of claim 18, wherein the first clock input is configured to receive a fixed frequency clock and the second clock input is configured to receive a variable frequency clock.

Images