Image forming apparatus

Abstract

According to the invention, black level output based on incidence of high-brightness light can be prevented. The imaging device includes: a signal line whose potential varies according to a charge stored by a current flowing when a signal is read out from a pixel; a signal line reset transistor that resets a signal line potential; a signal line reset level generation unit that generates a reset level of the signal line potential; a signal line clipping transistor clipping the signal line potential; and a signal line clipping voltage setting unit that sets a signal line clipping voltage for generating a clipping voltage of the signal line potential. The signal line reset level generation unit may be a diode-connected transistor.

Description

Technical Field

[0001] The present technology relates to an imaging device, and more particularly to an imaging device capable of preventing black level output due to incidence of high-brightness light. Background Art

[0002] A capacitive load readout method is known that uses the capacitance of a load for a source follower when reading out a signal from a pixel. As such a capacitive load readout method, for example, an imaging device has been proposed that causes a constant current to flow to an output line through a constant current source after a voltage of the output line is reset by a reset unit, and connects the source of an amplifying transistor to the output line (for example, see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent document 1: JP 2021-40270 A. Summary of the invention

[0006] Technical issues

[0007] However, according to the above conventional technology, when high brightness light such as sunlight is incident, charge overflows from the photodiode to the floating diffusion. Therefore, the P phase level (also referred to as the reset level) decreases and there is no difference between the P phase level and the D phase level (also referred to as the signal level), and therefore, even if the P phase level is originally a white level, a phenomenon (called a sunspot phenomenon) of outputting a black level occurs.

[0008] In view of such a situation, an object of the present technology is to prevent the output of a black level based on the incidence of high-brightness light.

[0009] Solution to the problem

[0010] The present technology has been made to solve the above-mentioned problems, and a first aspect of the present technology is an imaging device including: a signal line whose potential changes based on a charge stored according to a current flowing when a signal is read out from a pixel; a signal line reset transistor that resets the potential of the signal line; a signal line reset level generating unit that generates a reset level of the potential of the signal line; a signal line clip transistor that clips the potential of the signal line; and a signal line clip voltage setting unit that sets a signal line clip voltage for generating a clip voltage of the potential of the signal line. Therefore, an effect that the potential of the signal line is clipped without depending on the amount of incident light can be provided.

[0011] Furthermore, according to the first aspect, the potential of the signal line can be the potential of the parasitic capacitance of the signal line. Therefore, it is possible to provide an effect that the capacitance load can be read without adding a capacitance element to the signal line.

[0012] In addition, according to the first aspect, the pixel may include a photodiode, a transfer transistor that transfers the charge stored in the photodiode to a floating diffusion, a reset transistor that resets the floating diffusion, an amplifier transistor that outputs a signal corresponding to the potential of the floating diffusion, and a selection transistor connected between the amplifier transistor and the signal line. Therefore, it is possible to provide an effect of forming a source follower relative to the pixel when reading out a signal from the pixel.

[0013] Furthermore, according to the first aspect, the signal line reset level generating unit may include a diode-connected transistor. Therefore, it is possible to provide an effect of increasing the potential of the signal line according to the forward voltage of the diode-connected transistor when resetting the signal line.

[0014] Furthermore, according to the first aspect, the imaging device may further include a driver for driving the signal line reset transistor. Therefore, the effect of turning on / off the signal line reset transistor can be provided.

[0015] Furthermore, according to the first aspect, the imaging device may further include a signal line clip selection transistor connected between the signal line and the signal line clip transistor. Therefore, it is possible to provide an effect of controlling the clip level applied to the signal line.

[0016] In addition, according to the first aspect, the imaging device may further include: a first chip on which pixels, signal line clipping transistors and signal line clipping selection transistors are already formed; and a second chip on which the first chip is stacked and on which a signal line reset transistor, a signal line reset level generating unit and a signal line clipping voltage setting unit are formed. Therefore, it is possible to provide an effect of reducing the variation in the characteristics of the signal line clipping transistor and the signal line clipping selection transistor and the characteristics of the pixel transistor.

[0017] Furthermore, according to the first aspect, the gate length and gate width of the signal line clipping transistor may be equal to the gate length and gate width of the amplifying transistor of the pixel, and the gate length and gate width of the signal line clipping selection transistor may be equal to the gate length and gate width of the selection transistor of the pixel. Therefore, the effect that the characteristics of the signal line clipping transistor and the characteristics of the amplifying transistor of the pixel become equal, and the characteristics of the signal line clipping selection transistor and the characteristics of the selection transistor of the pixel become equal can be provided.

[0018] Furthermore, according to the first aspect, the signal line can be driven simultaneously by the signal line limit selection transistor and the amplification transistor of the pixel. Therefore, the effect of increasing the driving force of the signal line can be provided.

[0019] According to the first aspect, the imaging device may further include a comparator that compares the potential of the signal line with the ramp signal. Therefore, it is possible to provide an effect that a signal read out from a pixel can be detected based on the potential of the signal line.

[0020] According to the first aspect, the imaging device may further include a comparator for comparing the potentials of signal lines provided to different columns. Therefore, it is possible to provide an effect of detecting the edge of the object by reading out the capacitive load.

[0021] In addition, according to the first aspect, the imaging device may further include:

[0022] A first DC cut-off capacitor connected to a first input terminal of a comparator; a second DC cut-off capacitor connected to a second input terminal of the comparator; and an auto-zero control unit that controls the charges stored in the first DC cut-off capacitor and the second DC cut-off capacitor, respectively, so that the first input and the second input of the comparator are balanced during the auto-zero period. Thus, an effect of reducing fixed pattern noise can be provided.

[0023] Furthermore, according to the first aspect, the signal line clip selection transistor can be turned off after the auto-zero period. Therefore, it is possible to provide an effect that when the signal line is clipped, the non-inverting input and the inverting input of the comparator are adjusted to be balanced.

[0024] Furthermore, according to the first aspect, the signal line clip voltage can be lower than the reset level of the pixel. Therefore, it is possible to provide an effect that the reset level of the pixel can be read out.

[0025] In addition, according to the first aspect, the imaging device may further include a constant current transistor, which may be electrically connected to the signal line, and a constant current may flow based on a source follower formed between the constant current transistor and the pixel. Therefore, an effect that a constant current can be read out when no capacitive load is read out can be provided.

[0026] In addition, according to the first aspect, when the constant current is read out using the constant current transistor, the constant current transistor can be turned on, and when the capacitive load is read out using the signal line reset level generating unit, the constant current transistor can be turned off. Therefore, it is possible to provide an effect of switching between the reading of the capacitive load and the reading of the constant current.

[0027] Furthermore, according to the first aspect, the signal line slice voltage setting unit can generate a plurality of slice levels. Therefore, it is possible to provide an effect that the slice level of the signal line is adjusted.

[0028] Furthermore, according to the first aspect, the signal line slice voltage setting unit may include a resistor ladder circuit and a first selector that switches the divided voltage generated by the resistor ladder circuit. Therefore, an effect that the slice level of the signal line is switched can be provided.

[0029] Furthermore, according to the first aspect, the signal line reset level generating unit may include a second selector that switches the divided voltage generated by the resistor ladder circuit. Thus, the reset level and the slice level of the signal line can be switched separately.

[0030] In addition, according to the first aspect, the imaging device may further include a pixel array unit, wherein the pixels are arranged in a matrix in the row direction and the column direction, the signal line may be provided for each column, and the signal line reset transistor and the signal line limit transistor may be provided for each signal line. Therefore, it is possible to provide an effect that the potential of the signal line is reset and limited for each signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram showing a configuration example of a camera to which the imaging device according to the first embodiment is applied.

[0032] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment.

[0033] Figure 3 is a block diagram showing an example of a circuit configuration provided to a pixel of the solid-state imaging device according to the first embodiment.

[0034] Figure 4 is a cross-sectional view showing a configuration example of a pixel array unit provided to the solid-state imaging device according to the first embodiment.

[0035] Figure 5 is a cross-sectional view showing a modified example of the pixel array unit provided to the solid-state imaging device according to the first embodiment.

[0036] Figure 6 is a diagram showing a configuration example of a signal readout circuit for one column according to the first embodiment.

[0037] Figure 7 : is a diagram showing a first example of a waveform of each unit when the imaging device according to the first embodiment reads out a signal.

[0038] Figure 8 : is a diagram showing a second example of the waveform of each unit when the imaging device according to the first embodiment reads out a signal.

[0039] Fig. 9 is a diagram showing a configuration example of a signal readout circuit for one column according to the second embodiment.

[0040] Fig.10 is a diagram showing a configuration example of a signal readout circuit for three columns according to the third embodiment.

[0041] Fig.11 is a diagram showing a configuration example of a signal readout circuit for one column according to the fourth embodiment.

[0042] Fig.12 : is a diagram showing an example of a waveform of each cell when the signal readout circuit according to the fourth embodiment reads out a constant current.

[0043] Fig.13 is a diagram showing a configuration example of a signal readout circuit for one column according to the fifth embodiment.

[0044] Fig.14 : is a diagram showing an example of a waveform of each cell when a signal is read out according to the fifth embodiment.

[0045] Fig.15 is a diagram showing a configuration example of a signal readout circuit for one column according to the sixth embodiment.

[0046] Fig.16 : is a diagram showing an example of a waveform of each cell when a signal is read out according to the sixth embodiment.

[0047] Fig.17 is a diagram showing a configuration example of a signal readout circuit for one column according to a seventh embodiment.

[0048] Fig.18 is a diagram showing a configuration example of a signal readout circuit for two columns according to an eighth embodiment.

[0049] Fig.19 : is a diagram showing a configuration example of a comparator applied to a signal readout circuit according to the eighth embodiment.

[0050] Fig. 20 : is a diagram showing an example of a waveform of each unit when the imaging device according to the eighth embodiment reads out a signal.

[0051] Fig.21 : is a diagram showing an example of a waveform of each unit when an imaging device according to a comparative example of the eighth embodiment reads out a signal.

[0052] Fig. 22 is a diagram showing a configuration example of a signal readout circuit for one column according to a ninth embodiment.

[0053] Fig.23 : is a diagram showing a configuration example of a signal readout circuit for one column according to a tenth embodiment.

[0054] Fig.24is a perspective view showing a configuration example of an imaging device according to an eleventh embodiment.

[0055] Fig.25 is a block diagram showing a schematic configuration example of a vehicle control system.

[0056] Fig.26 : is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0057] A mode for carrying out the present technology (hereinafter also referred to as an "embodiment") will be described below. The description will be given in the following order.

[0058] 1. First Embodiment (Example of Connection of Signal Line Limiter Transistors via Signal Line Limiter Selection Transistors Electrically Connected to Vertical Signal Lines)

[0059] 2. Second Embodiment (Example in which a signal line limiter transistor and a signal line limiter selection transistor are provided to an upper chip provided with pixels and a signal line limiter voltage setting unit is provided to a lower chip)

[0060] 3. Third Embodiment (an example in which a driver for driving a signal line slice selection transistor and a driver for driving a signal line reset transistor are provided).

[0061] 4. Fourth Embodiment (Example of a Series Circuit in which a Constant Current Transistor is Connected in Parallel to a Signal Line to a Reset Transistor and a Diode-Connected Transistor)

[0062] 5. Fifth Embodiment (Example in which a signal line limiter transistor limits the potential of a signal line and selects a signal line)

[0063] 6. Sixth Embodiment (Example in which the amplifier transistor of the optical black (OB) pixel is used as the signal line limiter transistor and the selection transistor of the OB pixel is used as the signal line limiter selection transistor)

[0064] 7. Seventh Embodiment (Example in which a resistance ladder circuit is used to set a slice level of a signal line and to set a reset level of a signal line)

[0065] 8. Eighth Embodiment (Example in which readout of a capacitive load using a series circuit of a signal line transistor and a diode-connected transistor is applied to edge detection)

[0066] 9. Ninth Embodiment (Example in which readout of a capacitive load using a series circuit of a signal line transistor and a diode-connected transistor is applied to a unit in which an amplification transistor is shared among four photodiodes)

[0067] 10. Tenth Embodiment (Example in which readout of a capacitive load using a series circuit of a signal line transistor and a diode-connected transistor is applied to binning readout)

[0068] 11. Eleventh Embodiment (Example of stacking substrates on which a solid-state imaging device is formed).

[0069] 12. Application examples for mobile objects

[0070] <1. First Embodiment>

[0071] Figure 1 is a block diagram showing a configuration example of a camera to which the imaging device according to the first embodiment is applied.

[0072] exist Figure 1 , the camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to each other via a bus 108. Note that the camera 100 may be used alone, or may be incorporated in a portable terminal such as a smartphone, or may be incorporated in an authentication device or a monitoring device.

[0073] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an image to be mapped (subject image) on a light receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focusing lens, a zoom lens, an aperture, etc. The optical system 101 may include a plurality of lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0074] The solid-state imaging device 102 converts light from an object into an electric signal for each pixel, digitizes the electric signal, and outputs the digitized signal. For example, the solid-state imaging device 102 may be a complementary metal oxide semiconductor (CMOS) image sensor, or may be a charge coupled device (CCD).

[0075] The imaging control unit 103 controls imaging of the solid-state imaging device 102 based on a command from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, and the like of the solid-state imaging device 102.

[0076] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing is, for example, gamma correction, white balance processing, sharpness processing, grayscale conversion processing. The image processing unit 104 may include a processor that performs processing based on software.

[0077] The storage unit 105 stores a captured image captured by the solid-state imaging device 102, and stores imaging parameters of the solid-state imaging device 102. In addition, the storage unit 105 may store a program for causing the camera 100 to operate based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0078] The display unit 106 displays a captured image or displays various information for supporting an imaging operation. The display unit 106 may be a liquid crystal display, or may be an organic electroluminescence (EL) display.

[0079] The operation unit 107 provides a user interface for operating the camera 100. The operation unit 107 may include buttons, dials, and switches provided to the camera 100. The operation unit 107 may be configured by a touch panel together with the display unit 106.

[0080] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment.

[0081] exist Figure 2 In the embodiment, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, a control circuit 116, and a signal line limit voltage setting circuit 117.

[0082] The pixel array unit 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along a row direction (also referred to as a horizontal direction) and a column direction (also referred to as a vertical direction). Each pixel 120 may be configured with a source follower between each pixel 120 and a column readout circuit 113 when reading out a signal. Each pixel 120 is connected to a horizontal drive line 131 per row, and is connected to a vertical signal line 132 per column. The horizontal drive line 131 drives each pixel 120 per row when reading out a signal from each pixel 120. The vertical signal line 132 transmits a potential based on a charge stored according to a current flowing when reading out a signal from each pixel 120 to the column signal processing unit 114 per column. Note that the vertical signal line 132 is an example of a signal line described in the claims.

[0083] The vertical scanning circuit 112 scans the readout target pixels 120 in the column direction. The vertical scanning circuit 112 may be configured using a vertical register.

[0084] The column readout circuit 113 may configure a source follower between the column readout circuit 113 and each pixel 120 when reading out a signal from each pixel 120. At this time, the column readout circuit 113 may change the potential of the vertical signal line 132 based on the charge retained in the pixel 120. The column readout circuit 113 may support the readout of the capacitive load. The column readout circuit 113 may also support the readout of the constant current. In addition, the column readout circuit 113 sets the potential of the vertical signal line 132 to the clipping level when the P phase VSL of the readout of the capacitive load is set. In the case where the charge overflows from the photodiode to the floating diffusion, the clipping level may be set to a potential higher than the potential of the vertical signal line 132 when the signal is read out from the pixel 120. In addition, the column readout circuit 113 may also set the potential of the vertical signal line 132 to the clipping level when the P phase VSL of the constant current readout is set.

[0085] The column signal processing unit 114 processes a signal transmitted to the column direction from each pixel 120. For example, the column signal processing unit 114 may perform a correlated double sampling (CDS) process based on the signal transmitted to the column direction from each pixel 120. In addition, the column signal processing unit 114 may perform an analog-to-digital (AD) conversion process based on the signal transmitted to the column direction from each pixel 120, and output an imaging signal Gout.

[0086] The horizontal scanning circuit 115 scans the readout target pixels 120 in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0087] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.

[0088] The signal line slice level setting circuit 117 sets a signal line slice voltage Vb for generating a slice level of the potential of the vertical signal line 132. The signal line slice voltage Vb is supplied to the column readout circuit 113 and is used to generate a slice level of the potential of the vertical signal line 132. The signal line slice level setting circuit 117 can be used to generate a reset level of the potential of the vertical signal line 132.

[0089] Figure 3 is a block diagram showing an example of a circuit configuration provided to a pixel of the solid-state imaging device according to the first embodiment.

[0090] exist Figure 3, the pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplifying transistor 124, a selecting transistor 125, and a floating diffusion 126. As the transfer transistor 122, the reset transistor 123, the amplifying transistor 124, and the selecting transistor 125, metal oxide semiconductor (MOS) transistors may be used.

[0091] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion 126 via the transfer transistor 122. In addition, the floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123. In addition, the power supply Vdd is connected to the vertical signal line 132 via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion 126.

[0092] The gate of the transfer transistor 122 is applied with a transfer signal ΦTG. The gate of the reset transistor 123 is applied with a pixel reset signal ΦPRT. The gate of the selection transistor 125 is applied with a selection signal ΦSEL. The transfer signal ΦTG, the pixel reset signal ΦPRT and the selection signal ΦSEL may be connected to the gate of the transfer transistor 122 via Figure 2 The horizontal drive line 131 in is sent to each pixel 120.

[0093] Next, when the transfer transistor 122 is turned on, the charge stored in the photodiode 121 is transferred to the floating diffusion 126. In addition, when the selection transistor 125 is turned on, the source potential of the amplifier transistor 124 is changed according to the potential of the floating diffusion 126. In addition, the source potential of the amplifier transistor 124 is applied to the vertical signal line 132 via the selection transistor 125, and is transmitted via the vertical signal line 132. In addition, when the reset transistor 123 is turned on, the charge stored in the floating diffusion 126 is discharged.

[0094] Figure 4 : is a cross-sectional view showing a configuration example of a pixel array unit provided to the solid-state imaging device according to the first embodiment. Note that, Figure 4 An example of a front-illuminated solid-state imaging device is shown. Figure 4 A configuration example of three pixels is shown.

[0095] exist Figure 4 In the embodiment, a photodiode 232 is formed on a semiconductor substrate 231 of each pixel 120. The material of the semiconductor substrate 231 may be Si, InGaAs, or InP.

[0096] The gate electrode 214 and the wiring layer 210 are formed on the semiconductor substrate 231. The gate electrode 214 is formed on the semiconductor substrate 231 via the gate insulating film 213. The sidewall 215 is formed on the sidewall of the gate electrode 214. For example, polysilicon doped with impurities can be used as the material of the gate electrode 214. For example, a silicon oxide film can be used as the material of the gate insulating film 213. For example, a silicon oxide film or a silicon nitride film can be used as the material of the sidewall 215.

[0097] The gate electrode 214 may be used for a pixel transistor. The pixel transistor includes Figure 3 The transfer transistor 122, the reset transistor 123, the amplifying transistor 124 and the selecting transistor 125 are included in the embodiment.

[0098] A wiring 216 is formed on the gate electrode 214 . Figure 4 An example of three-layer wiring is shown. At this time, an opening portion OP1 that allows light to be incident on the photodiode 232 is provided on the wiring 216. The gate electrode 214 and the wiring 216 are insulated with an insulating layer 217 interposed therebetween. For example, a silicon oxide film can be used for the insulating layer 217. For example, a metal such as Al or Cu can be used as a material for the wiring 216.

[0099] A color filter 218 is formed on the wiring layer 210 of each pixel 120. A microlens 219 is formed on the color filter 218 of each pixel 120. Acrylic resin or polycarbonate transparent resin may be used as a material of the color filter 218 and the microlens 219. A pigment for coloring may be added to the color filter 218. The color filter 218 may form, for example, a Bayer layout.

[0100] Figure 5 : is a cross-sectional view showing a modified example of the pixel array unit provided to the solid-state imaging device according to the first embodiment. Note that, Figure 5 An example of a back-illuminated solid-state imaging device is shown. Figure 5 A configuration example of three pixels is shown.

[0101] exist Figure 5 In the embodiment, a photodiode 222 is formed in a semiconductor layer 221 of each pixel 120. The material of the semiconductor layer 221 may be Si, may be InGaAs, or may be InP. The semiconductor layer 221 may be formed by thinning a semiconductor substrate including the photodiode 222 formed on the front side from the back side.

[0102] The gate electrode 224 and the wiring layer 220 are formed on the semiconductor layer 221. The gate electrode 224 is formed on the semiconductor layer 221 via the gate insulating film 223. The sidewall 225 is formed on the sidewall of the gate electrode 224.

[0103] The gate electrode 224 may be used for a pixel transistor. The pixel transistor includes Figure 3 The transfer transistor 122, the reset transistor 123, the amplifying transistor 124 and the selecting transistor 125 are included in the embodiment.

[0104] A wiring 226 is formed on the gate electrode 224 . Figure 5 An example of three-layer wiring is shown. The gate electrode 224 and the wiring 226 are insulated with an insulating layer 227 interposed therebetween. The semiconductor layer 221 is supported on a support substrate 230 with the insulating layer 227 interposed therebetween. The support substrate 230 may be a glass substrate, may be a Si support substrate, or may be a sapphire substrate.

[0105] The color filter 228 is formed on the back side of the semiconductor layer 221 of each pixel 120. The microlens 229 is formed on the color filter 228 of each pixel 120. The color filter 228 may form, for example, a Bayer layout.

[0106] Figure 6 is a diagram showing a configuration example of a signal readout circuit for one column according to the first embodiment.

[0107] exist Figure 6 In FIG. 1 , the amplifying transistor 124 is connected to the vertical signal line 132 via the selecting transistor 125. Furthermore, a capacitor 133 is added to the vertical signal line 132. The capacitor 133 may be a parasitic capacitor of the vertical signal line 132, or may be a capacitive element connected to the vertical signal line 132.

[0108] Furthermore, the vertical signal line 132 is electrically connected to a signal line reset transistor 141. The signal line reset transistor 141 can reset the potential VSL of the vertical signal line 132. For example, a MOS transistor can be used as the signal line reset transistor 141. A signal line reset signal φRT is applied to the gate of the signal line reset transistor 141.

[0109] The signal line reset transistor 141 is connected in series with the diode-connected transistor 142. For example, a MOS transistor can be used as the diode-connected transistor 142. At this time, the gate of the diode-connected transistor 142 is connected to the drain of the diode-connected transistor 142. The source of the diode-connected transistor 142 is grounded. The source of the diode-connected transistor 142 can be connected to a potential higher than the ground potential. The diode-connected transistor 142 can generate a voltage higher than 0V (for example, 0.5V), and the potential VSL of the vertical signal line 132 is set to a potential higher than 0V via the signal line reset transistor 141. Note that the diode-connected transistor 142 is an example of a signal line reset level generating unit described in the claims.

[0110] In addition, the vertical signal line 132 is electrically connected to the signal line limiter transistor 146. The signal line limiter transistor 146 limits the potential VSL of the vertical signal line 132. For example, a MOS transistor can be used as the signal line limiter transistor 146. A signal line limiter voltage Vb is applied to the gate of the signal line limiter transistor 146. The signal line limiter transistor 146 can generate a limiter level Vcp based on the signal line limiter voltage Vb. The signal line limiter voltage Vb can be made lower than the reset level of the pixel 120.

[0111] The signal line clip selection transistor 147 is connected between the signal line clip transistor 146 and the vertical signal line 132. The signal line clip selection transistor 147 applies the clip voltage Vcp generated by the signal line clip transistor 146 to the vertical signal line 132. A plurality of clip levels Vcp can be provided and can be switched. For example, a MOS transistor can be used as the signal line clip selection transistor 147. The gate of the signal line clip selection transistor 147 is applied with a signal line clip selection signal ΦSUN.

[0112] The resistor ladder circuit 155 generates the signal line clipping voltage Vb step by step. The resistor ladder circuit 155 includes voltage-dividing resistors 151 to 154. The voltage-dividing resistors 151 to 154 are connected in series with each other. The selector 150 switches the divided voltage generated by the voltage-dividing resistors 151 to 154, and inputs the divided voltage as the signal line clipping voltage Vb to the gate of the signal line clipping transistor 146. Note that the selector 150 and the resistor ladder circuit 155 are examples of the signal line clipping voltage setting unit described in the claims. Note that although Figure 6 An example is shown in which the signal line clip voltage Vb is switchable at three levels, but the levels are not necessarily limited to three levels, and may be, for example, two levels or four levels or more.

[0113] The vertical signal line 132 is connected to the inverting input terminal of the comparator 143 via the DC cut capacitor 144. At this time, the potential VSL of the vertical signal line 132 is applied to the inverting input of the comparator 143 via the DC cut capacitor 144. The non-inverting input of the comparator 143 receives the input of the reference signal RAP via the DC cut capacitor 145. The reference signal RAP is, for example, a ramp signal. In addition, the comparator 143 receives the input of the auto-zero signal AZ.

[0114] The auto-zero control unit 148 inputs the auto-zero signal AZ to the comparator 143. The auto-zero signal AZ activates the auto-zero operation during the auto-zero period. At this time, the auto-zero control unit 148 can control the charges stored in the DC cut-off capacitors 144 and 145 so that the non-inverting input and the inverting input of the comparator 143 are balanced.

[0115] Here, when the signal line reset transistor 141 is turned on before the signal is read out from the pixel 120, the potential VSL of the vertical signal line 132 is set to a potential higher than 0V. In addition, after the signal line reset transistor 141 is turned off, the selection transistor 125 and the signal line limit selection transistor 147 are turned on. At this time, when high-brightness light such as sunlight is incident on the pixel 120, the potential VSL of the vertical signal line 132 is limited to the limit level Vcp by the signal line limit transistor 146 when the P phase VSL of the readout of the capacitive load is set. Therefore, even when the charge overflows from the photodiode 121 to the floating diffusion 126, the potential VSL can be set to a higher potential than the potential of the vertical signal line 132 when the signal is read out from the pixel 120. In addition, the comparator 143 compares the potential VSL of the vertical signal line 132 with the reference signal RAP, and outputs the comparison result COP. At this time, the potential VSL of the vertical signal line 132 is clipped to the clip level Vcp when the P phase VSL of the readout of the capacitive load is set, so that the sunspot phenomenon can be prevented.

[0116] On the other hand, when normal light or low brightness light is incident on the pixel 120, a charge of the potential VSL of the vertical signal line 132 corresponding to the pixel current IPX flowing to the vertical signal line 132 via the selection transistor 125 is stored in the capacitor 133, and the potential VSL of the vertical signal line 132 changes based on the charge stored in the capacitor 133. In addition, the comparator 143 compares the potential VSL of the vertical signal line 132 with the reference signal RAP, and outputs a comparison result COP.

[0117] Figure 7 is a diagram showing a first example of a waveform of each unit when the imaging device according to the first embodiment reads out a signal. Note that, Figure 7 The waveform of each unit when a signal is read out when high-brightness light such as sunlight is incident on the pixel 120 is shown.

[0118] exist Figure 7, when the imaging device reads out the capacitive load, pixel reset / VSL reset (K11) is performed. At this time, the pixel reset signal ΦPRT rises (t11), the reset transistor 123 is turned on, and the floating diffusion 126 is reset. Note that the reset level of the floating diffusion 126 can be set to the power supply potential Vdd. In addition, the signal line reset signal ΦRT rises (t11), the signal line reset transistor 141 is turned on, and the vertical signal line 132 is reset. In this case, when the signal line reset transistor 141 is turned on, the current flows to the diode-connected transistor 142 via the signal line reset transistor 141. Therefore, the reset level of the vertical signal line 132 is set to a potential (for example, 0.5V) higher than the forward voltage VR of the diode-connected transistor 142 by 0V. Note that the rising timing of the pixel reset signal ΦPRT and the rising timing of the signal line reset signal ΦRT are not necessarily the same, and can be offset from each other. In addition, the falling timing of the signal line reset signal ΦRT does not need to appear after the falling timing of the pixel reset signal ΦPRT, and there is no particular limitation as long as the falling timing appears before the selection signal ΦSEL rises.

[0119] Next, the P-phase VSL setting is performed (K12). At this time, the signal line reset signal ΦRT falls and the selection signal ΦSEL rises (t12), and the selection transistor 125 is turned on. In addition, the output of the resistor ladder circuit 155 is selected so that the signal line limit voltage Vb becomes lower than the reset level of the pixel 120, and the signal line limit voltage Vb is applied to the gate of the signal line limit transistor 146. In addition, the signal line limit selection signal ΦSUN rises (t12) and the signal line limit selection transistor 147 is turned on, and the auto-zero signal AZ rises (t12) and activates the auto-zero operation of the comparator 143. In addition, after the selection signal ΦSEL falls (t13), the auto-zero signal AZ falls, and after the auto-zero signal AZ falls, the signal line limit selection signal ΦSUN falls (t14). At this time, the potential VSL of the vertical signal line 132 is clipped to the clip level Vcp, and is adjusted so that the non-inverting input and the inverting input of the comparator 143 are balanced when the potential VSL of the vertical signal line 132 is clipped.

[0120] Next, P phase AD (K13) is performed. At this time, after the signal line clip selection signal ΦSUN falls (t14), the ramp signal is provided to the comparator 143 as the reference signal RAP. In addition, the comparator 143 compares the potential VSL of the vertical signal line 132 matching the clip level Vcp with the reference signal RAP, and outputs the timing at which the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 as the comparison result COP. At this time, based on the counting operation performed until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132, the clip level Vcp set to the vertical signal line 132 is subjected to AD conversion.

[0121] Next, transfer / VSL reset (K14) is performed. At this time, the transfer signal ΦTG rises (t15), the transfer transistor 122 is turned on, and the charge stored in the photodiode 121 is transferred to the floating diffusion 126. In addition, the signal line reset signal ΦRT rises (t15), the signal line reset transistor 141 is turned on, and the vertical signal line 132 is reset. At this time, when the signal line reset transistor 141 is turned on, the current flows to the diode-connected transistor 142 via the signal line reset transistor 141. Therefore, the reset level of the vertical signal line 132 is set to a potential (for example, 0.5V) higher than the forward voltage VR of the diode-connected transistor 142 by 0V. Note that the rising timing of the transfer signal ΦTG and the rising timing of the signal line reset signal ΦRT may not necessarily be the same, and may be offset from each other. In addition, the falling timing of the signal line reset signal ΦRT does not need to be after the falling timing of the transfer signal ΦTG, and there is no particular limitation as long as the falling timing is before the selection signal ΦSEL rises.

[0122] Next, D phase VSL setting is performed (K15). At this time, the signal line reset signal ΦRT falls, the selection signal ΦSEL rises (t16), and the selection transistor 125 is turned on. In addition, based on the source follower operation of the amplifier transistor 124, the pixel current IPX matching the signal level of the floating diffusion 126 flows to the vertical signal line 132 via the selection transistor 125. In addition, the charge matching the pixel current IPX is stored in the capacitor 133, and the potential VSL of the vertical signal line 132 is set based on the charge stored in the capacitor 133.

[0123] Next, D phase AD is performed (K16). At this time, the selection signal ΦSEL falls (t17), and the ramp signal is provided to the comparator 143 as the reference signal RAP (t17 to t18). In addition, the comparator 143 compares the potential VSL of the vertical signal line 132 that matches the signal level with the reference signal RAP, and outputs the timing at which the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 as the comparison result COP. At this time, based on the counting operation performed until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132, the signal level read out from the pixel 120 undergoes AD conversion.

[0124] Figure 8 : is a diagram showing a second example of the waveform of each unit when the imaging device according to the first embodiment reads out a signal. Note that, Figure 8 The waveform of each unit when a signal is read out when normal light is incident on the pixel 120 is shown.

[0125] exist Figure 8 , the signal readout operation when normal light is incident on the pixel 120 is similar to the signal readout operation when high-brightness light such as sunlight is incident on the pixel 120. In this regard, according to the signal readout operation when normal light is incident on the pixel 120, the charge does not overflow from the photodiode 121 to the floating diffusion 126 during the P-phase VSL setting (K12). In addition, when the selection transistor 125 is turned on, based on the source follower operation of the amplifier transistor 124, the pixel current IPX matching the reset level of the floating diffusion 126 flows to the vertical signal line 132 via the selection transistor 125. In addition, the charge matching the pixel current IPX is stored in the capacitor 133, and the potential VSL of the vertical signal line 132 is set based on the charge stored in the capacitor 133. At this time, the signal line limit voltage Vb is set to a voltage lower than the reset level of the pixel 120, and the signal line limit selection transistor 147 is turned on. Therefore, the vertical signal line 132 is also driven by the signal line limiter transistor 146 while being driven by the amplifying transistor 124. Therefore, the P-phase VSL setting VSLB provided with the signal line limiter transistor 146 can reduce the settling time compared with the P-phase VSL setting VSLA not provided with the signal line limiter transistor 146.

[0126] As described above, in the above-mentioned first embodiment, the signal line limit transistor 146 is electrically connected via the signal line limit selection transistor 147 connected to the vertical signal line 132. Therefore, the potential VSL of the vertical signal line 132 can be limited without depending on the amount of incident light, and the sunspot phenomenon can be prevented and the speed of P-phase VSL setting can be increased.

[0127] Furthermore, by resetting the vertical signal line 132 when a signal is read out from the pixel 120, a charge matching the pixel current IPX flowing when a signal is read out from the pixel 120 can be stored in the capacitor 133. Therefore, it is not necessary to flow a constant current matching the signal read out from the pixel 120 to the vertical signal line 132 in order to detect the signal read out from the pixel 120, and the consumption current when a signal is read out from the pixel 120 can be reduced.

[0128] <2. Second Embodiment>

[0129] In the above-described first embodiment, the signal line limiter transistor 146 is electrically connected via the signal line limiter selection transistor 147 connected to the vertical signal line 132. In this second embodiment, the signal line limiter transistor 146 and the signal line limiter selection transistor 147 are provided to the upper chip provided with the pixel 120, and the resistance ladder circuit 155 and the selector 150 are provided to the lower chip.

[0130] Fig. 9 is a diagram showing a configuration example of a signal readout circuit for one column according to the second embodiment.

[0131] exist Fig. 9 The circuit configuration of the signal readout circuit is similar to Figure 6 The circuit configuration of the signal readout circuit in is similar. In this regard, the signal readout circuit is formed in a stacked chip. The stacked chip includes an upper chip 161 and a lower chip 162. The upper chip 161 is stacked on the lower chip 162.

[0132] On the upper chip 161, there are formed the pixel 120, the vertical signal line 132, the signal line limit transistor 146, and the signal line limit selection transistor 147. In this case, the gate length and gate width of the signal line limit transistor 146 can be made equal to the gate length and gate width of the amplifying transistor 124 of the pixel 120. The gate length and gate width of the signal line limit selection transistor 147 can be made equal to the gate length and gate width of the selection transistor 125 of the pixel 120.

[0133] On the lower chip 162, a signal line reset transistor 141, a diode connection transistor 142, a comparator 143, a resistance ladder circuit 155, and a selector 150 are formed. In this case, the vertical signal line 132 may be wired from the upper chip 161 to the lower chip 162.

[0134] As described above, in the second embodiment, the signal line limit transistor 146 and the signal line limit selection transistor 147 are formed in the upper chip 161 formed with the pixel 120. Therefore, the characteristic change of the pixel transistor provided to the pixel 120 can be made equal to the characteristic change of the signal line limit transistor 146 and the signal line limit selection transistor 147.

[0135] <3. Third Embodiment>

[0136] In the first embodiment described above, the signal line clip transistor 146 is electrically connected via the signal line clip selection transistor 147 connected to the vertical signal line 132. In this third embodiment, a driver driving the signal line clip selection transistor 147 and a driver driving the signal line reset transistor 141 are provided to the peripheral circuit of the pixel 120.

[0137] Fig.10 is a diagram showing a configuration example of a signal readout circuit for three columns according to the third embodiment.

[0138] exist Fig.10 In the embodiment, a signal line reset transistor 141, a diode connection transistor 142, a comparator 143, a signal line limiter transistor 146, and a signal line limiter selection transistor 147 are provided to each column.

[0139] The driver 161 drives the signal line limit selection transistor 147. The driver 162 drives the signal line reset transistor 141. The drivers 161 and 162 are provided to the peripheral circuit of the pixel 120. The driver 161 shares a plurality of signal line limit selection transistors 147 whose columns are respectively different. The driver 162 shares a plurality of signal line reset transistors 141 whose columns are respectively different. The resistor ladder circuit 155 and the selector 150 share a plurality of signal line limit transistors 146 whose columns are respectively different.

[0140] As described above, in the third embodiment, the plurality of signal line limit selection transistors 147 whose columns are respectively different share the driver 161, and the plurality of signal line reset transistors 141 whose columns are respectively different share the driver 162. Therefore, the sunspot phenomenon when reading the capacitive load can be prevented while suppressing the increase in the occupied area of ​​the drivers 161 and 162.

[0141] <4. Fourth Embodiment>

[0142] In the first embodiment described above, the clipping operation of the potential VSL of the vertical signal line 132 during the P-phase VSL setting is applied to the readout of the capacitive load. This fourth embodiment makes it possible to switch between the readout of the current and the readout of the capacitive load while implementing the clipping operation of the potential VSL of the vertical signal line 132 during the P-phase VSL setting.

[0143] Fig.11 is a diagram showing a configuration example of a signal readout circuit for one column according to the fourth embodiment.

[0144] exist Fig.11 , the signal readout circuit further includes the sample hold circuit 201 and the constant current transistor 301 in the signal readout circuit according to the above-mentioned first embodiment. The other components of the signal readout circuit according to the fourth embodiment are the same as those of the signal readout circuit according to the above-mentioned first embodiment.

[0145] The sample and hold circuit 201 samples and holds a bias voltage Vbs for operating the constant current transistor 301, and applies the bias voltage Vbs to the gate of the constant current transistor 301. The sample and hold circuit 201 includes a transistor 211 and a capacitor 212. The transistor 211 may be a MOS transistor. The gate of the transistor 211 is applied with a sample and hold signal ΦSH. The capacitor 212 is connected between the source of the transistor 211 and the ground potential.

[0146] The constant current transistor 301 is electrically connected to the vertical signal line 132. The constant current transistor 301 may be a MOS transistor.

[0147] Here, during the readout of the capacitive load, the bias voltage Vbs is set to 0V, and the sample and hold signal ΦSH is set to a high level. In this case, the constant current transistor 301 is turned off, and current does not flow to the constant current transistor 301. In this case, the operation of the signal readout circuit is the same as Figure 7 or Figure 8 The operation is the same as in .

[0148] During the constant current reading, the transistor 211 is turned on, and the bias voltage Vbs is sampled and held. In addition, the transistor 211 is turned off, and the bias voltage Vbs sampled and held by the sample-hold circuit 201 is applied to the gate of the constant current transistor 301. In this case, the constant current transistor 301 is turned on, and a constant current flows to the constant current transistor 301.

[0149] Fig.12 : is a diagram showing an example of a waveform of each cell when the signal readout circuit according to the fourth embodiment reads out a constant current. Note that Fig.12 The waveform of each unit when a signal is read out when high-brightness light such as sunlight is incident on the pixel 120 is shown.

[0150] exist Fig.12In the constant current readout period, transistor 211 is turned on, and bias voltage Vbs is sampled and held to prevent horizontal streak noise during AD conversion. In addition, transistor 211 is turned off, and bias voltage Vbs sampled and held by sample-hold circuit 201 is applied to the gate of constant current transistor 301.

[0151] Next, pixel reset is performed (K21). At this time, the pixel reset signal ΦPRT rises (t21), the reset transistor 123 is turned on, and the floating diffusion 126 is reset. In addition, the selection signal ΦSEL rises (t21), and the selection transistor 125 is turned on. At this time, when the power supply potential Vdd is applied to the gate of the amplification transistor 124, the potential VSL of the vertical signal line 132 is set based on the source follower operation.

[0152] Next, the P-phase VSL setting is performed (K22). At this time, the pixel reset signal ΦPRT drops (t22), and the reset transistor 123 is turned off. In addition, when the reset level of the floating diffusion 126 is applied to the gate of the amplifying transistor 124, the potential VSL of the vertical signal line 132 changes based on the source follower operation. In addition, the signal line limit voltage Vb set to be lower than the reset level of the pixel 120 is applied to the gate of the signal line limit transistor 146. In addition, the signal line limit selection signal ΦSUN rises (t23) and the signal line limit selection transistor 147 is turned on, and the automatic zeroing signal AZ rises (t23) and the automatic zeroing operation of the comparator 143 is activated. In addition, after the automatic zeroing signal AZ drops, the signal line limit selection signal ΦSUN drops (t24). At this time, the potential VSL of the vertical signal line 132 is clipped to the clip level Vcp, and when the potential VSL of the vertical signal line 132 is clipped, it is adjusted so that the non-inverting input and the inverting input of the comparator 143 are balanced.

[0153] Next, P phase AD (K23) is performed. At this time, the ramp signal is provided to the comparator 143 as the reference signal RAP. In addition, the comparator 143 compares the potential VSL of the vertical signal line 132 matching the clip level Vcp with the reference signal RAP, and outputs the timing at which the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 as the comparison result COP. At this time, based on the counting operation performed until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132, the clip level Vcp set to the vertical signal line 132 undergoes AD conversion.

[0154] Next, transfer is performed (K24). At this time, the transfer signal ΦTG rises (t25), the transfer transistor 122 is turned on, and the charge stored in the photodiode 121 is transferred to the floating diffusion 126. In addition, when the cathode potential of the photodiode 121 is applied to the gate of the amplifying transistor 124, the potential VSL of the vertical signal line 132 is set based on the source follower operation.

[0155] Next, D phase VSL setting is performed (K25). At this time, the transfer signal ΦTG falls (t25), and the transfer transistor 122 is turned off. In addition, when the signal level of the floating diffusion 126 is applied to the gate of the amplification transistor 124, the potential VSL of the vertical signal line 132 is set based on the source follower operation.

[0156] Next, P phase AD (K26) is performed. At this time, the ramp signal is provided to the comparator 143 as the reference signal RAP (t27 to t28). In addition, the comparator 143 compares the potential VSL of the vertical signal line 132 that matches the signal level with the reference signal RAP, and outputs the timing at which the level of the reference signal RAP matches the potential VSL of the vertical signal line 132 as the comparison result COP. At this time, based on the counting operation performed until the level of the reference signal RAP matches the potential VSL of the vertical signal line 132, the signal level read out from the pixel 120 undergoes AD conversion.

[0157] As described above, in the fourth embodiment described above, the constant current transistor 301 is connected in parallel to the series circuit of the signal line reset transistor 141 and the diode-connected transistor 142. The potential VSL of the vertical signal line 132 is clipped during the P-phase VSL setting period. Therefore, it is possible to switch between the readout of the constant current and the readout of the capacitive load while preventing the sunspot phenomenon.

[0158] <5. Fifth embodiment>

[0159] In the first embodiment described above, the signal line limiter transistor 146 is electrically connected via the signal line limiter selection transistor 147 connected to the vertical signal line 132. In this fifth embodiment, the signal line limiter transistor 146 limits the potential VSL of the vertical signal line 132 and selects the vertical signal line 132.

[0160] Fig.13 is a diagram showing a configuration example of a signal readout circuit for one column according to the fifth embodiment.

[0161] exist Fig.13In this signal readout circuit, the signal line limit selection transistor 147 is removed from the signal readout circuit according to the above-described first embodiment. The other components of the signal readout circuit according to the fifth embodiment are the same as those of the signal readout circuit according to the above-described first embodiment.

[0162] The signal line limiter transistor 146 is directly connected to the vertical signal line 132. In this case, the signal line limiter transistor 146 limits the potential VSL of the vertical signal line 132, and selects the vertical signal line 132 instead of the signal line limiter selection transistor 147.

[0163] Fig.14 : is a diagram showing an example of a waveform of each cell when the signal readout circuit according to the fifth embodiment reads out a constant current. Note that Fig.14 The waveform of each unit when a signal is read out when high-brightness light such as sunlight is incident on the pixel 120 is shown.

[0164] exist Fig.14 , the operation in the case where the signal line limit selection transistor 147 is not set is the same as the operation in the case where the signal line limit selection transistor 147 is set. In this regard, during the P-phase VSL setting (K12), the signal line limit voltage Vb is converted from the voltage Vb1 to the voltage Vb2 based on the switching operation of the selector 150, and is applied to the gate of the signal line limit transistor 146 (t12). In addition, the signal line limit voltage Vb is converted from the voltage Vb2 to the voltage Vb1 based on the switching operation of the selector 150, and is applied to the gate of the signal line limit transistor 146 (t14). The voltage Vb1 is set to turn off the signal line limit transistor 146. The voltage Vb2 is set so that the potential VSL of the vertical signal line 132 limited by the signal line limit transistor 146 matches the limit level Vcp.

[0165] As described above, in the above fifth embodiment, the signal line limiter transistor 146 limits the potential VSL of the vertical signal line 132 and selects the vertical signal line 132. Therefore, the signal line limiter selection transistor 147 can be omitted, and the circuit configuration is simplified.

[0166] <6. Sixth Implementation>

[0167] In the first embodiment described above, the signal line limit transistor 146 is electrically connected via the signal line limit selection transistor 147 connected to the vertical signal line 132. In this sixth embodiment, the amplification transistor of the OB pixel serves as the signal line limit transistor 146, and the selection transistor of the OB pixel serves as the signal line limit selection transistor 147.

[0168] Fig.15is a diagram showing a configuration example of a signal readout circuit for one column according to the sixth embodiment.

[0169] exist Fig.15 In the embodiment, the signal readout circuit is provided with an OB pixel 400 instead of the signal line limiter transistor 146 and the signal line limiter selection transistor 147 according to the above-described first embodiment. Components other than the signal readout circuit according to the fourth embodiment are the same as those of the signal readout circuit according to the above-described first embodiment.

[0170] The OB pixel 400 includes a photodiode 421, a transfer transistor 422, a reset transistor 423, an amplification transistor 424, a selection transistor 425, and a floating diffusion 426. The photodiode 421 is covered with a light shielding film.

[0171] The amplification transistor 424 and the selection transistor 425 are connected in series. The cathode of the photodiode 421 is connected to the floating diffusion 426 via the transfer transistor 422. In addition, the power supply Vdd is connected to the vertical signal line 132 via the series circuit of the amplification transistor 424 and the selection transistor 425. The gate of the amplification transistor 424 is connected to the floating diffusion 426.

[0172] The gate of the transfer transistor 422 is applied with a transfer signal ΦTGB. The gate of the reset transistor 423 is applied with a pixel reset signal ΦPRTS. The drain of the reset transistor 423 is applied with a signal line clip voltage Vb. The gate of the select transistor 425 is applied with a selection signal ΦSELS. The transfer signal ΦTGB, the pixel reset signal ΦPRTS, and the selection signal ΦSELS can be connected to the transistor 425 via Figure 2 The horizontal driving line 131 in is sent to each OB pixel 400.

[0173] Fig.16 : is a diagram showing an example of a waveform of each cell when the signal readout circuit according to the sixth embodiment reads out a constant current. Note that Fig.16 The waveform of each unit when a signal is read out when high-brightness light such as sunlight is incident on the pixel 120 is shown.

[0174] exist Fig.16 In this case, the amplification transistor 424 of the OB pixel 400 is used as the signal line limit transistor 146, and the selection transistor 425 of the OB pixel 400 is used as the signal line limit selection transistor 147. The capacitive load readout operation in this case is similar to Figure 7The capacitive load readout operation in is the same. In this regard, the amplifier transistor 424 of the OB pixel 400 is used as the signal line limiter transistor 146, and the signal line limiter voltage Vb is applied to the gate of the amplifier transistor 424. At this time, the pixel reset signal ΦPRTS is set to a high level (t11 to t18), and the reset transistor 423 is turned on. In addition, the transfer signal ΦTGB is set to a low level (t11 to t18), and the transfer transistor 422 is turned off.

[0175] In addition, during the P-phase VSL setting (K12), the signal line reset signal ΦRT falls, the selection signal ΦSELS rises (t12), and the selection transistor 425 is turned on. In addition, the output of the resistor ladder circuit 155 is selected so that the signal line clipping voltage Vb becomes lower than the reset level of the pixel 120, and the signal line clipping voltage Vb is applied to the gate of the amplification transistor 424. In addition, the auto-zero signal AZ rises (t12), and the auto-zero operation of the comparator 143 is activated. In addition, after the auto-zero signal AZ falls, the selection signal ΦSELS falls (t14). At this time, the potential VSL of the vertical signal line 132 is clipped to the clipping level Vcp, and when the potential VSL of the vertical signal line 132 is clipped, it is adjusted so that the non-inverting input and the inverting input of the comparator 143 are balanced.

[0176] On the other hand, a signal is read out from the OB pixel 400. In this case, the transfer transistor 422, the reset transistor 423, the amplifying transistor 424, and the selecting transistor 425 of the OB pixel 400 are operated similarly to the transfer transistor 122, the reset transistor 123, the amplifying transistor 124, and the selecting transistor 125 of the pixel 120. In addition, the output of the resistor ladder circuit 155 is selected so that the signal line clipping voltage Vb supplied as the power supply Vdd is applied to the drain of the reset transistor 423. In this case, the OB pixel 400 is shielded, and light is not incident on the OB pixel 400, so that the clipping vertical signal line 132 is not required during the P-phase VLS setting.

[0177] As described above, in the sixth embodiment described above, the amplification transistor 424 of the OB pixel 400 is used as the signal line limiter transistor 146, and the selection transistor 425 of the OB pixel 400 is used as the signal line limiter selection transistor 147. Therefore, it is not necessary to provide the signal line limiter transistor 146 and the signal line limiter selection transistor 147 separately from the OB pixel 400 to prevent the sunspot phenomenon, so that the circuit configuration can be simplified.

[0178] <7. Seventh Implementation Method>

[0179] In the above-described first embodiment, the diode-connected transistor 142 is connected via the signal line reset transistor 141 electrically connected to the vertical signal line 132 to set the reset level of the vertical signal line 132. In this seventh embodiment, the resistor ladder circuit 155 is used to set the slice level Vcp of the vertical signal line 132, and is used to set the reset level of the vertical signal line 132.

[0180] Fig.17 is a diagram showing a configuration example of a signal readout circuit for one column according to a seventh embodiment.

[0181] exist Fig.17 In the embodiment, the signal readout circuit is provided with a selector 500 instead of the diode-connected transistor 142 according to the above-described first embodiment. Other components of the signal readout circuit according to the seventh embodiment are the same as those of the signal readout circuit according to the above-described first embodiment.

[0182] The selector 500 switches the divided voltage generated by the voltage-dividing resistors 151 to 154 and applies the divided voltage as a reset voltage VRT to the source of the signal line reset transistor 141. The reset voltage VRT may be set to a voltage greater than 0 V. The switching of the selector 500 may be controlled separately from the switching of the selector 150.

[0183] As described above, in the seventh embodiment, the resistor ladder circuit 155 is used to set the slice level Vcp of the vertical signal line 132 and to set the reset voltage VRT of the vertical signal line 132. Therefore, the reset voltage VRT of the vertical signal line 132 can be switched while suppressing an increase in circuit scale.

[0184] <8. Eighth Implementation Method>

[0185] In the above-described first embodiment, during the P-phase VSL setting, when the potential VSL of the vertical signal line 132 is clipped, the signal read out from the pixel 120 is detected based on the potential VSL of the vertical signal line 132. In this eighth embodiment, during the P-phase VSL setting, when the potential of the vertical signal line is clipped, edge detection is performed based on a comparison result of the potential of the vertical signal line based on the readout of the load capacitance from different columns.

[0186] Fig.18 is a diagram showing a configuration example of a signal readout circuit for two columns according to an eighth embodiment.

[0187] exist Fig.18, the signal readout circuit includes a plurality of vertical signal lines 132-1 and 132-2, and includes comparators 143-1 and 143-2 instead of the comparator 143 according to the above-described first embodiment. Other components of the signal readout circuit according to the eighth embodiment are the same as those of the signal readout circuit according to the above-described first embodiment, and although not shown, may include a signal line limit transistor 146 and a signal line limit selection transistor 147.

[0188] The vertical signal lines 132 - 1 and 132 - 2 are connected to the pixels 120 - 1 and 120 - 2 , respectively, and the comparators 143 - 1 and 143 - 2 are connected to both of the vertical signal lines 132 - 1 and 132 - 2 .

[0189] Each of the pixels 120-1 and 120-2 may be connected to Figure 6 The pixel 120 in FIG. 1 is configured similarly. The pixels 120 - 1 and 120 - 2 are connected to the vertical signal lines 132 - 1 and 132 - 2 , respectively. In addition, each of the vertical signal lines 132 - 1 and 132 - 2 is connected to the diode connection transistor 142 via the signal line reset transistor 141 .

[0190] Each of the comparators 143-1 and 143-2 detects the difference between the comparator inputs DVSL1 and DVSL2. In this case, the potentials VLS1 and VLS2 of the vertical signal lines 132-1 and 132-2 are output through the DC cut capacitors 144 and 145, and the comparator inputs DVSL1 and DVSL2 are generated. In addition, after the automatic zeroing of the comparators 143-1 and 143-2, when the difference between the comparator inputs DVSL1 and DVSL2 is a threshold value or more, it can be determined that there is an edge.

[0191] Fig.19 FIG. 1 is a diagram showing a configuration example of a comparator applied to a signal readout circuit according to the eighth embodiment. Fig.18 The configuration of the comparator 143-1 in FIG. 1 is taken as an example, but the comparator 143-2 may also be configured similarly.

[0192] exist Fig.19 , the comparator 143 - 1 includes a differential amplifier 501 , a post-stage amplifier 502 , and an inverter 503 . The post-stage amplifier 502 is connected to a post-stage of the differential amplifier 501 , and the inverter 503 is connected to a post-stage of the post-stage amplifier 502 .

[0193] The differential amplifier 501 balances the comparator inputs DVSL1 and DVSL2 based on an auto-zero operation and then outputs a voltage corresponding to the difference between the comparator inputs DVSL1 and DVSL2 . The differential amplifier 501 includes PMOS transistors 511 , 521 , 551 , and 561 and NMOS transistors 531 , 541 , and 571 .

[0194] The PMOS transistor 511 and the NMOS transistor 531 are connected in series with each other. The PMOS transistor 521 and the NMOS transistor 541 are connected in series with each other. The sources of the PMOS transistors 511 and 521 are connected to the power supply voltage VDDH, and the gates of the PMOS transistors 511 and 521 are connected to the drain of the PMOS transistor 521. In this case, the PMOS transistors 511 and 521 may constitute a current mirror.

[0195] The PMOS transistor 551 is connected between the gate and drain of the NMOS transistor 531, and the PMOS transistor 561 is connected between the gate and drain of the NMOS transistor 541. Sources of the NMOS transistors 531 and 541 are grounded via the NMOS transistor 571.

[0196] The auto-zero signal AZP is applied to the gates of the PMOS transistors 551 and 561, and the bias voltage BIAS is applied to the gate of the NMOS transistor 571. The NMOS transistor 571 may operate as a constant current source based on the bias voltage BIAS.

[0197] The post-stage amplifier 502 amplifies the output of the differential amplifier 501. The post-stage amplifier 502 includes a PMOS transistor 512, an NMOS transistor 522, and a switch 532.

[0198] The PMOS transistor 512 and the NMOS transistor 522 are connected in series with each other. The source of the PMOS transistor 512 is connected to the power supply voltage VDDH, and the gate of the PMOS transistor 512 is connected to the drain of the PMOS transistor 511. The switch 532 is connected between the gate and the drain of the NMOS transistor 522, and the source of the NMOS transistor 522 is grounded. The switch 532 is opened and closed based on the auto-zero signal AZN.

[0199] The inverter 503 converts the output of the post-stage amplifier 502 into a logic value of '0' or a logic value of '1'. The inverter 503 includes a PMOS transistor 513 and an NMOS transistor 523 .

[0200] The PMOS transistor 513 and the NMOS transistor 523 are connected in series with each other. The source of the PMOS transistor 513 is connected to the power supply voltage VDDL, and the source of the NMOS transistor 523 is grounded. The power supply voltage VDDL can be made lower than the power supply voltage VDDH. The gate of the PMOS transistor 513 and the gate of the NMOS transistor 523 are connected to the drain of the PMOS transistor 512.

[0201] In the auto-zero period, the PMOS transistors 551 and 561 are turned on based on the auto-zero signal AZP, and the switch 532 is closed based on the auto-zero signal AZN. Note that the timing at which the PMOS transistors 551 and 561 are turned off after being turned on can be set to a timing after the timing at which the switch 532 is opened after being closed. In this case, based on the current mirror operation of the PMOS transistors 511 and 521, current flows to the PMOS transistors 551 and 561. In addition, charge is stored in each of the DC cut-off capacitors 144 and 145, so that the non-inverting input and the inverting input of the comparator 143-1 are balanced.

[0202] Fig. 20 : is a diagram showing an example of a waveform of each unit when the imaging device according to the eighth embodiment reads out a signal. Note that, Fig. 20 It is assumed that normal light is incident on the pixel 120 - 1 , and high-brightness light such as sunlight is incident on the pixel 120 - 2 .

[0203] exist Fig. 20 In the case of pixel 120-1, the capacitive load readout operation is similar to Figure 8 and in the case of pixel 120-2, the capacitive load readout operation is the same as Figure 7 In this case, even when high brightness light is incident on the pixel 120-2, the potential VSL2 of the vertical signal line 132-2 is clipped during the P phase VSL setting (K12), and the potential VSL2 of the vertical signal line 132-2 is raised to a potential equal to the potential VSL1 of the vertical signal line 132-1. Therefore, during the D phase VSL setting, the difference between the comparator inputs DVSL1 and DVSL2 corresponding to the difference between the potentials VSL1 and VSL2 of the vertical signal lines 132-1 and 132-2 is basically maintained, and edge erroneous determination is prevented.

[0204] Fig.21 : is a diagram showing an example of a waveform of each unit when an imaging device according to a comparative example of the eighth embodiment reads out a signal. Note that this comparative example assumes that the vertical signal line 132-2 is not clipped during the P-phase VSL setting. In addition, Fig.21It is assumed that normal light is incident on the pixel 120 - 1 , and high-brightness light such as sunlight is incident on the pixel 120 - 2 .

[0205] exist Fig.21 In the case of pixel 120-1, the capacitive load readout operation is similar to Figure 8 and in the case of pixel 120-2, the capacitive load readout operation is the same as Figure 7 In this regard, the signal line clipping selection signal ΦSUN at the time of P-phase VSL setting (K12) is maintained at a low level. In this case, the potential VSL2 of the vertical signal line 132-2 is not clipped, and therefore when normal light is incident on the pixel 120-1 and high brightness light is incident on the pixel 120-2, the potentials VSL1 and VSL2 of the vertical signal lines 132-1 and 132-2 are turned on at the time of P-phase VSL setting. Therefore, the difference between the potentials VSL1 and VSL2 of the vertical signal lines 132-1 and 132-2 during the D-phase VSL setting is not reflected in the difference between the comparator inputs DVSL1 and DVSL2, which results in edge error determination.

[0206] As described above, in the eighth embodiment described above, when the potentials VLS1 and VLS2 of the vertical signal lines 132-1 and 132-2 are clipped during the P-phase VSL setting, the difference between the comparator inputs DVSL1 and DVSL2 is detected after the automatic zeroing of the comparators 143-1 and 143-2. ​​Therefore, even when high-brightness light such as sunlight is incident on the pixel 120-2, the edge of the object can be detected while reducing the influence of fixed pattern noise.

[0207] <9. Ninth Implementation Method>

[0208] In the first embodiment described above, a clipping operation of the potential VLS of the vertical signal line 132 is applied to read out the capacitive load from the pixel 120 provided with one photodiode 121 for one amplifier transistor 124. In this ninth embodiment, a clipping operation of the potential VLS of the vertical signal line 132 is applied to read out the capacitive load from a unit provided with four photodiodes for one amplifier transistor 124.

[0209] Fig. 22 is a diagram showing a configuration example of a signal readout circuit for one column according to a ninth embodiment.

[0210] exist Fig. 22 , the signal readout circuit is provided with a cell 130 instead of the pixel 120 of the signal readout circuit according to the above-described first embodiment. Other components of the signal readout circuit according to the ninth embodiment are the same as those of the signal readout circuit according to the above-described first embodiment.

[0211] The cell 130 includes photodiodes 121-1 to 121-4 and transfer transistors 122-1 to 122-4 instead of the photodiode 121 and transfer transistor 122 according to the first embodiment described above. Other components of the cell 130 according to the ninth embodiment are the same as those of the pixel 120 according to the first embodiment described above.

[0212] The photodiodes 121-1 to 121-4 may be arranged in two rows by two columns. Each of the photodiodes 121-1 to 121-4 is connected to the floating diffusion 126 via each of the transfer transistors 122-1 to 122-4. The gates of the transfer transistors 122-1 to 122-4 are applied with transfer signals ΦTG1 to ΦTG4. By controlling the application timing of these transfer signals ΦTG1 to ΦTG4, a signal may be read out from each of the photodiodes 121-1 to 121-4 to the vertical signal line 132, respectively. The operation of reading out the capacitive load from each of the photodiodes 121-1 to 121-4 is similar to the operation of reading out the capacitive load from each of the photodiodes 121-1 to 121-4. Figure 7 or Figure 8 The operation is the same as in .

[0213] As described above, in the above-mentioned ninth embodiment, the clipping operation of the potential VLS of the vertical signal line 132 is applied to read out the capacitive load from the unit 130 provided with the four photodiodes 121-1 to 121-4 for one amplification transistor 124. Therefore, the increase in the number of pixels can be prevented while suppressing the increase in the pixel area, and the readout of the capacitive load of each pixel can be applied while preventing the sunspot phenomenon.

[0214] Note that although the above ninth embodiment has described an example in which four photodiodes 121-1 to 121-4 are shared by one amplifier transistor 124, eight photodiodes may be shared by one amplifier transistor 124. In addition, for the configuration provided with the single cell 130, any of the above second to eighth embodiments may be applied.

[0215] <10. Tenth Implementation Method>

[0216] In the above-described first embodiment, a clipping operation of the potential VLS of the vertical signal line 132 is applied to read out the capacitive load from each pixel 120 connected to the vertical signal line 132. In this tenth embodiment, based on reading out the capacitive load from the pixel 120 connected to the vertical signal line 132, a clipping operation of the potential VLS of the vertical signal line 132 is applied to the binning operation.

[0217] Fig.23 is a diagram showing a configuration example of a signal readout circuit for one column according to a tenth embodiment.

[0218] exist Fig.23 , the signal readout circuit is provided with pixels 140 and 150 instead of the pixel 120 of the signal readout circuit according to the above-mentioned first embodiment. In addition, in the signal readout circuit according to the above-mentioned first embodiment, the signal readout circuit includes a merging line 134. The other components of the signal readout circuit according to the tenth embodiment are the same as those of the signal readout circuit according to the above-mentioned first embodiment.

[0219] According to the above-described first embodiment, each of the pixels 140 and 150 further includes a binning transistor 127 in the pixel 120. Other components of each of the pixels 140 and 150 according to the tenth embodiment are the same as those of the pixel 120 according to the above-described first embodiment.

[0220] The merging transistor 127 is connected between the floating diffusion 126 and the merging line 134 of each pixel 140 and 150. The merging transistor 127 may be a MOS transistor. For each pixel 140 and 150, the gate of the merging transistor 127 is applied with pixel merging signals ΦBN1 and ΦBN2. For each pixel 140 and 150, the gate of the transfer transistor 122 is applied with transfer signals ΦTG1 and ΦTG2. For each pixel 140 and 150, the gate of the reset transistor 123 is applied with pixel reset signals ΦPRT1 and ΦPRT2. For each pixel 140 and 150, the gate of the select transistor 125 is applied with selection signals ΦSEL1 and ΦSEL2.

[0221] When signals are read out from each of the pixels 140 and 150, respectively, the merge signals ΦBN1 and ΦBN2 are set to a low level, and the merge transistor 127 of each of the pixels 140 and 150 is turned off. When signals from each of the pixels 140 and 150 are read out by merging, the merge signals ΦBN1 and ΦBN2 are set to a high level, and the merge transistor 127 of each of the pixels 140 and 150 is turned off. The operation of reading out the capacitive load from each of the pixels 140 and 150 is similar to Figure 7 In this case, at the time of binning readout, one of the selection transistors 125 of the pixels 140 and 150 may be turned on, or both of the selection transistors 125 of the pixels 140 and 150 may be turned on.

[0222] As described above, in the above-described tenth embodiment, the binning transistor 127 is provided to the pixels 140 and 150 connected to the vertical signal line 132. Therefore, it is possible to apply readout of a capacitive load and reduce power consumption while reducing the number of readout times per frame.

[0223] Note that any of the configurations according to the above-described second to ninth embodiments can be applied to a configuration in which the pixels 140 and 150 are provided.

[0224] <11. Eleventh Implementation Method>

[0225] In the above-described first embodiment, the signal line limit transistor 146 is electrically connected via the signal line limit selection transistor 147 connected to the vertical signal line 132 that transmits the signal read out from the pixel 120. In this twelfth embodiment, a substrate having a solid-state imaging device provided with a pixel array unit including pixels 120 arranged in a matrix is ​​formed thereon is stacked.

[0226] Fig.24 is a perspective view showing a configuration example of an imaging device according to an eleventh embodiment.

[0227] exist Fig.24 In a, the solid-state imaging device 901 includes a supporting substrate 911 and a semiconductor substrate 912. The semiconductor substrate 912 is stacked on the supporting substrate 911. The semiconductor substrate 912 includes a pixel array unit 913 and a peripheral circuit 914. In the peripheral circuit 914, a column readout circuit 915 and a column ADC 916 are formed. The column readout circuit 915 and the column ADC 916 can be formed on both sides of the pixel array unit 913 in the column direction.

[0228] In the pixel array unit 913, the pixels 120 are aligned in a matrix form along the row direction and the column direction. The column readout circuit 915 can limit the potential of the vertical signal line during the D phase VSL setting period and read out a signal from each pixel 120 based on the readout of the capacitive load. In the column readout circuit 915, for example, Figure 6 The signal line reset transistor 141, the diode connection transistor 142, the signal line limiter transistor 146 and the signal line limiter selection transistor 147 in the column ADC 916 can perform AD conversion for each column on the signal read out via the column readout circuit 915. In this case, the solid-state imaging device 901 can be configured as a back-illuminated image sensor.

[0229] exist Fig.24 In b, the solid-state imaging device 902 includes semiconductor substrates 921 and 922. The semiconductor substrate 922 is stacked on the semiconductor substrate 921. On the semiconductor substrate 922, a pixel array unit 923 is formed. On the semiconductor substrate 922, a peripheral circuit 924 is formed. In the peripheral circuit 924, a column readout circuit 925 and a column ADC 926 are formed. The column readout circuit 925 and the column ADC 926 can be formed to meet the positions on both sides of the column direction of the pixel array unit 923. In this case, the solid-state imaging device 902 can be configured as a back-illuminated image sensor.

[0230] As described above, in the above-mentioned twelfth embodiment, the substrates on which each of the solid-state imaging devices 901 and 902 is formed are stacked. Therefore, the semiconductor substrates 912 and 922 on which each of the pixel array units 913 and 923 is formed can be thinned while supporting each of the pixel array units 913 and 923, and a back-illuminated image sensor can be formed.

[0231] <12. Application examples of mobile objects>

[0232] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device equipped in any type of mobile body, such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0233] Fig.25 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology of the present disclosure can be applied.

[0234] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Fig.25 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0235] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a drive force generating device such as an internal combustion engine or a drive motor for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0236] The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, a radio wave transmitted from a portable device instead of a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives the input of the radio wave or the signal, and controls the door lock device, the power window device, and the lights of the vehicle.

[0237] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle and receive the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing on a person, a car, an obstacle, a sign, and letters on a road based on the received image.

[0238] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can also output the electrical signal as an image or distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.

[0239] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0240] The microcomputer 12051 may calculate a control target value of a driving force generation device, a steering mechanism, or a braking device based on information about the interior and exterior of the vehicle acquired by the exterior information detection unit 12030 or the interior information detection unit 12040, and may output a control command to the drive system control unit 12010. For example, the microcomputer 12051 may perform cooperative control for realizing functions of an advanced driver assistance system (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on vehicle-to-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, and the like.

[0241] In addition, the microcomputer 12051 can control the driving force generating device, steering mechanism, braking device, etc. based on the information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, thereby performing collaborative control for automatic driving, etc., in which the vehicle travels autonomously without relying on the operation of the driver.

[0242] In addition, the microcomputer 12051 may output a control command to the body system control unit 12020 based on the information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 may perform cooperative control for preventing glare, such as switching from high beam to low beam, by controlling the headlights according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0243] The audio / image output unit 12052 transmits an output signal of at least one of audio and image to an output device capable of visually or auditorily notifying information to passengers or the outside of the vehicle. Fig.25 In the example of FIG. 12064 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as examples of output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0244] Fig.26 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0245] exist Fig.26 In the embodiment, imaging units 12101, 12102, 12103, 12104 and 12105 are set as imaging unit 12031.

[0246] For example, the imaging units 12101, 12102, 12103, 12104, and 12105 are disposed at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 disposed at the front nose and the imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 disposed on the rear bumper or rear door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0247] Notice, Fig.26An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose, the imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 1210, a bird's-eye view image viewed from the upper side of the vehicle 12100 can be obtained.

[0248] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0249] For example, the microcomputer 12051 can obtain the distance to each three-dimensional object in the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting the three-dimensional object that is the closest on the driving path of the vehicle 12100 and is traveling in the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher) as the front vehicle. In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be ensured with respect to the front vehicle, and can perform automatic braking control (also including follow-up stop control) or automatic acceleration control (also including follow-up start control). In this way, cooperative control for the purpose of automatic driving, etc., can be performed, in which autonomous driving is performed without relying on the driver's operation.

[0250] For example, the microcomputer 12051 can classify and extract three-dimensional data related to the three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects (such as utility poles) based on the distance information obtained from the imaging units 12101 to 12104, and can use the three-dimensional data to perform automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes the surrounding obstacles of the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. In addition, the microcomputer 12051 determines the collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an alarm is output to the driver through the audio speaker 12061 or the display unit 12062, and forced deceleration or avoidance steering is performed through the drive system control unit 12010, and thus driving support for collision avoidance can be performed.

[0251] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is performed by, for example, a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and a process of performing pattern matching processing on a series of feature points indicating the outline of the object and determining whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104 and identifies the pedestrian, the audio / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is superimposed and displayed on the identified pedestrian. In addition, the audio / image output unit 12052 may control the display unit 12062 to display an icon indicating a pedestrian at a desired position, etc.

[0252] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 within the above configuration. More specifically, for example, the above-mentioned camera 100 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, a captured image can be obtained while suppressing an increase in power consumption.

[0253] Note that the above-mentioned embodiments describe examples for implementing the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship with each other. Similarly, the matters specifying the present invention in the claims correspond to the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be implemented by applying various modifications to the embodiments without departing from its purport. In addition, the effects described in this specification are merely exemplary and are not intended to be limiting, and other effects may also be provided.

[0254] Note that the present technology may also have the following configurations.

[0255] (1) An imaging device comprising:

[0256] a signal line whose potential changes based on electric charge stored according to a current flowing when a signal is read out from a pixel;

[0257] A signal line reset transistor is used to reset the potential of the signal line;

[0258] A signal line reset level generating unit, generating a reset level of a potential of a signal line;

[0259] a signal line limiting transistor for limiting the potential of the signal line; and

[0260] The signal line slice voltage setting unit sets a signal line slice voltage for generating a slice level of a potential of the signal line.

[0261] (2) In the imaging device described in (1) above, the potential of the signal line is the potential of the parasitic capacitance of the signal line.

[0262] (3) In the imaging device described in (1) or (2) above, the pixel further includes:

[0263] Photodiode,

[0264] The transfer transistor transfers the charge stored in the photodiode to the floating diffusion,

[0265] Reset transistor, reset floating diffusion,

[0266] an amplifying transistor that outputs a signal corresponding to the potential of the floating diffusion, and

[0267] The selection transistor is connected between the amplification transistor and the signal line.

[0268] (4) In the imaging device described in any one of (1) to (3) above, the signal line reset level generating unit includes a diode-connected transistor.

[0269] (5) The imaging device described in any one of (1) to (4) above further includes: a driver that drives the signal line reset transistor.

[0270] (6) The imaging device described in any one of (1) to (5) above, further comprising: a signal line limiter selection transistor connected between the signal line and the signal line limiter transistor.

[0271] (7) The imaging device described in (6) above further comprises:

[0272] a first chip on which pixels, signal line limit transistors and signal line limit selection transistors are formed, and

[0273] The first chip is stacked on the second chip, and a signal line reset transistor, a signal line reset level generating unit, and a signal line limit voltage setting unit are formed on the second chip.

[0274] (8) In the imaging device described in (6) or (7) above,

[0275] The gate length and gate width of the signal line clipping transistor are equal to the gate length and gate width of the amplifying transistor of the pixel, and

[0276] The gate length and gate width of the signal line clipping selection transistor are equal to the gate length and gate width of the pixel's selection transistor.

[0277] (9) In the imaging device described in any one of (6) to (8) above, the signal line is driven simultaneously by the signal line limit selection transistor and the amplification transistor of the pixel.

[0278] (10) The imaging device described in any one of (6) to (9) above, further includes: a comparator that compares the potential of the signal line with the ramp signal.

[0279] (11) The imaging device described in any one of (6) to (9) above, further including: a comparator that compares potentials of signal lines set to different columns.

[0280] (12) The imaging device described in any one of (6) to (11) above includes:

[0281] a first DC cut-off capacitor connected to a first input terminal of the comparator;

[0282] a second DC cut-off capacitor connected to a second input terminal of the comparator; and

[0283] The auto-zero control unit controls charges stored in the first DC cut-off capacitor and the second DC cut-off capacitor, respectively, so that the first input and the second input of the comparator are balanced during the auto-zero period.

[0284] (13) In the imaging device described in (12) above, the signal line slice selection transistor is turned off after the auto-zero period.

[0285] (14) In the imaging device described in any one of (1) to (13) above, the signal line slice voltage is lower than a reset level of the pixel.

[0286] (15) The imaging device described in any one of (1) to (14) above further includes: a constant current transistor capable of being electrically connected to the signal line and causing a constant current to flow based on a source follower formed between the constant current transistor and the pixel.

[0287] (16) In the imaging device described in (15) above,

[0288] When a constant current is read using a constant current transistor, the constant current transistor is turned on, and

[0289] When the capacitive load is read out using the signal line reset level generating unit, the constant current transistor is turned off.

[0290] (17) In the imaging device described in any one of (1) to (16) above, the signal line slice voltage setting unit generates a plurality of slice levels.

[0291] (18) In the imaging device described in any one of (1) to (17) above, the signal line slice voltage setting unit includes:

[0292] resistor ladder circuit, and

[0293] The first selector switches the divided voltage generated by the resistor ladder circuit.

[0294] (19) In the imaging device described in (18) above, the signal line reset level generating unit includes:

[0295] The second selector switches the divided voltage generated by the resistor ladder circuit.

[0296] (20) The imaging device described in any one of (1) to (19) above further includes: a pixel array unit in which pixels are arranged in a matrix in the row direction and the column direction,

[0297] Signal lines are set per column, and

[0298] A signal line reset transistor and a signal line limiter transistor are provided to each signal line.

[0299] Reference Mark List

[0300] 100 Camera

[0301] 101 Optical System

[0302] 102 Solid-state imaging device

[0303] 103 Imaging control unit

[0304] 104 Image processing unit

[0305] 105 Storage Unit

[0306] 106 Display Unit

[0307] 107 Operating unit

[0308] 108 Bus

[0309] 111 pixel array unit

[0310] 112 vertical scanning circuit

[0311] 113 Column readout circuit

[0312] 114 signal processing units

[0313] 115 Horizontal scanning circuit

[0314] 116 Control Circuit

[0315] 117 Signal line limit voltage setting circuit

[0316] 121 Photodiode

[0317] 122 Pass transistor

[0318] 123 Reset transistor

[0319] 124 Amplifier transistor

[0320] 125 Select transistor

[0321] 126 Floating Diffusion

[0322] 131 Horizontal drive line

[0323] 132 vertical signal line

[0324] 133 Capacitor

[0325] 141 Signal line reset transistor

[0326] 142 Diode-connected transistor

[0327] 143 Comparator

[0328] 144, 145 DC cut-off capacitor

[0329] 146 Signal Line Limiting Transistor

[0330] 147 Signal line limit selection transistor

[0331] 148 Automatic zeroing control unit

[0332] 150 Selector

[0333] 151 to 154 Voltage divider resistor

[0334] 155Resistor ladder circuit.

Claims

1. An imaging device, comprising: a signal line whose potential changes based on electric charge stored according to a current flowing when a signal is read out from a pixel; A signal line reset transistor for resetting the potential of the signal line; a signal line reset level generating unit, generating a reset level of the potential of the signal line; A signal line limiting transistor for limiting the potential of the signal line; as well as The signal line slice voltage setting unit sets a signal line slice voltage for generating a slice level of the potential of the signal line.

2. The imaging device according to claim 1, wherein: The potential of the signal line is a potential of a parasitic capacitance of the signal line.

3. The imaging device according to claim 1, wherein: The pixel further comprises: Photodiode, a transfer transistor that transfers the charge stored in the photodiode to the floating diffusion, a reset transistor, resetting the floating diffusion, an amplifying transistor that outputs a signal corresponding to the potential of the floating diffusion, and a selecting transistor that is connected between the amplifying transistor and the signal line.

4. The imaging device according to claim 1, wherein: The signal line reset level generating unit includes a diode-connected transistor.

5. The imaging device according to claim 1, further comprising: A driver drives the signal line reset transistor.

6. The imaging device according to claim 1, further comprising: The signal line limiter selection transistor is connected between the signal line and the signal line limiter transistor.

7. The imaging device according to claim 6, further comprising: a first chip on which the pixel, the signal line limit transistor and the signal line limit selection transistor are formed, and A second chip, the first chip is stacked on the second chip, and the signal line reset transistor, the signal line reset level generating unit and the signal line limit voltage setting unit are formed on the second chip.

8. The imaging device according to claim 7, wherein: The gate length and gate width of the signal line limiter transistor are equal to the gate length and gate width of the amplifying transistor of the pixel, and The gate length and gate width of the signal line clipping selection transistor are equal to the gate length and gate width of the selection transistor of the pixel.

9. The imaging device according to claim 7, wherein: The signal line is driven simultaneously by the signal line limit selection transistor and the amplification transistor of the pixel.

10. The imaging device according to claim 6, further comprising: A comparator compares the potential of the signal line with a ramp signal.

11. The imaging device according to claim 6, further comprising: The comparator compares the potentials of signal lines provided to different columns.

12. The imaging device according to claim 10, further comprising: a first DC cut-off capacitor connected to a first input terminal of the comparator; a second DC cut-off capacitor connected to a second input terminal of the comparator; as well as An auto-zero control unit controls charges stored in the first DC cut-off capacitor and the second DC cut-off capacitor, respectively, so that the first input and the second input of the comparator are balanced during an auto-zero period.

13. The imaging device according to claim 12, wherein: The signal line limit selection transistor is turned off after the auto-zero period.

14. The imaging device according to claim 1, wherein: The signal line clipping voltage is lower than a reset level of the pixel.

15. The imaging device according to claim 1, further comprising: A constant current transistor is electrically connectable to the signal line and allows a constant current to flow based on a source follower formed between the constant current transistor and the pixel.

16. The imaging device according to claim 15, wherein: When the constant current is read out using the constant current transistor, the constant current transistor is turned on, and When the capacitive load is read out using the signal line reset level generating unit, the constant current transistor is turned off.

17. The imaging device according to claim 1, wherein: The signal line slice voltage setting unit generates a plurality of the slice levels.

18. The imaging device according to claim 1, wherein: The signal line limit voltage setting unit comprises: resistor ladder circuit, and The first selector switches the divided voltage generated by the resistor ladder circuit.

19. The imaging device according to claim 18, wherein: The signal line reset level generating unit comprises: The second selector switches the divided voltage generated by the resistor ladder circuit.

20. The imaging device according to claim 1, further comprising: A pixel array unit, wherein the pixels are arranged in a matrix in row and column directions, wherein: The signal lines are provided per column, and The signal line reset transistor and the signal line limiter transistor are provided to each signal line.

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