Image forming apparatus

Abstract

According to the invention, capacitive load reading can be carried out while current consumption and an increase in stabilization time are suppressed. The imaging device includes: a signal line whose potential changes based on a charge stored in accordance with a current flowing during reading of a signal from a pixel; a signal line transistor electrically connected to the signal line; and a voltage generation unit connected in series to the signal line transistor and capable of generating a voltage higher than 0V. The pixel may include: a photodiode; a transfer transistor that transfers the charge stored in the photodiode to the floating diffusion; a reset transistor that resets the floating diffusion; an amplification transistor that outputs a signal according to the floating-diffused potential; and a selection transistor connected between the amplification transistor and the signal line.

Description

Technical Field

[0001] The present technology relates to an imaging device. The present technology relates to an imaging device capable of performing capacitive load reading. Background Art

[0002] A known capacitive load reading method uses the capacitance of a load of a source follower during signal reading from a pixel. As such a capacitive load reading method, for example, an imaging device is proposed such that after the voltage of an output line is reset by a reset unit, a constant current is passed through the output line by a constant current source, and the source of an amplifier transistor is connected to the output line (for example, see PTL 1).

[0003] [Citation List]

[0004] [Patent Document]

[0005] [PTL 1]

[0006] JP 2021-40270A Summary of the invention

[0007] [Technical issues]

[0008] However, in the conventional technology, an output line reset voltage generating circuit for generating an output line reset voltage is provided to reset the voltage of the output line through the reset unit, so that the current consumption increases accordingly. If the output line reset voltage generating circuit is omitted and the output line reset voltage is set to the ground voltage, the stabilization time increases.

[0009] The present technology has been designed in view of such circumstances. The purpose of the present technology is to realize capacitive load reading while suppressing increases in current consumption and stabilization time.

[0010] [Solution to the problem]

[0011] The present technology has been made to solve this problem. A first aspect of the present technology is an imaging device including: a signal line that changes a potential based on a charge accumulated according to a current flowing when a signal is read from a pixel; a signal line transistor that is electrically connected to the signal line; and a voltage generating unit that is connected in series to the signal line transistor and is capable of generating a voltage higher than 0V. This provides an effect of setting the signal line at a voltage higher than 0V when the signal line is reset.

[0012] In addition, in the first aspect, the potential of the signal line may be the potential of the parasitic capacitance of the signal line. This provides an effect of capacitive load reading without adding a capacitive element to the signal line.

[0013] Furthermore, in the first aspect, the pixel may include: a photodiode; a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion; a reset transistor that resets the floating diffusion; an amplifier transistor that outputs a signal corresponding to the potential of the floating diffusion; and a selection transistor that is connected between the amplifier transistor and the signal line. This provides an effect of forming a source follower together with the pixel when a signal is read from the pixel.

[0014] Furthermore, in the first aspect, the voltage generating unit may include a diode-connected transistor. This provides an effect of raising the potential of the signal line according to the forward voltage of the diode-connected transistor when the signal line is reset.

[0015] In addition, in the first aspect, the voltage generating unit may include a plurality of diode-connected transistors connected in series in different numbers. This provides an effect of switching the voltage of the signal line when the signal line is reset.

[0016] Furthermore, in the first aspect, the voltage generating unit makes the reset level of the signal line when reading the reset level from the pixel equal to or higher than the reset level of the signal line when reading the signal level from the pixel. This provides an effect of shortening the stabilization time when reading the reset level from the pixel.

[0017] In addition, in the first aspect, the imaging device may further include a comparator that compares the potential of the signal line with the ramp signal. This provides an effect of detecting a signal read from a pixel based on the potential of the signal line.

[0018] Furthermore, in the first aspect, the imaging device may further include a comparator that compares the potentials of the signal lines arranged in different columns. This provides an effect of detecting the edge of the subject based on the capacitive load reading.

[0019] In addition, in the first aspect, the imaging device may further include a constant current transistor that can be electrically connected to the signal line and transmits a constant current based on a source follower formed between the pixel and the constant current transistor. This provides an effect of constant current reading when capacitive load reading is not performed.

[0020] In addition, in the first aspect, in constant current reading using a constant current transistor, the constant current transistor can be turned on, and in capacitive load reading using a voltage generating unit, the constant current transistor can be turned off. This provides an effect of switching between capacitive load reading and constant current reading.

[0021] In addition, in the first aspect, the imaging device may further include: a sample-and-hold circuit that operates the signal line transistor as a constant current transistor; and a switch that switches the connection of the signal line transistor between the voltage generating unit and the ground potential. This provides an effect of sharing the signal line transistor in constant current reading and capacitive load reading.

[0022] In the first aspect, in constant current reading, the connection of the signal line transistor can be switched to the ground potential and the signal line transistor is turned on, and in capacitive load reading, the connection of the signal line transistor is switched to the voltage generating unit, and after the signal line is reset, the signal line transistor is turned off. This provides an effect of switching between capacitive load reading and constant current reading.

[0023] Furthermore, in the first aspect, the voltage generating unit may include: a series transistor connected in series to the signal line transistor; and a switch transistor switching between the gate and drain of the series transistor. This provides an effect of sharing the series transistor in constant current reading and capacitive load reading.

[0024] Furthermore, in the first aspect, the switch transistor can be turned off at the time of constant current reading, and the switch transistor can be turned on at the time of capacitive load reading. This provides an effect of switching between capacitive load reading and constant current reading.

[0025] In the first aspect, the imaging device may include a chip on which the pixel is formed, wherein the signal line transistor is formed on the chip. This provides an effect of reducing variations in characteristics of the signal line transistor and characteristics of the pixel transistor.

[0026] In addition, in the first aspect, the voltage generating unit may be formed on a chip. This provides an effect of reducing variations in characteristics of the voltage generating unit and characteristics of the pixel transistor.

[0027] Furthermore, in the first aspect, the imaging device may further include a pixel array unit including pixels arranged in a matrix in the row direction and the column direction, wherein a plurality of signal lines may be arranged in the row direction in such a manner that the signal lines are wired in the column direction, and a signal line transistor may be provided for each signal line. This provides an effect of resetting the potential of the signal line for each signal line.

[0028] In addition, in the first aspect, a voltage generating unit may be provided for each signal line in different columns. This provides an effect of setting the potential of the signal line for each signal line.

[0029] Furthermore, in the first aspect, the voltage generating unit can be shared between a plurality of signal lines in different columns. This provides an effect of reducing the number of voltage generating units relative to the number of columns.

[0030] Furthermore, in the first aspect, the imaging device may further include a short-circuit line that short-circuits the voltage generating unit provided for each signal line in different columns. This provides an effect of reducing variations in potential of the signal lines in each column. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram showing a configuration example of a camera to which the imaging device according to the first embodiment is applied.

[0032] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment.

[0033] Figure 3 is a block diagram showing a circuit configuration example of a pixel provided in the solid-state imaging device according to the first embodiment.

[0034] Figure 4 is a cross-sectional view showing a configuration example of a pixel array unit provided in the solid-state imaging device according to the first embodiment.

[0035] Figure 5 is a cross-sectional view showing a modified example of the pixel array unit provided in the solid-state imaging device according to the first embodiment.

[0036] Figure 6 A configuration example of a signal reading circuit for each column according to the first embodiment is shown.

[0037] Figure 7 An example of a waveform of each unit during signal reading of the imaging device according to the first embodiment is shown.

[0038] Figure 8 A circuit configuration example of a voltage generating unit connected to a vertical signal line of an imaging device according to the first embodiment is shown.

[0039] Fig. 9 : is a block diagram showing an example of switching during capacitive load reading of a signal reading circuit for each column according to the second embodiment.

[0040] Fig.10 is a block diagram showing an example of switching during constant current reading of a signal reading circuit for each column according to the second embodiment.

[0041] Fig.11 An example of a waveform of each cell during constant current reading by the signal reading circuit according to the second embodiment is shown.

[0042] Fig.12A configuration example of a signal reading circuit for each column according to the third embodiment is shown.

[0043] Fig.13 A configuration example of a signal reading circuit for each column according to the fourth embodiment is shown.

[0044] Fig.14 A configuration example of a signal reading circuit for two columns according to the fifth embodiment is shown.

[0045] Fig.15 A configuration example of a signal reading circuit for four columns according to the sixth embodiment is shown.

[0046] Fig.16 A configuration example of a signal reading circuit for each column according to the seventh embodiment is shown.

[0047] Fig.17 An example of a waveform of each unit during signal reading of the imaging device according to the seventh embodiment is shown.

[0048] Fig.18 A configuration example of a signal reading circuit for each column according to the eighth embodiment is shown.

[0049] Fig.19 A configuration example of a signal reading circuit for each column according to the ninth embodiment is shown.

[0050] Fig. 20 A configuration example of a signal reading circuit for each column according to the tenth embodiment is shown.

[0051] Fig.21 A configuration example of a signal reading circuit for two columns according to the eleventh embodiment is shown.

[0052] Fig. 22 An example of a waveform of each unit during signal reading of the imaging device according to the eleventh embodiment is shown.

[0053] Fig.23 is a perspective view showing a configuration example of an imaging device according to a twelfth embodiment.

[0054] Fig.24 is a block diagram showing a schematic configuration example of a vehicle control system.

[0055] Fig.25 is an explanatory diagram showing an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0056] Modes for carrying out the present technology (hereinafter referred to as embodiments) will be described below. The description will be given in the following order.

[0057] 1. First Embodiment (Example of Connecting a Diode-Connected Transistor via a Signal Line Transistor Electrically Connected to a Vertical Signal Line)

[0058] 2. Second Embodiment (Example of Switching of a Signal Line Transistor Electrically Connected to a Vertical Signal Line so that the Signal Line Transistor Operates as a Constant Current Transistor, or Connecting the Signal Line Transistor to a Diode-Connected Transistor)

[0059] 3. Third Embodiment (Example of a Series Circuit in which a Constant Current Transistor is Connected in Parallel to a Signal Line Transistor and a Diode-Connected Transistor)

[0060] 4. Fourth Embodiment (Example in which a series transistor connected in series to a signal line transistor is electrically connected to a vertical signal line so that the series transistor operates as a diode-connected transistor or a constant current transistor)

[0061] 5. Fifth Embodiment (Example of Diode-Connected Transistor Shared Between Multiple Columns)

[0062] 6. Sixth Embodiment (Example of Diode-Connected Transistor Having Drain Shared Between Multiple Columns)

[0063] 7. Seventh Embodiment (Example of a variable number of diode-connected transistors connected in series via a signal line transistor electrically connected to a vertical signal line)

[0064] 8. Eighth Embodiment (Example in which a signal line transistor and a diode-connected transistor are provided on an upper chip having pixels and a constant current transistor is provided on a lower chip)

[0065] 9. Ninth Embodiment (Example of Application of Capacitive Load Reading Using a Series Circuit of a Signal Line Transistor and a Diode-Connected Transistor to a Unit Having an Amplifying Transistor Shared Among Four Photodiodes)

[0066] 10. Tenth Embodiment (Example of Application of Capacitive Load Reading Using a Series Circuit of a Signal Line Transistor and a Diode-Connected Transistor to Binning Reading)

[0067] 11. Eleventh Embodiment (Example of Application of Capacitive Load Reading Using a Series Circuit of a Signal Line Transistor and a Diode-Connected Transistor to Edge Detection)

[0068] 12. Twelfth Embodiment (Example of Lamination of Substrates Forming Solid-State Imaging Device)

[0069] 13. Examples of applications in moving objects

[0070] <1. First Embodiment>

[0071] Figure 1 is a block diagram showing a configuration example of a camera to which the imaging device according to the first embodiment is applied.

[0072] exist Figure 1 , the camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to each other via a bus 108. The camera 100 may be used as an independent unit, may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.

[0073] The optical system 101 allows light from the subject to enter the solid-state imaging device 102 and forms a subject image on a light receiving surface of the solid-state imaging device 102. For example, the optical system 101 may be provided with a focus lens, a zoom lens, and an aperture. The optical system 101 may be provided with a plurality of lenses such as a wide-angle lens, a standard lens, and a telephoto lens.

[0074] The solid-state imaging device 102 converts light from a subject into an electric signal for each pixel, digitizes the electric signal, and then outputs the signal. For example, the solid-state imaging device 102 is a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device).

[0075] The imaging control unit 103 controls imaging of the solid-state imaging device 102 based on a command from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure value, and imaging time of the solid-state imaging device 102.

[0076] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. For example, the image processing is gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that performs processing based on software.

[0077] The storage unit 105 stores images captured by the solid-state imaging device 102 and imaging parameters of the solid-state imaging device 102, etc. In addition, the storage unit 105 can store a program for operating the camera 100 based on software. The storage unit 105 can include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.

[0078] The display unit 106 displays a captured image or displays various types of information supporting an imaging operation. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0079] The operation unit 107 provides a user interface for operating the camera 100. For example, the operation unit 107 may include buttons, dials, and switches provided on the camera 100. The operation unit 107 may be configured as a touch panel with the display unit 106.

[0080] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment.

[0081] exist Figure 2 In FIG. 1 , the solid-state imaging device 102 includes a pixel array unit 111 , a vertical scanning circuit 112 , a column readout circuit 113 , a column signal processing unit 114 , a horizontal scanning circuit 115 , and a control circuit 116 .

[0082] The pixel array unit 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along a row direction (also referred to as a horizontal direction) and a column direction (also referred to as a vertical direction). When reading a signal, the pixel 120 can configure a source follower between the pixel 120 and the column readout circuit 113. The pixels 120 in each row are connected to a horizontal drive line 131, and the pixels 120 in each column are connected to a vertical signal line 132. When reading a signal from the pixel 120, the horizontal drive line 131 drives the pixel 120 of each row. The vertical signal line 132 transmits a potential based on a charge accumulated according to a current flowing when reading a signal from the pixel 120 to the column signal processing unit 114 of each column. The vertical signal line 132 is an example of a signal line described in the claims.

[0083] The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured with a vertical register.

[0084] When reading a signal from the pixel 120, the column readout circuit 113 may configure a source follower between the column readout circuit 113 and the pixel 120. At this time, the column readout circuit 113 may change the potential of the vertical signal line 132 based on the charge held in the pixel 120. The column readout circuit 113 may support capacitive load reading. The column readout circuit 113 may also support constant current reading.

[0085] The column signal processing unit 114 processes the signal transmitted in the column direction from the pixel 120. For example, the column signal processing unit 114 may perform correlated double sampling (CDS: correlated double sampling) based on the signal transmitted in the column direction from the pixel 120. In addition, the column signal processing unit 114 may perform AD (Analog-to-Digital) conversion based on the signal transmitted in the column direction from the pixel 120 and output an imaging signal Gout.

[0086] The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured with a horizontal register.

[0087] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning time in the column direction, the scanning time in the row direction, the operation time of the column readout circuit 113, and the processing time of the column signal processing unit 114.

[0088] Figure 3 is a block diagram showing a circuit configuration example of a pixel provided in the solid-state imaging device according to the first embodiment.

[0089] exist Figure 3 , the pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplifier transistor 124, a selection transistor 125, and a floating diffusion 126. MOS (Metal Oxide Semiconductor) transistors may be used as the transfer transistor 122, the reset transistor 123, the amplifier transistor 124, and the selection transistor 125.

[0090] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion 126 via the transfer transistor 122. In addition, the floating diffusion 126 is connected to the power supply Vdd via the reset transistor 123. The power supply Vdd is connected to the vertical signal line 132 via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion 126.

[0091] The transfer signal ΦTG is applied to the gate of the transfer transistor 122. The pixel reset signal ΦPRT is applied to the gate of the reset transistor 123. The selection signal ΦSEL is applied to the gate of the selection transistor 125. The transfer signal ΦTG, the pixel reset signal ΦPRT and the selection signal ΦSEL can be applied to the gate of the transfer transistor 122. Figure 2 The horizontal driving line 131 transmits the signal to the pixel 120 .

[0092] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode 121 is transferred to the floating diffusion 126. Thereafter, when the selection transistor 125 is turned on, the source potential of the amplifier transistor 124 changes according to the potential of the floating diffusion 126. Then, the source potential of the amplifier transistor 124 is applied to the vertical signal line 132 via the selection transistor 125, and is transmitted via the vertical signal line 132. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion 126 is released.

[0093] Figure 4is a cross-sectional view showing a configuration example of a pixel array unit provided in the solid-state imaging device according to the first embodiment. Figure 4 An example of a front-illuminated solid-state imaging device is shown. Figure 4 A configuration example of three pixels is shown.

[0094] exist Figure 4 In the embodiment, a photodiode 232 for each pixel 120 is formed in a semiconductor substrate 231. The semiconductor substrate 231 may be made of Si, InGaAs, or InP.

[0095] The gate electrode 214 and the wiring layer 210 are formed on the semiconductor substrate 231. The gate electrode 214 is formed on the semiconductor substrate 231 with the gate insulating film 213 interposed therebetween. The sidewall 215 is formed on the sidewall of the gate electrode 214. For example, the gate electrode 214 may be made of polysilicon containing impurities. For example, the gate insulating film 213 may be composed of a silicon oxide film. For example, the sidewall 215 may be composed of a silicon oxide film or a silicon nitride film.

[0096] The gate electrode 214 may be used for a pixel transistor. The pixel transistor includes Figure 3 The transfer transistor 122, the reset transistor 123, the amplifying transistor 124 and the selecting transistor 125 are provided.

[0097] A wiring 216 is formed over the gate electrode 214 . Figure 4 An example of three-layer wiring is shown. At this time, the wiring 216 has an opening OP1 that allows light to enter the photodiode 232. The gate electrode 214 and the wiring 216 are electrically isolated from each other by an insulating layer 217. For example, the insulating layer 217 can be a silicon oxide film. For example, the wiring 216 can be made of a metal such as Al or Cu.

[0098] On the wiring layer 210, a color filter 218 is formed for each pixel 120. On the color filter 218, a microlens 219 is formed for each pixel 120. For example, the color filter 218 and the microlens 219 may be made of a transparent resin such as acrylic resin or polycarbonate. The color filter 218 may be colored with added pigments. For example, the color filter 218 may constitute a Bayer layout.

[0099] Figure 5 is a cross-sectional view showing a modified example of the pixel array unit provided in the solid-state imaging device according to the first embodiment. Figure 5 An example of a back-illuminated solid-state imaging device is shown. Figure 5 A configuration example of three pixels is shown.

[0100] exist Figure 5In the embodiment, a photodiode 222 for each pixel 120 is formed in a semiconductor layer 221. The semiconductor layer 221 may be made of Si, InGaAs, or InP. For example, the semiconductor layer 221 may be formed by reducing the thickness of a semiconductor substrate having the photodiode 222 on the front side from the rear side.

[0101] On the semiconductor layer 221 , a gate electrode 224 and a wiring layer 220 are formed. The gate electrode 224 is formed on the semiconductor layer 221 with the gate insulating film 223 interposed therebetween. The sidewall 225 is formed on the sidewall of the gate electrode 224 .

[0102] The gate electrode 224 may be used for a pixel transistor. The pixel transistor includes Figure 3 The transfer transistor 122, the reset transistor 123, the amplifying transistor 124 and the selecting transistor 125 are provided.

[0103] A wiring 226 is formed over the gate electrode 224 . Figure 5 An example of three-layer wiring is shown. The gate electrode 224 and the wiring 226 are electrically isolated from each other by an insulating layer 227. The semiconductor layer 221 is supported on a support substrate 230 with the insulating layer 227 interposed therebetween. The support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.

[0104] On the rear side of the semiconductor layer 221, a color filter 228 is formed for each pixel 120. On the color filter 228, a microlens 229 is formed for each pixel 120. For example, the color filter 228 may constitute a Bayer layout.

[0105] Figure 6 A configuration example of a signal reading circuit for each column according to the first embodiment is shown.

[0106] exist Figure 6 In FIG. 1 , the amplification transistor 124 is connected to the vertical signal line 132 via the selection transistor 125. Furthermore, a capacitor 133 is added to the vertical signal line 132. The capacitor 133 may be a parasitic capacitance of the vertical signal line 132 or a capacitive element connected to the vertical signal line 132.

[0107] In addition, the signal line transistor 141 is electrically connected to the vertical signal line 132. The signal line transistor 141 can reset the potential VSL of the vertical signal line 132. For example, the signal line transistor 141 can be a MOS transistor. A signal line reset signal ΦRT is applied to the gate of the signal line transistor 141.

[0108] The diode-connected transistor 142 is connected in series to the signal line transistor 141. For example, the diode-connected transistor 142 may be a MOS transistor. At this time, the gate of the diode-connected transistor 142 is connected to the drain of the diode-connected transistor 142. The source of the diode-connected transistor 142 is grounded. The source of the diode-connected transistor 142 may be connected to a potential higher than the ground potential. The diode-connected transistor 142 may generate a voltage higher than 0V (e.g., 0.5V), and the potential VSL of the vertical signal line 132 is set to a potential higher than 0V through the signal line transistor 141. The diode-connected transistor 142 is an example of a voltage generating unit described in the claims.

[0109] The vertical signal line 132 is connected to the inverting input terminal of the comparator 143 via the DC blocking capacitor 144. At this time, the potential VSL of the vertical signal line 132 is applied to the inverting input terminal of the comparator 143 via the DC blocking capacitor 144. The reference signal RAP is input to the non-inverting input terminal of the comparator 143 via the DC blocking capacitor 145. For example, the reference signal RAP is a ramp signal.

[0110] In this configuration, before a signal is read from the pixel 120, the signal line transistor 141 is turned on, so that the potential VSL of the vertical signal line 132 is set to a potential higher than 0 V. Then, after the signal line transistor 141 is turned off, the selection transistor 125 is turned on, so that a signal is read from the pixel 120, and the pixel current IPX passes through the vertical signal line 132 via the selection transistor 125. At this time, a charge corresponding to the pixel current IPX is accumulated in the capacitor 133, and the potential VSL of the vertical signal line 132 changes based on the charge accumulated in the capacitor 133. Thereafter, in the comparator 143, the potential VSL of the vertical signal line 132 is compared with the reference signal RAP, and the comparison result COP is output.

[0111] Figure 7 An example of a waveform of each unit during signal reading of the imaging device according to the first embodiment is shown.

[0112] exist Figure 7, pixel reset / VSL reset is performed in capacitive load reading (K11). At this time, the pixel reset signal ΦPRT rises (t11), and the reset transistor 123 is turned on to reset the floating diffusion 126. In addition, the reset level of the floating diffusion 126 can be set to the power supply potential Vdd. In addition, the signal line reset signal ΦRT rises (t11), and the signal line transistor 141 is turned on to reset the vertical signal line 132. At this time, when the signal line transistor 141 is turned on, the current passes through the diode-connected transistor 142 via the signal line transistor 141. Therefore, the reset level of the vertical signal line 132 is set at a potential higher than 0V (for example, 0.5V) by the forward voltage VR1 of the diode-connected transistor 142. The pixel reset signal ΦPRT and the signal line reset signal ΦRT do not always need to rise at the same time, and can rise at different times. In addition, the signal line reset signal ΦRT does not always need to fall after the pixel reset signal ΦPRT. There is no specific limitation on the time of the fall before the selection signal ΦSEL rises.

[0113] Subsequently, P-phase VSL stabilization is performed (K12). At this time, the signal line reset signal ΦRT falls, the selection signal ΦSEL rises (t12), and the selection transistor 125 is turned on. Thereafter, based on the source follower operation of the amplification transistor 124, the pixel current IPX corresponding to the reset level of the floating diffusion 126 passes through the vertical signal line 132 via the selection transistor 125. Then, a charge corresponding to the pixel current IPX is accumulated in the capacitor 133, and based on the charge accumulated in the capacitor 133, the potential VSL of the vertical signal line 132 is set.

[0114] Subsequently, P-phase AD (K13) is performed. At this time, the selection signal ΦSEL falls (t13), and then the ramp signal is provided to the comparator 143 as the reference signal RAP. Thereafter, in the comparator 143, the potential VSL of the vertical signal line 132 is compared with the reference signal RAP, and the potential VSL corresponds to the reset level. The time when the level of the reference signal RAP coincides with the potential VSL of the vertical signal line 132 is output as the comparison result COP. At this time, the reset level read from the pixel 120 undergoes AD conversion based on the counting operation until the level of the reference signal RAP coincides with the potential VSL of the vertical signal line 132.

[0115] Subsequently, transfer / VSL reset (K14) is performed. At this time, the transfer signal ΦTG rises (t14), and the transfer transistor 122 is turned on to transfer the charge accumulated in the photodiode 121 to the floating diffusion 126. In addition, the signal line reset signal ΦRT rises (t14), and the signal line transistor 141 is turned on to reset the vertical signal line 132. At this time, when the signal line transistor 141 is turned on, the current passes through the diode-connected transistor 142 via the signal line transistor 141. Therefore, by the forward voltage VR1 of the diode-connected transistor 142, the reset level of the vertical signal line 132 is set to a potential higher than 0V (for example, 0.5V). The transfer signal ΦTG and the signal line reset signal ΦRT do not always need to rise at the same time, and may rise at different times. In addition, the signal line reset signal ΦRT does not always need to fall after the transfer signal ΦTG. There is no specific limitation on the time of the fall before the selection signal ΦSEL rises.

[0116] Subsequently, D-phase VSL stabilization is performed (K15). At this time, the signal line reset signal ΦRT falls, the selection signal ΦSEL rises (t15), and the selection transistor 125 is turned on. Thereafter, based on the source follower operation of the amplification transistor 124, the pixel current IPX corresponding to the signal level of the floating diffusion 126 passes through the vertical signal line 132 via the selection transistor 125. Then, a charge corresponding to the pixel current IPX is accumulated in the capacitor 133, and the potential VSL of the vertical signal line 132 is set based on the charge accumulated in the capacitor 133.

[0117] Subsequently, D-phase AD is performed (K16). At this time, the selection signal ΦSEL falls (t16), and then the ramp signal is provided to the comparator 143 as the reference signal RAP (t16 to t17). Thereafter, in the comparator 143, the potential VSL of the vertical signal line 132 is compared with the reference signal RAP, and the potential VSL corresponds to the signal level. The time when the level of the reference signal RAP coincides with the potential VSL of the vertical signal line 132 is output as the comparison result COP. At this time, the signal level read from the pixel 120 undergoes AD conversion based on the counting operation until the level of the reference signal RAP reaches the potential VSL of the vertical signal line 132.

[0118] Figure 8 A circuit configuration example of a voltage generating unit connected to a vertical signal line of an imaging device according to the first embodiment is shown.

[0119] exist Figure 8In a, the voltage generating unit connected to the vertical signal line 132 may include a signal line transistor 141 and a diode-connected transistor 142. At this time, the diode-connected transistor 142 may be an NMOS transistor. In addition, the signal line transistor 141 may be connected to the drain side of the diode-connected transistor 142.

[0120] exist Figure 8 In b, the voltage generating unit connected to the vertical signal line 132 may include a signal line transistor 141 and a diode-connected transistor 142. At this time, the signal line transistor 141 may be connected to the source side of the diode-connected transistor 142.

[0121] exist Figure 8 In c, the voltage generating unit connected to the vertical signal line 132 may include a signal line transistor 141 and a diode-connected transistor 146. At this time, the diode-connected transistor 146 may be a PMOS transistor. In addition, the signal line transistor 141 may be connected to the drain side of the diode-connected transistor 146, or the signal line transistor 141 may be connected to the source side of the diode-connected transistor 146.

[0122] exist Figure 8 In d, the voltage generating unit connected to the vertical signal line 132 may include a signal line transistor 141 and a PN junction diode 147. At this time, the signal line transistor 141 may be connected to the anode side of the PN junction diode 147, or the signal line transistor 141 may be connected to the cathode side of the PN junction diode 147.

[0123] exist Figure 8 In the embodiment of the present invention, the voltage generating unit connected to the vertical signal line 132 may include a signal line transistor 141 and a voltage dividing resistor 148 and a voltage dividing resistor 149. The voltage dividing resistor 148 and the voltage dividing resistor 149 are connected in series. In addition, the source of the signal line transistor 141 is connected to the node of the voltage dividing resistor 148 and the voltage dividing resistor 149. In this configuration, the resistance value of the voltage dividing resistor 148 and the voltage dividing resistor 149 can be increased to reduce the current passing through the voltage dividing resistor 148 and the voltage dividing resistor 149.

[0124] As described above, in the first embodiment, when a signal is read from the pixel 120, the vertical signal line 132 is reset so that a charge corresponding to the pixel current IPX that passes when the signal is read from the pixel 120 can be accumulated in the capacitor 133. Therefore, a constant current corresponding to the signal read from the pixel 120 does not need to pass through the vertical signal line 132 to detect the signal read from the pixel 120, thereby reducing current consumption when the signal is read from the pixel 120.

[0125] In addition, the diode-connected transistor 142 is connected in series to the signal line transistor 141, so that during the reset period of the vertical signal line 132, the potential of the vertical signal line 132 can rise according to the forward voltage VR1 of the diode-connected transistor 142. Therefore, at the start of the stabilization of the P-phase VSL, the potential of the vertical signal line 132 can be set to be higher than 0V, thereby shortening the stabilization time.

[0126] <2. Second Embodiment>

[0127] In the first embodiment, the diode-connected transistor 142 is connected via the signal line transistor 141 electrically connected to the vertical signal line 132. In the second embodiment, the signal line transistor 141 electrically connected to the vertical signal line 132 is switched to operate as a constant current transistor or is switched to be connected to the diode-connected transistor 142.

[0128] Fig. 9 : is a block diagram showing an example of switching during capacitive load reading of a signal reading circuit for each column according to the second embodiment.

[0129] exist Fig. 9 In the embodiment, the signal reading circuit is configured such that a sample hold circuit 201 and switches 202 and 203 are added to the signal reading circuit of the first embodiment. The other configuration of the signal reading circuit of the second embodiment is the same as that of the signal reading circuit of the first embodiment.

[0130] The sample-and-hold circuit 201 samples and holds a bias voltage Vb, which allows the signal line transistor 141 to operate as a constant current transistor, and applies a voltage to the gate of the signal line transistor 141. The sample-and-hold circuit 201 includes a transistor 211 and a capacitor 212. The transistor 211 may be a MOS transistor. A sample-and-hold signal ΦSH is applied to the gate of the transistor 211. The capacitor 212 is connected between the source of the transistor 211 and the ground potential.

[0131] The switch 202 switches the gate input of the signal line transistor 141 between the signal line reset signal φRT and the output of the sample and hold circuit 201. The switch 203 switches the connection of the signal line transistor 141 between the ground potential and the diode-connected transistor 142.

[0132] In this configuration, switch 202 switches the gate input of signal line transistor 141 to signal line reset signal φRT in capacitive load reading. Switch 203 switches the connection of signal line transistor 141 to diode-connected transistor 142. At this time, the operation of the signal reading circuit is the same as Figure 7 The operation is the same as

[0133] Fig.10is a block diagram showing an example of switching during constant current reading of a signal reading circuit for each column according to the second embodiment.

[0134] exist Fig.10 In constant current reading, the switch 202 switches the gate input of the signal line transistor 141 to the output of the sample and hold circuit 201. At this time, the bias voltage Vb is set to turn on the signal line transistor 141. The switch 203 switches the connection of the signal line transistor 141 to the ground potential.

[0135] Fig.11 An example of a waveform of each cell during constant current reading by the signal reading circuit according to the second embodiment is shown.

[0136] exist Fig.11 In order to prevent horizontal noise during AD conversion in constant current reading, transistor 211 is turned on to sample and hold bias voltage Vb. Thereafter, transistor 211 is turned off, and bias voltage Vb sampled and held by sample-and-hold circuit 201 is applied to the gate of signal line transistor 141, allowing signal line transistor 141 to operate as a constant current transistor.

[0137] Subsequently, pixel reset is performed (K21). At this time, the pixel reset signal ΦPRT rises (t21), and the reset transistor 123 is turned on to reset the floating diffusion 126. In addition, the selection signal ΦSEL rises (t21), and the selection transistor 125 is turned on. At this time, based on the source follower operation performed when the power supply potential Vdd is applied to the gate of the amplification transistor 124, the potential VSL of the vertical signal line 132 is set.

[0138] Subsequently, P-phase VSL stabilization is performed (K22). At this time, the pixel reset signal ΦPRT falls (t22), and the reset transistor 123 is turned off. Then, based on the source follower operation performed when the reset level of the floating diffusion 126 is applied to the gate of the amplifying transistor 124, the potential VSL of the vertical signal line 132 is set.

[0139] Thereafter, P-phase AD (K23) is performed. At this time, the ramp signal is provided to the comparator 143 as the reference signal RAP. Thereafter, in the comparator 143, the potential VSL of the vertical signal line 132 is compared with the reference signal RAP, and the potential VSL corresponds to the reset level. The time when the level of the reference signal RAP is consistent with the potential VSL of the vertical signal line 132 is output as the comparison result COP. At this time, the reset level read from the pixel 120 undergoes AD conversion based on the counting operation until the level of the reference signal RAP is consistent with the potential VSL of the vertical signal line 132.

[0140] Subsequently, transfer is performed (t24). At this time, the transfer signal ΦTG rises (t24), and the transfer transistor 122 is turned on to transfer the charge accumulated in the photodiode 121 to the floating diffusion 126. In addition, based on the source follower operation performed when the cathode potential of the photodiode 121 is applied to the gate of the amplifying transistor 124, the potential VSL of the vertical signal line 132 is set.

[0141] Subsequently, D-phase VSL stabilization is performed (K25). At this time, the transfer signal ΦTG falls (t25), and the transfer transistor 122 is turned off. Then, based on the source follower operation performed when the signal level of the floating diffusion 126 is applied to the gate of the amplifying transistor 124, the potential VSL of the vertical signal line 132 is set.

[0142] Subsequently, P-phase AD (K26) is performed. At this time, the ramp signal is provided to the comparator 143 as the reference signal RAP (t26 to t27). Thereafter, in the comparator 143, the potential VSL of the vertical signal line 132 is compared with the reference signal RAP, and the potential VSL corresponds to the signal level. The time when the level of the reference signal RAP is consistent with the potential VSL of the vertical signal line 132 is output as the comparison result COP. At this time, the signal level read from the pixel 120 undergoes AD conversion based on the counting operation until the level of the reference signal RAP reaches the potential VSL of the vertical signal line 132.

[0143] As described in the second embodiment, the signal line transistor 141 can be used to reset the vertical signal line 132, or the signal line transistor 141 can be used as a constant current transistor. This makes it possible to switch between capacitive load reading and constant current reading, so that the imaging device can operate at low power consumption or high speed according to the usage mode of the imaging device.

[0144] <3. Third Embodiment>

[0145] In the second embodiment, constant current reading and capacitive load reading can be switched based on the switching operation of the switch 202 and the switch 203. In the third embodiment, in order to switch constant current reading and capacitive load reading, a constant current transistor is connected in parallel with a series circuit of a signal line transistor 141 and a diode-connected transistor 142.

[0146] Fig.12 A configuration example of a signal reading circuit for each column according to the third embodiment is shown.

[0147] exist Fig.12In the embodiment, the signal reading circuit is configured such that a sample hold circuit 201 and a constant current transistor 301 are added to the signal reading circuit of the first embodiment. The other configuration of the signal reading circuit of the third embodiment is the same as that of the signal reading circuit of the first embodiment.

[0148] The constant current transistor 301 is electrically connected to the vertical signal line 132. The constant current transistor 301 may be a MOS transistor. The output terminal of the sample and hold circuit 201 is connected to the gate of the constant current transistor 301.

[0149] In the capacitive load reading of this configuration, the bias voltage Vb is set to 0V, and the sample hold signal ΦSH is set to a high level. In this case, the constant current transistor 301 is turned off so that the current does not pass through the constant current transistor 301. At this time, the operation of the signal reading circuit is the same as Figure 7 The operation is the same as

[0150] In constant current reading, transistor 211 is turned on to sample and hold bias voltage Vb. Thereafter, transistor 211 is turned off, and bias voltage Vb sampled and held by sample-and-hold circuit 201 is applied to the gate of constant current transistor 301. In this case, constant current transistor 301 is turned on so that a constant current passes through constant current transistor 301. At this time, the operation of the signal reading circuit is the same as Fig.11 The operation is the same as

[0151] As described above, in the third embodiment, the constant current transistor 301 is connected in parallel with the series circuit of the signal line transistor 141 and the diode-connected transistor 142. This makes it possible to switch between constant current reading and capacitive load reading without setting the switch 202 and the switch 203, and to achieve a shorter stabilization time during the capacitive load reading.

[0152] <4. Fourth Embodiment>

[0153] In the third embodiment, in order to switch between constant current reading and capacitive load reading, the constant current transistor 301 is connected in parallel with the series circuit of the signal line transistor 141 and the diode-connected transistor 142. In the fourth embodiment, in order to switch between constant current reading and capacitive load reading, the switching transistor is connected between the gate and the drain of the series transistor, and the series transistor is connected in series with the signal line transistor 141 electrically connected to the vertical signal line 132.

[0154] Fig.13 A configuration example of a signal reading circuit for each column according to the fourth embodiment is shown.

[0155] exist Fig.13In the embodiment, the signal reading circuit includes a series transistor 402 instead of the diode-connected transistor 142 of the first embodiment. In addition, in the signal reading circuit, a sample-and-hold circuit 201 and a switch transistor 401 are added to the signal reading circuit of the first embodiment. The other configurations of the signal reading circuit of the fourth embodiment are the same as those of the signal reading circuit of the first embodiment.

[0156] The series transistor 402 is connected in series to the signal line transistor 141. The switch transistor 401 is connected between the gate and the drain of the series transistor 402. The switch signal DSF is applied to the gate of the switch transistor 401. The series transistor 402 and the switch transistor 401 may be MOS transistors.

[0157] In the capacitive load reading of this configuration, the switch signal DSF is set to a high level and the switch transistor 401 is turned on. At this time, the gate and drain of the series transistor 402 are short-circuited, and the series transistor 402 operates as a diode-connected transistor. The sampling and holding signal ΦSH is set to a low level, and the transistor 211 is turned off. At this time, the operation of the signal reading circuit is the same as Figure 7 The operation is the same as

[0158] In constant current reading, the switch signal DSF is set to a low level, and the switch transistor 401 is turned off. In addition, the transistor 211 is turned on to sample and hold the bias voltage Vb. Thereafter, the transistor 211 is turned off, and the bias voltage Vb sampled and held by the sample-and-hold circuit 201 is applied to the gate of the series transistor 402. In this case, the series transistor 402 is turned on, so that a constant current passes through the series transistor 402. At this time, the operation of the signal reading circuit is the same as Fig.11 The operation is the same as

[0159] As described above, in the fourth embodiment, the series transistor 402 is connected in series to the signal line transistor 141, and the switch transistor 401 is connected between the gate and the drain of the series transistor 402. This makes it possible to switch between constant current reading and capacitive load reading without providing the switch 202 and the switch 203, and to achieve a shorter stabilization time during the capacitive load reading.

[0160] <5. Fifth embodiment>

[0161] In the first embodiment, the diode-connected transistor 142 is provided for each column. In the fifth embodiment, the diode-connected transistor 142 is shared among a plurality of columns.

[0162] Fig.14 A configuration example of a signal reading circuit for two columns according to the fifth embodiment is shown.

[0163] exist Fig.14 In the embodiment, the signal reading circuit includes a plurality of vertical signal lines 132-1 and 132-2, and switches 501 and 502 are added to the signal reading circuit of the first embodiment. The other configuration of the signal reading circuit of the fifth embodiment is the same as that of the signal reading circuit of the first embodiment.

[0164] The pixel 120 is connected to each of the vertical signal line 132-1 and the vertical signal line 132-2, and a comparator 143 is provided for each of the vertical signal line 132-1 and the vertical signal line 132-2. In addition, a signal line transistor 141 is connected to each of the vertical signal line 132-1 and the vertical signal line 132-2, and a switch 501 and a switch 502 are provided for the vertical signal line 132-1 and the vertical signal line 132-2, respectively.

[0165] The switch 501 switches the connection of the signal line transistor 141 connected to the vertical signal line 132-1 between the ground potential and the diode-connected transistor 142. The switch 502 switches the connection of the signal line transistor 141 connected to the vertical signal line 132-2 between the ground potential and the diode-connected transistor 142. In this configuration, the connection of the signal line transistor 141 connected to each of the vertical signal line 132-1 and the vertical signal line 132-2 is switched to the diode-connected transistor 142, so that the diode-connected transistor 142 can be shared between a plurality of columns.

[0166] At this time, in the comparator 143 connected to the vertical signal line 132-1, the potential VSL1 of the vertical signal line 132-1 is compared with the reference signal RAP, and the comparison result COP1 is output. In the comparator 143 connected to the vertical signal line 132-2, the potential VSL2 of the vertical signal line 132-2 is compared with the reference signal RAP, and the comparison result COP2 is output.

[0167] As described above, in the fifth embodiment, the diode-connected transistor 142 is shared among a plurality of columns. This can increase the number of columns while suppressing an increase in the number of diode-connected transistors 142.

[0168] <6. Sixth Implementation Method>

[0169] In the first embodiment, the reset level of the vertical signal line 132 is set for each column. In the sixth embodiment, the reset level of the vertical signal line 132 is set for common use in a plurality of columns.

[0170] Fig.15 A configuration example of a signal reading circuit for four columns according to the sixth embodiment is shown.

[0171] exist Fig.15In the embodiment, the signal reading circuit includes a plurality of vertical signal lines 132-1 to 132-4, and a short-circuit line 601 is added to the signal reading circuit of the first embodiment. The other configuration of the signal reading circuit of the sixth embodiment is the same as that of the signal reading circuit of the first embodiment.

[0172] The pixel 120 is connected to each of the vertical signal lines 132-1 to 132-4, and a comparator 143 is provided for each of the vertical signal lines 132-1 to 132-4. In addition, a diode-connected transistor 142 is connected to each of the vertical signal lines 132-1 to 132-4 via a signal line transistor 141. The drains of the diode-connected transistors 142 provided for the respective vertical signal lines 132-1 to 132-4 are connected to each other via a short-circuit line 601.

[0173] At this time, in the comparator 143 connected to the vertical signal line 132-1, the potential VSL1 of the vertical signal line 132-1 is compared with the reference signal RAP, and a comparison result COP1 is output. In the comparator 143 connected to the vertical signal line 132-2, the potential VSL2 of the vertical signal line 132-2 is compared with the reference signal RAP, and a comparison result COP2 is output. In the comparator 143 connected to the vertical signal line 132-3, the potential VSL3 of the vertical signal line 132-3 is compared with the reference signal RAP, and a comparison result COP3 is output. In the comparator 143 connected to the vertical signal line 132-4, the potential VSL4 of the vertical signal line 132-4 is compared with the reference signal RAP, and a comparison result COP4 is output.

[0174] As described above, in the sixth embodiment, the drains of the diode-connected transistors 142 of different columns are connected to each other via the short-circuit line 601. This can perform capacitive load reading for each column while reducing variations in the reset level of the vertical signal line 132 between columns.

[0175] <7. Seventh Implementation Method>

[0176] In the first embodiment, the reset level of the vertical signal line 132 is fixed to a specific value in P-phase VSL stabilization and D-phase VSL stabilization. In the seventh embodiment, the reset level of the vertical signal line 132 can be switched between P-phase VSL stabilization and D-phase VSL stabilization.

[0177] Fig.16 A configuration example of a signal reading circuit for each column according to the seventh embodiment is shown.

[0178] exist Fig.16In the embodiment, the signal reading circuit is configured such that a switch 701 and a diode-connected transistor 702 and a diode-connected transistor 703 are added to the signal reading circuit of the first embodiment. The other configurations of the signal reading circuit of the seventh embodiment are the same as those of the signal reading circuit of the first embodiment.

[0179] The diode-connected transistor 702 and the diode-connected transistor 703 are connected in series. The switch 701 switches the connection of the signal line transistor 141 between the diode-connected transistor 142 and the series circuit of the diode-connected transistor 702 and the diode-connected transistor 703.

[0180] At this time, when the signal line transistor 141 is connected to the diode-connected transistor 142, the reset level of the vertical signal line 132 can rise according to the forward voltage VR1 of the diode-connected transistor 142. When the signal line transistor 141 is connected to the series circuit of the diode-connected transistor 702 and the diode-connected transistor 703, the reset level of the vertical signal line 132 can rise according to the forward voltage sum VR2 of the diode-connected transistor 702 and the diode-connected transistor 703.

[0181] Fig.17 An example of a waveform of each unit during signal reading of the imaging device according to the seventh embodiment is shown.

[0182] and Figure 7 Same as in, execute Fig.17 . However, in the pixel reset / VSL reset (K11) before the P phase AD (K13), the signal line transistor 141 is connected to the series circuit of the diode-connected transistor 702 and the diode-connected transistor 703. At this time, the reset level of the vertical signal line 132 is set to the sum of the forward voltages VR2 of the diode-connected transistor 702 and the diode-connected transistor 703. In the transfer / VSL reset (K14) before the D phase AD (K16), the signal line transistor 141 is connected to the diode-connected transistor 142. At this time, the reset level of the vertical signal line 132 is set to the forward voltage VR1 of the diode-connected transistor 142.

[0183] As described above, in the seventh embodiment, the reset level of the vertical signal line 132 in the P-phase VSL stabilization is set to be higher than the reset level of the vertical signal line 132 in the D-phase VSL stabilization. This can shorten the stabilization time before the P-phase AD (K13) in the capacitive load reading. In addition, when the amount of incident light is large, the potential VSL of the vertical signal line 132 of the vertical signal line 132 can be limited by the forward voltage sum VR2 of the diode-connected transistor 702 and the diode-connected transistor 703. This can prevent the sunspot phenomenon.

[0184] In the seventh embodiment, in order to switch the reset level of the vertical signal line 132, a series circuit of a diode-connected transistor 702 and a diode-connected transistor 703 is provided in addition to the diode-connected transistor 142. A series circuit of three or more diode-connected transistors may be provided to switch the reset level of the vertical signal line 132. In addition, the configuration that allows switching of the reset level of the vertical signal line 132 is applicable to any of the configurations in the second to sixth embodiments.

[0185] <8. Eighth Implementation Method>

[0186] In the first embodiment, the diode-connected transistor 142 is connected via the signal line transistor 141 electrically connected to the vertical signal line 132, which transmits the signal read from the pixel 120. In the eighth embodiment, the signal line transistor 141 and the diode-connected transistor 142 are provided on an upper chip having the pixel 120, and the constant current transistor 301 is provided on a lower chip.

[0187] Fig.18 A configuration example of a signal reading circuit for each column according to the eighth embodiment is shown.

[0188] exist Fig.18 In the circuit configuration of the signal reading circuit, Fig.12 The circuit configuration of the signal reading circuit is the same as that of the signal reading circuit of FIG. However, the signal reading circuit is formed on a laminated chip. The laminated chip includes an upper chip 801 and a lower chip 802. The upper chip 801 is stacked on the lower chip 802.

[0189] On the upper chip 801, a pixel 120, a vertical signal line 132, a signal line transistor 141, and a diode-connected transistor 142 are formed. At this time, the size and threshold of the signal line transistor 141 can be set like the size and threshold of the selection transistor 125. The size and threshold of the diode-connected transistor 142 can be set like the size and threshold of the reset transistor 123.

[0190] On the lower chip 802, the sample and hold circuit 201, the constant current transistor 301, and the comparator 143 are formed. At this time, the vertical signal line 132 can be routed from the upper chip 801 to the lower chip 802.

[0191] As described above, in the eighth embodiment, the signal line transistor 141 and the diode-connected transistor 142 are formed on the upper chip 801 having the pixel 120. This can equalize the variation in the characteristics of the pixel transistor provided in the pixel 120 and the variation in the characteristics of the signal line transistor 141 and the diode-connected transistor 142. In addition, the configuration in which the signal reading circuit is formed on the laminated chip is applicable to any of the configurations in the second to seventh embodiments.

[0192] <9. Ninth Implementation Method>

[0193] In the first embodiment, capacitive load reading is applied to the pixel 120 in which a single photodiode 121 is provided for a single amplifier transistor 124. In the ninth embodiment, capacitive load reading is applied to a unit in which four photodiodes are provided for a single amplifier transistor 124.

[0194] Fig.19 A configuration example of a signal reading circuit for each column according to the ninth embodiment is shown.

[0195] exist Fig.19 In the embodiment, the signal reading circuit includes a unit 130 instead of the pixel 120 of the signal reading circuit according to the first embodiment. The other configuration of the signal reading circuit of the ninth embodiment is the same as that of the signal reading circuit of the first embodiment.

[0196] The cell 130 includes photodiodes 121-1 to 121-4 and transfer transistors 122-1 to 122-4 instead of the photodiode 121 and the transfer transistor 122 of the first embodiment. The other configuration of the cell 130 of the ninth embodiment is the same as that of the pixel 120 of the first embodiment.

[0197] The photodiodes 121-1 to 121-4 may be arranged in two rows and two columns. The photodiodes 121-1 to 121-4 are connected to the floating diffusion 126 via the transfer transistors 122-1 to 122-4, respectively. The transfer signals ΦTG1 to ΦTG4 are applied to the gates of the transfer transistors 122-1 to 122-4. By controlling the application time of the transfer signals ΦTG1 to ΦTG4, signals can be read from the respective photodiodes 121-1 to 121-4 to the vertical signal line 132. The capacitive load reading operation from the photodiodes 121-1 to 121-4 is similar to Figure 7 The same.

[0198] As described above, in the ninth embodiment, four photodiodes are shared by the single amplifying transistor 124. This can increase the number of pixels while suppressing an increase in the pixel area, and apply capacitive load reading for each pixel.

[0199] In the example of the ninth embodiment, four photodiodes 121-1 to 121-4 are shared by a single amplifier transistor 124. Eight photodiodes can be shared by a single amplifier transistor 124. Furthermore, any one of the configurations in the second to eighth embodiments can be applied to the configuration including the unit 130.

[0200] <10. Tenth Implementation Method>

[0201] In the first embodiment, capacitive load reading is applied to read signals from individual pixels 120 connected to the vertical signal line 132. In the tenth embodiment, capacitive load reading is applied to binning reading from pixels 120 connected to the vertical signal line 132.

[0202] Fig. 20 A configuration example of a signal reading circuit for each column according to the tenth embodiment is shown.

[0203] exist Fig. 20 In the embodiment, the signal reading circuit includes a pixel 140 and a pixel 150 instead of the pixel 120 of the signal reading circuit of the first embodiment. In addition, the signal reading circuit is configured so that a merging line 134 is added to the signal reading circuit of the first embodiment. The other configurations of the signal reading circuit of the tenth embodiment are the same as those of the signal reading circuit of the first embodiment.

[0204] The pixel 140 and the pixel 150 are configured such that the merging transistor 127 is added to the pixel 120 of the first embodiment. The other configurations of the pixel 140 and the pixel 150 of the tenth embodiment are the same as those of the pixel 120 of the first embodiment.

[0205] A merging transistor 127 for each of the pixels 140 and 150 is connected between the floating diffusion 126 and the merging line 134. The merging transistor 127 may be a MOS transistor. For each of the pixels 140 and 150, a merging signal ΦBN1 and a merging signal ΦBN2 are applied to the gate of the merging transistor 127. For each of the pixels 140 and 150, a transfer signal ΦTG1 and a transfer signal ΦTG2 are applied to the gate of the transfer transistor 122. For each of the pixels 140 and 150, a pixel reset signal ΦPRT1 and a pixel reset signal ΦPRT2 are applied to the gate of the reset transistor 123. For each of the pixels 140 and 150, a selection signal ΦSEL1 and a selection signal ΦSEL2 are applied to the gate of the selection transistor 125.

[0206] When reading signals from each pixel 140 and 150, the merge signal ΦBN1 and the merge signal ΦBN2 are set to a low level, and the merge transistor 127 of each of the pixels 140 and 150 is turned off. In the case of merging read signals from each pixel 140 and 150, the merge signal ΦBN1 and the merge signal ΦBN2 are set to a high level, and the merge transistor 127 of each of the pixels 140 and 150 is turned on. The capacitive load reading operation of the pixel 140 and the pixel 150 is different from the Figure 7 At this time, in the binning read, either one of the selection transistors 125 of the pixel 140 and the pixel 150 may be turned on, or both of the selection transistors 125 of the pixel 140 and the pixel 150 may be turned on.

[0207] As described above, in the tenth embodiment, the binning transistor 127 is provided in each of the pixel 140 and the pixel 150 connected to the vertical signal line 132. This can apply capacitive load reading while reducing the number of readings in each frame, thereby reducing power consumption.

[0208] Furthermore, any one of the configurations of the second embodiment to the ninth embodiment may be applied to the configuration including the pixel 140 and the pixel 150 .

[0209] <11. Eleventh Implementation Method>

[0210] In the first embodiment, a signal read from a pixel 120 is detected based on the potential VSL of a vertical signal line 132 connected to the pixel 120. In the eleventh embodiment, edge detection is performed based on a comparison result of the potential of a vertical signal line based on load capacitance read from different columns.

[0211] Fig.21 A configuration example of a signal reading circuit for two columns according to the eleventh embodiment is shown.

[0212] exist Fig.21 In the embodiment, the signal reading circuit includes a plurality of vertical signal lines 132-1 and 132-2 and comparators 143-1 and 143-2 instead of the comparator 143 of the first embodiment. The other configuration of the signal reading circuit of the eleventh embodiment is the same as that of the first embodiment.

[0213] The pixel 120-1 and the pixel 120-2 are connected to the vertical signal line 132-1 and the vertical signal line 132-2, respectively. The vertical signal line 132-1 and the vertical signal line 132-2 are connected to the comparators 143-1 and 143-2, respectively.

[0214] The pixel 120-1 and the pixel 120-2 may be configured as Figure 6The pixel 120-1 and the pixel 120-2 are connected to the vertical signal line 132-1 and the vertical signal line 132-2, respectively. In addition, the diode-connected transistor 142 is connected to each of the vertical signal line 132-1 and the vertical signal line 132-2 via the signal line transistor 141. The comparator 143-1 and the comparator 143-2 compare the potential VLS1 and the potential VLS2 of the vertical signal line 132-1 and the vertical signal line 132-2. When the difference between the potential VLS1 and the potential VLS2 of the vertical signal line 132-1 and the vertical signal line 132-2 is equal to or greater than the threshold value, it can be determined that there is an edge.

[0215] Fig. 22 An example of a waveform of each unit during signal reading of the imaging device according to the eleventh embodiment is shown.

[0216] exist Fig. 22 The capacitive load reading operation is similar to Figure 7 However, in the eleventh embodiment, when signals are read from the pixel 120-1 and the pixel 120-2, the pixel current IPX1 and the pixel current IPX2 pass through each vertical signal line 132-1 and 132-2. At this time, the charges corresponding to the pixel current IPX1 and the pixel current IPX2 of each vertical signal line 132-1 and the vertical signal line 132-2 are accumulated in the capacitor 133. Thereafter, the potential VSL1 and the potential VSL2 of the vertical signal line 132-1 and the vertical signal line 132-2 change according to the charges accumulated in the capacitor 133 of the vertical signal line 132-1 and the vertical signal line 132-2, and are input to the comparator 143-1 and the comparator 143-2, respectively. When the comparison signal COT rises in the comparator 143 - 1 and the comparator 143 - 2 ( t16 ), the potential VSL1 and the potential VSL2 of the vertical signal line 132 - 1 and the vertical signal line 132 - 2 are compared with each other, and the comparison result is output.

[0217] As described above, in the eleventh embodiment, each of the comparators 143-1 and 143-2 detects the difference between the potential VLS1 and the potential VLS2 of the vertical signal line 132-1 and the vertical signal line 132-2, and the potential VLS1 and the potential VLS2 are read based on the load capacitance. This can detect the edge of the subject while reducing power consumption.

[0218] <12. Twelfth Implementation Method>

[0219] In the first embodiment, the diode-connected transistor 142 is connected to the signal line transistor 141 electrically connected to the vertical signal line 132 that transmits a signal read from the pixel 120. In the twelfth embodiment, a substrate forming a solid-state imaging device including a pixel array unit having pixels 120 arranged in a matrix form is laminated.

[0220] Fig.23 is a perspective view showing a configuration example of an imaging device according to a twelfth embodiment.

[0221] exist Fig.23 In a, the solid-state imaging device 901 includes a supporting substrate 911 and a semiconductor substrate 912. The semiconductor substrate 912 is stacked on the supporting substrate 911. On the semiconductor substrate 912, a pixel array unit 913 and a peripheral circuit 914 are formed. In the peripheral circuit 914, a column readout circuit 915 and a column ADC 916 are formed. The column readout circuit 915 and the column ADC 916 can be formed on both sides of the pixel array unit 913 in the column direction.

[0222] In the pixel array unit 913, the pixels 120 are arranged in a matrix along the row direction and the column direction. The column readout circuit 915 can read signals from the pixels 120 based on capacitive load reading. For example, in the column readout circuit 915, Figure 6 The signal line of the reset transistor 141 and the diode-connected transistor 142. The column ADC 916 can perform AD conversion for each column on the signal read by the column readout circuit 915. At this time, the solid-state imaging device 901 can configure a rear-illuminated image sensor.

[0223] exist Fig.23 In b, the solid-state imaging device 902 includes a semiconductor substrate 921 and a semiconductor substrate 922. The semiconductor substrate 922 is stacked on the semiconductor substrate 921. A pixel array unit 923 is formed on the semiconductor substrate 922. A peripheral circuit 924 is formed on the semiconductor substrate 922. In the peripheral circuit 924, a column readout circuit 925 and a column ADC 926 are formed. The column readout circuit 925 and the column ADC 926 can be formed at positions on both sides of the pixel array unit 923 in the column direction. At this time, the solid-state imaging device 902 can be configured as a rear-illuminated image sensor.

[0224] As described above, in the twelfth embodiment, the substrates formed with the solid-state imaging device 901 and the solid-state imaging device 902 are stacked. This configuration can reduce the thickness of the semiconductor substrate 912 and the semiconductor substrate 922 formed with the pixel array unit 913 and the pixel array unit 923, while supporting the pixel array unit 913 and the pixel array unit 923, and form a back-illuminated image sensor.

[0225] <13. Example of application to moving objects>

[0226] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device equipped in any type of mobile object (such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, and a robot).

[0227] Fig.24 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0228] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. Fig.24 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0229] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a drive force generator (such as an internal combustion engine or a drive motor) for generating the drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a control device (such as a brake device) for generating the braking force of the vehicle.

[0230] The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, a radio wave transmitted from a portable device that replaces the key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives the input of the radio wave or the signal and controls the door locking device, the power window device, and the lights of the vehicle.

[0231] The vehicle exterior information detection unit 12030 detects information of the exterior of the vehicle in which the vehicle control system 12000 is installed. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle and receive the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing on a person, car, obstacle, sign, and letter on the road based on the received image.

[0232] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output the electrical signal as an image or distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.

[0233] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration or can determine whether the driver is dozing off based on the detection information input from the driver state detection unit 12041.

[0234] The microcomputer 12051 may calculate a control target value for a driving force generating device, a steering mechanism, or a braking device based on vehicle exterior or interior information acquired by the vehicle exterior information detecting unit 12030 or the vehicle interior information detecting unit 12040, and may output a control command to the driving system control unit 12010. For example, the microcomputer 12051 may perform coordinated control to implement functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact buffering, following driving based on following distance, vehicle speed maintaining driving, vehicle collision warning, or lane departure warning.

[0235] In addition, the microcomputer 12051 can perform coordinated control for purposes such as autonomous driving by controlling the driving force generator, steering mechanism, or braking device based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, without relying on the driver's operation.

[0236] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control for the purpose of preventing glare, such as switching from high beam to low beam, by controlling the headlights according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0237] The audio / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of notifying information to passengers or the outside of the vehicle in a visual or auditory manner. Fig.24 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0238] Fig.25 An example of the installation position of the imaging unit 12031 is shown.

[0239] exist Fig.25 In the embodiment, imaging units 12101, 12102, 12103, 12104 and 12105 are set as imaging unit 12031.

[0240] For example, the imaging units 12101, 12102, 12103, 12104, and 12105 are disposed at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 disposed at the front nose of the vehicle interior and the imaging unit 12105 disposed at the upper portion of the windshield in the vehicle interior mainly acquire images in front of the vehicle 12100. The imaging unit 12102 and the imaging unit 12103 disposed on the side mirrors mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 disposed on the rear bumper or the rear door mainly acquires images on the rear of the vehicle 12100. The imaging unit 12105 disposed at the upper portion of the windshield in the vehicle is mainly used to detect a vehicle in front, a pedestrian, an obstacle, a traffic signal, a traffic sign, or a lane, etc.

[0241] Fig.25An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose, the imaging range 12112 and the imaging range 12113 respectively indicate the imaging ranges of the imaging unit 12102 and the imaging unit 12103 provided at the side mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image observed from above the vehicle 12100 can be obtained.

[0242] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0243] For example, specifically, the microcomputer 12051 can extract the nearest three-dimensional object as the front vehicle by acquiring the distance to each three-dimensional object within the imaging range 12111 to the imaging range 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging unit 12101 to the imaging unit 12104. The three-dimensional object is located on the path of the vehicle 12100 and travels in the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). In addition, the microcomputer 12051 can pre-set the distance to be maintained from the front vehicle, and can perform automatic braking control (also including follow-up stop control) or automatic acceleration control (also including follow-up start control). As a result, it is possible to perform coordinated control for the purpose of automatic driving such as autonomous driving without relying on the driver's operation.

[0244] For example, the microcomputer 12051 can classify the three-dimensional data about the three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians and other three-dimensional objects (such as electric poles) based on the distance information obtained from the imaging unit 12101 to the imaging unit 12104, and extract information. The three-dimensional data can be used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes the obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the degree of risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and there is a possibility of collision, an alarm is output to the driver through the audio speaker 12061 or the display unit 12062, and forced deceleration or avoidance steering is performed by the drive system control unit 12010, thereby providing driving support for collision avoidance.

[0245] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is performed by, for example, extracting feature points in the captured images of the imaging units 12101 to 12104 used as infrared cameras, and determining whether the object is a pedestrian by performing pattern matching processing on a series of feature points indicating the outline of the object. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104 and identifies the pedestrian, the audio / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is superimposed on the recognized pedestrian. In addition, the audio / image output unit 12052 may control the display unit 12062 so that an icon of a pedestrian, etc. is displayed at a desired position.

[0246] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, for example, the camera 100 can be applied to the imaging unit 12031. The application of the technology according to the present disclosure in the vehicle control system 12000 can obtain a captured image while suppressing an increase in power consumption and preventing the sunspot phenomenon.

[0247] It should be noted that the above-mentioned embodiments show examples for embodying the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments and can be embodied by applying various modifications to the embodiments without departing from its main purpose. In addition, the effects described in this specification are merely exemplary and are not intended to be limiting, and other effects may also be provided.

[0248] This technology can also be configured as follows:

[0249] (1) An imaging device comprising:

[0250] A signal line that changes potential based on electric charge accumulated according to current flowing when a signal is read from a pixel;

[0251] a signal line transistor electrically connected to the signal line; and

[0252] The voltage generating unit is connected in series to the signal line transistor and is capable of generating a voltage higher than 0V.

[0253] (2) The imaging device according to (1), wherein the potential of the signal line is a potential of a parasitic capacitance of the signal line.

[0254] (3) The imaging device according to (1) or (2), wherein the pixel comprises:

[0255] Photodiode;

[0256] a transfer transistor that transfers the charge accumulated in the photodiode to the floating diffusion;

[0257] A reset transistor resets the floating diffusion;

[0258] an amplifying transistor that outputs a signal corresponding to the potential of the floating diffusion; and

[0259] The selection transistor is connected between the amplification transistor and the signal line.

[0260] (4) The imaging device according to any one of (1) to (3), wherein the voltage generating unit includes a diode-connected transistor.

[0261] (5) The imaging device according to any one of (1) to (3), wherein the voltage generating unit includes a plurality of diode-connected transistors connected in series in different numbers.

[0262] (6) The imaging device according to any one of (1) to (5), wherein the voltage generating unit makes a reset level of the signal line when the reset level is read from the pixel equal to or higher than a reset level of the signal line when the signal level is read from the pixel.

[0263] (7) The imaging device according to any one of (1) to (6), further including a comparator that compares the potential of the signal line with the ramp signal.

[0264] (8) The imaging device according to any one of (1) to (7), further including a comparator that compares potentials of signal lines provided in different columns.

[0265] (9) The imaging device according to any one of (1) to (8), further including a constant current transistor that can be electrically connected to the signal line and transmits a constant current based on a source follower formed between the pixel and the constant current transistor.

[0266] (10) The imaging device according to (9), wherein:

[0267] In constant current reading using a constant current transistor, the constant current transistor is turned on, and

[0268] In the capacitive load reading using the voltage generating unit, the constant current transistor is turned off.

[0269] (11) The imaging device according to any one of (1) to (8), further comprising:

[0270] a sample-and-hold circuit that operates the signal line transistor as a constant current transistor; and

[0271] The switch switches the connection of the signal line transistor between the voltage generating unit and the ground potential.

[0272] (12) The imaging device according to (11), wherein

[0273] In constant current reading, the connection of the signal line transistor is switched to the ground potential and the signal line transistor is turned on, and

[0274] In the capacitive load reading, the connection of the signal line transistor is switched to the voltage generating unit, and after the signal line is reset, the signal line transistor is turned off.

[0275] (13) The imaging device according to any one of (1) to (8), wherein the voltage generating unit includes:

[0276] a series transistor connected in series to the signal line transistor; and

[0277] A switching transistor that switches between the gate and drain of the series transistor.

[0278] (14) The imaging device according to (13), wherein

[0279] The switching transistor is turned off during constant current reading, and

[0280] The switching transistor is turned on when the capacitive load is read.

[0281] (15) The imaging device according to any one of (1) to (14), further comprising a chip, the pixels being formed on the chip, wherein:

[0282] Signal line transistors are formed on the chip.

[0283] (16) The imaging device according to (15), wherein the voltage generating unit is formed on a chip.

[0284] (17) The imaging device according to any one of (1) to (16), further comprising a pixel array unit including pixels arranged in a matrix form in a row direction and a column direction, wherein:

[0285] arranging a plurality of signal lines in a row direction in such a manner that the signal lines are wired in a column direction; and

[0286] A signal line transistor is provided for each signal line.

[0287] (18) The imaging device according to (17), wherein the voltage generating unit is provided for each signal line in a different column.

[0288] (19) The imaging device according to (17), wherein the voltage generating unit is shared between a plurality of signal lines in different columns.

[0289] (20) The imaging device according to (18), further including a short-circuit line that short-circuits a voltage generating unit provided for each signal line in a different column.

[0290] [Reference Numbers List]

[0291] 100 Camera

[0292] 101 Optical System

[0293] 102 Solid-state imaging device

[0294] 103 Imaging control unit

[0295] 104 Image processing unit

[0296] 105 Storage Unit

[0297] 106 Display Unit

[0298] 107 Operating unit

[0299] 108 Bus

[0300] 111 pixel array unit

[0301] 112 vertical scanning circuit

[0302] 113 Column readout circuit

[0303] 114 columns of signal processing units

[0304] 115 Horizontal scanning circuit

[0305] 116 Control Circuit

[0306] 121 Photodiode

[0307] 122 Transfer transistor

[0308] 123 Reset transistor

[0309] 124 Amplifier transistor

[0310] 125 Select transistor

[0311] 126 Floating Diffusion

[0312] 131 Horizontal drive line

[0313] 132 vertical signal line

[0314] 133 Capacitor

[0315] 141 Signal Line Transistor

[0316] 142 Diode-connected transistor

[0317] 143 Comparator

[0318] 144, 145 DC blocking capacitors.

Claims

1. An imaging device, comprising: A signal line that changes potential based on electric charge accumulated according to current flowing when a signal is read from a pixel; a signal line transistor electrically connected to the signal line; as well as A voltage generating unit is connected in series to the signal line transistor and is capable of generating a voltage higher than 0V.

2. The imaging device according to claim 1, wherein: The potential of the signal line is the potential of the parasitic capacitance of the signal line.

3. The imaging device according to claim 1, wherein: The pixels include: Photodiode; a transfer transistor that transfers the charge accumulated in the photodiode to a floating diffusion; a reset transistor to reset the floating diffusion; an amplifying transistor that outputs a signal corresponding to the potential of the floating diffusion; and The selection transistor is connected between the amplification transistor and the signal line.

4. The imaging device according to claim 1, wherein: The voltage generating unit includes a diode-connected transistor.

5. The imaging device according to claim 1, wherein: The voltage generating unit includes a plurality of diode-connected transistors connected in series in different numbers.

6. The imaging device according to claim 1, wherein: The voltage generating unit makes a reset level of the signal line when a reset level is read from the pixel equal to or higher than a reset level of the signal line when a signal level is read from the pixel. 7 . The imaging device according to claim 1 , further comprising a comparator that compares the potential of the signal line with a ramp signal. 8 . The imaging device according to claim 1 , further comprising a comparator that compares potentials of the signal lines provided in different columns. 9 . The imaging device according to claim 1 , further comprising a constant current transistor which is electrically connectable to the signal line and which passes a constant current based on a source follower formed between the pixel and the constant current transistor.

10. The imaging device according to claim 1, wherein: In constant current reading using a constant current transistor, the constant current transistor is turned on, and In the capacitive load reading using the voltage generating unit, the constant current transistor is turned off.

11. The imaging device according to claim 1, further comprising: a sample-and-hold circuit that operates the signal line transistor as a constant current transistor; as well as A switch switches the connection of the signal line transistor between the voltage generating unit and a ground potential.

12. The imaging device according to claim 11, wherein: In constant current reading, the connection of the signal line transistor is switched to the ground potential and the signal line transistor is turned on, and In capacitive load reading, the connection of the signal line transistor is switched to the voltage generating unit, and after the signal line is reset, the signal line transistor is turned off.

13. The imaging device according to claim 1, wherein: The voltage generating unit comprises: a series transistor connected in series to the signal line transistor; and A switching transistor switches between the gate and the drain of the series transistor.

14. The imaging device according to claim 13, wherein: The switching transistor is turned off during constant current reading, and The switch transistor is turned on when the capacitive load is read.

15. The imaging device according to claim 1, further comprising a chip, the pixels being formed on the chip, wherein: The signal line transistor is formed on the chip.

16. The imaging device according to claim 15, wherein: The voltage generating unit is formed on the chip.

17. The imaging device according to claim 1, further comprising a pixel array unit including pixels arranged in a matrix form in a row direction and a column direction, wherein arranging a plurality of the signal lines in the row direction in such a manner that the signal lines are wired in the column direction; and The signal line transistor is provided for each of the signal lines.

18. The imaging device according to claim 17, wherein: The voltage generating unit is provided for each of the signal lines in different columns.

19. The imaging device according to claim 17, wherein: The voltage generating unit is shared between a plurality of signal lines in different columns. 20 . The imaging device according to claim 18 , further comprising a short-circuit line that short-circuits the voltage generating unit provided for each of the signal lines in different columns.

Images