Image forming apparatus

Abstract

The present invention enables merging while suppressing an increase in the number of switches connected to a signal line for transmitting a signal read out from a pixel in a column direction. The imaging device includes: a pixel array section in which pixels are arranged in a matrix shape in a row direction and a column direction; a signal line transmitting a signal read out from the pixel in a column direction; a sample-and-hold switch for sampling and holding a signal transmitted via the signal line for each column; and a connection switch connecting signal lines of mutually different columns in which signals have been sampled and held. The imaging apparatus may further include: an AD conversion unit that AD converts the signal transmitted via the signal line in each column; and an activation control unit that activates one of the AD conversion units of the columns connected via the connection switch.

Description

Technical Field

[0001] The present technology relates to an imaging device. More specifically, the present technology relates to an imaging device equipped with a merging function. Background Art

[0002] For cameras mounted on monitoring cameras and mobile terminals, there is a technology that continuously operates the camera for purposes such as moving object detection and reduces power consumption by reducing spatial resolution using analog binning. As such an imaging device, for example, an imaging device has been proposed that holds one pixel signal in each of a plurality of signal holding units, averages the pixel signals held in the plurality of signal holding units, and outputs the pixel signal (see, for example, Patent Document 1).

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1] JP 2020-92353A Summary of the invention

[0006] [Technical issues]

[0007] However, in the above conventional technology, the first switch circuit selectively connects the pixel to each of the plurality of signal holding units to hold one pixel signal in each of the plurality of signal holding units, and the second switch circuit averages and outputs the pixel signals held in the plurality of signal holding units. For this reason, in the above conventional technology, the number of switches connected to the signal line that transmits the signal read from the pixel in the column direction increases, and this may cause an increase in the area occupied by the switch.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to suppress an increase in the number of switches connected to a signal line for transmitting a signal read out from a pixel in the column direction and to enable integration.

[0009] [Solution to the problem]

[0010] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof provides an imaging device, comprising: a pixel array unit in which pixels are arranged in a matrix in row and column directions; a signal line that transmits a signal read out from pixels in the column direction; a sample-and-hold switch that samples and holds the signal transmitted via the signal line for each column; and a connection switch that connects the signal lines of different columns for sampling and holding the signal. Thus, in each column, after sampling and holding the signal transmitted via the signal line, an effect of performing pixel merging is produced.

[0011] In addition, in the first aspect, the imaging device may further include: an AD conversion unit that performs AD conversion for each of the columns of the signal transmitted via the signal line; and an activation control unit that activates one of the AD conversion units of each column connected via the connection switch. This leads to an effect of reducing power consumption of the AD conversion unit that does not need to operate during the merging process.

[0012] Furthermore, in the first aspect, the AD conversion unit may include: a comparator that compares the potential of the signal line with the ramp signal; and a counter that performs a counting operation based on the comparison result from the comparator. This causes an effect that the signal transmitted via the signal line is digitized.

[0013] Furthermore, in the first aspect, the activation control unit may control the AD conversion unit separately for the column to be activated and the column to be deactivated. This results in an effect that the AD conversion unit of at least one of the plurality of columns is deactivated during the binning period.

[0014] Furthermore, in the first aspect, the device may further include: a first DC cut capacitor connected to the first input terminal of the comparator; and a second DC cut capacitor connected to the second input terminal of the comparator. This causes an effect that a DC cut signal is input to the comparator.

[0015] In addition, in the first aspect, the activation control unit may further include a conversion switch that switches between the first input terminal of the comparator and the ground terminal, and the connection destination of the second capacitance electrode of the first DC cut-off capacitor has the first capacitance electrode connected to the signal line. This causes an effect that the capacitance of the first DC cut-off capacitor of one column is added to the signal line of another column.

[0016] In addition, in the first aspect, the activation control unit can control the changeover switches separately for the columns to be activated and the columns to be deactivated. This causes the effect that the capacitance added to the columns to be deactivated is added to the capacitance of the signal line of the columns to be activated.

[0017] Furthermore, in the first aspect, the device may further include an amplifier that amplifies a signal transmitted via the signal line for each column and inputs the amplified signal to the AD conversion unit. This results in an effect that the signal input to the AD conversion unit increases.

[0018] In addition, in the first aspect, the activation control unit may control the amplifiers to activate the columns and deactivate the columns, respectively. This results in an effect that the amplifiers of at least one column among the plurality of columns are deactivated during binning.

[0019] Furthermore, in the first aspect, the sample-and-hold switch may be a transistor provided for each signal line. This results in an effect that a signal transmitted via the signal line is sampled and held for each column.

[0020] In the first aspect, the device may further include a driver that drives the transistor from both sides in the row direction. This causes an effect that the driving force of the transistor of each column is increased based on two drivers provided in common for a plurality of columns.

[0021] In the first aspect, the device may further include: a signal line reset transistor that resets the potential of the signal line; and a signal line reset level generating unit that generates a reset level of the potential of the signal line. This leads to the following effect: based on the potential of the signal line reset to a voltage higher than 0 V, capacitive load reading is possible.

[0022] In the first aspect, the signal line reset level generating unit may include a diode-connected transistor. This causes an effect that the potential of the signal line rises according to the forward voltage of the diode-connected transistor when the signal line is reset.

[0023] In the first aspect, the capacitance used to sample and hold the signal may be the parasitic capacitance of the signal line. This leads to the effect that capacitive load readout is possible without adding a capacitive element to the signal line.

[0024] In addition, in the first aspect, the connection switch may be connected in series to the capacitance of each column for sampling and holding the signal. This leads to the following effect: when the number of columns to be merged is variable, merging is possible.

[0025] In addition, in the first aspect, the connection switch may be connected in parallel to the capacitance of each column for sampling and holding the signal. This leads to the following effect: when the number of columns to be merged is fixed, merging is possible.

[0026] In addition, in the first aspect, the device further includes a constant current transistor that can be electrically connected to the signal line and transmits a constant current based on a source follower formed between the signal line and the pixel, wherein the constant current transistor is turned on during constant current readout, and the constant current transistor is turned off during capacitive load readout. This leads to an effect of being able to switch between capacitive load readout and constant current readout.

[0027] In the first aspect, a pixel may include: a photodiode; a transfer transistor that transfers the charge stored in the photodiode to a floating diffusion; a reset transistor that resets the floating diffusion; an amplifier transistor that outputs a signal corresponding to the potential of the floating diffusion; and a selection transistor that is connected between the amplifier transistor and a signal line. This causes an effect of forming a source follower between the pixel and the amplifier transistor when a signal is read out from the pixel.

[0028] In a first aspect, the sample-and-hold switch may be a selection transistor. This causes the effect that the signal sent via the signal line is sampled and held for each column.

[0029] In the first aspect, the pixel may further include a merging transistor connecting the floating diffusions of different rows, which leads to the effect of realizing the partitioning of different rows. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a block diagram showing an example of the configuration of a camera to which the imaging device according to the first embodiment is applied.

[0031] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment.

[0032] Figure 3 : is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0033] Figure 4 is a cross-sectional view showing a configuration example of a pixel array unit provided in the solid-state imaging device of the first embodiment.

[0034] Figure 5 is a cross-sectional view showing a modified example of the pixel array unit provided in the solid-state imaging device according to the first embodiment.

[0035] Figure 6 : is a diagram showing a configuration example of a signal readout circuit for four columns according to the first embodiment.

[0036] Figure 7 : is a diagram showing an example of a waveform of each section during signal readout of the imaging device according to the first embodiment.

[0037] Figure 8 : is a diagram showing an example of the configuration of a comparator applied to the signal readout circuit according to the first embodiment.

[0038] Fig. 9 is a diagram showing a configuration example of a signal readout circuit for four columns according to the second embodiment.

[0039] Fig.10 : is a diagram showing an example of the configuration of a signal readout circuit for four columns according to the third embodiment.

[0040] Fig.11 : is a diagram showing an example of the configuration of a signal readout circuit for two columns according to the fourth embodiment.

[0041] Fig.12: is a diagram showing an example of the configuration of a signal readout circuit for four columns according to the fifth embodiment.

[0042] Fig.13 : is a diagram showing an example of the configuration of a signal readout circuit for four columns according to the sixth embodiment.

[0043] Fig.14 : is a diagram showing an example of a waveform of each section during signal readout of the imaging device according to the sixth embodiment.

[0044] Fig.15 : is a diagram showing an example of the configuration of a signal readout circuit for four columns according to the seventh embodiment.

[0045] Fig.16 : is a diagram showing an example of the configuration of a signal readout circuit for four columns according to the eighth embodiment.

[0046] Fig.17 : is a diagram showing an example of a waveform of each section during signal readout of the imaging device according to the eighth embodiment.

[0047] Fig.18 : is a diagram showing an example of the configuration of a signal readout circuit of one column according to the ninth embodiment.

[0048] Fig.19 is a perspective view showing a configuration example of an imaging device according to a tenth embodiment.

[0049] Fig. 20 is a block diagram showing a schematic example of a configuration of a vehicle control system.

[0050] Fig.21 is an explanatory diagram showing an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0051] A mode for carrying out the present technology (hereinafter also referred to as an “embodiment”) will be described below. The description will be given in the following order.

[0052] 1. First Embodiment (Example in which a signal line reset transistor performs binning based on a signal sampled and held for each column connected to a vertical signal line)

[0053] 2. Second Embodiment (Example of pixel binning in which diode-connected transistors perform pixel binning based on signals sampled and held in each column connected to a vertical signal line via a signal line reset transistor)

[0054] 3. Third Embodiment (Example in which a signal line reset transistor performs merging based on a signal sampled and held for each column connected to a vertical signal line, and a connection switch is connected in parallel to a capacitor for each column for sampling and holding)

[0055] 4. Fourth Embodiment (Example in which a signal line reset transistor performs pixel combination in the row direction and the column direction based on a signal sampled and held for each column connected to a vertical signal line)

[0056] 5. Fifth Embodiment (Example of Providing an Amplifier for Amplifying a Signal Input to an AD Converter Unit for Each Column)

[0057] 6. Sixth Embodiment (Example in which a driver is arranged to drive a sample-and-hold switch provided for each signal line from both sides in the row direction)

[0058] 7. Seventh Embodiment (Example in which the connection destination of the DC cut capacitor is switched between the comparator input and the ground)

[0059] 8. Eighth Embodiment (Example in which a constant current transistor performs pixel combination based on a signal sampled and held for each column connected to a vertical signal line)

[0060] 9. Ninth Embodiment (Example in which a constant current transistor is connected in parallel to a series circuit of a reset transistor and a diode-connected transistor of a signal line)

[0061] 10. Tenth Embodiment (Example of Substrates Stacked to Form a Solid-State Imaging Device)

[0062] 11. Application examples for moving objects

[0063] <1. First Embodiment>

[0064] Figure 1 is a block diagram showing an example of the configuration of a camera to which the imaging device according to the first embodiment is applied.

[0065] In the figure, a camera 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to each other via a bus 108. The camera 100 may be used as an independent device, or may be incorporated into a mobile terminal such as a smartphone, or may be incorporated into an authentication device or a monitoring device.

[0066] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an image of the subject on a light receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focusing lens, a zoom lens, and an aperture. The optical system 101 may include a plurality of lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0067] The solid-state imaging device 102 converts light from a subject into an electric signal for each pixel, digitizes the electric signal, and outputs it. The solid-state imaging device 102 may be, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device).

[0068] The imaging control unit 103 controls imaging of the solid-state imaging device 102 based on a command from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, and the like of the solid-state imaging device 102.

[0069] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing is, for example, gamma correction, white balance processing, sharpness processing, and grayscale conversion processing. The image processing unit 104 may include a processor that performs processing based on software.

[0070] The storage unit 105 stores a captured image captured by the solid-state imaging device 102, and stores imaging parameters and the like of the solid-state imaging device 102. The storage unit 105 may also store a program for operating the camera 100 based on software. The storage unit 105 may include a ROM (Read Only Memory), a RAM (Random Access Memory), and a memory card.

[0071] The display unit 106 displays a captured image and various information supporting the imaging operation. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0072] The operation unit 107 provides a user interface for operating the camera 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the camera 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0073] Figure 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment.

[0074] In the figure, the solid-state imaging device 102 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, a control circuit 116, drivers 117 and 118, and an activation control unit 119.

[0075] The pixel array unit 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along a row direction (also referred to as a horizontal direction) and a column direction (also referred to as a vertical direction). When reading out a signal, each pixel 120 can form a source follower with a column readout circuit 113. Each pixel 120 is connected to a horizontal drive line 131 of each row, and to a vertical signal line 132 of each column. When a signal is read out from each pixel 120, the horizontal drive line 131 drives each pixel 120 of each row. The vertical signal line 132 sends a potential based on a stored charge according to a current flowing when a signal is read out from the pixel 120 to a column signal processing unit 114 for each column. Note that the vertical signal line 132 is an example of a signal line described in the claims.

[0076] The vertical scanning circuit 112 scans the pixels 120 to be read out in the column direction. The vertical scanning circuit 112 can be configured using a vertical register.

[0077] When reading out a signal from each pixel 120, the column readout circuit 113 can form a source follower with each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120. The column readout circuit 113 can support capacitive load readout. The column readout circuit 113 can also support constant current readout.

[0078] The column readout circuit 113 also includes a sample-and-hold switch that samples and holds a signal transmitted via the vertical signal line 132 for each column, and a connection switch that connects the vertical signal lines 132 of different columns whose signals are sampled and held. At this time, the column readout circuit 113 can sample and hold a signal transmitted via the vertical signal line 132 for each column, and then perform merging and output the signal to the column signal processing unit 114.

[0079] Drivers 117 and 118 drive the sample-hold switches provided in the column readout circuit 113 from both sides in the row direction. Drivers 117 and 118 may be shared by the sample-hold switches provided for each column. Drivers 117 and 118 may be arranged on both sides of the column readout circuit 113.

[0080] The column signal processing unit 114 processes a signal transmitted from each pixel 120 in the column direction. For example, the column signal processing unit 114 may perform a correlated double sampling (CDS) process based on the signal transmitted in the column direction from each pixel 120. In addition, the column signal processing unit 114 may perform an AD (analog-to-digital) conversion process based on the signal transmitted in the column direction from each pixel 120 and output an imaging signal Gout. At this time, the column signal processing unit 114 may be provided with an AD conversion unit for each column, and the AD conversion unit performs AD conversion on the signal transmitted via the vertical signal line 132.

[0081] The activation control unit 119 activates one of the AD conversion units of each column connected via the connection switch. At this time, the activation control unit 119 may output a control signal CTL to each AD conversion unit, which controls the activation timing of each AD conversion unit during the merging period. The activation control unit 119 may control the AD conversion units separately for the column to be activated and the column to be deactivated. At this time, the activation control unit 119 may activate the AD conversion unit of the column to be activated, and put the AD conversion unit of the column to be deactivated in a standby state.

[0082] The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 can be configured using a horizontal register.

[0083] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, the horizontal scanning circuit 115, and the drivers 117 and 118. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. The control circuit 116 can also control the driving timing of the drivers 117 and 118 and the operation timing of the activation control unit 119.

[0084] exist Figure 2 In the configuration example of , a sample-hold switch is provided in the column readout circuit 113 to perform merging based on the signal sampled and held for each column. The selection transistor provided in the pixel 120 can be used to sample and hold the signal read out from the pixel 120 for each column. In this method, the sample-hold switch provided in the column readout circuit 113 is not necessary. The drivers 117 and 118 on both sides of the column readout circuit 113 are also unnecessary.

[0085] In addition, combined readout and full-pixel individual readout may be switched according to the application of the camera 100. For example, in a mobile terminal equipped with the camera 100, when an application such as motion detection is started, the merging process may be constantly operated, and when an application such as still image capture is started, the merging process may be switched to full-pixel individual readout.

[0086] Figure 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device of the first embodiment.

[0087] In the figure, a pixel 120 includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplifier transistor 124, a selection transistor 125, and a floating diffusion 126. MOS (Metal Oxide Semiconductor) transistors can be used as the transfer transistor 122, the reset transistor 123, the amplifier transistor 124, and the selection transistor 125.

[0088] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion 126 via the transfer transistor 122. The floating diffusion 126 is also connected to the power supply Vdd via the reset transistor 123. The power supply Vdd is also connected to the vertical signal line 132 via the series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion 126.

[0089] The transfer signal ΦTG is applied to the gate of the transfer transistor 122. The pixel reset signal ΦPRT is applied to the gate of the reset transistor 123. The selection signal ΦSEL is applied to the gate of the selection transistor 125. The transfer signal ΦTG, the pixel reset signal ΦPRT and the selection signal ΦSEL can be applied to the gate of the transfer transistor 122. Figure 2 The horizontal drive line 131 in is sent to each pixel 120.

[0090] When the transfer transistor 122 is turned on, the charge stored in the photodiode 121 is transferred to the floating diffusion 126. When the selection transistor 125 is turned on, the source potential of the amplifier transistor 124 changes according to the potential of the floating diffusion 126. The source potential of the amplifier transistor 124 is applied to the vertical signal line 132 via the selection transistor 125 and is transmitted via the vertical signal line 132. When the reset transistor 123 is turned on, the charge stored in the floating diffusion 126 is discharged.

[0091] Figure 4 : is a cross-sectional view showing a configuration example of a pixel array unit provided in the solid-state imaging device of the first embodiment. It is to be noted that Figure 4 An example of a front-illuminated solid-state imaging device is shown. Figure 4 An example of a three-pixel configuration is also shown.

[0092] In the figure, a photodiode 232 is formed for each pixel 120 on a semiconductor substrate 231. The semiconductor substrate 231 may be made of Si, InGaAs, or InP.

[0093] The gate electrode 214 and the wiring layer 210 are formed on the semiconductor substrate 231. The gate electrode 214 is formed on the semiconductor substrate 231 via the gate insulating film 213. A sidewall 215 is formed on the sidewall of the gate electrode 214. The gate electrode 214 can be made of, for example, polysilicon doped with impurities. The gate insulating film 213 can be made of, for example, a silicon oxide film. The sidewall 215 can be made of, for example, a silicon oxide film or a silicon nitride film.

[0094] The gate electrode 214 may be used for a pixel transistor. The pixel transistor includes Figure 3The transfer transistor 122, the reset transistor 123, the amplifying transistor 124 and the selecting transistor 125 are provided.

[0095] A wiring 216 is formed on the gate electrode 214 . Figure 4 An example of three-layer wiring is shown. At this time, an opening OP1 for allowing light to enter the photodiode 232 is provided on the wiring 216. The gate electrode 214 and the wiring 216 are insulated by an insulating layer 217. The insulating layer 217 can be made of, for example, a silicon oxide film. The wiring 216 can be made of, for example, a metal (such as Al or Cu).

[0096] A color filter 218 is formed for each pixel 120 on the wiring layer 210. A microlens 219 is formed for each pixel 120 on the color filter 218. For example, the color filter 218 and the microlens 219 may be made of a transparent resin such as acrylic resin or polycarbonate. The color filter 218 may be colored by adding a pigment. The color filter 218 may be arranged in, for example, a Bayer array.

[0097] Figure 5 is a cross-sectional view showing a modified example of the pixel array unit provided in the solid-state imaging device according to the first embodiment. Figure 5 An example of a back-illuminated solid-state imaging device is shown. Figure 5 A configuration example of three pixels is also shown.

[0098] In the figure, a photodiode 222 is formed for each pixel 120 in a semiconductor layer 221. The semiconductor layer 221 may be made of Si, InGaAs, or InP. The semiconductor layer 221 may be formed, for example, by thinning a semiconductor substrate having the photodiode 222 formed on the front side from the back side.

[0099] The gate electrode 224 and the wiring layer 220 are formed on the semiconductor layer 221. The gate electrode 224 is formed on the semiconductor layer 221 through the gate insulating film 223. The sidewall 225 is formed on the sidewall of the gate electrode 224.

[0100] The gate electrode 224 may be used for a pixel transistor. The pixel transistor includes Figure 3 The transfer transistor 122, the reset transistor 123, the amplifying transistor 124 and the selecting transistor 125 are provided.

[0101] A wiring 226 is formed on the gate electrode 224 . Figure 5 An example of three-layer wiring is shown. The gate electrode 224 and the wiring 226 are insulated via an insulating layer 227. The semiconductor layer 221 is supported on a support substrate 230 via the insulating layer 227. The support substrate 230 may be a glass substrate, a Si substrate, or a sapphire substrate.

[0102] A color filter 228 is formed for each pixel 120 on the back side of the semiconductor layer 221. A microlens 229 is formed on the color filter 228 for each pixel 120. For example, the color filters 228 may be arranged in a Bayer array.

[0103] Figure 6 : is a diagram showing a configuration example of a signal readout circuit for four columns according to the first embodiment.

[0104] In the figure, the pixels 120 are connected to the vertical signal lines 132-1 to 132-4, respectively. At this time, the amplifying transistor 124 of each pixel 120 is connected to the vertical signal lines 132-1 to 132-4 via the selecting transistor 125. In addition, the capacitor 133 is added to the vertical signal lines 132-1 to 132-4. The capacitor 133 can be used for sampling and holding the signal read out from each pixel 120 of each column. The capacitor 133 can be a parasitic capacitor of the vertical signal lines 132-1 to 132-4, or a capacitive element connected to the vertical signal lines 132-1 to 132-4. In this case, the selecting transistor 125 of each pixel 120 can be used as a sampling and holding switch, which makes the capacitor 133 sample and hold the signal of each column sent via the vertical signal lines 132-1 to 132-4.

[0105] In addition, the signal line reset transistor 141 is electrically connected to the vertical signal lines 132-1 to 132-4. The signal line reset transistor 141 can reset the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Each signal line reset transistor 141 can be, for example, a MOS transistor. A signal line reset signal ΦRT is applied to the gate of each signal line reset transistor 141. The source of each signal line reset transistor 141 is connected to the reset potential VR. The reset potential VR can be set to a potential higher than the ground potential.

[0106] The signal readout circuit is also provided with an AD conversion unit that performs AD conversion on the signal of each column transmitted via the vertical signal lines 132-1 to 132-4. The AD conversion unit is provided with a comparator 143 and a counter 146 for each column. Each comparator 143 compares the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 with the reference signal RAP of each column. The reference signal RAP may be a ramp signal. Each counter 146 performs a counting operation on each column based on the comparison result from each comparator 143.

[0107] The vertical signal lines 132-1 to 132-4 are connected to the inverting input terminal of the comparator 143 via each DC cut capacitor 144. When the signal is read out individually from each pixel 120, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are applied to the inverting input terminal of each comparator 143 via the DC cut capacitor 144. When the signals of different columns are combined and read out, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is applied to the inverting input of each comparator 143 via the DC cut capacitor 144. The reference signal RAP is input to the non-inverting input terminal of each comparator 143 via the DC cut capacitor 145.

[0108] An auto-zero signal AZ is also input to each comparator 143. The auto-zero signal AZ activates the auto-zero operation during the auto-zero operation. In the auto-zero operation, the charges stored in the DC cut capacitors 144 and 145 can be controlled so that the non-inverting input and the inverting input of the comparator 143 are balanced.

[0109] The connection switch 151 is also provided in the signal readout circuit. The connection switch 151 connects the vertical signal lines 132-1 to 132-4 of different columns. At this time, the connection switch 151 is connected in series to the capacitor 133 for sampling and holding the signal read out from each pixel 120. Each connection switch 151 can be provided between the vertical signal lines 132-1 to 132-4 adjacent to each other in the row direction. Each connection switch 151 can be turned on / off based on the opening / closing signals ΦCn1 to ΦCn4, respectively.

[0110] Before the signal is read out from each pixel 120, the signal line reset transistor 141 connected to the vertical signal lines 132-1 to 132-4 is turned on, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set to potentials higher than 0V. Then, after the signal line reset transistor 141 connected to the vertical signal lines 132-1 to 132-4 is turned off, the selection transistor 125 of each pixel 120 is turned on, and the signal is read out from each pixel 120. At this time, the charge corresponding to the signal read out from each pixel 120 is respectively stored in the capacitor 133 added to the vertical signal lines 132-1 to 132-4. The potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 change based on the charge stored in the capacitor 133 added to the vertical signal lines 132-1 to 132-4.

[0111] Then, in the comparator 143 connected to the vertical signal lines 132-1 to 132-4, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are compared with the reference signal RAP, and the corresponding comparison results COP1 to COP4 are output. At this time, each comparator 143 can output the timing at which the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 match the level of the reference signal RAP as the comparison results COP1 to COP4 to each counter 146. Each counter 146 performs a counting operation based on the comparison results COP1 to COP4 from each comparator 143, and outputs a count value based on each counting operation.

[0112] On the other hand, when the signal from each pixel 120 is merged and read out, the selection transistor 125 of each pixel 120 is turned off, and then the opening / closing signals ΦCn1 to ΦCn4 rise, connecting the vertical signal lines 132-1 to 132-4 to each other. At this time, the charges stored in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are merged, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143.

[0113] at this time, Figure 2 The activation control unit 119 in activates one of the comparator 143 and the counter 146, which performs AD conversion on each of the vertical signal lines 132-1 to 132-4. For example, the activation control unit 119 can activate the comparator 143 and the counter 146 provided corresponding to the vertical signal line 132-1 and the counter 146 provided corresponding to the vertical signal lines 132-1 to 132-4. At this time, the activation control unit 119 can set the control signal CTL of the comparator 143 and the counter 146 set corresponding to the vertical signal line 132-1 to ACT. The activation control unit 119 can also set the control signal CTL of the comparator 143 and the counter 146 set corresponding to the vertical signal lines 132-2 to 132-4 to STB. ACT can indicate activation, and STB can indicate standby.

[0114] Then, in the comparator 143 connected to the vertical signal line 132-1, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is compared with the reference signal RAP, and the comparison result COP1 is output. At this time, the comparator 143 connected to the vertical signal line 132-1 can output the timing at which the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 matches the level of the reference signal RAP as the comparison result COP1 to the counter 146. The counter 146 performs a counting operation based on the comparison result COP1 from the comparator 143, and outputs a count value based on the counting operation.

[0115] Figure 7 1 is a diagram showing an example of a waveform of each portion when the imaging device according to the first embodiment reads out a signal. In addition, the figure shows an example of a waveform of each portion when binning readout is performed. In addition, in the figure, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 and their average value are represented by VSL.

[0116] In the figure, in the capacitive load readout, pixel reset / VSL reset (K11) is performed. At this time, the pixel reset signal ΦPRT of each pixel 120 rises (t11), the reset transistor 123 of each pixel 120 is turned on, and the floating diffusion 126 of each pixel 120 is reset. The reset level of the floating diffusion 126 of each pixel 120 can be set to the power supply potential Vdd. In addition, the signal line reset signal ΦRT rises (t11), the signal line reset transistor 141 connected to the vertical signal lines 132-1 to 132-4 is turned on, and the vertical signal lines 132-1 to 132-4 are reset. At this time, the reset level of the vertical signal lines 132-1 to 132-4 is set to the reset potential VR via the signal line reset transistor 141 connected to the vertical signal lines 132-1 to 132-4.

[0117] In addition, the opening / closing signal ΦCn* rises (t11), and the plurality of connection switches 151 connected to the vertical signal lines 132-1 to 132-4 are turned on. Note that the opening / closing signal ΦCn* represents a plurality of opening / closing signals selected from the opening / closing signals ΦCn1 to ΦCn4. In the following description, the case where the opening / closing signal ΦCn* is the opening / closing signal ΦCn1 to ΦCn4 is taken as an example. At this time, the charges stored in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are equalized.

[0118] Then, the auto-zero signal AZ rises (t11), and the auto-zero operation of the comparator 143 connected to the vertical signal lines 132-1 to 132-4 is activated. At this time, the charges stored in the DC cut capacitors 144 and 145 are controlled so that the non-inverting input and the inverting input of the comparator 143 connected to the vertical signal lines 132-1 to 132-4 are balanced. Then, the pixel reset signal ΦPRT falls, the open / close signal ΦCn* falls, and the signal line reset signal ΦRT falls.

[0119] Next, P-phase VSL sinking / P-phase VSL sampling and holding (K12) is performed. At this time, the selection signal ΦSEL of each pixel 120 rises (t12), and the selection transistor 125 of each pixel 120 is turned on. Then, based on the source follower operation of the amplification transistor 124 of each pixel 120, the charge corresponding to the reset level of the floating diffusion 126 of each pixel 120 is stored in the capacitor 133 added to the vertical signal lines 132-1 to 132-4. Then, based on the charge stored in the capacitor 133 added to the vertical signal lines 132-1 to 132-4, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set.

[0120] Next, P-phase merge / P-phase AD (K13) is performed. At this time, after the selection signal ΦSEL of each pixel 120 falls (t13), the open / close signal ΦCn* rises and the auto-zero signal AZ falls. When the open / close signal ΦCn* rises, the connection switch 151 connected to the vertical signal lines 132-1 to 132-4 is turned on. Then, the charges stored in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are merged, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. In addition, for example, among the comparators 143 and the counter 146 provided corresponding to the vertical signal lines 132-1 to 132-4, only the comparator 143 and the counter 146 provided corresponding to the vertical signal line 132-1 are activated. The activated comparator 143 is supplied with a ramp signal as a reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 corresponding to the reset level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as a comparison result COP1. At this time, in the activated counter 146, a counting operation is performed until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the reset level read from each pixel 120 connected to the vertical signal lines 132-1 to 132-4 is AD converted.

[0121] Next, transfer / VSL reset (K14) is performed. At this time, the transfer signal ΦTG of each pixel 120 rises (t14), the transfer transistor 122 of each pixel 120 is turned on, and the charge stored in the photodiode 121 of each pixel 120 is transferred to the floating diffusion 126 of each pixel 120. In addition, the signal line reset signal ΦRT rises (t14), and the signal line reset transistor 141 connected to the vertical signal lines 132-1 to 132-4 is turned on, and the vertical signal lines 132-1 to 132-4 are reset. At this time, the reset level of the vertical signal lines 132-1 to 132-4 is set to the reset potential VR via the signal line reset transistor 141 connected to the vertical signal lines 132-1 to 132-4. Then, the transfer signal ΦTG falls, the open / close signal ΦCn* falls, and the signal line reset signal ΦRT falls (t15).

[0122] Next, D-phase VSL sinking / D-phase VSL sampling and holding (K15) is performed. At this time, the selection signal ΦSEL rises (t16), and the selection transistor 125 of each pixel 120 is turned on. Then, based on the source follower operation of the amplifier transistor 124 of each pixel 120, the charge corresponding to the signal level of the floating diffusion 126 of each pixel 120 is stored in the capacitor 133 added to the vertical signal lines 132-1 to 132-4. Then, based on the charge stored in the capacitor 133 added to the vertical signal lines 132-1 to 132-4, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set.

[0123] Next, D-phase merge / D-phase AD (K16) is performed. At this time, after the selection signal ΦSEL falls (t17), the opening / closing signal ΦCn* rises. When the opening / closing signal ΦCn* rises, the connection switch 151 connected to the vertical signal lines 132-1 to 132-4 is turned on. Then, the charges stored in the capacitors 133 added to the vertical signal lines 132-1 to 132-4 are merged, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. The activated comparator 143 is also provided with a ramp signal as a reference signal RAP. The activated comparator 143 compares the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 corresponding to the signal level with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, the activated counter 146 performs a counting operation until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the signal level read out from each pixel 120 connected to the vertical signal lines 132-1 to 132-4 is AD converted.

[0124] Figure 8 : is a diagram showing an example of the configuration of a comparator applied to the signal readout circuit according to the first embodiment.

[0125] In the figure, the comparator 143 includes a differential amplifier 501, a post-stage amplifier 502, an output circuit 503, and an AND circuit 504. The post-stage amplifier 502 is connected to the post-stage of the differential amplifier 501, and the output circuit 503 is connected to the post-stage of the post-stage amplifier 502. The AND circuit 504 is connected to the post-stage of the output circuit 503, and the counter 146 is connected to the post-stage of the AND circuit 504.

[0126] The differential amplifier 501 balances the comparator inputs CIN1 and CIN2 based on an auto-zero operation and outputs a voltage according to the difference between the comparator inputs CIN1 and CIN2. The differential amplifier 501 includes PMOS transistors 511, 521, 551, 561 and 591 and NMOS transistors 531, 541, 571 and 581.

[0127] The PMOS transistor 511 and the NMOS transistor 531 are connected in series with each other. The PMOS transistor 521 and the NMOS transistor 541 are connected in series with each other. The sources of the PMOS transistors 511 and 521 are connected to the power supply voltage VDDH, and the gates of the PMOS transistors 511 and 521 are connected to the drain of the PMOS transistor 521. In this case, the PMOS transistors 511 and 521 can form a current mirror. The PMOS transistor 591 is connected in parallel with the PMOS transistor 511.

[0128] The PMOS transistor 551 is connected between the gate and drain of the NMOS transistor 531, and the PMOS transistor 561 is connected between the gate and drain of the NMOS transistor 541. The NMOS transistors 571 and 581 are connected in series with each other. The sources of the NMOS transistors 531 and 541 are grounded via the series circuit of the NMOS transistors 571 and 581.

[0129] The auto-zero signal AZP is applied to the gates of the PMOS transistors 551 and 561, and the bias voltage BIAS is applied to the gate of the NMOS transistor 571. The NMOS transistor 571 can operate as a constant current source based on the bias voltage BIAS. The control signal XA is applied to the gate of the NMOS transistor 581. The control signal XB is applied to the gate of the PMOS transistor 591.

[0130] The post-stage amplifier 502 amplifies the output of the differential amplifier 501. The post-stage amplifier 502 includes a PMOS transistor 512, an NMOS transistor 522, and a switch 532.

[0131] The PMOS transistor 512 and the NMOS transistor 522 are connected in series with each other. The source of the PMOS transistor 512 is connected to the power supply voltage VDDH, and the gate of the PMOS transistor 512 is connected to the drain of the PMOS transistor 511. The switch 532 is connected between the gate and the drain of the NMOS transistor 522, and the source of the NMOS transistor 522 is grounded. The switch 532 is turned on and off based on the auto-zero signal AZN.

[0132] The output circuit 503 converts the output of the post-stage amplifier 502 into a logic value “0” or a logic value “1.” The output circuit 503 includes PMOS transistors 513 and 543 , and NMOS transistors 523 and 533 .

[0133] The PMOS transistor 513 and the NMOS transistor 523 are connected in series with each other, and the NMOS transistors 523 and 533 are connected in series with each other. The sources of the PMOS transistors 513 and 543 are connected to the power supply voltage VDDL, and the source of the NMOS transistor 533 is grounded. The drain of the PMOS transistor 543 is connected to the drain of the PMOS transistor 513. The power supply voltage VDDL may be lower than the power supply voltage VDDH. The gate of the PMOS transistor 543 and the gate of the NMOS transistor 523 are connected to the drain of the PMOS transistor 512. The control signal XC is applied to the gate of the PMOS transistor 513 and the gate of the NMOS transistor 533.

[0134] The first input terminal of the AND circuit 504 is connected to the drain of the PMOS transistor 513. The control signal XD is applied to the second input terminal of the AND circuit 504. The control signals XA, XB, XC and XD are Figure 6 The control signal CTL in is input to the comparator 143.

[0135] When the comparator 143 is set to the standby state, the control signals XA, XB, XC and XD are set to the low level. At this time, the NMOS transistors 533 and 581 are turned off, the PMOS transistors 512 and 513 are turned on, and a logic value “0” is output from the AND circuit 504 .

[0136] When the comparator 143 is set to an active state, the control signals XA, XB, XC and XD are set to a high level. At this time, the NMOS transistors 533 and 581 are turned on, the PMOS transistors 512 and 513 are turned off, and the AND circuit 504 outputs a logic value "0" or "1" according to the output from the output circuit 503.

[0137] At this time, during the auto-zero period, the PMOS transistors 551 and 561 are turned on based on the auto-zero signal AZP, and the switch 532 is closed based on the auto-zero signal AZN. Note that the timing at which the PMOS transistors 551 and 561 are turned on and then turned off may be delayed compared to the timing at which the switch 532 is closed and then turned off. At this time, current flows through the PMOS transistors 551 and 561 based on the current mirror operation of the PMOS transistors 511 and 521. Then, charges are stored in the DC cut-off capacitors 144 and 145, so that the non-inverting input and the inverting input of the comparator 143 are balanced.

[0138] In this way, in the first embodiment described above, the signal line reset transistor 141 performs combination based on the signal sampled and held for each column connected to the vertical signal lines 132-1 to 132-4. As a result, it is possible to perform combination in the column direction while suppressing an increase in the area of ​​the signal readout circuit, and to ensure linearity during combination without limiting the number of combinations.

[0139] Furthermore, by activating the AD conversion unit provided for each of the vertical signal lines 132 - 1 to 132 - 4 , an AD conversion unit that does not need to operate during the combining process can be set to a standby state, thereby achieving low power consumption.

[0140] Furthermore, by resetting the vertical signal line 132 when a signal is read out from each pixel 120, a charge corresponding to a pixel current flowing when a signal is read out from each pixel 120 can be stored in the capacitor 133. Therefore, it is no longer necessary to pass a constant current corresponding to a signal read out from each pixel 120 via the vertical signal lines 132-1 to 132-4 in order to detect the signal read out from each pixel 120, and current consumption when a signal is read out from each pixel 120 can be reduced.

[0141] <2. Second Embodiment>

[0142] In the first embodiment described above, the signal line reset transistor 141 performs merging based on the signal sampled and held for each column connected to the vertical signal lines 132-1 to 132-4. In this second embodiment, the diode-connected transistor performs merging based on the signal sampled and held for each column connected to the vertical signal lines 132-1 to 132-4 via the signal line reset transistor 141.

[0143] Fig. 9 is a diagram showing a configuration example of a signal readout circuit for four columns according to the second embodiment.

[0144] In the figure, the signal readout circuit is obtained by adding a diode-connected transistor 142 to the signal readout circuit of the above-described first embodiment. The other configuration of the signal readout circuit of the second embodiment is similar to that of the above-described first embodiment.

[0145] The diode-connected transistor 142 is connected in series to the signal line reset transistor 141 for each of the vertical signal lines 132-1 to 132-4. The diode-connected transistor 142 may be, for example, a MOS transistor. At this time, the gate of the diode-connected transistor 142 is connected to the drain of the diode-connected transistor 142. The source of the diode-connected transistor 142 is grounded. The source of the diode-connected transistor 142 may be connected to a potential higher than the ground potential. The diode-connected transistor 142 generates a voltage higher than 0V (for example, 0.5V), and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 may be set to a potential higher than 0V via the signal line reset transistor 141. The diode-connected transistor 142 is an example of a signal line reset level generating unit described in the claims. The operation of the signal readout circuit of the second embodiment when combined is the same as the operation of the signal readout circuit of the first embodiment when combined.

[0146] Thus, in the above-mentioned second embodiment, the diode-connected transistor 142 performs integration based on the signals sampled and held by the columns connected to the vertical signal lines 132-1 to 132-4 via the signal line reset transistor 141. In this way, when the vertical signal lines 132-1 to 132-4 are reset, the potentials of the vertical signal lines 132-1 to 132-4 can be increased according to the forward voltage of the diode-connected transistor 142. Therefore, the potentials of the vertical signal lines 132-1 to 132-4 at the start of the stabilization of the P-phase VSL can be made higher than 0V, and the stabilization time can be shortened.

[0147] <3. Third Embodiment>

[0148] In the first embodiment, the connection switch 151 is connected in series to the capacitor 133 of each column for sampling and holding according to the signal of each column sampling and holding. In the third embodiment, the connection switch is connected in parallel to the capacitor of each column for sampling and holding according to the signal of each column sampling and holding according to the signal of each column sampling and holding.

[0149] Fig.10 : is a diagram showing an example of the configuration of a signal readout circuit for four columns according to the third embodiment.

[0150] In the figure, the signal readout circuit has a connection switch 152 instead of the connection switch 151 of the signal readout circuit of the above-described first embodiment. The other configuration of the signal readout circuit of the third embodiment is similar to that of the signal readout circuit of the above-described first embodiment.

[0151] The connection switch 152 connects the vertical signal lines 132-1 to 132-4 of different columns. At this time, the connection switch 152 is connected in parallel to each column of the capacitor 133 for sampling and holding the signal read out from each pixel 120. Each connection switch 152 can be opened / closed based on the opening / closing signal ΦCn. When the connection switch 152 is used, the number of connections in the column direction is fixed. The operation of the signal readout circuit of the third embodiment during the merging is similar to the operation of the signal readout circuit of the first embodiment during the merging, except that the number of merging in the column direction is fixed.

[0152] As described above, in the third embodiment described above, the signal line reset transistor 141 performs combination based on the signal sampled and held for each column connected to the vertical signal lines 132-1 to 132-4. As a result, combination can be performed in the column direction while suppressing an increase in the area of ​​the signal readout circuit, and linearity can be ensured during combination without limiting the number of combinations.

[0153] <4. Fourth Embodiment>

[0154] In the first embodiment described above, binning is performed in the column direction based on the signal sampled and held for each column. In the fourth embodiment, binning is performed in the column and row directions based on the signal sampled and held for each column.

[0155] Fig.11 : is a diagram showing an example of the configuration of a signal readout circuit for two columns according to the fourth embodiment.

[0156] In this figure, the signal readout circuit has a unit 130 instead of the pixel 120 of the signal readout circuit of the first embodiment. In addition, in this signal readout circuit, a binning line 140 is added to the signal readout circuit of the first embodiment. The other configurations of the signal readout circuit of the fourth embodiment are similar to those of the signal readout circuit of the first embodiment.

[0157] The cells 130 are arranged in a matrix in the row direction and the column direction. Each cell 130 is connected to the vertical signal lines 132-1 and 132-2 of each column. Instead of the photodiode 121 and the transfer transistor 122 of the first embodiment described above, the cell 130 includes photodiodes 121-1 to 121-4, transfer transistors 122-1 to 122-4, and a merging transistor 127. The other structures of the cell 130 of the fourth embodiment are the same as the pixel 120 of the first embodiment described above.

[0158] The photodiodes 121-1 to 121-4 may be arranged in two rows and two columns. The photodiodes 121-1 to 121-4 are connected to the floating diffusion 126 via transfer transistors 122-1 to 122-4, respectively. Transfer signals ΦTG1 to ΦTG4 are applied to the gates of the transfer transistors 122-1 to 122-4. By controlling the application timing of the transfer signals ΦTG1 to ΦTG4, signals can be read out from the photodiodes 121-1 to 121-4 individually, or signals can be read out from the photodiodes 121-1 to 121-4 by grading. The capacitive load readout operation of the photodiodes 121-1 to 121-4 is similar to the capacitive load readout operation of the photodiode 121 in the first embodiment described above.

[0159] For each cell 130, a merging transistor 127 is connected between the floating diffusion 126 and the combining line 140. The merging transistor 127 may be a MOS transistor. For each cell 130, a merging signal ΦBN is applied to the gate of the merging transistor 127.

[0160] When a signal is read out from each cell 130 , the binning signal ΦBN becomes low level, and the binning transistor 127 of each cell 130 is turned off.

[0161] On the other hand, when reading out a signal from each cell 130 by combining in the row direction, the combined signal ΦBN becomes high level, and the combined transistor 127 of each cell 130 becomes conductive. The operation of the signal readout circuit of the fourth embodiment during combining in the row direction and the column direction is similar to the operation of the signal readout circuit of the first embodiment during combining, except that the combined transistor 127 of each cell 130 is turned on.

[0162] For example, it is assumed that the signals of the photodiodes 121-1 to 121-4 are averaged in 32 rows x 2 columns, and the signals of the 16 columns of the unit 130 are averaged by capacitance. At this time, the number of columns of the activated AD conversion unit can be 1 / 16 of the number of columns of the AD conversion unit for individual readout of all pixels, and power consumption can be reduced.

[0163] Thus, in the fourth embodiment, a combination transistor 127 for connecting cells 130 in different rows is provided in each cell 130. Thus, not only combination in the column direction but also combination in the row direction is possible, so that a decrease in spatial resolution in the row direction can be suppressed and the number of combinations can be increased.

[0164] <5. Fifth embodiment>

[0165] In the first embodiment described above, the average value of the signal sampled and held for each column connected to the vertical signal lines 132-1 to 132-4 is input to the comparator 143. In the fifth embodiment, the average value of the signal sampled and held for each column connected to the vertical signal lines 132-1 to 132-4 is input to the comparator 143 via the amplifier 161.

[0166] Fig.12 : is a diagram showing a configuration example of a signal readout circuit for four columns according to the fifth embodiment.

[0167] In this figure, the signal readout circuit is obtained by adding an amplifier 161 to the signal readout circuit of the first embodiment described above. The other configuration of the signal readout circuit of the fifth embodiment is similar to that of the signal readout circuit of the first embodiment described above.

[0168] The amplifier 161 amplifies the signal sent to the comparator 143 via the vertical signal lines 132-1 to 132-4 of each column. The amplifier 161 is set for each vertical signal line 132-1 to 132-4. Each amplifier 161 is connected to the inverting input terminal of each comparator 143 via the DC cut-off capacitor 144. The control signal CTL is input to the amplifier 161. At this time, the amplifier 161 in the same column as the comparator 143 and the counter 146 can be activated in response to their activation. In addition, the amplifier 161 in the same column as the comparator 143 and the counter 146 can be set to a standby state in response to the standby state of the comparator 143 and the counter 146.

[0169] As described above, in the fifth embodiment described above, the amplifier 161 is provided for each vertical signal line 132-1 to 132-4, and the control signal CTL is input to each amplifier 161. As a result, the signal sent to the comparator 143 can be amplified while suppressing an increase in power consumption during binning.

[0170] <6. Sixth Implementation Method>

[0171] In the third embodiment described above, the selection transistor 125 is used as a sample-and-hold switch for sampling and holding a signal of each column transmitted via the vertical signal lines 132-1 to 132-4. In the sixth embodiment, a sample-and-hold switch for sampling and holding a signal transmitted via the vertical signal lines 132-1 to 132-4 for each column is provided on the vertical signal lines 132-1 to 132-4.

[0172] Fig.13 : is a diagram showing an example of the configuration of a signal readout circuit for four columns according to the sixth embodiment.

[0173] In the figure, the signal readout circuit is obtained by adding a sample hold switch 153 and drivers 301 and 302 to the signal readout circuit of the third embodiment described above. The other configuration of the signal readout circuit of the sixth embodiment is similar to that of the third embodiment described above.

[0174] The sample-hold switch 153 samples and holds the signal transmitted via the vertical signal lines 132-1 to 132-4 in each capacitor 153 of each column. The sample-hold switch 153 is provided for each vertical signal line 132-1 to 132-4. Each sample-hold switch 153 is turned on / off based on the sample-hold signal ΦVS. Each sample-hold switch 153 may be a MOS transistor.

[0175] The drivers 301 and 302 drive the sample-hold switch 153 from both sides in the row direction. The drivers 301 and 302 may be shared by the sample-hold switch 153 provided for each column.

[0176] Fig.14 is a diagram showing an example of a waveform of each portion when a signal is read out in the imaging device according to the sixth embodiment. In addition, this diagram shows an example of a waveform of each portion when a signal is read out by combining.

[0177] In the figure, the operation during the combined readout in the sixth embodiment is similar to the operation during the combined readout in the above-described first embodiment, except that a sample-and-hold signal ΦVS is added.

[0178] The sample hold signal ΦVS rises simultaneously with the rise of the pixel reset signal ΦPRT in pixel reset / VSL reset (K11) (t11). In addition, the sample hold signal ΦVS falls in P-phase VSL stabilization / P-phase VSL sample and hold (K12) before the selection signal ΦSEL falls.

[0179] Furthermore, the sample hold signal ΦVS rises simultaneously with the rise of the transfer signal ΦTG in the transfer / VSL reset (K14) (t14). Furthermore, the sample hold signal ΦVS falls in the D-phase VSL stabilize / D-phase VSL sample and hold (K15) before the selection signal ΦSEL falls.

[0180] In this manner, in the sixth embodiment described above, the sample hold switch 153 is provided to sample and hold the signal of each column transmitted via the vertical signal lines 132-1 to 132-4. As a result, binning in the column direction can be performed while ensuring linearity during binning.

[0181] In addition, drivers 301 and 302 that drive the sample-hold switch 153 from both sides in the row direction are provided. As a result, the driving force of the sample-hold switch 153 of each column can be increased without providing the drivers 301 and 302 for driving the sample-hold switch 153 of each row. As a result, the in-plane difference of the driving force can be reduced, so that the fixed pattern noise can be reduced, and also the increase in the area required for the arrangement of the drivers 301 and 302 is suppressed.

[0182] <7. Seventh Implementation Method>

[0183] In the first embodiment described above, for activated and deactivated columns, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are input to the comparator 143 via the DC cut capacitor 144. In the seventh embodiment, for deactivated columns, the connection destination of the DC cut capacitor 144 is switched from the comparator input to the ground.

[0184] Fig.15 : is a diagram showing an example of the configuration of a signal readout circuit for four columns according to the seventh embodiment.

[0185] In this figure, the signal readout circuit is obtained by adding changeover switches 154 and 155 to the signal readout circuit of the above-described first embodiment. The other configuration of the signal readout circuit of the seventh embodiment is similar to that of the signal readout circuit of the above-described first embodiment.

[0186] The first capacitance electrode of the DC cut capacitor 144 of each column is connected to the vertical signal lines 132-1 to 132-4. Conversion switches 154 and 155 are provided for each column. The conversion switch 154 is connected between the second capacitance electrode of the DC cut capacitor 144 of each column and the inverting input terminal of each comparator 143. The conversion switch 155 is connected between the second capacitance electrode of the DC cut capacitor 144 of each column and the ground.

[0187] Then, for the activated column, the conversion switch 154 is turned on and the conversion switch 155 is turned off. On the other hand, for the deactivated column, the conversion switch 154 is turned off and the conversion switch 155 is turned on. At this time, the conversion switches 154 and 155 are controlled individually for the activated column and the deactivated column.

[0188] For example, among the comparators 143 and the counters 146 provided corresponding to the vertical signal lines 132-1 to 132-4, the comparator 143 and the counter 146 provided corresponding to the vertical signal line 132-1 are activated. At this time, the conversion switch 154 connected to the vertical signal line 132-1 is turned on, and the conversion switch 155 is turned off. On the other hand, the conversion switches 154 connected to the vertical signal lines 132-2 to 132-4 are turned off, and the conversion switch 155 is turned on. In addition, during the combination period, the opening / closing signals ΦCn1 to ΦCn4 are turned on. Therefore, the capacitance of the DC cut-off capacitor 144 connected to the vertical signal lines 132-2 to 132-4 is added to the capacitance 133 of the vertical signal line 132-1.

[0189] In this way, in the seventh embodiment described above, for the deactivated column, the connection destination of the DC cut capacitor 144 is switched from the comparator input to the ground. Therefore, the capacitance added to the vertical signal line 132-1 of the activated column can be increased, thereby reducing kTC noise.

[0190] <8. Eighth Implementation Method>

[0191] In the first embodiment described above, binning is performed based on capacitive load readout. In the eighth embodiment, binning is performed based on constant current readout.

[0192] Fig.16 : is a diagram showing an example of the configuration of a signal readout circuit for four columns according to the eighth embodiment.

[0193] In the figure, the signal readout circuit has a current source 401 instead of the signal line reset transistor 141 of the signal readout circuit of the first embodiment described above. In addition, the signal readout circuit has a connection switch 402, sample-hold switches 403 and 404, and a capacitor 405 added to the signal readout circuit of the first embodiment described above. The other configurations of the signal readout circuit of the eighth embodiment are similar to those of the signal readout circuit of the first embodiment described above.

[0194] A current source 401 may be provided for each column. Each current source 401 is connected to the vertical signal lines 132-1 to 132-4. The current source 401 may be a MOS transistor.

[0195] The sample-hold switches 403 and 404 enable the capacitor 405 to sample and hold the signal sent via the vertical signal lines 132-1 to 132-4 of each column. The sample-hold switches 403 and 404 are provided for each of the vertical signal lines 132-1 to 132-4. At this time, each sample-hold switch 403 is connected in series to each of the vertical signal lines 132-1 to 132-4. The sample-hold switch 404 is connected between the vertical signal lines 132-1 to 132-4 and the capacitor 405. The sample-hold switch 403 is turned on / off based on the sample-hold signal ΦVS. The sample-hold switch 404 is turned on / off based on the sample-hold signal ΦS. The sample-hold switches 403 and 404 may be MOS transistors.

[0196] A capacitor 405 may be provided for each column. Each capacitor 405 is connected to each of the vertical signal lines 132-1 to 132-4 via a sample-and-hold switch 404. The capacitor 405 may be used to sample and hold a signal read out from each pixel 120 of each column.

[0197] The connection switch 402 connects the vertical signal lines 132-1 to 132-4 of different columns. At this time, the connection switch 402 is connected in parallel with a capacitor 405 for sampling and holding a signal read out from each pixel 120. Each connection switch 402 may be a MOS transistor. Each connection switch 402 is turned on / off based on an opening / closing signal ΦCn.

[0198] Fig.17 : is a diagram showing an example of the waveform of each section during the signal readout of the imaging device according to the eighth embodiment. In addition, this diagram shows an example of the waveform of each section at the time of binning readout.

[0199] In the figure, in the constant current readout, pixel reset (K21) is performed. At this time, the pixel reset signal ΦPRT of each pixel 120 rises (t21), the reset transistor 123 of each pixel 120 is turned on, and the floating diffusion 126 of each pixel 120 is reset. In addition, the selection signal ΦSEL of each pixel 120 rises (t21), and the selection transistor 125 of each pixel 120 is turned on. At this time, when the power supply potential Vdd is applied to the gate of the amplification transistor 124 of each pixel 120, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the source follower operation.

[0200] Furthermore, the sample hold signal ΦS rises (t21), and the sample hold switches 404 connected to the vertical signal lines 132-1 to 132-4 are turned on. At this time, the capacitors 405 provided for each column are connected to the vertical signal lines 132-1 to 132-4 via the sample hold switches 404.

[0201] Then, the sample hold signal ΦVS rises (t21), and the sample hold switch 403 connected to the vertical signal lines 132-1 to 132-4 is turned on. At this time, the capacitor 405 provided for each column is connected to the pixel 120 of each column via the vertical signal lines 132-1 to 132-4.

[0202] Then, the auto-zero signal AZ rises (t21), and the auto-zero operation of the comparator 143 connected to the vertical signal lines 132-1 to 132-4 is activated. At this time, the charges stored in the DC cut-off capacitors 144 and 145 are controlled so that the non-inverting input and the inverting input of the comparator 143 connected to the vertical signal lines 132-1 to 132-4 are balanced.

[0203] Next, P-phase VSL sinking / P-phase VSL sampling and holding (K22) is performed. At this time, the pixel reset signal ΦPRT of each pixel 120 drops (t22), and the reset transistor 123 of each pixel 120 is turned off. Then, when the reset level of the floating diffusion 126 of each pixel 120 is applied to the gate of the amplification transistor 124 of each pixel 120, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the source follower operation. Then, the charges corresponding to the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are sampled and held in the capacitor 405 of each column. Then, the sample-hold signal ΦVS drops.

[0204] Next, P-phase merge / P-phase AD (K23) is performed. At this time, the opening / closing signal ΦCn rises (t23), and the auto-zero signal AZ falls. When the opening / closing signal ΦCn rises, the connection switch 402 connected to the vertical signal lines 132-1 to 132-4 is turned on. Then, the charges stored in the capacitors 405 added to the vertical signal lines 132-1 to 132-4 are merged, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. In addition, for example, among the comparators 143 and the counter 146 provided corresponding to the vertical signal lines 132-1 to 132-4, only the comparator 143 and the counter 146 provided corresponding to the vertical signal line 132-1 are activated. In addition, the ramp signal is supplied to the activated comparator 143 as the reference signal RAP. Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 corresponding to the reset level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, in the activated counter 146, the counting operation is performed until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the reset level read out from each pixel 120 connected to the vertical signal lines 132-1 to 132-4 is AD converted. Thereafter, the opening / closing signal ΦCn falls.

[0205] Next, transfer is performed (K24). At this time, the transfer signal ΦTG of each pixel 120 rises (t24), the transfer transistor 122 of each pixel 120 is turned on, and the charge stored in the photodiode 121 of each pixel 120 is transferred to the floating diffusion 126 of each pixel 120. In addition, when the cathode potential of the photodiode 121 of each pixel 120 is applied to the gate of the amplification transistor 124 of each pixel 120, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the source follower operation.

[0206] Furthermore, the sample hold signal ΦVS rises (t24), and the sample hold switch 403 connected to the vertical signal lines 132-1 to 132-4 is turned on. At this time, the capacitor 405 provided for each column is connected to the pixel 120 of each column via the vertical signal lines 132-1 to 132-4.

[0207] Next, D-phase VSL sinking / D-phase VSL sampling and holding (K25) is performed. At this time, the transfer signal ΦTG of each pixel 120 drops (t25), and the transfer transistor 122 of each pixel 120 is turned off. Then, when the signal level of the floating diffusion 126 of each pixel 120 is applied to the gate of the amplification transistor 124 of each pixel 120, the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are set based on the source follower operation. Then, the charges corresponding to the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are sampled and held in the capacitor 405 of each column. Then, the sample-hold signal ΦVS drops.

[0208] Next, D-phase merge / P-phase AD (K26) is performed. At this time, the opening / closing signal ΦCn rises (t26), and the connection switch 402 connected to the vertical signal lines 132-1 to 132-4 is turned on. Then, the charges stored in the capacitors 405 added to the vertical signal lines 132-1 to 132-4 are merged, and the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 are averaged. Then, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is input to each comparator 143. In addition, the ramp signal is supplied to the activated comparator 143 as a reference signal RAP (t26 to t27). Then, in the activated comparator 143, the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 corresponding to the signal level is compared with the reference signal RAP. Then, the timing when the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4 is output as the comparison result COP1. At this time, in the activated counter 146, the counting operation is performed until the level of the reference signal RAP matches the average value of the potentials VSL1 to VSL4 of the vertical signal lines 132-1 to 132-4. Then, based on the counting operation of the activated counter 146, the average value of the signal level read out from each pixel 120 connected to the vertical signal lines 132-1 to 132-4 is AD converted. Thereafter, the sampling hold signal ΦS and the opening / closing signal ΦCn fall, and the selection signal ΦSEL of each pixel 120 falls.

[0209] Thus, in the eighth embodiment described above, merging is performed based on constant current sensing. This allows the time required for settling to be reduced compared to capacitive load sensing.

[0210] <9. Ninth Implementation Method>

[0211] In the above second embodiment, merging is performed based on capacitive load readout. In the ninth embodiment, a constant current transistor is connected in parallel to the series circuit of the signal line reset transistor 141 and the diode-connected transistor 142, so that switching between constant current readout and capacitive load readout is possible.

[0212] Fig.18 1 is a block diagram showing a configuration example of a signal readout circuit for one column according to the ninth embodiment. Note that although the figure shows the signal readout circuit for one column, other columns can be configured in the same manner.

[0213] In the figure, the signal readout circuit is obtained by adding a sample hold circuit 201 and a constant current transistor 301 to the signal readout circuit of the second embodiment described above. The other configuration of the signal readout circuit of the ninth embodiment is similar to that of the signal readout circuit of the second embodiment described above.

[0214] The sample and hold circuit 201 samples and holds the bias voltage Vb and applies it to the gate of the constant current transistor 301. The sample and hold circuit 201 includes a transistor 211 and a capacitor 212. The transistor 211 may be a MOS transistor. The sample and hold signal ΦSH is applied to the gate of the transistor 211. The capacitor 212 is connected between the source of the transistor 211 and the ground potential.

[0215] The constant current transistor 301 is electrically connected to the vertical signal line 132 - 1 . The constant current transistor 301 may be a MOS transistor. The gate of the constant current transistor 301 is connected to the output of the sample-and-hold circuit 201 .

[0216] Here, in the capacitive load readout, the bias voltage Vb is set to 0 V, and the sample hold signal ΦSH is set to a high level. In this case, the constant current transistor 301 is turned off, and no current flows through the constant current transistor 301. The operation of the signal readout circuit at this time is similar to the operation of the signal readout circuit of the first embodiment described above.

[0217] In the constant current readout, in order to prevent cross-draw noise during AD conversion, the transistor 211 is turned on and the bias voltage Vb is sampled and held. Then, the transistor 211 is turned off and the bias voltage Vb sampled and held by the sample-hold circuit 201 is applied to the gate of the constant current transistor 301. In this case, the constant current transistor 301 is turned on and a constant current flows through the constant current transistor 301. The operation of the signal readout circuit at this time is similar to the operation of the signal readout circuit of the eighth embodiment described above.

[0218] As described above, in the above-mentioned ninth embodiment, the constant current transistor 301 is connected in parallel to the series circuit of the signal line reset transistor 141 and the diode-connected transistor 142. As a result, it is possible to perform combination in the column direction while suppressing an increase in the area of ​​the signal readout circuit, and it is possible to switch between constant current readout and capacitive load readout.

[0219] <10. Tenth Implementation Method>

[0220] In the first embodiment described above, the signal line reset transistor 141 performs merging based on the signal sampled and held for each column connected to the vertical signal lines 132-1 to 132-4. In this tenth embodiment, substrates on which a solid-state imaging device having a pixel array unit in which pixels 120 are arranged in a matrix are formed are stacked.

[0221] Fig.19 is a perspective view showing a configuration example of an imaging device according to a tenth embodiment.

[0222] exist Fig.19 , the solid-state imaging device 901 includes a supporting substrate 911 and a semiconductor substrate 912. The semiconductor substrate 912 is stacked on the supporting substrate 911. A pixel array unit 913 and a peripheral circuit 914 are formed on the semiconductor substrate 912. A column readout circuit 915 and a column ADC 916 are formed on the peripheral circuit 914. The column readout circuit 915 and the column ADC 916 may be formed on both sides of the pixel array unit 913 along the column direction.

[0223] The pixels 120 are arranged in a matrix in the row direction and the column direction in the pixel array unit 913. The column readout circuit 915 can read out a signal from each pixel 120 individually based on capacitive load readout, or can read out the signal by gradation. In the column readout circuit 915, for example, Figure 6 The signal line in the reset transistor 141 and the connection switch 151. The column ADC 916 can perform AD conversion for each column of the signal read out via the column readout circuit 915. In this case, the solid-state imaging device 901 can constitute a back-illuminated image sensor.

[0224] In b of the figure, the solid-state imaging device 902 includes semiconductor substrates 921 and 922. The semiconductor substrate 922 is stacked on the semiconductor substrate 921. The pixel array unit 923 is formed in the semiconductor substrate 922. The peripheral circuit 924 is formed in the semiconductor substrate 922. The column readout circuit 925 and the column ADC 926 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 can be formed to correspond to the positions on both sides of the pixel array unit 923 in the column direction. In this case, the solid-state imaging device 902 can constitute a back-illuminated image sensor.

[0225] In this manner, in the above-described twelfth embodiment, the substrates on which the solid-state imaging devices 901 and 902 are formed are stacked. This allows the semiconductor substrates 912 and 922 on which the pixel array units 913 and 923 are formed to be thinned while supporting the pixel array units 913 and 923, respectively, and allows a back-illuminated image sensor to be formed.

[0226] <11. Example of application to mobile objects>

[0227] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device equipped in any type of mobile object, such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, and a robot.

[0228] Fig. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0229] The vehicle control system 12000 includes a plurality of electronic control units connected thereto via a communication network 12001. Fig. 20 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0230] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device such as a drive force generating unit that generates the drive force of the vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism that transmits the drive force to the wheels, a steering mechanism that adjusts the steering angle of the vehicle, and a brake device that generates the braking force of the vehicle.

[0231] The body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as headlights, rear lights, brake lights, turn signals, and fog lights. In this case, a radio wave transmitted from a portable device instead of a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives the input of the radio wave or the signal and controls the door locking device, the power window device, and the lights of the vehicle.

[0232] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receive the captured image. In addition, the vehicle exterior information detection unit 12030 may also perform object detection processing and distance detection processing on a person, car, obstacle, sign, text, etc. on the road based on the received image.

[0233] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output the electrical signal as an image or distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0234] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle unit information detection unit 12040 can calculate the driver's fatigue or concentration based on the detection information input from the driver state detection unit 12041 or can determine whether the driver is dozing off.

[0235] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside and outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and can output a control command to the driving system control unit 12010. For example, in order to realize the function of ADAS (Advanced Driver Assistance System), the microcomputer 12051 can perform cooperative control, including vehicle collision avoidance or impact mitigation, following driving based on following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0236] In addition, the microcomputer 12051 controls the driving force generating device, steering mechanism or braking device based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby enabling coordinated control such as automatic driving that allows autonomous driving regardless of the driver's operation.

[0237] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information acquired by the vehicle exterior information detection unit 12030 outside the vehicle. For example, the microcomputer 12051 can perform cooperative control for preventing glare, such as switching from high beam to low beam, by controlling the headlights based on the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0238] The audio / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying information to a passenger or the outside of the vehicle. Fig. 20 In the example of FIG. 1 , an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as examples of output devices. For example, the display unit 12062 may include at least one of an on-board display and a head-up display.

[0239] Fig.21 The figure shows an example of the setting position of the imaging unit 12031.

[0240] exist Fig.21 In the embodiment, imaging units 12101, 12102, 12103, 12104 and 12105 are provided as imaging unit 12031.

[0241] Imaging units 12101, 12102, 12103, 12104, and 12105 are disposed at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield of the vehicle 12100. The imaging unit 12101 disposed at the front nose of the vehicle interior and the imaging unit 12105 disposed at the upper portion of the windshield mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 disposed on the rear bumper or rear door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 disposed in the upper portion of the windshield inside the vehicle is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, and the like.

[0242] Fig.21An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose, the imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by overlapping the image data captured by the imaging units 12101 to 12104, it is possible to obtain a bird's-eye view image observed from above the vehicle 12100.

[0243] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0244] For example, the microcomputer 12051 can extract the nearest three-dimensional object on the path of the vehicle 12100 (i.e., a three-dimensional object traveling at a predetermined speed (e.g., 0 km / h or higher) in the same direction as the vehicle 12100) as the vehicle in front by acquiring the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be ensured with respect to the vehicle in front, and can perform automatic braking control (also including follow-up stop control) or automatic acceleration control (also including follow-up start control). As a result, coordinated control such as automatic driving in which the vehicle automatically drives without the driver's operation can be performed.

[0245] For example, the microcomputer 12051 can classify and extract three-dimensional data related to the three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects (such as electrodes) based on the distance information obtained from the imaging units 12101 to 12104, and can use the three-dimensional data to perform automatic avoidance of obstacles. For example, the microcomputer 12051 divides the surrounding obstacles of the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the degree of risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an alarm is output to the driver through the audio speaker 12061 or the display unit 12062, and forced deceleration or evasive steering is performed by the drive system control unit 12010, and thus driving support for collision avoidance can be performed.

[0246] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is performed by, for example, a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and a process of performing pattern matching processing on a series of feature points representing the outline of the object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and the pedestrian is recognized, the audio / image output unit 12052 controls the display unit 12062 so that the square outline for emphasis overlaps with the recognized pedestrian and is displayed. In addition, the audio / image output unit 12052 may control the display unit 12062 so that an icon indicating a pedestrian, etc., is displayed at a desired position.

[0247] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 within the above configuration. Specifically, for example, the above-mentioned camera 100 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to obtain a captured image while suppressing an increase in power consumption.

[0248] It should be noted that the above-mentioned embodiments illustrate examples that embody the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship with each other. Similarly, the items specifying the present invention set forth within the scope of the patent claims correspond to the items with the same name in the embodiments of the present technology. However, the present technology is not limited to the embodiments and may be embodied by applying various modifications to the embodiments without departing from its purport. In addition, the effects described in this specification are merely exemplary and are not intended to be limiting, and other effects may also be provided.

[0249] The present technology may also have the following configurations.

[0250] (1) An imaging device comprising:

[0251] A pixel array unit, wherein pixels are arranged in a matrix in row and column directions;

[0252] A signal line that transmits a signal read out from pixels in a column direction;

[0253] a sample-and-hold switch for sampling and holding a signal transmitted via the signal line for each column pair; and

[0254] Connect switches to connect signal lines of different columns for sampling and holding signals.

[0255] (2) The imaging device according to (1), further comprising:

[0256] An AD conversion unit that performs AD conversion on each of the columns of the signal transmitted via the signal line; and

[0257] The activation control unit activates one of the AD conversion units of each column connected via the connection switch.

[0258] (3) The imaging device according to (2), wherein

[0259] The AD conversion unit includes:

[0260] a comparator that compares the potential of the signal line with the ramp signal; and

[0261] A counter performs a counting operation based on a comparison result from the comparator.

[0262] (4) The imaging device according to (3), wherein

[0263] The activation control unit controls the AD conversion units separately for the columns to be activated and the columns to be deactivated.

[0264] (5) The imaging device according to (3) or (4), further comprising:

[0265] a first DC cut-off capacitor connected to a first input terminal of the comparator; and

[0266] The second DC cut-off capacitor is connected to the second input terminal of the comparator.

[0267] (6) The imaging device according to (5), further comprising:

[0268] The changeover switch switches a connection destination of the second capacitance electrode of the first DC cut capacitor having the first capacitance electrode connected to the signal line between the first input terminal of the comparator and ground.

[0269] (7) The imaging device according to (6), wherein

[0270] The activation control unit controls the changeover switches for the columns to be activated and the columns to be deactivated, respectively.

[0271] (8) The imaging device according to any one of (2) to (7), further comprising:

[0272] The amplifier amplifies the signal transmitted via the signal line for each column and inputs the amplified signal to the AD conversion unit.

[0273] (9) The imaging device according to (8), wherein:

[0274] The activation control unit controls the amplifiers for the columns to be activated and the columns to be deactivated, respectively.

[0275] (10) The imaging device according to any one of (1) to (9), wherein

[0276] The sample-and-hold switch is a transistor provided for each signal line.

[0277] (11) The imaging device according to (10), further comprising:

[0278] Driver drives the transistors from both sides in the row direction.

[0279] (12) The imaging device according to any one of (1) to (11), further comprising:

[0280] a signal line reset transistor, the signal line reset transistor resetting the potential of the signal line; and

[0281] The signal line reset level generating unit generates a reset level of the potential of the signal line.

[0282] (13) The imaging device according to (12), wherein:

[0283] The signal line reset level generating unit includes a diode-connected transistor.

[0284] (14) The imaging device according to any one of (1) to (13), wherein:

[0285] The capacitance used to sample and hold the signal is the parasitic capacitance of the signal line.

[0286] (15) The imaging device according to any one of (1) to (14), wherein:

[0287] A connection switch is connected in series with the capacitor of each column for sampling and holding the signal.

[0288] (16) The imaging device according to any one of (1) to (14), wherein:

[0289] The connection switch is connected in parallel with the capacitor of each column for sampling and holding the signal.

[0290] (17) The imaging device according to any one of (1) to (16), further comprising:

[0291] a constant current transistor electrically connected to the signal line and passing a constant current based on a source follower formed between the signal line and the pixel, wherein

[0292] The constant current transistor is turned on during constant current readout, and

[0293] The constant current transistor is turned off during the capacitive load readout period.

[0294] (18) The imaging device according to any one of (1) to (17), wherein:

[0295] Pixels include:

[0296] Photodiode;

[0297] a transfer transistor, which transfers the charge stored in the photodiode to the floating diffusion;

[0298] A reset transistor, the reset transistor resets the floating diffusion;

[0299] an amplifying transistor that outputs a signal corresponding to the potential of the floating diffusion; and

[0300] The selection transistor is connected between the amplification transistor and the signal line.

[0301] (19) The imaging device according to (19), wherein

[0302] The sample and hold switch is the select transistor.

[0303] (20) The imaging device according to (18) or (19), further comprising:

[0304] Merge transistors to connect floating diffusions from different rows.

[0305] [Reference Numbers List]

[0306] 100 Camera

[0307] 101 Optical System

[0308] 102 Solid-state imaging device

[0309] 103 Imaging control unit

[0310] 104 Image processing unit

[0311] 105 Storage Unit

[0312] 106 Display Unit

[0313] 107 Operating unit

[0314] 108 Bus

[0315] 111 pixel array unit

[0316] 112 vertical scanning circuit

[0317] 113 Column readout circuit

[0318] 114 columns of signal processing units

[0319] 115 Horizontal scanning circuit

[0320] 116 Control Circuit

[0321] 117, 118 Driver

[0322] 119 Activate control unit

[0323] 121 Photodiode

[0324] 122 Transfer transistor

[0325] 123 Reset transistor

[0326] 124 Amplifier transistor

[0327] 125 Select transistor

[0328] 126 Floating Diffusion

[0329] 131 Horizontal drive line

[0330] 132 vertical signal line

[0331] 133 Capacitor

[0332] 141 Signal line reset transistor

[0333] 142 Diode-connected transistor

[0334] 143 Comparator

[0335] 144, 145DC cut-off capacitor

[0336] 146 Counter

[0337] 151 Connection switch

Claims

1. An imaging device, comprising: A pixel array unit, wherein pixels are arranged in a matrix in row and column directions; A signal line for transmitting a signal read out from pixels in the column direction; a sample-and-hold switch that samples and holds a signal transmitted via the signal line for each column; and Connect switches to connect signal lines of different columns of sample-and-hold signals.

2. The imaging device according to claim 1, further comprising: an AD conversion unit that performs AD conversion for each column of the signal transmitted via the signal line; as well as The activation control unit activates one of the AD conversion units of each column connected via the connection switch.

3. The imaging device according to claim 2, wherein: The AD conversion unit comprises: a comparator that compares the potential of the signal line with a ramp signal; and A counter performs a counting operation based on the comparison result from the comparator.

4. The imaging device according to claim 2, wherein: The activation control unit controls the AD conversion unit separately for a column to be activated and a column to be deactivated.

5. The imaging device according to claim 3, further comprising: a first DC cut-off capacitor connected to a first input terminal of the comparator; as well as A second DC cut-off capacitor is connected to the second input terminal of the comparator.

6. The imaging device according to claim 5, further comprising: A changeover switch switches a connection destination of a second capacitance electrode of the first DC cut capacitor having a first capacitance electrode connected to the signal line between the first input terminal of the comparator and ground.

7. The imaging device according to claim 6, wherein: The activation control unit controls the change-over switches for the columns to be activated and the columns to be deactivated, respectively.

8. The imaging device according to claim 2, further comprising: An amplifier amplifies the signal transmitted via the signal line for each column and inputs the amplified signal to the AD conversion unit.

9. The imaging device according to claim 8, wherein: The activation control unit controls the amplifiers separately for the columns to be activated and the columns to be deactivated.

10. The imaging device according to claim 1, wherein: The sample-and-hold switch is a transistor provided for each signal line.

11. The imaging device according to claim 10, further comprising: A driver drives the transistor from both sides in the row direction.

12. The imaging device according to claim 1, further comprising: A signal line reset transistor for resetting the potential of the signal line; as well as The signal line reset level generating unit generates a reset level of the potential of the signal line.

13. The imaging device according to claim 4, wherein: The signal line reset level generating unit includes a diode-connected transistor.

14. The imaging device according to claim 1, wherein: The capacitance used to sample and hold the signal is the parasitic capacitance of the signal line.

15. The imaging device according to claim 1, wherein: The connection switch is connected in series with the capacitor of each column for sampling and holding the signal.

16. The imaging device according to claim 1, wherein: The connection switch is connected in parallel with the capacitor of each column for sampling and holding the signal.

17. The imaging device according to claim 1, further comprising: a constant current transistor capable of being electrically connected to the signal line and transmitting a constant current based on a source follower formed between the signal line and the pixel, wherein The constant current transistor is turned on during constant current readout, and The constant current transistor is turned off during the capacitive load readout period.

18. The imaging device according to claim 1, wherein: The pixels include: Photodiode; a transfer transistor that transfers charge stored in the photodiode to a floating diffusion; a reset transistor to reset the floating diffusion; an amplifying transistor that outputs a signal corresponding to the potential of the floating diffusion; and The selection transistor is connected between the amplification transistor and the signal line.

19. The imaging device according to claim 18, wherein: The sample-and-hold switch is the select transistor.

20. The imaging device according to claim 18, further comprising: Merge transistors to connect floating diffusions from different rows.

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