Light-emitting pixel structure system for improving light-emitting efficiency and manufacturing method of light-emitting pixel structure system

Abstract

The invention discloses a pixel structure for improving luminous efficiency. The pixel structure includes, from top to bottom, a pixel lens, a negative electrode pad layer, a conductive semiconductor layer, a quantum well, an isolation layer, a positive electrode layer, a dielectric layer, and an integrated circuit (IC) chip layer, and the quantum well is disposed within the conductive semiconductor layer. A three-sided covering reflective layer is disposed between a lower surface of the conductive semiconductor layer and a top of the positive electrode layer. The conductive semiconductor layer includes an inverted trapezoidal semiconductor portion and a continuous planarization layer. The inclined planes on the two sides of the inverted trapezoidal semiconductor part converge in the direction of the pixel lens and reflect light emitted by the quantum well. And the negative electrode pad layer is disposed on the continuous planarization layer.

Description

Technical Field

[0001] The present invention generally relates to the field of display technology, and more particularly to a light-emitting pixel structure and a manufacturing process thereof for reducing light blocking effect and improving light reflection efficiency. Background Art

[0002] Display technology is becoming increasingly important in today's commercial electronic devices. These display panels are widely used in fixed large screens such as liquid crystal display televisions (LCD TVs) and organic light emitting diode TVs (OLED TVs), as well as portable electronic devices such as laptops, smartphones, tablets and wearable electronic devices.

[0003] Light-emitting diode (LED) chips usually include organic light-emitting diode (OLED) chips, mini light-emitting diode (submillimeter light-emitting diode) chips or micro LED (micrometer light-emitting diode) chips. LED is widely used in the field of lighting. As LED display screens gradually penetrate into the high-end market, the requirements for the luminous efficiency of LED display screen equipment are getting higher and higher.

[0004] Pixels are made up of small squares of an image, and the small squares have a clear position and are assigned a color value, and the color and position of the small squares determine the appearance of the image. Pixels can be considered as indivisible units or elements of the entire image. Indivisible means that pixels cannot be further cut into smaller units or elements that exist in a single color unit. Each dot matrix image contains a certain number of pixels, which determine the size of the image presented on the screen.

[0005] Some embodiments disclose a light emitting diode unit, which includes a plurality of pixels for a display and a display device having the light emitting diode unit. The embodiment discloses (1) a plurality of pixels, wherein each pixel includes a first light emitting unit, a second light emitting unit and a third light emitting unit, and each unit includes a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, respectively; (2) the third light emitting unit is electrically connected to the first light emitting unit, so that the first light emitting unit is independently driven by the third light emitting unit; (3) a second wavelength converter, which converts the wavelength of light emitted from the second light emitting unit; and (4) a third wavelength converter, which converts the wavelength of light emitted from the third light emitting unit, wherein the third wavelength converter converts the wavelength of light to a longer wavelength than the second wavelength converter, the second light emitting unit has a light emitting area larger than the light emitting area of ​​the first light emitting unit, and the third light emitting unit has a light emitting area larger than the light emitting area of ​​the second light emitting unit. Due to the use of a light emitting diode unit including a plurality of pixels, the light emitting unit can be easily attached to a substrate.

[0006] However, the pixel structure in these embodiments has the following technical problems. Since the light emitted by the light-emitting unit is emitted to the periphery of the light-emitting unit, the light emitted by the display device or the near-eye augmented reality (AR) device may be limited to the light emitted by the light-emitting unit toward the lens. At the same time, light blocking may exist between the light-emitting unit and the lens, so that the brightness of the light emitted by the light-emitting unit received by the lens accounts for only 50% or less of the light emitted by the light-emitting unit in the pixel. Therefore, the working efficiency of the light-emitting unit is low and needs to be improved.

[0007] Thus, it is desirable to provide a light emitting structure for a display panel that solves the above-mentioned disadvantages and the like. Summary of the invention

[0008] There is a need for improved display device designs that improve and help address the problems and shortcomings of conventional display systems as described above. In particular, there is a need for display panels with improved light efficiency and better images.

[0009] The invention relates to the technical field of display, and discloses a pixel structure and a manufacturing process of the pixel structure for reducing light blocking effect and improving light reflection efficiency, thereby solving the technical problem of low light conversion efficiency of the current pixel light emitting unit.

[0010] The present invention includes, but is not limited to, the following exemplary embodiments.

[0011] Some exemplary embodiments of the present invention include a micro-light-emitting pixel structure. The micro-light-emitting pixel structure includes: a conductive semiconductor layer, wherein the conductive semiconductor layer has an inverted trapezoidal shape and includes a continuous planarization layer at the top of the inverted trapezoidal shape; a quantum well layer for emitting light, wherein the quantum well layer is within the conductive semiconductor layer; a three-sided covered reflective layer below the conductive semiconductor layer, wherein the material of the three-sided covered reflective layer is Ag; a negative electrode pad layer, which is electrically connected to the conductive semiconductor layer; a positive electrode layer, which is electrically connected to the conductive semiconductor layer; and an integrated circuit (IC) chip layer, which is electrically connected to the positive electrode layer.

[0012] Some exemplary embodiments of the present invention include a micro-light-emitting pixel structure. The micro-light-emitting pixel structure includes: a conductive semiconductor layer, wherein the conductive semiconductor layer has an inverted trapezoidal shape; a quantum well layer for emitting light, wherein the quantum well layer is within the conductive semiconductor layer; a three-sided covered reflective layer below the conductive semiconductor layer, wherein the material of the three-sided covered reflective layer is Ag; an isolation layer between the conductive semiconductor layer and the three-sided covered reflective layer, wherein the material of the isolation layer is Al2O3 or Si3N4; a negative electrode pad layer, which is electrically connected to the conductive semiconductor layer; a positive electrode layer, which is electrically connected to the conductive semiconductor layer; and an integrated circuit (IC) chip layer, which is electrically connected to the positive electrode layer.

[0013] In some exemplary embodiments or any combination of exemplary embodiments of the micro-luminescent pixel structure, the three-sided covered reflective layer includes: a middle conductive portion, which is in contact with the positive electrode layer and the conductive semiconductor layer; two side reflective portions, which are in contact with the isolation layer; and two edge reflective portions, which are in contact with the isolation layer; wherein the three-surface covered reflective layer forms an inverted trapezoidal shape around the quantum well layer.

[0014] In some exemplary embodiments or any combination of exemplary embodiments of the micro-light-emitting pixel structure, the quantum well layer is enclosed in an inverted trapezoidal shape of the conductive semiconductor layer so that light from the quantum well is focused toward the top of the light-emitting pixel structure.

[0015] In some exemplary embodiments or any combination of exemplary embodiments of the micro light emitting pixel structure, the isolation layer forms an inverted trapezoidal shape around the quantum well layer.

[0016] In some exemplary embodiments or any combination of exemplary embodiments of the micro light emitting pixel structure, the conductive semiconductor layer includes a continuous planarization layer located on top of the inverted trapezoidal shape.

[0017] In some exemplary embodiments or any combination of exemplary embodiments of the micro light emitting pixel structure, the continuous planarization layer covers the entire surface of the micro light emitting pixel structure and extends to adjacent micro light emitting pixel structures.

[0018] In some exemplary embodiments or any combination of exemplary embodiments of the micro-light-emitting pixel structure, the micro-light-emitting pixel structure further includes an isolation layer, which is located between the conductive semiconductor layer and the three-sided covering reflective layer, wherein the material of the isolation layer is Al 2O 3 or Si 3N 4 .

[0019] In some exemplary embodiments or any combination of exemplary embodiments of a micro-luminescent pixel structure, a negative electrode pad layer is formed above a continuous planarization layer and is hollowed out in an area above the quantum well so that light emitted by the quantum well is not blocked by the negative electrode pad layer.

[0020] In some exemplary embodiments or any combination of exemplary embodiments of the micro-light-emitting pixel structure, the micro-light-emitting pixel structure further includes a dielectric layer located between the three-sided covering reflective layer and the IC chip layer, wherein the dielectric layer includes a top dielectric layer made of Si3N4 covering the surface of the three-sided covering reflective layer and a bottom dielectric layer made of SiO2.

[0021] In some exemplary embodiments or any combination of exemplary embodiments of the micro-luminescent pixel structure, the positive electrode layer includes an upper epitaxial positive electrode and a bottom chip positive electrode, the upper epitaxial positive electrode is located in the dielectric layer, and the bottom chip positive electrode is located in the IC chip layer.

[0022] In some exemplary embodiments or any combination of exemplary embodiments of the micro light emitting pixel structure, the IC chip layer includes an upper chip dielectric layer and a bottom chip electrical board.

[0023] In some exemplary embodiments or any combination of exemplary embodiments of a micro-light emitting pixel structure, an IC chip layer including a bottom chip positive electrode contacts a dielectric layer including an upper epitaxial positive electrode.

[0024] In some exemplary embodiments or any combination of exemplary embodiments of the micro light emitting pixel structure, the micro light emitting pixel structure further includes a pixel lens located above the conductive semiconductor layer.

[0025] Some exemplary embodiments of the present invention include a method for manufacturing a micro-light-emitting pixel structure, the method comprising: providing an epitaxial wafer including a conductive semiconductor layer and a quantum well layer for light emission, wherein the quantum well layer is within the conductive semiconductor layer; etching the conductive semiconductor layer having the quantum well layer into an inverted trapezoidal shape; forming an isolation layer on the bottom surface of the conductive semiconductor layer, wherein the material of the isolation layer is Al2O3 or Si3N4; forming a three-sided covering reflective layer on the bottom surface of the isolation layer, wherein the material of the three-sided covering reflective layer is Ag; forming a first positive electrode layer on the bottom surface of the middle conductive portion of the three-sided covering reflective layer; bonding an integrated circuit (IC) chip layer to the first positive electrode layer; and forming a negative electrode pad layer on the upper surface of the conductive semiconductor layer.

[0026] In some exemplary embodiments or any combination of exemplary embodiments of the method for manufacturing a micro-luminescent pixel structure, the method further includes forming a dielectric layer between the three-sided covering reflective layer and the IC chip layer after forming the three-sided covering reflective layer and before forming the first positive electrode layer, wherein the dielectric layer includes a top dielectric layer made of Si3N4 covering the surface of the three-sided covering reflective layer, and a bottom dielectric layer made of SiO2.

[0027] In some exemplary embodiments or any combination of exemplary embodiments of the method of manufacturing a micro light emitting pixel structure, etching the conductive semiconductor layer having the quantum well layer further includes: leaving a continuous planarization layer on top of the inverted trapezoidal shape in the conductive semiconductor layer.

[0028] In some exemplary embodiments or any combination of exemplary embodiments of a method of manufacturing a micro-light-emitting pixel structure, the epitaxial wafer includes a sapphire substrate layer, and after bonding the IC chip layer and before forming the negative electrode pad layer, the method further includes removing the sapphire substrate layer.

[0029] In some exemplary embodiments or any combination of exemplary embodiments of the method for manufacturing a micro-light-emitting pixel structure, forming an isolation layer includes: etching the isolation layer to form an opening for depositing a middle conductive portion covered with a reflective layer on three sides on a bottom surface of the conductive semiconductor layer through the opening.

[0030] In some exemplary embodiments or any combination of exemplary embodiments of the method of manufacturing a micro light emitting pixel structure, forming the dielectric layer includes etching the dielectric layer to form an opening for depositing the first positive electrode layer.

[0031] In some exemplary embodiments or any combination of exemplary embodiments of a method for manufacturing a micro-luminescent pixel structure, bonding includes aligning and bonding an IC chip layer embedded with a second positive electrode layer to a bottom surface of a dielectric layer embedded with a first positive electrode layer, wherein the first positive electrode layer is an upper epitaxial positive electrode and the second positive electrode layer is a bottom chip positive electrode.

[0032] In some exemplary embodiments or any combination of exemplary embodiments of a method of manufacturing a micro-light-emitting pixel structure, forming a negative electrode pad layer includes: using a lift-off process to form a hollow shape in the negative electrode pad layer in an area above the quantum well so that light emitted from the quantum well is not blocked by the negative electrode pad layer.

[0033] In some exemplary embodiments or any combination of exemplary embodiments of a method of manufacturing a micro-light-emitting pixel structure, the method further includes forming a pixel lens over the conductive semiconductor layer after forming the negative electrode pad layer and aligning it with the hollow shape in the negative electrode pad.

[0034] In order to solve the problem of low light efficiency conversion in traditional light-emitting units, the present invention achieves the purpose of improving light efficiency through the design of the interior of the pixel structure.

[0035] In some exemplary embodiments, the present invention provides the following technical aspects:

[0036] In some embodiments, a pixel structure for reducing light blocking effects and improving light reflection efficiency includes, from top to bottom or from outside to inside, a pixel lens, a negative electrode pad layer, a conductive semiconductor layer, a quantum well, an isolation layer, a positive electrode layer, a dielectric layer, and an integrated circuit (IC) chip layer, wherein the quantum well is arranged in the conductive semiconductor layer.

[0037] In some embodiments, the three-sided covering reflective layer is arranged between the lower surface of the conductive semiconductor layer and the top of the positive electrode layer, and the three-sided covering reflective layer respectively covers and conforms to the shape of the bottom surface, side surface and bottom surface of the upper surface of the conductive semiconductor layer.

[0038] In some embodiments, the conductive semiconductor layer includes an inverted trapezoidal semiconductor portion and a continuous planarization layer. The quantum well is located inside the inverted trapezoidal semiconductor portion. The inverted trapezoidal semiconductor portion is divided into a P-GaN portion at the bottom and an N-GaN portion at the top in the horizontal direction of the quantum well. The inclined surfaces on both sides of the inverted trapezoidal semiconductor portion (the inclined sides of the inverted trapezoid) converge and reflect the light emitted by the quantum well in the direction of the pixel lens. The continuous planarization layer between multiple pixels is configured continuously as a whole. The top surface of the continuous planarization layer is provided with a negative electrode pad layer, so that the negative electrode pad layer and the conductive semiconductor layer are not located on the same plane layer. The positive electrode layer is arranged in the dielectric layer, and the dielectric layer and the IC chip layer are in alignment connection.

[0039] According to the above structure disclosed in this article, the light emitted by the quantum well is reflected by the three-sided covering reflective layer, and the light from the side of the quantum well facing away from the pixel lens surface is reflected back to the pixel lens, so that the utilization efficiency of the light emitted by the quantum well is greatly improved. At the same time, by using the inclined surface of the inverted trapezoidal semiconductor part to reflect the light emitted by the quantum well to both sides of the pixel lens, the light emitted by the quantum well to both sides of the pixel lens can also be gathered and collected in the direction toward the pixel lens, thereby further improving the utilization efficiency of the light emitted by the quantum well. In addition, using the continuous planarization layer structure design, the negative electrode pad layer can be arranged at any position of the continuous planarization layer. In some embodiments, the negative electrode pad layer can be arranged at a position where the quantum well is not blocked to emit light to the pixel lens, so that the negative electrode pad layer does not block the light, and further improves the efficiency of the pixel lens in collecting light.

[0040] In some embodiments, the three-sided covered reflective layer includes a conductive portion, a side reflective portion, and an edge reflective portion. The upper surface of the conductive portion is attached to the conductive semiconductor layer, and the lower surface of the conductive portion is attached to the positive electrode layer. The upper surface of the side reflective portion and the upper surface of the edge reflective portion are both attached to the isolation layer, and the lower surface of the side reflective portion is attached to the dielectric layer.

[0041] In some embodiments, the conductive portion has a main reflection effect, the side reflection portion has a residual light reflection effect, and the isolation layer is a transparent layer.

[0042] In some embodiments, the three-side covering reflective layer is or includes an Ag layer formed by electron beam evaporation or thermal evaporation.

[0043] In some embodiments, a good reflection effect is achieved by using an Ag layer, and the reflectivity of Ag is the highest among reflective materials.

[0044] In some embodiments, the isolation layer is configured as Al 2 O 3 or Si 3 N 4 .

[0045] In some embodiments, the negative electrode pad layer is hollow, a pixel lens is disposed in the hollow portion of the negative electrode pad layer, and a main portion of the negative electrode pad layer is arranged at an upper surface position of the continuous planarization layer rather than a position that blocks light from being directed toward the pixel lens.

[0046] According to the structure disclosed herein, light from the quantum well toward the lens direction of the pixel lens is not blocked by positioning the negative electrode pad layer.

[0047] In some embodiments, the dielectric layer includes a Si 3N 4 layer structure at the top and a SiO 2 layer structure at the bottom, and the Si 3N 4 layer structure covers and attaches the surface of the three-sided covering reflective layer. The positive electrode includes an epitaxial positive electrode and a chip positive electrode, and the epitaxial positive electrode is continuously arranged in the Si 3N 4 layer structure and the SiO 2 layer structure in a penetrating configuration, and the chip positive electrode is arranged in the IC chip layer.

[0048] In some embodiments, the IC chip layer includes a chip dielectric layer located at the top and a chip board located at the bottom, and the chip positive electrode is arranged in the chip dielectric layer in a penetrating configuration, the top of the chip positive electrode is connected to the epitaxial positive electrode by alignment bonding, and the bottom of the chip positive electrode is electrically connected to the chip board.

[0049] Due to the fact that the Ag three-sided covered reflective layer is arranged in the pixel structure and the pixel structure is manufactured using a conventional pixel process, Ag layer loss may occur, which further causes an internal short circuit in the pixel structure. In some embodiments, a chip dielectric layer and a dielectric layer alignment bonding connection structure and process are used to achieve non-short circuit installation of the IC chip layer.

[0050] In some embodiments, the positive electrode layer is configured as a Cu pillar.

[0051] In some exemplary embodiments, the following technical aspects are disclosed herein:

[0052] In some embodiments, based on the internal structure of a pixel, a pixel structure manufacturing process for reducing light blocking effect and improving light reflection efficiency is provided. The pixel structure manufacturing process includes the following process steps:

[0053] Step 1: Select an epitaxial wafer. In some embodiments, the epitaxial wafer includes a sapphire layer on the top surface and a conductive semiconductor layer on the bottom, with a quantum well in the middle of the conductive semiconductor layer;

[0054] Step 2: semiconductor etching;

[0055] Sub-step 2-1 of step 2: etching the conductive semiconductor layer inside the epitaxial wafer to form an inverted trapezoidal semiconductor portion having an inverted trapezoidal shape, wherein the quantum well is located inside the inverted trapezoidal semiconductor portion;

[0056] Step 3: Isolation layer deposition and patterned etching;

[0057] Sub-step 3-1 of step 3: forming an isolation layer on the bottom surface of the conductive semiconductor layer;

[0058] Sub-step 3-2 of step 3: etching the isolation layer after the isolation layer is deposited, and etching to form an opening at the bottom of the inverted trapezoidal semiconductor portion for depositing a conductive portion covered with a reflective layer on three sides;

[0059] Step 4: Deposition and patterned etching of the three-sided covering reflective layer;

[0060] Sub-step 4-1 of step 4: forming a three-sided covering reflective layer by deposition on the bottom surface of the isolation layer;

[0061] Sub-step 4-2 of step 4: trimming to form a shape covered with a reflective layer on three sides;

[0062] Step 5: Dielectric layer deposition and patterned etching;

[0063] Sub-step 5-1 of step 5: forming a dielectric layer by deposition on the lower surface covered with the reflective layer on three sides;

[0064] Sub-step 5-2 of step 5: etching and trimming to form a shape of the dielectric layer;

[0065] Step 6: positive electrode deposition and polishing;

[0066] Sub-step 6-1 of step 6: depositing and forming a positive electrode layer;

[0067] Sub-step 6-2 of step 6: performing a polishing operation on the positive electrode layer;

[0068] Step 7: Align and bond;

[0069] Sub-step 7-1 of step 7: connecting the IC chip layer to the bottom surface of the dielectric layer using an alignment bonding process;

[0070] Step 8: Remove the sapphire layer;

[0071] Step 9: Deposition and patterning of negative electrode pad layer;

[0072] Sub-step 9-1 of step 9: depositing and forming a negative electrode pad layer;

[0073] Sub-step 9-2 of step 9: patterning the negative electrode pad layer to form a hollow shape;

[0074] Step 10: Lens deposition and patterning;

[0075] Sub-step 10-1 of step 10: depositing a layer structure forming a pixel lens;

[0076] Sub-step 10 - 2 of step 10 : patterning the layer structure of the pixel lens to form a lens shape.

[0077] Through this technical solution, a novel pixel structure can be manufactured by using this technology.

[0078] In some embodiments, the epitaxial wafer in step 1 includes a sapphire layer, a conductive semiconductor layer, and a quantum well as an initial material for pixel structure process processing, wherein the conductive semiconductor layer includes a P-type material such as a P-GaN material layer at the bottom of the quantum well and an N-type material such as an N-GaN material layer at the top of the quantum well.

[0079] In some embodiments, the process of etching the conductive semiconductor layer in the epitaxial wafer in step 2 is an inductively coupled plasma (ICP) semiconductor etching process, and an inverted trapezoidal or bowl-shaped pattern is formed by etching.

[0080] In some embodiments, the process of forming the isolation layer in step 3 is an atomic layer deposition (ALD) process, and the etching process of the deposited isolation layer is performed by an ICP etching process.

[0081] In some embodiments, the process of forming the three-sided covering reflective layer in step 4 is a physical vapor deposition (PVD) process of electron beam evaporation or thermal evaporation, and the process of etching the three-sided covering reflective layer implements a lift-off process to etch and trim to form a shape.

[0082] In some embodiments, the process of forming the dielectric layer in step 5 is performed by a chemical vapor deposition (CVD) process, and etching and trimming are performed by an ICP semiconductor etching process to form the shape of the dielectric layer.

[0083] In some embodiments, in step 6, the positive electrode layer is formed by performing an electroplating deposition process, and the positive electrode layer is polished by a chemical mechanical polishing (CMP) process.

[0084] In some embodiments, in step 8, the sapphire layer on the upper surface of the epitaxial wafer is stripped by a laser lift-off process.

[0085] In some embodiments, the negative electrode pad layer is formed by PVD deposition of a physical vapor deposition process of electron beam evaporation or thermal evaporation in step 9, and the negative electrode pad layer is peeled off by performing a peeling process to form the hollow shape.

[0086] In some embodiments, the process in step 10 is a CVD deposition process to form a layer structure of a pixel lens, and an ICP semiconductor etching process is performed on the layer structure of the pixel lens to form a pixel lens having a lens shape.

[0087] In general, the system and method disclosed herein have the following advantages and improvements:

[0088] (1) The light emitted by the quantum well is reflected by the reflective layers covering three sides, and the light on the side of the quantum well facing away from the pixel lens is reflected back to the pixel lens, which greatly improves the utilization efficiency of the light emitted by the quantum well.

[0089] (2) By using the inclined surface of the inverted trapezoidal semiconductor portion to reflect the light emitted from the quantum well to both sides of the pixel lens, the light emitted from the quantum well to both sides of the pixel lens can also be gathered and collected in the direction toward the pixel lens, and the utilization efficiency of the light emitted by the quantum well is further improved.

[0090] (3) The negative electrode pad layer is arranged at any position of the continuous planarization layer by utilizing the continuous planarization layer structure design. Therefore, the position of the negative electrode pad layer can be arranged at a position where the quantum well is not blocked to emit light to the pixel lens, so that the negative electrode pad layer does not block the light and further improves the efficiency of the pixel lens in collecting light. At the same time, the negative electrode pad layer and the table (that is, the epitaxial wafer, which includes a conductive semiconductor layer, and the conductive semiconductor layer includes a quantum well as an intermediate layer) are not in the same plane layer, so it is not easy to short-circuit between the negative electrode pad layer and the three-sided covering reflective layer. The positioning of the negative electrode pad layer realizes the current diffusion from the top of the pixel structure to the table. The positioning of the negative electrode pad layer can further prevent interference between adjacent pixels.

[0091] (4) Since the three-sided covering reflective layer of Ag forms a three-sided covering pattern in the processing technology, when the three-sided covering reflective layer is connected to the IC chip layer, an alignment bonding process is implemented, and the epitaxial positive electrode and the chip positive electrode are aligned one by one, followed by bonding and connection.

[0092] (5) The continuous planarization layer between multiple pixels realizes a continuous design, which protects Ag and facilitates current diffusion.

[0093] (6) Provide an isolation layer of Al2O3 or Si3N4 material to isolate the three-sided covering reflective layer and the conductive semiconductor layer including the quantum well. Selecting Al2O3 as the isolation layer can prevent the diffusion of Ag because Al2O3 has fewer lattice defects than other traditional materials. Selecting Si3N4 as the isolation layer can prevent the diffusion of Ag because Si3N4 has fewer lattice defects than other traditional materials.

[0094] (7) A novel structural design was implemented to divide the dielectric layer into a top Si 3N 4 layer structure and a bottom SiO 2 layer structure, where the Si 3N 4 layer structure covers and is attached to the surface of the Ag reflective layer.

[0095] It should be noted that the various embodiments described above may be combined with any other embodiments described herein. The features and advantages described in the specification are not all-inclusive, and in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, the specification, and the claims. Furthermore, it should be noted that the language used in the specification is primarily selected for readability and instructional purposes, and may not be selected to describe or limit the subject matter of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0096] In order that the present invention may be understood in more detail, a more particular description may be made by reference to the features of various embodiments, some of which are illustrated in the accompanying drawings. However, the drawings illustrate only the relevant features of the present invention and are therefore not to be considered limiting, as the description may allow for other effective features.

[0097] For convenience, "upward" is used to refer to a substrate or circuit board away from the light emitting structure, "downward" means toward the substrate, and other directional terms such as top, bottom, above, below, under, under, etc. are also interpreted accordingly.

[0098] Figure 1 is an exemplary cross-sectional schematic diagram of the overall structure of the pixel structure according to some examples of the present embodiment.

[0099] Figure 2 is an exemplary top view schematic diagram of a pixel structure according to some examples of the present embodiment.

[0100] Figure 3 is an exemplary structural diagram of step 1 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0101] Figure 4 is an exemplary structural diagram of step 2 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0102] Figure 5 is an exemplary structural diagram of step 3 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0103] Figure 6 is an exemplary structural diagram of step 4 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0104] Figure 7 is an exemplary structural diagram of step 5 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0105] Figure 8 is an exemplary structural diagram of step 6 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0106] Fig. 9 is an exemplary structural diagram of step 7 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0107] Fig.10 is an exemplary structural diagram of step 8 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0108] Fig.11 is an exemplary structural diagram of step 9 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0109] Fig.12 is an exemplary structural diagram of step 10 in the pixel structure manufacturing process according to some examples of the present embodiment.

[0110] The accompanying drawings include the following component identifications: 1, pixel lens; 2, negative electrode pad layer; 3, conductive semiconductor layer; 3-1, inverted trapezoidal semiconductor part; 3-11, P-GaN part; 3-12, N-GaN part; 3-2, continuous planarization layer; 4, quantum well; 5, isolation layer; 6, positive electrode layer; 6-1, epitaxial positive electrode; 6-2, chip positive electrode; 7, dielectric layer; 7-1, Si 3N4 layer structure; 7-2, SiO2 layer structure; 8, IC chip layer; 8-1, dielectric layer of chip; 8-2, chip board; 9, three-sided covering reflection layer; 9-1, conductive part; 9-2, side reflection part; and 9-3, edge reflection part.

[0111] According to common practice, the various features shown in the drawings may not be drawn to scale. Therefore, the sizes of the various features may be arbitrarily expanded or reduced for clarity. In addition, some drawings may not depict all components of a given system, method, or device. Finally, throughout the specification and drawings, the same figure designations may be used to represent the same features. DETAILED DESCRIPTION

[0112] Numerous details are described herein to provide a thorough understanding of the example embodiments shown in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is limited only by the features and aspects specifically recited in the claims. In addition, exhaustive details of publicly known processes, components, and materials have not been described in order to avoid unnecessarily obscuring relevant aspects of the embodiments described herein.

[0113] Figure 1 is an exemplary cross-sectional schematic diagram of the overall structure of the pixel structure according to some examples of the present embodiment.

[0114] Figure 2is an exemplary top view schematic diagram of a pixel structure according to some examples of the present embodiment.

[0115] In some embodiments, Figure 1 and Figure 2 Pixel structures configured to reduce light blocking effects and improve reflection efficiency are shown in FIG. Pitch refers to the distance between the centers of adjacent pixels on a display panel. In some embodiments, the pitch may vary from about 40 microns to about 20 microns, to about 10 microns, and / or preferably to about 5 microns or less. Many efforts have been made to reduce the pitch. When determining the pitch specification, the area of ​​a single pixel is fixed.

[0116] The structure includes a pixel lens 1, a negative electrode pad layer 2, a conductive semiconductor layer 3, a quantum well 4, an isolation layer 5, a positive electrode layer 6, a dielectric layer 7 and an IC chip layer 8 from the outside (top) to the inside (bottom). And the quantum well 4 is arranged inside the conductive semiconductor layer 3. The conductive semiconductor layer 3 is made of GaN semiconductor material, and the positive electrode layer 6 is configured as a Cu column. The overall working principle is described as follows. The quantum well 4 is used as a light-emitting unit. The negative electrode pad layer 2 and the positive electrode layer 6 are grounded and connected to the electrical signal on the IC chip layer 8, respectively. And the electrical signal is transmitted inside the pixel through the negative electrode pad layer 2 and the positive electrode layer 6, thereby providing a driving signal for the quantum well 4 and controlling whether the quantum well 4 emits light. Therefore, the signal control instruction of the IC chip layer 8 enters the interior of the pixel structure through the positive electrode layer 6.

[0117] Compared with the traditional pixel structure, the present invention provides improved internal details of the pixel structure, so the processing technology for manufacturing the pixel structure is also different, the purpose is to improve the collection efficiency of the light emitted by the quantum well 4 in the pixel structure. In some embodiments, specifically, the three-sided covered reflective layer 9 is arranged between the lower surface of the conductive semiconductor layer 3 and the top of the positive electrode layer 6, wherein the three-sided covered reflective layer 9 includes a conductive portion 9-1, a side reflective portion 9-2 and an edge reflective portion 9-3. The upper surface of the conductive portion 9-1 is in contact with the conductive semiconductor layer 3, and the lower surface of the conductive portion 9-1 is in contact with the positive electrode layer 6. The upper surface of the side reflective portion 9-2 and the upper surface of the edge reflective portion 9-3 are both in contact with the isolation layer 5, and the lower surface of the side reflective portion 9-2 and the lower surface of the edge reflective portion 9-3 are both in contact with the dielectric layer 7. In some embodiments, as Figure 1As shown, the three-sided covered reflective layer 9 is symmetrical with the side reflective portion 9-2 and the edge reflective portion 9-3 on both sides of the three-sided covered reflective layer 9. In the present embodiment, the three-sided covered reflective layer 9 is or includes an Ag layer formed by electron beam evaporation or thermal evaporation, but other reflective material layers can also be used. Since the reflection effect of Ag is the best, Ag is used as the reflective layer material. However, since Ag is a material that is very easy to diffuse during etching, Ag is generally not used as a reflective layer in the internal structure of a pixel device. In the present invention, the reflective layer structure of Ag and its pixel processing technology are described herein.

[0118] In some embodiments, light emitted by the quantum well 4 is reflected by the three-sided covering reflective layer 9, and light from the side of the quantum well 4 facing away from the pixel lens 1 is reflected back to the pixel lens 1, so that the utilization efficiency of the light emitted by the quantum well 4 is greatly improved.

[0119] In some embodiments, the conductive semiconductor layer 3 includes two parts, an inverted trapezoidal semiconductor portion 3-1 and a continuous planarization layer 3-2. Since the quantum well 4 is located inside the inverted trapezoidal semiconductor portion 3-1, the inclined surface 3-1B of the inverted trapezoidal semiconductor portion 3-1 collects the light emitted by the quantum well 4 and reflects it in the direction of the pixel lens 1. Therefore, by using the inclined surface of the inverted trapezoidal semiconductor portion 3-1 to reflect the light emitted by the quantum well 4 on both sides of the pixel lens 1, the light emitted from both sides of the pixel lens 1 can also be converged and collected in the direction of the pixel lens 1, and the utilization efficiency of the light emitted by the quantum well 4 is further improved. The inverted trapezoidal semiconductor portion 3-1 is divided into a bottom portion 3-11 and a top portion 3-12 along the horizontal direction of the quantum well 4, and the quantum well 4 isolates the bottom portion 3-11 from the top portion 3-12. In some embodiments, the bottom portion 3-11 is a layer including a P-type conductive semiconductor material such as P-GaN, PI nGaP, and the top portion 3-12 is a layer including an N-type conductive semiconductor material such as N-GaN, NI nGaP. In some embodiments, a transparent thin conductive film indium tin oxide (ITO) film is deposited on top of the conductive semiconductor layer 3. In some other embodiments, the positions of the P-type and N-type materials can be switched, and the positions of the positive electrode layer and the negative electrode layer can be switched.

[0120] Furthermore, in some embodiments, the negative electrode pad layer 2 is configured as follows Figure 1 and Figure 2The hollow shape shown. The hollow portion of the negative electrode pad layer 2 is arranged and aligned with the pixel lens 1, and the main portion of the negative electrode pad layer 2 is arranged at the upper surface position of the continuous planarization layer 3-2, rather than at a position that blocks light from heading toward the pixel lens 1. The main portion of the negative electrode pad layer 2 protrudes from the upper surface position of the continuous planarization layer 3-2. Therefore, through the design of the continuous planarization layer 3-2, the negative electrode pad layer 2 can be arranged at a position where the quantum well 4 emits light to the pixel lens 1, so that the negative electrode pad layer 2 does not block light, and the efficiency of the pixel lens 1 in collecting light is further improved. In some embodiments, as Figure 1 As shown, the mesa is formed by an epitaxial wafer, which is (or includes) a conductive semiconductor layer 3 with a quantum well 4 in the middle. The mesa is a light-emitting PN junction. At the same time, the negative electrode pad layer and the mesa are not in a plane layer, making it unlikely that a short circuit between the negative electrode pad layer and the three-sided covering reflective layer 9 will occur.

[0121] In some exemplary embodiments, the isolation layer 5 between the mesa and the three-sided covering reflective layer 9 and the dielectric layer 7 is configured as an Al 2 O 3 or Si 3 N 4 material layer manufactured by deposition and etching.

[0122] Since the Ag three-sided covering reflective layer 9 is arranged in the pixel structure, when the pixel structure is manufactured using the traditional pixel manufacturing process, the Ag layer will be lost, which will further cause the internal short circuit of the pixel structure. In some embodiments, in the present invention, the dielectric layer 7 includes a double-layer structure of a Si 3N4 layer structure 7-1 at the top and a SiO2 layer structure 7-2 at the bottom, and the Si 3N4 layer structure 7-1 covers and contacts the surface of the three-sided covering reflective layer 9. The positive electrode layer 6 includes an epitaxial positive electrode 6-1 and a chip positive electrode 6-2, and the epitaxial positive electrode 6-1 is continuously arranged in the Si 3N4 layer structure 7-1 and the SiO2 layer structure 7-2, and the chip positive electrode 6-2 is arranged in the IC chip layer 8. At the same time, the IC chip layer 8 includes a top chip dielectric layer 8-1 and a bottom chip board 8-2. When the chip positive electrode 6-2 penetrates the chip dielectric layer 8-1, the top of the chip positive electrode 6-2 is connected to the epitaxial positive electrode 6-1 by bonding according to position alignment, and the bottom of the chip positive electrode 6-2 is electrically connected to the chip electrical board 8-2. The two electrodes, the epitaxial positive electrode 6-1 and the chip positive electrode 6-2, are located on two wafers before bonding and form a bond after bonding. The positive electrode layer 6 is configured as a Cu column. In some embodiments, according to the above-mentioned structural arrangement and connection mode, the manufacture of the pixel structure can be realized, that is, the reflective layer forms a three-sided covering pattern in the manufacturing process, and then is connected using an alignment bonding process in a subsequent stage.

[0123] According to the structural design inside the pixel described above, this embodiment provides a pixel structure manufacturing process for reducing light blocking effect and improving light reflection efficiency. The process includes the following processing steps:

[0124] Step 1: Select epitaxial wafer. Figure 3 FIG. 1 is an exemplary structural diagram of step 1 in the pixel structure manufacturing process of some embodiments of the present embodiment. Figure 3 , an epitaxial wafer including a sapphire layer 10, a conductive semiconductor layer 3 and a quantum well 4' is selected as an initial material through a pixel structure manufacturing process. In some embodiments, the conductive semiconductor layer 3' includes a P-GaN material layer at the bottom of the quantum well 4' and an N-GaN material layer at the top of the quantum well 4'.

[0125] Step 2: Semiconductor etching. Figure 4 FIG. 2 is an exemplary structural diagram of step 2 in the pixel structure manufacturing process according to some embodiments of the present embodiment. Figure 4 , using ICP semiconductor etching process to etch inside the epitaxial wafer Figure 3 The conductive semiconductor layer 3' in the inverted trapezoidal shape is etched to form an inverted trapezoidal semiconductor portion 3-1 and a continuous planarization layer 3-2. And the etched quantum well 4 is located inside the inverted trapezoidal semiconductor portion 3-1. The inverted trapezoidal semiconductor portion 3-1 is etched to form a P-GaN portion 3-11 at the bottom and an N-GaN portion 3-12 at the top in the horizontal direction of the quantum well 4.

[0126] Step 3: Isolation layer deposition and patterned etching. Figure 5 FIG. 1 is an exemplary structural diagram of step 3 in the pixel structure manufacturing process according to some embodiments of the present embodiment. Figure 5 The method comprises two sub-steps: (A) depositing an ALD layer on the bottom surface of the conductive semiconductor layer 3 by a deposition process to form an isolation layer 5 (the original shape of the isolation layer 5 after deposition is not shown in FIG. 1 ); Figure 5 ), wherein the isolation layer 5 is deposited by using Al 2 O 3 or Si 3 N 4 material; and (B) etching the deposited isolation layer 5 to form a Figure 5 The isolation layer 5 with the opening shown is formed, and the bottom of the inverted trapezoidal semiconductor portion 3-1 is etched by using an ICP etching process to form an opening for depositing a conductive portion 9-1 covered with a reflective layer 9 on three sides (in Figure 5 not fully shown).

[0127] Step 4: Deposition and patterning of the three-sided covering reflective layer. Figure 6 FIG. 4 is an exemplary structural diagram of step 4 in the pixel structure manufacturing process according to some embodiments of the present embodiment. Figure 6The method comprises two sub-steps: (A) forming a three-sided covering reflective layer 9 on the bottom surface of the isolation layer 5 by using an electron beam evaporation or thermal evaporation PVD process (the original shape of the reflective layer 9 after deposition is not in FIG. 1 ); Figure 6 (B) The three-side covering reflective layer 9 is etched and trimmed into shape by using a lift-off process.

[0128] Step 5: Dielectric layer deposition and patterned etching. Figure 7 FIG. 5 is an exemplary structural diagram of step 5 in the pixel structure manufacturing process according to some embodiments of the present embodiment. Figure 7 The method comprises two sub-steps: (A) forming a dielectric layer 7 on the lower surface of the three-sided covering reflective layer 9 by using a CVD deposition process (the original shape of the deposited dielectric layer 7 is not in FIG. Figure 7 ), wherein the dielectric layer 7 is divided into a double-layer structure of a top Si 3N 4 layer structure 7-1 and a bottom SiO 2 layer structure 7-2, as shown in FIG. Figure 1 and (B) etching and trimming the dielectric layer 7 into a shape to leave space for the positive electrode layer 6 by using an I CP semiconductor etching process.

[0129] Step 6: Positive electrode deposition and polishing. Figure 8 FIG. 6 is an exemplary structural diagram of step 6 in the pixel structure manufacturing process according to some embodiments of the present embodiment. Figure 8 The method includes two sub-steps: (A) depositing the positive electrode layer 6 by using an electroplating process deposition method, that is, depositing to form an epitaxial positive electrode 6-1; and (B) performing a polishing operation on the epitaxial positive electrode 6-1 by using a CMP polishing process.

[0130] Step 7: Align and bond. Fig. 9 FIG. 1 is an exemplary structural diagram of step 7 in the pixel structure manufacturing process according to some embodiments of the present embodiment. Fig. 9 , the bottom surface of the dielectric layer 7 is connected to the IC chip layer 8 by using an alignment bonding process, wherein the epitaxial positive electrode 6-1 and the chip positive electrode 6-2 are aligned and bonded to each other. Alignment bonding is usually performed between wafers having patterns on each surface. In some embodiments, the sapphire layer 10 and the IC chip layer 8 both have patterned electrodes (copper) and SiO2 on their surfaces. In order to achieve alignment bonding between them, the electrodes from the two wafers are well aligned face to face. Then, the two wafers are contacted and an initial bond is formed. Bonding is completed by the following annealing process, which enhances the bonding strength of the contact between copper and copper and SiO2 and SiO2.

[0131] Step 8: Remove the sapphire layer 10. Fig.10FIG. 8 is an exemplary structural diagram of step 8 in the pixel structure manufacturing process according to some embodiments of the present embodiment. Fig.10 , the sapphire layer 10 on the upper surface of the epitaxial wafer is peeled off by a laser lift-off process.

[0132] Step 9: Negative electrode pad layer deposition and patterning. Fig.11 FIG. 1 is an exemplary structural diagram of step 9 in the pixel structure manufacturing process according to some embodiments of the present embodiment. Fig.11 The method includes two sub-steps: (A) using a PVD process for electron beam evaporation or thermal evaporation to form a negative electrode pad layer 2 (the original shape of the negative electrode pad layer 2 after PVD is not in Fig.11 and (B) peeling off the negative electrode pad layer 2 by using a lift-off process to form a hollow shape.

[0133] Step 10: Lens deposition and patterning. Fig.12 FIG. 1 is an exemplary structural diagram of step 10 in the pixel structure manufacturing process according to some embodiments of the present embodiment. Fig.12 The method comprises two sub-steps: (A) forming a layer structure of the pixel lens 1 using a CVD deposition process (the original shape of the pixel lens 1 layer after deposition is not in the Fig.12 (B) etching the layer structure of pixel lens 1 using an ICP semiconductor etching process to form a lens-shaped pixel lens 1. In another example, lens 1 is formed by self-assembly through a CVD deposition process by directly forming a lens shape on the underlying structure without etching. In some examples, lens 1 is aligned with the hollow shape. For example, from a vertical viewing angle, the edge of lens 1 and the edge of the hollow shape are substantially aligned with each other.

[0134] The dimensions used in the manufacturing process follow the micro-LED product pixel structure design. In some embodiments, the following dimension designs are implemented, for example, the diameter of the circular portion of the pixel lens 1 is 3.2±0.8μm, the bottom thickness of the pixel lens 1 (e.g., excluding the focal lens portion) is 1±1μm, the top width of the inverted trapezoidal semiconductor portion 3-1 is 2.05μm to 3.8μm, the thickness of the continuous planarization layer 3-2 is 0.01μm to 0.2μm, the diameter of the epitaxial positive electrode 6-1 and the chip positive electrode 6-2 is 1μm, the height of the negative electrode pad layer 2 is 100nm to 1μm, the thickness of the isolation layer 5 is 10nm to 200nm, and other dimensions are designed according to the design requirements of the product.

[0135] In the manufacturing process of the pixel structure, the present invention relates to some special processing methods. The method includes the following processes: ICP semiconductor etching process, ALD process, PVD process, LI FT-OFF process, CVD process, electroplating deposition process, CMP polishing process, alignment bonding process and laser lift-off process. Those skilled in the art can understand these technical methods.

[0136] It should be understood by those skilled in the art that the pixel structure is not limited to the above structure, and may include more or less components than those shown, or some components may be combined, or different components may be used.

[0137] The above description is only an embodiment of the present invention, and the present invention is not limited thereto. Modifications, equivalent substitutions and improvements made without departing from the concept and principle of the present invention should fall within the protection scope of the present invention.

[0138] Further embodiments further include various subsets of the above embodiments, including combinations or other rearrangements in various other embodiments such as Figures 1 to 12 The embodiment shown.

[0139] Although the detailed description contains many details, these details should not be interpreted as limiting the scope of the invention, but should only be interpreted as illustrating different examples and aspects of the invention. It should be understood that the scope of the invention includes other embodiments not discussed in detail above. For example, the method described above can be applied to the integration of functional devices other than LEDs with OLEDs of control circuit systems other than pixel drivers. Examples of non-LED devices include vertical cavity surface emitting lasers (VCSELs), photodetectors, microelectromechanical systems (MEMS), silicon photonic devices, power electronics devices, and distributed feedback lasers (DFBs). Examples of other control circuit systems include current drivers, voltage drivers, transimpedance amplifiers, and logic circuits.

[0140] The foregoing description of the disclosed embodiments is provided to enable those skilled in the art to make or use the embodiments described herein and variations thereof. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the subject matter disclosed herein. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but should be given the widest scope consistent with the following claims and the principles and novel features disclosed herein.

[0141] Features of the present invention can be implemented in a computer program product such as a storage medium (media) or a computer readable storage medium (media), or implemented with the assistance of the computer program product, and the computer process product has instructions stored thereon / therein that can be used for a programmed processing system to perform any features presented herein. Storage media can include but are not limited to high-speed random access memory such as DRAM, SRAM, DDR RAM or other random access solid-state memory devices, and can include non-volatile memory such as one or more disk storage devices, optical disk storage devices, flash memory devices or other non-volatile solid-state memory devices. Memory optionally includes one or more storage devices located away from the CPU. Memory or non-volatile memory devices in the memory include non-transient computer readable storage media.

[0142] The features of the present invention stored on any machine-readable medium (media) may be incorporated into software and / or firmware for controlling the hardware of a processing system and enabling the processing system to interact with other mechanisms utilizing the results of the present invention. Such software or firmware may include, but is not limited to, application code, device drivers, operating systems, and execution environments / containers.

[0143] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various elements or steps, these elements or steps should not be limited by these terms. These terms are only used to distinguish one element or step from another element or step.

[0144] The terms used herein are only for describing specific embodiments and are not intended to limit the claims. As used in the description of the embodiments and the appended claims, the singular forms "one", "an" and "the" are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any and all possible combinations of one or more associated listed items. It should be further understood that when the terms "including" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof is not excluded.

[0145] The term "if" may be understood as "when the antecedent is true" or "when the antecedent is true" or "in response to determining that the antecedent is true" or "in accordance with a determination that the antecedent is true" or "in response to detecting that the antecedent is true", depending on the context. Similarly, the phrase "if it is determined that [the antecedent is true]" or "if [the antecedent is true]" or "when [the antecedent is true]" may be understood as "upon determining that the antecedent is true" or "in response to determining that the antecedent is true" or "in accordance with a determination that the antecedent is true" or "in response to detecting that the antecedent is true" or "in response to detecting that the antecedent is true", depending on the context.

[0146] For purposes of explanation, the above description has been described with reference to specific embodiments. However, the above illustrative discussions are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of operation and practical application, thereby enabling others skilled in the art to best utilize the invention and the various embodiments.

Claims

1. A micro-luminescent pixel structure, comprising: a conductive semiconductor layer, wherein the conductive semiconductor layer has an inverted trapezoidal shape and includes a continuous planarization layer located on top of the inverted trapezoidal shape; A quantum well layer for emitting light, wherein the quantum well layer is within the conductive semiconductor layer; A three-sided covered reflective layer, which is below the conductive semiconductor layer, wherein the material of the three-sided covered reflective layer is Ag; a negative electrode pad layer electrically connected to the conductive semiconductor layer; a positive electrode layer electrically connected to the conductive semiconductor layer; and An integrated circuit (IC) chip layer is electrically connected to the positive electrode layer.

2. A micro-luminescent pixel structure, comprising: a conductive semiconductor layer, wherein the conductive semiconductor layer has an inverted trapezoidal shape; A quantum well layer for emitting light, wherein the quantum well layer is within the conductive semiconductor layer; A three-sided covered reflective layer, which is below the conductive semiconductor layer, wherein the material of the three-sided covered reflective layer is Ag; An isolation layer, which is between the conductive semiconductor layer and the three-sided covering reflective layer, wherein the isolation layer is made of Al 2O 3 or Si 3N 4; a negative electrode pad layer electrically connected to the conductive semiconductor layer; a positive electrode layer electrically connected to the conductive semiconductor layer; and An integrated circuit (IC) chip layer is electrically connected to the positive electrode layer.

3. The micro-luminescent pixel structure according to claim 1 or 2, wherein the three-sided covering reflective layer comprises: an intermediate conductive portion, which contacts the positive electrode layer and the conductive semiconductor layer; two side reflective portions, which are in contact with the isolation layer; as well as two edge reflection parts, which are in contact with the isolation layer; The three-sided covering reflective layer surrounds the quantum well layer to form an inverted trapezoidal shape.

4. The micro-luminescent pixel structure according to claim 1 or 2, wherein the quantum well layer is enclosed in an inverted trapezoidal shape of the conductive semiconductor layer, so that light from the quantum well is focused toward the top of the luminescent pixel structure.

5. The micro-luminescent pixel structure according to claim 1 or 2, The isolation layer forms an inverted trapezoidal shape around the quantum well layer. 6 . The micro-light-emitting pixel structure according to claim 2 , wherein the conductive semiconductor layer comprises a continuous planarization layer located on top of the inverted trapezoidal shape. 7 . The micro-pixel structure according to claim 1 , wherein the continuous planarization layer covers the entire surface of the micro-pixel structure and extends to adjacent micro-pixel structures. 8 . The micro-light-emitting pixel structure according to claim 1 , further comprising an isolation layer located between the conductive semiconductor layer and the three-surface covering reflective layer, wherein the isolation layer is made of Al 2 O 3 or Si 3 N 4 .

9. The micro-luminescent pixel structure according to claim 1 or 6, characterized in that: The negative electrode pad layer is formed over the continuous planarization layer and is hollowed out in a region over the quantum well so that light emitted from the quantum well is not blocked by the negative electrode pad layer.

10. The micro-luminescent pixel structure according to claim 1 or 2 further comprises a dielectric layer located between the three-sided covering reflective layer and the IC chip layer, wherein the dielectric layer comprises a top dielectric layer made of Si 3N 4 covering the surface of the three-sided covering reflective layer and a bottom dielectric layer made of SiO 2 .

11. The micro-luminescent pixel structure according to claim 10, characterized in that: The positive electrode layer includes an upper epitaxial positive electrode and a bottom chip positive electrode, the upper epitaxial positive electrode is within the dielectric layer, and the bottom chip positive electrode is within the IC chip layer.

12. The micro-luminescent pixel structure according to claim 1 or 2, characterized in that: The IC chip layers include an upper chip dielectric layer and a bottom chip electrical board.

13. The micro-luminescent pixel structure according to claim 10, characterized in that: The IC chip layer including the bottom chip positive electrode contacts the dielectric layer including the upper epitaxial positive electrode.

14. The micro-light-emitting pixel structure according to claim 1 or 2, further comprising a pixel lens located above the conductive semiconductor layer.

15. A method for manufacturing a micro-luminescent pixel structure, comprising: Providing an epitaxial wafer including a conductive semiconductor layer and a quantum well layer for emitting light, wherein the quantum well layer is within the conductive semiconductor layer; Etching the conductive semiconductor layer having the quantum well layer into an inverted trapezoidal shape; forming an isolation layer on the bottom surface of the conductive semiconductor layer, wherein the isolation layer is made of Al2O3 or Si3N4; Forming a three-sided covering reflective layer on the bottom surface of the isolation layer, wherein the material of the three-sided covering reflective layer is Ag; forming a first positive electrode layer on the bottom surface of the middle conductive portion covered with reflective layers on three sides; bonding an integrated circuit (IC) chip layer to the first positive electrode layer; and A negative electrode pad layer is formed on an upper surface of the conductive semiconductor layer.

16. The method according to claim 15 further includes forming a dielectric layer between the three-sided covering reflective layer and the IC chip layer after forming the three-sided covering reflective layer and before forming the first positive electrode layer, wherein the dielectric layer includes a top dielectric layer made of Si 3N 4 covering the surface of the three-sided covering reflective layer and a bottom dielectric layer made of SiO 2.

17. The method according to claim 15, characterized in that Etching the conductive semiconductor layer having the quantum well layer further includes leaving a continuous planarization layer on top of the inverted trapezoidal shape in the conductive semiconductor layer.

18. The method according to claim 15, characterized in that The epitaxial wafer includes a sapphire substrate layer, and after bonding the IC chip layer and before forming the negative electrode pad layer, the method further includes removing the sapphire substrate layer.

19. The method according to claim 15, characterized in that Forming the isolation layer includes: etching the isolation layer to form an opening for depositing the middle conductive portion of the three-side covered reflective layer on the bottom surface of the conductive semiconductor layer through the opening.

20. The method according to claim 16, characterized in that Forming the dielectric layer includes etching the dielectric layer to form an opening for depositing the first positive electrode layer.

21. The method according to claim 16, characterized in that Bonding includes aligning and bonding the IC chip layer embedded with the second positive electrode layer to the bottom surface of the dielectric layer embedded with the first positive electrode layer, wherein the first positive electrode layer is an upper epitaxial positive electrode and the second positive electrode layer is a bottom chip positive electrode.

22. The method according to claim 15, characterized in that Forming the negative electrode pad layer includes forming a hollow shape in the negative electrode pad layer in a region above the quantum well using a lift-off process so that light emitted from the quantum well is not blocked by the negative electrode pad layer. 23 . The method of claim 22 , further comprising forming a pixel lens over the conductive semiconductor layer and aligned with the hollow shape in the negative electrode pad layer after forming a negative electrode pad layer.

Images