Display substrate and display device

Abstract

A display substrate includes a first display area (A1). The first display area (A1) includes a plurality of display island areas (A11) arranged in an array and light-transmissive areas (A121, A122) between adjacent display island areas (A11). The display island area (A11) includes a plurality of first pixel circuits (11) and a plurality of first light-emitting elements (13) disposed on a substrate. At least one first pixel circuit (11) is electrically connected with at least one first light-emitting element (13) and configured to drive the at least one first light-emitting element (13) to emit light. The first pixel circuits (11) in adjacent display island areas (A11) are connected by a plurality of first signal traces in a first direction (X), and the first pixel circuits (11) in adjacent display island areas (A11) are connected by a plurality of second signal traces in a second direction (Y). The material of the plurality of second signal traces includes a transparent conductive material, or the material of the plurality of first signal traces and the plurality of second signal traces both includes a metal material.

Description

[0001] This application claims priority to Chinese Patent Application No. 202210615748.7, filed on May 31, 2022, entitled “Display Substrate and Display Device”, the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This article relates to the field of display technology, and in particular to a display substrate and display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate and a display device.

[0006] On one hand, this embodiment provides a display substrate, including: a first display area, the first display area including: a plurality of display island areas arranged in an array, and a light-transmitting area located between adjacent display island areas. Each display island area includes: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate. At least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light. The first pixel circuits in adjacent display island areas are connected in a first direction via a plurality of first signal lines, and the first pixel circuits in adjacent display island areas are connected in a second direction via a plurality of second signal lines; the first direction and the second direction intersect. The material of the plurality of second signal lines includes a transparent conductive material, or the materials of both the plurality of first signal lines and the plurality of second signal lines include metallic materials.

[0007] In some exemplary embodiments, the film layer containing the plurality of second signal traces is located on the side of the film layer containing the plurality of first signal traces away from the substrate.

[0008] In some exemplary embodiments, the material of the plurality of first signal traces includes a metallic material, the material of the plurality of second signal traces includes a transparent conductive material, and the plurality of second signal traces are of the same layer structure.

[0009] In some exemplary embodiments, at least a portion of the plurality of second signal traces is located in the light-transmitting area.

[0010] In some exemplary embodiments, the light-transmitting area includes: a first light-transmitting area located between adjacent display island areas along the second direction, and a second light-transmitting area located between adjacent display island areas along the first direction; the area of ​​the first light-transmitting area is larger than the area of ​​the second light-transmitting area.

[0011] In some exemplary embodiments, the materials of the plurality of first signal traces and the plurality of second signal traces both include metallic materials. The plurality of second signal traces are in the same layer, or at least one of the plurality of second signal traces is in a different layer from the remaining second signal traces.

[0012] In some exemplary embodiments, the light-transmitting area includes at least: a first light-transmitting area located between adjacent display island areas along the second direction; the display substrate further includes: a first trace area located between adjacent first light-transmitting areas, the first trace area being connected to the display island area; the plurality of second signal traces are located in the first trace area.

[0013] In some exemplary embodiments, the plurality of second signal lines include: a plurality of data connection lines that transmit data signals to a plurality of first pixel circuits in the display island area, and at least one first power connection line that transmits a first voltage signal to a plurality of first pixel circuits in the display island area.

[0014] In some exemplary embodiments, the plurality of first pixel circuits of the display island area are electrically connected to the same first power supply connection line.

[0015] In some exemplary embodiments, the multiple first pixel circuits of the display island area are electrically connected to multiple first power connection lines respectively, and the multiple data connection lines and the multiple first power connection lines are spaced apart.

[0016] In some exemplary embodiments, the plurality of first pixel circuits in the display island area are arranged sequentially along the first direction, and the data connection line connected to the first first pixel circuit among the plurality of first pixel circuits is a heterogeneous structure with the data connection lines connected to the other first pixel circuits.

[0017] In some exemplary embodiments, at least one of the plurality of first signal traces is in a different layer structure from the remaining first signal traces.

[0018] In some exemplary embodiments, the plurality of first signal traces include: a first initial connection line for transmitting a first initial signal, a first scan connection line for transmitting a first scan signal, a second scan connection line for transmitting a second scan signal, and a light emission control connection line for transmitting a light emission control signal. The first scan connection line, the second scan connection line, and the light emission control connection line are in the same layer.

[0019] In some exemplary embodiments, at least one of the plurality of display island areas includes: three first pixel circuits and three first light-emitting elements, wherein the three first pixel circuits and the three first light-emitting elements are electrically connected in a one-to-one correspondence, and the three first pixel circuits are arranged sequentially along the first direction.

[0020] In some exemplary embodiments, the three first light-emitting elements include: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light. The first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light are arranged in the same column, the first light-emitting elements emitting the third color light and the first light-emitting elements emitting the first color light are arranged in different columns, and the first light-emitting elements emitting the first color light, the first light-emitting elements emitting the second color light, and the first light-emitting elements emitting the third color light are arranged in different rows.

[0021] In some exemplary embodiments, the area of ​​the light-emitting region of the first light-emitting element emitting the second color light is larger than the area of ​​the light-emitting region of the first light-emitting element emitting the first color light, and the area of ​​the light-emitting region of the first light-emitting element emitting the third color light is larger than the area of ​​the light-emitting region of the first light-emitting element emitting the first color light.

[0022] In some exemplary embodiments, the orthographic projection of the light-emitting region of the first light-emitting element emitting a first color light onto the substrate at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting the first color light onto the substrate. The orthographic projection of the light-emitting region of the first light-emitting element emitting a second color light onto the substrate does not overlap with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting the second color light onto the substrate. The orthographic projection of the light-emitting region of the first light-emitting element emitting a third color light onto the substrate at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting the third color light onto the substrate.

[0023] In some exemplary embodiments, the overlapping area of ​​the light-emitting region of the first light-emitting element emitting the third color light and the first pixel circuit connected to the first light-emitting element emitting the third color light is greater than the overlapping area of ​​the light-emitting region of the first light-emitting element emitting the first color light and the first pixel circuit connected to the first light-emitting element emitting the first color light.

[0024] In some exemplary embodiments, the display substrate further includes: a second display area located on at least one side of the first display area; the second display area includes: a plurality of second pixel circuits and a plurality of second light-emitting elements disposed on the substrate, wherein at least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element to emit light.

[0025] On the other hand, this embodiment provides a display device including a display substrate as described above.

[0026] On the other hand, this embodiment provides a display substrate, including: a first display area. The first display area includes: a plurality of display island areas arranged in an array, and a light-transmitting area located between adjacent display island areas. The light-transmitting area includes a first light-transmitting area, which is located between adjacent display island areas along a second direction. At least one of the plurality of display island areas and the first light-transmitting area are alternately arranged along the second direction. The display island area includes: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate. At least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements. At least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light. The first pixel circuits in adjacent display island areas are connected in a first direction through a plurality of first signal lines, and the first pixel circuits in adjacent display island areas are connected in the second direction through a plurality of second signal lines; the first direction and the second direction intersect.

[0027] In some exemplary embodiments, the first light-transmitting area is located between multiple second signal traces along a first direction.

[0028] In some exemplary embodiments, the light-transmitting area may further include a second light-transmitting area. The second light-transmitting area is located between adjacent display island areas along the first direction. The area of ​​the first light-transmitting area may be larger than the area of ​​the second light-transmitting area.

[0029] In some exemplary embodiments, the second light-transmitting area is located between the plurality of first signal lines.

[0030] In some exemplary embodiments, at least one of the plurality of display island areas includes: three first pixel circuits and three first light-emitting elements. The three first pixel circuits and the three first light-emitting elements are electrically connected in a one-to-one correspondence, and the three first pixel circuits are arranged sequentially along the first direction. The three first light-emitting elements include: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light. The light-emitting region of the first light-emitting element emitting the first color light, in its orthographic projection on the substrate, at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting the first color light on the substrate. The light-emitting region of the first light-emitting element emitting the second color light, in its orthographic projection on the substrate, does not overlap with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting the second color light on the substrate. The light-emitting region of the first light-emitting element emitting the third color light, in its orthographic projection on the substrate, at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting the third color light on the substrate.

[0031] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0032] Overview of the attached figures

[0033] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0034] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0035] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0036] Figure 3 This is a partial schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0037] Figure 4 This is a schematic diagram showing the arrangement of the first pixel circuit and the first light-emitting element in the first display area of ​​at least one embodiment of the present disclosure;

[0038] Figure 5 for Figure 4 A partial top-view diagram of the central region S1;

[0039] Figure 6 for Figure 5 A schematic diagram of a display substrate after the semiconductor layer has been formed;

[0040] Figure 7A for Figure 5 A schematic diagram of the display substrate after the first conductive layer has been formed;

[0041] Figure 7B for Figure 7A A schematic diagram of the first conductive layer in the middle;

[0042] Figure 8A for Figure 5 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0043] Figure 8B for Figure 8A A schematic diagram of the second conductive layer in the middle;

[0044] Figure 9 for Figure 5 A schematic diagram of the display substrate after the third insulating layer has been formed;

[0045] Figure 10A for Figure 5 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0046] Figure 10B for Figure 10A A schematic diagram of the third conductive layer in the diagram;

[0047] Figure 11 for Figure 5 A schematic diagram of the display substrate after the fourth insulating layer has been formed;

[0048] Figure 12A for Figure 5 A schematic diagram of a display substrate after a transparent conductive layer has been formed.

[0049] Figure 12B for Figure 12A A schematic diagram of the transparent conductive layer in the diagram;

[0050] Figure 13 for Figure 5 A schematic diagram of the display substrate after the fifth insulating layer has been formed;

[0051] Figure 14A for Figure 5 A schematic diagram of the display substrate after the fourth conductive layer has been formed;

[0052] Figure 14B for Figure 14A A schematic diagram of the fourth conductive layer in the diagram;

[0053] Figure 15 for Figure 5 A schematic diagram of the display substrate after the formation of the sixth insulating layer;

[0054] Figure 16A for Figure 5 A schematic diagram of the display substrate after the anode layer has been formed;

[0055] Figure 16B for Figure 16A Schematic diagram of the middle anode layer;

[0056] Figure 17A This is another schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0057] Figure 17B This is another schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0058] Figure 17C This is another schematic diagram of the first display area according to at least one embodiment of the present disclosure;

[0059] Figure 18 for Figure 17A A partial top-view diagram of the central region S2;

[0060] Figure 19 for Figure 18 A schematic diagram of the display substrate after the first conductive layer has been formed;

[0061] Figure 20 for Figure 18 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0062] Figure 21A for Figure 18 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0063] Figure 21B for Figure 21A A schematic diagram of the third conductive layer in the diagram;

[0064] Figure 22 for Figure 18 A schematic diagram of the display substrate after the fifth insulating layer has been formed;

[0065] Figure 23A for Figure 18 A schematic diagram of the display substrate after the fourth conductive layer has been formed;

[0066] Figure 23B for Figure 23A A schematic diagram of the fourth conductive layer in the diagram;

[0067] Figure 24 for Figure 18 A schematic diagram of the display substrate after the formation of the sixth insulating layer;

[0068] Figure 25 for Figure 18 A schematic diagram of the display substrate after the anode layer has been formed;

[0069] Figure 26 for Figure 17A Another partial top view of the central region S2;

[0070] Figure 27 for Figure 26 A schematic diagram of the display substrate after the second conductive layer has been formed;

[0071] Figure 28A for Figure 26 A schematic diagram of the display substrate after the third conductive layer has been formed;

[0072] Figure 28B for Figure 28A A schematic diagram of the third conductive layer in the diagram;

[0073] Figure 29 for Figure 26 A schematic diagram of the display substrate after the fifth insulating layer has been formed;

[0074] Figure 30A for Figure 26 A schematic diagram of the display substrate after the fourth conductive layer has been formed;

[0075] Figure 30B for Figure 30A A schematic diagram of the fourth conductive layer in the diagram;

[0076] Figure 31 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0077] Detailed Explanation

[0078] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0079] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0080] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0081] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0082] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0083] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0084] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0085] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0086] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0087] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0088] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0089] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0090] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0091] This embodiment provides a display substrate, including a first display area. The first display area includes a plurality of display island areas arranged in an array, and a light-transmitting area located between adjacent display island areas. Each display island area includes a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate. At least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light. The first pixel circuits in adjacent display island areas are connected in a first direction via a plurality of first signal traces, and the first pixel circuits in adjacent display island areas are connected in a second direction via a plurality of second signal traces. The first direction and the second direction intersect. The material of the plurality of second signal traces includes a transparent conductive material, or the materials of both the plurality of first signal traces and the plurality of second signal traces include metallic materials.

[0092] The display substrate provided in this embodiment can reduce the number of islands and slits by arranging multiple first pixel circuits and multiple first light-emitting elements in the display island area. This is beneficial for reducing the diffraction effect of the display substrate and for smoothing the surface, thereby reducing the display defects (mura) in the first display area and improving the photographic effect.

[0093] In some exemplary embodiments, the material of the multiple first signal traces may include a metallic material, and the material of the multiple second signal traces may include a transparent conductive material. The multiple second signal traces may be in a co-layer structure. This example, by including a transparent conductive material in the material of the multiple second signal traces, facilitates increasing the spacing between adjacent display island areas, increasing the routing freedom of the second signal traces, increasing the linewidth of the second signal traces, mitigating display defects caused by excessive resistance of the second signal traces, and increasing the light-transmitting area. By including a metallic material in the material of the multiple first signal traces, lateral display defects caused by excessive impedance of the transparent conductive material are reduced, and the process is simplified, avoiding excessive aperture operations and reducing costs.

[0094] In some exemplary embodiments, the materials of the plurality of first signal traces and the plurality of second signal traces may all include metallic materials. The plurality of second signal traces may be in the same layer, or at least one of the second signal traces may be in a different layer from the remaining second signal traces. This example, by setting the materials of the plurality of first signal traces and the plurality of second signal traces to all include metallic materials, can reduce the possibility of poor lateral or longitudinal display caused by excessive impedance due to the use of transparent conductive materials. Furthermore, it can simplify the manufacturing process, avoid excessive openings to reduce costs, and reduce the space occupied by the traces, which is beneficial for improving light transmittance.

[0095] The following examples illustrate the solution of this embodiment.

[0096] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display substrate may include a display area AA and a peripheral area BB located around the display area AA. The display area AA of the display substrate may include at least a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited to this. In other examples, the display area may only include the first display area, and the peripheral area may surround the first display area.

[0097] In some examples, such as Figure 1As shown, the first display area A1 can be a light-transmitting display area, or it can also be called the under-display camera (FDC) area. The second display area A2 can be called the normal display area. For example, the orthographic projection of a photosensor (such as a camera) onto the display substrate can be located within the first display area A1 of the display substrate. In some examples, such as... Figure 1 As shown, the first display area A1 can be circular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 can be rectangular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the inscribed circle of the first display area A1.

[0098] In some examples, such as Figure 1 As shown, the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited in this respect. For example, the first display area A1 can be located at other positions such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0099] In some examples, such as Figure 1 As shown, the display area AA can be rectangular, such as a rounded rectangle. The first display area A1 can be circular or elliptical. However, this embodiment is not limited to this. For example, the first display area A1 can be other shapes such as rectangle, semicircle, pentagon, etc.

[0100] In some examples, the display area AA can be configured with multiple sub-pixels. At least one sub-pixel can include pixel circuitry and a light-emitting element. The pixel circuitry can be configured to drive the connected light-emitting element. For example, the pixel circuitry can be configured to provide a drive current to drive the light-emitting element to emit light. The pixel circuitry can include multiple transistors and at least one capacitor. For example, the pixel circuitry can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Here, in the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0101] In some examples, the multiple transistors in the pixel circuit can be either P-type or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the manufacturing process, reduces the complexity of the display substrate manufacturing, and improves product yield. In other examples, the multiple transistors in the pixel circuit can include both P-type and N-type transistors.

[0102] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate—an LTPS+Oxide (LTPO) display substrate—leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0103] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0104] In some examples, a pixel unit of the display area AA may include three sub-pixels. For example, the three sub-pixels may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0105] In some examples, the shape of the light-emitting element can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0106] Figure 2This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit in this example is described using a 7T1C structure as an example.

[0107] In some examples, such as Figure 2 As shown, the pixel circuit of this example may include seven transistors (i.e., first transistor T1 to seventh transistor T7) and a storage capacitor Cst. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0108] In some examples, such as Figure 2 As shown, the display substrate may include: a first scan line GL1, a second scan line GL2, a third scan line GL3, a data line DL, a first power line VDD, a second power line VSS, a light emission control line EML, a first initial signal line INIT1, and a second initial signal line INIT2.

[0109] In some examples, the first power line VDD can be configured to provide a constant first voltage signal to the pixel circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the pixel circuit, wherein the first voltage signal can be greater than the second voltage signal. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit; the data line DL can be configured to provide a data signal to the pixel circuit; the light emission control line EML can be configured to provide a light emission control signal EM to the pixel circuit; the second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit, and the third scan line GL3 can be configured to provide a third scan signal SCAN3 to the pixel circuit.

[0110] In some examples, the second scan line GL2, electrically connected to the nth row pixel circuit, can be electrically connected to the first scan line GL1, electrically connected to the (n-1)th row pixel circuit, to be input to the first scan signal SCAN1(n-1), meaning the second scan signal SCAN2(n) and the first scan signal SCAN1(n-1) can be the same. Similarly, the third scan line GL3, electrically connected to the first scan line GL1, can be input to the first scan signal SCAN1(n), meaning the third scan signal SCAN3(n) and the first scan signal SCAN1(n) can be the same. Here, n is an integer greater than 0. This reduces the number of signal lines on the display substrate, enabling a narrow bezel design. However, this embodiment is not limited to this.

[0111] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. Both the first and second initial signals can be constant voltage signals, the magnitude of which may be, for example, between a first voltage signal and a second voltage signal, but is not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0112] In some examples, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 can also be called a driving transistor. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The fourth transistor T4 can also be called a data writing transistor. The gate of the second transistor T2 is electrically connected to the first scan line GL1, the first terminal of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3. The second transistor T2 can also be called a threshold compensation transistor. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light-emitting control line EML, the first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 can also be referred to as light-emitting control transistors. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected to the second scan line GL2, the first terminal of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the third scan line GL3, the first terminal of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second terminal of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first transistor T1 and the seventh transistor T7 can also be referred to as reset control transistors. The first plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second plate of the storage capacitor Cst is electrically connected to the first power supply line VDD.

[0113] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0114] The working process of the pixel circuit is explained below. Figure 2The pixel circuit shown is illustrated using P-type transistors as an example. In this example, the third scan signal provided by the third scan line GL3 can be the same as the first scan signal provided by the first scan line GL1.

[0115] In some examples, the operation of the pixel circuit during a display time frame may include a first stage, a second stage, and a third stage.

[0116] The first stage is called the reset stage. The second scan signal SCAN2 provided by the second scan line GL2 can be a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize N1 and clear the original data voltage in the storage capacitor Cst. The first scan signal SCAN1 provided by the first scan line GL1 can be a high-level signal, and the light emission control signal EM provided by the light emission control line EML can be a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this stage, the light-emitting element EL does not emit light.

[0117] The second stage is called the data writing stage or threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 can be a low-level signal, while the second scan signal SCAN2 provided by the second scan line GL2 and the light emission control signal EM provided by the light emission control line EML can both be high-level signals. The data line DL outputs the data signal DATA. During this stage, since the first plate of the storage capacitor Cst is at a low level, the third transistor T3 is turned on. The low-level first scan signal SCAN1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn-on of the second transistor T2 and the fourth transistor T4 allows the data voltage Vdata output by the data line DL to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage of the first plate of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the anode of the light-emitting element EL. This initializes (resets) the anode of the light-emitting element EL, clearing its internal pre-stored voltage and completing the initialization process, ensuring that the light-emitting element EL does not emit light. The second scan signal SCAN2 provided by the second scan line GL2 can be a high-level signal, causing the first transistor T1 to turn off. The light-emitting control signal EM provided by the light-emitting control signal line EML is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0118] The third stage is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, while the first scan signal SCAN1 provided by the first scan line GL1 and the second scan signal SCAN2 provided by the second scan line GL2 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control line EML is low-level, the fifth transistor T5 and the sixth transistor T6 are turned on. The first voltage signal output by the first power line VDD provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0119] During the pixel circuit driving process, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and its first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0120] I = K × (Vgs - Vth) 2=K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×[Vdd-Vdata] 2 .

[0121] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0122] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3.

[0123] In some examples, such as Figure 1 As shown, the first display area A1 may include a plurality of first pixel circuits 11 and a plurality of first light-emitting elements 13. At least one of the plurality of first pixel circuits 11 and at least one of the plurality of first light-emitting elements 13 are electrically connected. The at least one pixel circuit 11 may be configured to drive the at least one connected first light-emitting element 13 to emit light. The orthographic projections of the first light-emitting element 13 and the connected first pixel circuit 11 onto the substrate may at least partially overlap. For example, the plurality of first pixel circuits 11 and the plurality of first light-emitting elements 13 may be electrically connected in a one-to-one correspondence.

[0124] In some examples, such as Figure 1 As shown, the second display area A2 may include a plurality of second pixel circuits 12 and a plurality of second light-emitting elements 14. At least one of the plurality of second pixel circuits 12 and at least one of the plurality of second light-emitting elements 14 are electrically connected, and at least one second pixel circuit 12 may be configured to drive the at least one connected second light-emitting element 14 to emit light. The orthographic projections of the second light-emitting element 14 and the connected second pixel circuit 12 onto the substrate may at least partially overlap. For example, the plurality of second pixel circuits 12 and the plurality of second light-emitting elements 14 may be electrically connected in a one-to-one correspondence.

[0125] Figure 3 This is a partial schematic diagram of a first display area according to at least one embodiment of the present disclosure. In some examples, such as... Figure 3As shown, in a plane parallel to the display substrate, the first display area A1 may include a plurality of display island areas A11 arranged in an array. Each display island area A11 can be configured to display an image. The plurality of display island areas A11 can be arranged in an array along a first direction X and a second direction Y. The first direction X and the second direction Y can intersect; for example, the first direction X can be perpendicular to the second direction Y. The plurality of display island areas A11 arranged along the first direction X can be referred to as a row of display island areas, and the plurality of display island areas arranged along the second direction Y can be referred to as a column of display island areas.

[0126] In some examples, such as Figure 3 As shown, within a plane parallel to the display substrate, the shapes of multiple display island areas A11 can be approximately identical. For example, display island areas A11 can be irregularly shaped to provide sufficient light-emitting area to ensure display quality. Display island areas A11 can have smooth edges to reduce light diffraction effects, thereby helping to improve image quality.

[0127] In some examples, such as Figure 3 As shown, a light-transmitting area is provided between adjacent display island areas A11. Each light-transmitting area can be configured to provide light transmission space. For example, the light-transmitting area may include: a first light-transmitting area A121 and a second light-transmitting area A122. The first light-transmitting area A121 may be located between two adjacent rows of display island areas (e.g., the k-th row and the (k+1)-th row of display island areas, where k is an integer greater than 0). Multiple first light-transmitting areas A121 and multiple rows of display island areas A11 may be arranged alternately. Multiple second light-transmitting areas A122 may be located between two adjacent columns of display island areas A11 (e.g., the m-th column and the (m+1)-th column of display island areas, where m is an integer greater than 0). For example, multiple second light-transmitting areas A122 may be set independently. Multiple second light-transmitting areas A122 may be arranged sequentially along the second direction Y, and the second light-transmitting areas A122 and the first light-transmitting areas A121 may not be connected. A second light-transmitting area A122 may be located between two adjacent display island areas A11 in a row of display island areas A11. For example, the area of ​​a single first light-transmitting area A121 can be larger than the area of ​​a single second light-transmitting area A122. However, this embodiment is not limited in this respect. For example, the second light-transmitting area A122 can be connected to the first light-transmitting area A121 adjacent in the second direction Y.

[0128] In some examples, such as Figure 3As shown, multiple first wiring areas A131 can also be provided between display island areas A11. Multiple first wiring areas A131 can be set independently. A first wiring area A131 can be located between two adjacent display island areas A11 in a row. Adjacent display island areas A11 in a row can be connected through the first wiring area A131. A second light-transmitting area A122 can be surrounded by the first wiring area A131; or, the second light-transmitting area A122 can be surrounded by the first wiring area A131 and the display island area A11. This example uses the first wiring area A131 to achieve signal transmission between display island areas A11 along the first direction X.

[0129] Figure 4 This is a schematic diagram showing the arrangement of the first pixel circuit and the first light-emitting element in the first display area according to at least one embodiment of the present disclosure. In some examples, such as Figure 4 As shown, a display island area A11 may include a first pixel unit, and a first pixel unit may include three first sub-pixels. Each first sub-pixel may include a first pixel circuit and a first light-emitting element. The three first sub-pixels within the display island area A11 can be configured to emit light of different colors.

[0130] In some examples, such as Figure 4 As shown, the display island area A11 may include: three first pixel circuits (e.g., first pixel circuits 11a, 11b, and 11c) and three first light-emitting elements (e.g., first light-emitting elements 13a, 13b, and 13c). The three first pixel circuits and the three first light-emitting elements can be electrically connected in a one-to-one correspondence. First pixel circuit 11a can be electrically connected to first light-emitting element 13a, first pixel circuit 11b can be electrically connected to first light-emitting element 13b, and first pixel circuit 11c can be electrically connected to first light-emitting element 13c.

[0131] In some examples, the first light-emitting element 13a can be configured to emit light of a first color, the first light-emitting element 13b can be configured to emit light of a second color, and the first light-emitting element 13c can be configured to emit light of a third color. In some examples, the first color light can be red light, the second color light can be green light, and the third color light can be blue light. That is, the first light-emitting element 13a can be a red light-emitting element, the first light-emitting element 13b can be a green light-emitting element, and the first light-emitting element 13c can be a blue light-emitting element.

[0132] In some examples, such as Figure 4As shown, the first pixel circuits 11a, 11b, and 11c within a display island area A11 can be arranged sequentially along the first direction X. Multiple first pixel circuits within a row of a display island area A11 can be arranged in a row along the first direction X, and multiple first pixel circuits within a column of a display island area A11 can be arranged in three columns along the second direction Y.

[0133] In some examples, such as Figure 4 As shown, within a display island area A11, the first light-emitting elements 13a and 13b can be arranged sequentially along the second direction Y, and the first light-emitting element 13c can be located on the same side of the first light-emitting elements 13a and 13b in the first direction X. Multiple first light-emitting elements 13a in a row of display island area A11 can be arranged in the i-th row, multiple first light-emitting elements 13c in the (i+1)-th row, and multiple first light-emitting elements 13b in the (i+2)-th row, and so on, repeating this arrangement for multiple rows. The first light-emitting elements 13a and 13b in display island area A11 can be arranged alternately in the second direction Y. Multiple first light-emitting elements 13a and 13b in a column of display island area A11 can be arranged alternately in the j-th column, and multiple first light-emitting elements 13c can be arranged sequentially in the (j+1)-th column, repeating this arrangement for multiple columns. Here, i and j are both integers greater than 0. In this example, one row shows that three rows of first light-emitting elements can be arranged in island area A11, and one column shows that two columns of first light-emitting elements can be arranged in island area A11.

[0134] In some examples, such as Figure 4 As shown, the first light-emitting element 13a may have a light-emitting region 130a, the first light-emitting element 13b may have a light-emitting region 130b, and the first light-emitting element 13c may have a light-emitting region 130c. The light-emitting regions 130a, 130b, and 130c of the first light-emitting element 13a and 13c may all be approximately circular or elliptical. The area of ​​the light-emitting region 130a of the first light-emitting element 13a may be smaller than the area of ​​the light-emitting region 130b of the first light-emitting element 13b, and may be smaller than the area of ​​the light-emitting region 130c of the first light-emitting element 13c. The area of ​​the light-emitting region 130b of the first light-emitting element 13b and the area of ​​the light-emitting region 130c of the first light-emitting element 13c may be approximately the same. In this example, the light-emitting region of the light-emitting element refers to the portion of the light-emitting element located at the pixel opening in the pixel definition layer.

[0135] In some examples, such as Figure 4As shown, the orthographic projection of the light-emitting region 130a of the first light-emitting element 13a onto the substrate and the orthographic projection of the first pixel circuit 11a onto the substrate may partially overlap. The orthographic projection of the light-emitting region 130b of the first light-emitting element 13b onto the substrate and the orthographic projection of the connected first pixel circuit 11b onto the substrate may not overlap, or the orthographic projection of the light-emitting region 130b onto the substrate may partially overlap with the orthographic projection of the first pixel circuit 11a onto the substrate. The orthographic projection of the light-emitting region 130c of the first light-emitting element 13c onto the substrate and the orthographic projection of the connected first pixel circuit 11c onto the substrate may at least partially overlap; for example, the orthographic projection of the light-emitting region 130c onto the substrate may be located within the range of the orthographic projection of the first pixel circuit 11c onto the substrate.

[0136] The arrangement of the three first pixel circuits and three first light-emitting elements in the display substrate of this example is conducive to centralized setting. By setting the three first pixel circuits and three first light-emitting elements as a first pixel unit in a display island area, it is convenient to arrange the display island areas in an array, which can increase the space between the display island areas and avoid the large number of display islands and recessed slits caused by setting a first pixel circuit and a first light-emitting element separately in each display island area. By reducing the number of islands and slits, the light diffraction of the first display area can be improved, and it is also convenient to smooth the edges of the display island areas.

[0137] Figure 5 for Figure 4 A partial top-view diagram of the central region S1. Figure 5 The diagram illustrates four display islands A11 arranged in a 2×2 array.

[0138] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, a circuit structure layer and a light-emitting structure layer sequentially disposed on the substrate. The circuit structure layer of the first display area may include at least a plurality of first pixel circuits, and the light-emitting structure layer may include at least a plurality of first light-emitting elements. The first light-emitting element may include at least: an anode, an organic light-emitting layer and a cathode, and the anode of the first light-emitting element may be connected to the corresponding first pixel circuit.

[0139] In some examples, the circuit structure layer of the first display area, in a direction perpendicular to the display substrate, may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a transparent conductive layer, and a fourth conductive layer sequentially disposed on the substrate. A first insulating layer may be disposed between the semiconductor layer and the first conductive layer; a second insulating layer may be disposed between the first and second conductive layers; a third insulating layer may be disposed between the second and third conductive layers; a fourth insulating layer may be disposed between the third conductive layer and the transparent conductive layer; a fifth insulating layer may be disposed between the transparent conductive layer and the fourth conductive layer; and a sixth insulating layer may be disposed on the side of the fourth conductive layer away from the substrate.

[0140] In some examples, the light-emitting structure layer may include at least: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer sequentially disposed on the substrate. The anode layer may be electrically connected to the first pixel circuit of the circuit structure layer, the organic light-emitting layer may be connected to the anode layer, and the cathode layer may be connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the drive of the anode and cathode layers. An encapsulation structure layer may be disposed on the side of the light-emitting structure layer away from the substrate. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer may be disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited herein.

[0141] The structure and fabrication process of the display substrate in this example are described below. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching, and this disclosure does not limit the methods. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0142] The terms "A and B are in the same layer" or "A and B are of the same layer structure" in this disclosure mean that A and B are formed simultaneously through the same patterning process. "A and B are of different layers structure" means that A and B are formed separately through at least two patterning processes. The "thickness" of the film layer is its dimension in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The term "shape of A" in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0143] In some examples, the fabrication process of the display substrate in this example may include the following operations. The structure of each region containing the first pixel circuit in the circuit structure layer of the display substrate is roughly the same; the following description uses the structure of the region containing the first first pixel circuit as an example.

[0144] (1-1) Providing a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be one or more of glass and quartz, while the flexible substrate can be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, among others. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNy, y>0) or silicon oxide (SiOx, x>0), etc., to improve the substrate's resistance to water and oxygen.

[0145] (1-2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned using a patterning process to form a semiconductor layer disposed on the substrate, such as... Figure 6 As shown. Figure 6 for Figure 5 A schematic diagram of a display substrate after the semiconductor layer has been formed.

[0146] In some examples, such as Figure 6 As shown, the semiconductor layer of a single display island region in the display substrate may include at least: a first active layer 21 of the first transistor T1 of the three first pixel circuits, a second active layer 22 of the second transistor T2, a third active layer 23 of the third transistor T3, a fourth active layer 24 of the fourth transistor T4, a fifth active layer 25 of the fifth transistor T5, a sixth active layer 26 of the sixth transistor T6, and a seventh active layer 27 of the seventh transistor T7.

[0147] In some examples, the first active layer 21, second active layer 22, third active layer 23, fourth active layer 24, fifth active layer 25, sixth active layer 26, and seventh active layer 27 of each first pixel circuit can be an interconnected monolithic structure. The fifth active layer 25 and sixth active layer 26 can be located on one side of the third active layer 23 in the second direction Y, and the fourth active layer 24, second active layer 22, first active layer 21, and seventh active layer 27 can be located on the other side of the third active layer 23 in the second direction Y. The first active layer 21 can be located on the side of the second active layer 22 away from the third active layer 23 in the second direction Y. The seventh active layer 27 can be located on the side of the second active layer 22 away from the fourth active layer 24 in the first direction X. The active layers of the transistors of adjacent first pixel circuits within a display island area can be independently configured.

[0148] In some examples, the first active layer 21 can be roughly U-shaped, the second active layer 22 can be roughly L-shaped, the third active layer 23 can be roughly n-shaped, and the fourth active layer 24, the fifth active layer 25, the sixth active layer 26 and the seventh active layer 27 can be roughly I-shaped.

[0149] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In some examples, the first region 211 of the first active layer 21 is connected to the first region 271 of the seventh active layer 27, and the first region 211 of the first active layer 21 can simultaneously serve as the first region 271 of the seventh active layer 27. The second region 212 of the first active layer 21 is connected to the first region 221 of the second active layer 22, and the second region 212 of the first active layer 21 can simultaneously serve as the first region 221 of the second active layer 22. The first region 231 of the third active layer 23 can be connected to the second region 242 of the fourth active layer 24 and the second region 252 of the fifth active layer 25, and the first region 231 of the third active layer 23 can simultaneously serve as the second region 242 of the fourth active layer 24 and the second region 252 of the fifth active layer 25, forming the second node of the first pixel circuit. The second region 232 of the third active layer 23 can be connected to the second region 222 of the second active layer 22 and the first region 261 of the sixth active layer 26. The second region 232 of the third active layer 23 can simultaneously serve as the second region 222 of the second active layer 22 and the first region 261 of the sixth active layer 26, forming the third node of the first pixel circuit. The first region 241 of the fourth active layer 24, the first region 251 of the fifth active layer 25, the second region 252 of the sixth active layer 26, and the second region 272 of the seventh active layer 27 can be set independently. The first region 241 of the fourth active layer 24 can be located on the side of the second region 212 of the first active layer 21 away from the first region 211 of the first active layer 21 in the first direction X. The first region 251 of the fifth active layer 25 can be located on the side of the third active layer 23 away from the first region 241 of the fourth active layer 24 in the second direction Y. The second region 262 of the sixth active layer 26 can be adjacent to the first region 251 of the fifth active layer 25 in the first direction X. The second region 272 of the seventh active layer 27 can be adjacent to the second region 222 of the second active layer 22 in the first direction X.

[0150] In some examples, the semiconductor layers in adjacent display island areas may be spaced apart from each other. For example, the active layers of multiple transistors of the first pixel circuit in an adjacent display island area along the first direction X may not be connected, and the active layers of multiple transistors of the first pixel circuit in an adjacent display island area along the second direction Y may not be connected.

[0151] (1-3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The first conductive film is patterned using a patterning process to form a first insulating layer disposed on the semiconductor layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer. The first insulating layer may also be referred to as a first gate insulating layer.

[0152] Figure 7A for Figure 5 A schematic diagram of the display substrate after the first conductive layer has been formed. Figure 7B for Figure 7A A schematic diagram of the first conductive layer in the image. In some examples, such as... Figure 7A and Figure 7B As shown, the first conductive layer of a single display island area in the first display area may include at least: a first scan line 31, a second scan line 32, a light emission control line 33, and a first electrode plate 281 of the storage capacitor of the three first pixel circuits.

[0153] In some examples, the shapes of the first scan line 31, the second scan line 32, and the light emission control line 33 can all be lines extending along the first direction X of the main body, for example, straight lines extending along the first direction X. The second scan line 32, the first scan line 31, and the light emission control line 33 within the display island area can be arranged sequentially along the second direction Y. The first scan line 31 can be located on one side of the second scan line 32 in the second direction Y, and the light emission control line 33 can be located on one side of the first scan line 31 in the second direction Y. The first scan line 31 can be located between the second scan line 32 and the light emission control line 33. The first plate 281 of the storage capacitor of the first pixel circuit can be located between the first scan line 31 and the light emission control line 33. The first plates 281 of the storage capacitors of the three first pixel circuits can be arranged sequentially along the first direction X.

[0154] In some examples, the orthographic projection of the first electrode 281 of the storage capacitor onto the substrate can be approximately rectangular, for example, a rounded rectangle. The orthographic projection of the first electrode 281 of the storage capacitor onto the substrate can at least partially overlap with the orthographic projection of the third active layer 13 of the third transistor T3 onto the substrate, and the first electrode 281 can simultaneously serve as the lower electrode of the storage capacitor and the gate of the third transistor T3.

[0155] In some examples, the second scan line 32 and the orthographic projection of the first active layer 21 of the first transistor T1 onto the substrate may partially overlap. The region where the second scan line 32 overlaps with the first active layer 21 can serve as the gate of the first transistor T1 in a dual-gate structure.

[0156] In some examples, the region where the first scan line 31 overlaps with the fourth active layer 24 of the fourth transistor T4 can serve as the gate of the fourth transistor T4. The region where the first scan line 31 overlaps with the seventh active layer 27 of the seventh transistor T7 can serve as the gate of the seventh transistor T7. The region where the first scan line 31 overlaps with the second active layer 22 of the second transistor T2 can serve as the first gate of the second transistor T2.

[0157] In some examples, a scan extension 31-1 may be provided on the side of the first scan line 31 near the second scan line 32. The scan extension 31-1 may be provided in each pixel circuit. The first end of the scan extension 31-1 is connected to the first scan line 31, and the second end of the scan extension 31-1 extends towards the second scan line 32. The region where the scan extension 31-1 overlaps with the second active layer 22 can serve as the second gate of the second transistor T2, realizing a dual-gate structure for the second transistor T2. Multiple scan extensions 31-1 and the first scan line 31 can be an integrally connected structure.

[0158] In some examples, the region where the light-emitting control line 33 overlaps with the fifth active layer 25 of the fifth transistor T5 can serve as the gate of the fifth transistor T5. The region where the light-emitting control line 33 overlaps with the sixth active layer 26 of the sixth transistor T6 can serve as the gate of the sixth transistor T6.

[0159] In some examples, the first conductive layer of the first trace area between adjacent display island areas in the first direction X may include at least: a first scan connection line 71, a second scan connection line 72, and a light emission control connection line 73. The shapes of the first scan connection line 71, the second scan connection line 72, and the light emission control connection line 73 may all be lines extending along the first direction X. For example, the second scan connection line 72 and the light emission control connection line 73 may be straight lines extending along the first direction X, and the first scan connection line 71 may be a broken line or an arc extending along the first direction X. The first scan connection line 71 may be bent towards one side of the second scan connection line 72. The first scan connection line 71 may be located on one side of the second scan connection line 72 in the second direction Y, and the light emission control connection line 73 may be located on one side of the first scan connection line 71 in the second direction Y. The first scan connection line 71 may be located between the second scan connection line 72 and the light emission control connection line 73.

[0160] In some examples, the boundary of the second light-transmitting area along the second direction Y can be defined by the first scanning connection line 71 and the emission control connection line 73. This example, by employing a design where the first scanning connection line 71 bends towards the second scanning connection line 72, helps to increase the area of ​​the second light-transmitting area. In other examples, the second scanning connection line 72 can be bent away from the first scanning connection line 71, and the emission control connection line 73 can also be bent away from the first scanning connection line 71, to further increase the area of ​​the second light-transmitting area. In still other examples, the emission control connection line 73 can be bent towards the first scanning connection line 71, allowing the first and second light-transmitting areas to connect, thus improving the diffraction caused by isolated slits.

[0161] In some examples, the first scan line 31 within adjacent display island areas along the first direction X can be connected via a first scan connection line 71. The two ends of the first scan connection line 71 can be connected to the first scan line 31 within two adjacent display island areas, respectively. The second scan line 32 within adjacent display island areas along the first direction X can be connected via a second scan connection line 72. The two ends of the second scan connection line 72 can be connected to the second scan line 32 within two adjacent display island areas, respectively. The light emission control line 33 within adjacent display island areas along the first direction X can be connected via a light emission control connection line 73. The two ends of the light emission control connection line 73 can be connected to the light emission control line 33 within two adjacent display island areas, respectively.

[0162] In some examples, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7. The semiconductor layer in the region not shielded by the first conductive layer can be conducted, that is, the first region and the second region of the first active layer 21 to the seventh active layer 27 can both be conducted.

[0163] (1-4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second conductive film is patterned using a patterning process to form a second insulating layer disposed on the first conductive layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer. The second insulating layer may also be referred to as a second gate insulating layer.

[0164] Figure 8A for Figure 5 A schematic diagram of the display substrate after the second conductive layer has been formed. Figure 8B for Figure 8A A schematic diagram of the second conductive layer. In some examples, such as... Figure 8A and Figure 8B As shown, the second conductive layer of a single display island area in the first display area may include at least: a first initial signal line 34, and a second electrode 282 of the storage capacitors of the three first pixel circuits.

[0165] In some examples, the shape of the first initial signal line 34 can be a straight line with its main body extending along the first direction X. The orthographic projection of the first initial signal line 34 onto the substrate can be located on the side of the second scan line 32 onto the substrate away from the orthographic projection of the first scan line 31 onto the substrate. The orthographic projections of the first initial signal line 34 onto the substrate and the second scan line 32 onto the substrate can partially overlap, or they can not overlap.

[0166] In some examples, the second plate 282 of the storage capacitor of the first pixel circuit can be located on one side of the first initial signal line 34 in the second direction Y. The orthographic projection of the second plate 282 of the storage capacitor onto the substrate can partially overlap with the orthographic projection of the first plate 281 onto the substrate. For example, the orthographic projection of the second plate 282 onto the substrate can be approximately L-shaped. The second plates 282 of the storage capacitors of the three first pixel circuits can be arranged sequentially along the first direction X.

[0167] In some examples, an initial connection block 34-1 may be provided on the side of the first initial signal line 34 away from the second electrode plate 282. The initial connection block 34-1 may be provided in each pixel circuit of the display island area. The first end of the initial connection block 34-1 is connected to the first initial signal line 34, and the second end of the initial connection block 34-1 extends away from the second electrode plate 282. The initial connection block 34-1 may be configured to be electrically connected to the first connection electrode 41 through a subsequently formed ninth via V9. In some examples, the first initial signal line 34 and multiple initial connection blocks 34-1 may be an integral structure interconnected with each other.

[0168] In some examples, the second conductive layer of the first trace area between adjacent display island areas in the first direction X may include at least: a first initial connection line 74. The shape of the first initial connection line 74 may be a straight line with its main portion extending along the first direction X. The orthographic projection of the first initial connection line 74 onto the substrate may be located on the side of the orthographic projection of the second scan connection line 72 onto the substrate that is away from the orthographic projection of the first scan connection line 71 onto the substrate.

[0169] In some examples, the first initial signal lines 34 in adjacent display island areas along the first direction X can be connected by a first initial connection line 74. The two ends of the first initial connection line 74 can be connected to the first initial signal lines 34 in adjacent display island areas, respectively.

[0170] (1-5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the third insulating film is patterned by a patterning process to form a third insulating layer. The third insulating layer may have multiple vias. The third insulating layer may also be referred to as an interlayer insulating layer.

[0171] Figure 9 for Figure 5 A schematic diagram of a display substrate after the formation of the third insulating layer. In some examples, the multiple vias of the third insulating layer in a single display island area may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9.

[0172] In some examples, the orthographic projection of the first via V1 onto the substrate may lie within the orthographic projection of the first region 211 of the first active layer 21 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 may be etched away, exposing a portion of the surface of the first region 211 of the first active layer 21. The first via V1 may be configured to allow a subsequently formed first connection electrode to be connected to the first region 211 of the first active layer 21 through the via.

[0173] In some examples, the orthographic projection of the second via V2 onto the substrate may lie within the orthographic projection of the second region 212 of the first active layer 21 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the second via V2 may be etched away, exposing a portion of the surface of the second region 212 of the first active layer 21. The second via V2 may be configured to allow a subsequently formed second connection electrode to be connected to the second region 212 of the first active layer 21 through the via.

[0174] In some examples, the orthographic projection of the third via V3 onto the substrate may lie within the orthographic projection of the first region 241 of the fourth active layer 24 onto the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the third via V3 may be etched away, exposing a portion of the surface of the first region 241 of the fourth active layer 24. The third via V3 may be configured to allow a subsequently formed third connection electrode to be connected to the first region 241 of the fourth active layer 24 through the via.

[0175] In some examples, the orthographic projection of the fourth via V4 onto the substrate may lie within the orthographic projection of the first region 251 of the fifth active layer 25 onto the substrate. The third, second, and first insulating layers within the fourth via V4 may be etched away, exposing a portion of the surface of the first region 251 of the fifth active layer 25. The fourth via V4 may be configured to allow a subsequently formed fourth connection electrode to be connected to the first region 251 of the fifth active layer 25 through this via.

[0176] In some examples, the orthographic projection of the fifth via V5 onto the substrate may lie within the orthographic projection of the second region 262 of the sixth active layer 26 onto the substrate. The third, second, and first insulating layers within the fifth via V5 may be etched away, exposing a portion of the surface of the second region 262 of the sixth active layer 26. The fifth via V5 may be configured to allow a subsequently formed fifth connection electrode to be connected to the second region 262 of the sixth active layer 26 through this via.

[0177] In some examples, the orthographic projection of the sixth via V6 onto the substrate may lie within the orthographic projection of the second region 272 of the seventh active layer 27 onto the substrate. The third, second, and first insulating layers within the sixth via V6 may be etched away, exposing a portion of the surface of the second region 272 of the seventh active layer 27. The sixth via V6 may be configured to allow a subsequently formed fifth connection electrode to be connected to the second region 272 of the seventh active layer 27 through this via.

[0178] In some examples, the orthographic projection of the seventh via V7 onto the substrate may lie within the orthographic projection of the first electrode 281 onto the substrate. The third and second insulating layers within the seventh via V7 may be etched away, exposing a portion of the surface of the first electrode 281. The seventh via V7 may be configured to allow a subsequently formed second connection electrode to be connected to the first electrode 281 through this via.

[0179] In some examples, the orthographic projection of the eighth via V8 onto the substrate may lie within the orthographic projection of the second electrode 282 onto the substrate. The third and second insulating layers within the eighth via V8 may be etched away, exposing a portion of the surface of the second electrode 282. The eighth via V8 may be configured to allow a subsequently formed fourth connection electrode to be connected to the second electrode 282 through this via.

[0180] In some examples, the orthographic projection of the ninth via V9 onto the substrate may lie within the orthographic projection of the initial interconnect block 34-1 of the first initial signal line 34 onto the substrate. The third insulating layer within the ninth via V9 may be etched away, exposing a portion of the surface of the initial interconnect block 34-1. The ninth via V9 may be configured to allow a subsequently formed first interconnect electrode to be connected to the initial interconnect block 34-1 through this via.

[0181] (1-6) Forming a third conductive layer. In some examples, a third conductive thin film is deposited on the substrate on which the aforementioned pattern is formed, and the third conductive thin film is patterned by a patterning process to form a third conductive layer disposed on the third insulating layer. In some examples, the third conductive layer may also be referred to as a first source / drain metal layer.

[0182] Figure 10A for Figure 5 A schematic diagram of the display substrate after the third conductive layer has been formed. Figure 10B for Figure 10A A schematic diagram of the third conductive layer. In some examples, such as... Figure 10A and Figure 10B As shown, the third conductive layer of a single display island area in the first display area may include at least: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, and a sixth connecting electrode 46.

[0183] In some examples, the first connection electrode 41 can be approximately L-shaped. The first connection electrode 41 can be connected to the first region 211 of the first active layer 21 via the first via V1, and can also be connected to the initial connection block 34-1 via the ninth via V9. Since the initial connection block 34-1 is connected to the first initial signal line 34, the first initial signal transmitted by the first initial signal line 34 can be provided to the first transistor T1 and the seventh transistor T7 through the first connection electrode 41.

[0184] In some examples, the second connection electrode 42 can be approximately L-shaped. The second connection electrode 42 can be connected to the second region 212 of the first active layer 21 of the first transistor T1 via the second via V2, and can also be electrically connected to the first electrode plate 281 via the seventh via V7. The second connection electrode 42 can realize the electrical connection between the first transistor, the second transistor, the third transistor, and the first electrode plate 281 of the storage capacitor, and can constitute the first node of the first pixel circuit.

[0185] In some examples, the third connection electrode 43 can be approximately rectangular in shape, such as a rounded rectangle. The third connection electrode 43 can be connected to the first region 241 of the fourth active layer 24 of the fourth transistor T4 via the third via V3.

[0186] In some examples, the fourth connection electrode 44 can be approximately shaped like a figure 7. The fourth connection electrode 44 can be connected to the first region 251 of the fifth active layer 25 of the fifth transistor T5 through the fourth via V4, and can also be connected to the second electrode plate 282 through the eighth via V8.

[0187] In some examples, the fifth connection electrode 45 may be approximately zigzag-shaped. The fifth connection electrode 45 may be connected to the second region 262 of the sixth active layer 26 of the sixth transistor T6 via the fifth via V5, and may also be connected to the second region 272 of the seventh active layer 27 of the seventh transistor T7 via the sixth via V6.

[0188] In some examples, the sixth connection electrode 46 may be generally rectangular, such as a rounded rectangle. The sixth connection electrode 46 may be located to one side of the first connection electrode 41 in the first direction X. The orthographic projection of the sixth connection electrode 46 onto the substrate may partially overlap with the orthographic projections of the first initial signal line 34 and the second scan line 32 onto the substrate. The sixth connection electrode 46 may be configured to be electrically connected to the first power connection line via a subsequently formed fifteenth via.

[0189] (1-7) Forming a fourth insulating layer. In some examples, a fourth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer. The fourth insulating layer may have multiple vias. In some examples, the fourth insulating layer may also be referred to as a passivation layer.

[0190] Figure 11 for Figure 5 A schematic diagram of a display substrate after the fourth insulating layer has been formed. In some examples, the multiple vias of the fourth insulating layer in a single display island area may include at least: eleventh via V11, twelfth via V12, thirteenth via V13, fourteenth via V14, and fifteenth via V15.

[0191] In some examples, the orthographic projection of the eleventh via V11 onto the substrate may lie within the orthographic projection of the first connection electrode 41 onto the substrate. The fourth insulating layer within the eleventh via V11 may be removed, exposing a portion of the surface of the first connection electrode 41. The eleventh via V11 may be configured to allow a subsequently formed first conductive block to be connected to the first connection electrode 41 through this via.

[0192] In some examples, the orthographic projection of the twelfth via V12 onto the substrate may lie within the orthographic projection of the third connection electrode 43 onto the substrate. The fourth insulating layer within the twelfth via V12 may be removed, exposing a portion of the surface of the third connection electrode 43. The twelfth via V12 may be configured to allow subsequently formed data lines to connect to the third connection electrode 43 through this via.

[0193] In some examples, the orthographic projection of the thirteenth via V13 onto the substrate may lie within the orthographic projection of the fourth connection electrode 44 onto the substrate. The fourth insulating layer within the thirteenth via V13 may be removed, exposing a portion of the surface of the fourth connection electrode 44. The thirteenth via V13 may be configured to allow a first power connection portion of a subsequently formed first power connection line to be connected to the fourth connection electrode 44 through this via.

[0194] In some examples, the orthographic projection of the fourteenth via V14 onto the substrate may lie within the orthographic projection of the fifth connection electrode 45 onto the substrate. The fourth insulating layer within the fourteenth via V14 may be removed, exposing a portion of the surface of the fifth connection electrode 45. The fourteenth via V14 may be configured to allow a subsequently formed first anode connection electrode to be connected to the fifth connection electrode 45 through this via.

[0195] In some examples, the orthographic projection of the fifteenth via V15 onto the substrate may lie within the orthographic projection of the sixth connection electrode 46 onto the substrate. The fourth insulating layer within the fifteenth via V15 may be removed, exposing a portion of the surface of the sixth connection electrode 46. The fifteenth via V15 may be configured to allow a second power connection portion of a subsequently formed first power connection line to be connected to the sixth connection electrode 46 through this via.

[0196] (1-8) Forming a transparent conductive layer. In some examples, a transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the transparent conductive film is patterned by a patterning process to form a transparent conductive layer disposed on the fourth insulating layer.

[0197] Figure 12A Figure 5 A schematic diagram of the display substrate after the transparent conductive layer has been formed. Figure 12B for Figure 12A A schematic diagram of the transparent conductive layer. In some examples, such as... Figure 12A and Figure 12B As shown, the transparent conductive layer of a single display island area in the first display area may include at least: three data lines (e.g., data lines 51a, 51b and 51c), three first conductive blocks 52, and three first anode connection electrodes (e.g., first anode connection electrodes 53a, 53b and 53c).

[0198] In some examples, the shape of each data line within the island area can be approximately the same, for example, it can be a zigzag line extending along the second direction Y of the main body. The three data lines 51a, 51b, and 51c can be arranged sequentially along the first direction X. The extension directions of the three data lines 51a, 51b, and 51c can be approximately parallel. Data line 51a can be electrically connected to the third connection electrode 43 of the first first pixel circuit through the twelfth via V12, configured to provide a data signal to the first electrode of the fourth transistor T4 of the first first pixel circuit. Data line 51b can be configured to provide a data signal to the first electrode of the fourth transistor of the second first pixel circuit. Data line 51c can be configured to provide a data signal to the first electrode of the fourth transistor of the third first pixel circuit.

[0199] In some examples, the three first conductive blocks 52 within the island area can have approximately the same shape, for example, all being rectangles, such as rounded rectangles. The first conductive blocks 52 can be electrically connected to the first connecting electrode 41 through the eleventh via V11. The first conductive blocks 52 are not electrically connected to the subsequently fabricated conductive film layer. The first conductive blocks 52 can be connected in parallel with the first connecting electrode 41, which can reduce the resistance of the first connecting electrode 41, thereby ensuring the transmission quality of the first initial signal. In other examples, the first conductive blocks can be omitted.

[0200] In some examples, the three first anode connection electrodes within the island area can have approximately the same shape, for example, they can be approximately rectangular. The first anode connection electrode 53a can be located between data lines 51a and 51b, the first anode connection electrode 53b can be located between data lines 51b and 51c, and the first anode connection electrode 53c can be located on the side of data line 51c away from data line 51b. The first anode connection electrode 53a can be connected to the fifth connection electrode 45 of the first first pixel circuit through the fourteenth via V14. The first anode connection electrode 53a can be configured to be electrically connected to the anode of the subsequently formed first first light-emitting element, thereby realizing the electrical connection between the first first pixel circuit and the first first light-emitting element. The first anode connection electrode 53b can be configured to be electrically connected to the fifth connection electrode of the second first pixel circuit to subsequently realize the electrical connection between the second first pixel circuit and the second first light-emitting element. The first anode connection electrode 53c can be configured to be electrically connected to the fifth connection electrode of the third first pixel circuit to subsequently realize the electrical connection between the third first pixel circuit and the third first light-emitting element.

[0201] In some examples, the transparent conductive layer of the first light-transmitting area between adjacent display island areas in the second direction Y may include at least: multiple first power connection lines (e.g., first power connection lines 76a, 76b, and 76c) and multiple data connection lines (e.g., data connection lines 75a, 75b, and 75c). The multiple data connection lines and the multiple first power connection lines may be arranged at intervals. The shape of the multiple data connection lines and the multiple first power connection lines may be generally a zigzag shape extending along the second direction Y of the main body.

[0202] In some examples, data lines 51a in adjacent display islands in the second direction Y can be connected via data connection line 75a. The first end of data connection line 75a is connected to a data line 51a in one display island, and the second end is connected to a data line 51a in another display island. Data lines 51b in adjacent display islands can be connected via data connection line 75b. Data lines 51c in adjacent display islands can be connected via data connection line 75c. The data connection line and the connected data lines can be an integrated structure interconnected.

[0203] In some examples, the first power connection line may be located between two adjacent data lines. The spacing between the first power connection line 76a and the data line 75a may be smaller than the spacing between the first power connection line 76a and the data line 75b. The first power connection line may extend along the second direction Y into the display island area.

[0204] In some examples, the first power connection line 76a may have a first power connection portion 76a-1 and a second power connection portion 76a-2. The first power connection portion 76a-1 of the first power connection line 76a can be electrically connected to the fourth connection electrode of the first first pixel circuit in the display island area via a thirteenth via V13, thereby configuring it to provide a first voltage signal to the storage capacitor and the fifth transistor of the first first pixel circuit. The second power connection portion 76a-2 of the first power connection line 76a can extend to another display island area and be electrically connected to the sixth connection electrode of the first first pixel circuit in another display island area via a fifteenth via V15. The second power connection line 76b can be configured to provide a first voltage signal to a second first pixel circuit in the display island area. The second power connection line 76c can be configured to provide a first voltage signal to a third first pixel circuit in the display island area.

[0205] (1-9) Forming the fifth insulating layer. In some examples, a fifth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form the fifth insulating layer. The fifth insulating layer may have multiple vias. In some examples, the fifth insulating layer may also be referred to as the first planarization layer.

[0206] Figure 13 for Figure 5 A schematic diagram of a display substrate after the formation of the fifth insulating layer. In some examples, the multiple vias of the fifth insulating layer in a single display island area may include at least: a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, and a nineteenth via V19.

[0207] In some examples, the orthographic projection of the sixteenth via V16 onto the substrate may lie within the orthographic projection of the data line 51a onto the substrate. The fifth insulating layer within the sixteenth via V16 may be removed, exposing a portion of the surface of the data line 51a. The sixteenth via V16 may be configured to allow a subsequently formed second conductive block to be connected to the data line 51a through this via.

[0208] In some examples, the orthographic projection of the seventeenth via V17 onto the substrate may lie within the orthographic projection of the second power connection portion 76a-2 of a first power connection line onto the substrate. The fifth insulating layer within the seventeenth via V17 may be removed, exposing a portion of the surface of the second power connection portion 76a-2 of the first power connection line. The seventeenth via V17 may be configured to allow a subsequently formed second power connection line to connect to the second power connection portion 76a-2 of a first power connection line through this via.

[0209] In some examples, the orthographic projection of the eighteenth via V18 onto the substrate may lie within the orthographic projection of the first power connection portion 76a-1 of another first power connection line onto the substrate. The fifth insulating layer within the eighteenth via V18 may be removed, exposing a portion of the surface of the first power connection portion 76a-1 of the other first power connection line. The eighteenth via V18 may be configured to allow a subsequently formed second power connection line to connect to the first power connection portion 76a-1 of the other first power connection line through this via.

[0210] In some examples, the orthographic projection of the nineteenth via V19 onto the substrate may lie within the orthographic projection of the first anode connection electrode 53a onto the substrate. The fifth insulating layer within the nineteenth via V19 may be removed, exposing a portion of the surface of the first anode connection electrode 53a. The nineteenth via V19 may be configured to allow a subsequently formed second anode connection electrode to be connected to the first anode connection electrode 53a through this via.

[0211] (1-10) Forming a fourth conductive layer. In some examples, a fourth conductive thin film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive thin film is patterned by a patterning process to form a fourth conductive layer disposed on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a second source / drain metal layer.

[0212] Figure 14A for Figure 5 A schematic diagram of the display substrate after the fourth conductive layer has been formed. Figure 14B for Figure 14A A schematic diagram of the fourth conductive layer. In some examples, such as... Figure 14A and Figure 14B As shown, the fourth conductive layer of a single display island area in the first display area may include at least: three second power connection lines (e.g., second power connection lines 61a, 61b and 61c), three second conductive blocks 62, and three second anode connection electrodes (e.g., second anode connection electrodes 63a, 63b and 63c).

[0213] In some examples, the three second conductive blocks 62 and the three second power connection lines can be arranged at intervals in the first direction X. The second anode connection electrode 63a can be located between one of the second conductive blocks 62 and the second power connection line 61a in the first direction X. The second anode connection electrodes 63b and 63c can be located on one side of the second power connection lines 61b and 61c in the second direction Y.

[0214] In some examples, the three second conductive blocks 62 can have roughly the same shape, such as being roughly rectangular, or even rounded rectangles. The three second conductive blocks 62 can be electrically connected to the three data lines one-to-one. For example, one second conductive block 62 can be electrically connected to data line 51a through the sixteenth via V16. By connecting the second conductive blocks 62 in parallel with their corresponding data lines, the resistance of the data lines can be reduced, thereby ensuring the quality of data signal transmission. In other examples, the second conductive blocks can be omitted.

[0215] In some examples, the three second power connection lines can have approximately the same shape, for example, they can be approximately zigzag lines extending along the second direction Y. The extension directions of the three second power connection lines can be approximately parallel. The three second power connection lines can be arranged sequentially in the three first pixel circuits. The second power connection line 61a can be connected to the second power connection portion 76a-2 of one first power connection line 76a through the seventeenth via V17, and can also be connected to the first power connection portion 76a-1 of another first power connection line 76a through the eighteenth via V18. The first power connection line 61a can realize the vertical transmission of the first voltage signal in the first first pixel circuit. The first power connection line 61b can realize the vertical transmission of the first voltage signal in the second first pixel circuit. The first power connection line 61c can realize the vertical transmission of the first voltage signal in the third first pixel circuit.

[0216] In some examples, the shape of the second anode connection electrode 63a can be approximately a zigzag shape extending along the second direction Y of the main body. The second anode connection electrode 63a can be electrically connected to the first anode connection electrode 53a through the nineteenth via V19. In this example, the first anode connection electrode 53a and the second anode connection electrode 63a can achieve the electrical connection between the first first pixel circuit and the first first light-emitting element. In this example, the position of the first light-emitting element can be changed by adjusting the shape and position of the second anode connection electrode 63a.

[0217] In some examples, the second anode connecting electrodes 63b and 63c can have approximately the same shape, for example, both can be approximately rectangular. The second anode connecting electrode 63b can be electrically connected to the first anode connecting electrode 53b to facilitate the subsequent electrical connection between the second first pixel circuit and the second first light-emitting element. The second anode connecting electrode 63c can be electrically connected to the first anode connecting electrode 53c to facilitate the subsequent electrical connection between the third first pixel circuit and the third first light-emitting element.

[0218] (1-11) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer. The sixth insulating layer may have multiple vias. In some examples, the sixth insulating layer may also be referred to as a second planarization layer.

[0219] Figure 15 for Figure 5 A schematic diagram of the display substrate after the formation of the sixth insulating layer. In some examples, the multiple vias of the sixth insulating layer in a single display island area may include at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0220] In some examples, the orthographic projection of the 21st via V21 onto the substrate may lie within the orthographic projection of the second anode connection electrode 63a onto the substrate. The sixth insulating layer within the 21st via V21 may be removed, exposing a portion of the surface of the second anode connection electrode 63a. The 21st via V21 may be configured to allow the anode of a subsequently formed first light-emitting element to be connected to the second anode connection electrode 63a through this via.

[0221] In some examples, the orthographic projection of the 22nd via V22 onto the substrate may lie within the orthographic projection of the second anode connection electrode 63b onto the substrate. The sixth insulating layer within the 22nd via V22 may be removed, exposing a portion of the surface of the second anode connection electrode 63b. The 22nd via V22 may be configured to allow the anode of a subsequently formed second first light-emitting element to be connected to the second anode connection electrode 63b through this via.

[0222] In some examples, the orthographic projection of the 23rd via V23 onto the substrate may lie within the orthographic projection of the second anode connection electrode 63c onto the substrate. The sixth insulating layer within the 23rd via V23 may be removed, exposing a portion of the surface of the second anode connection electrode 63c. The 23rd via V23 may be configured to allow the anode of a subsequently formed first light-emitting element to be connected to the second anode connection electrode 63c through this via.

[0223] In some examples, after the formation of the sixth insulating layer, the first wiring area may include: a substrate, a first insulating layer, a first conductive layer (e.g., including a first scan connection line 71, a second scan connection line 72 and a light emission control connection line 73) sequentially disposed on the substrate, a second insulating layer, a second conductive layer (e.g., including a first initial connection line 74), a third insulating layer, a fourth insulating layer, a fifth insulating layer and a sixth insulating layer.

[0224] In some examples, after the formation of the sixth insulating layer, the first light-transmitting region may include: a substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a transparent conductive layer (e.g., including a first power connection line and a data connection line), a fifth insulating layer, and a sixth insulating layer disposed sequentially on the substrate.

[0225] In some examples, after the formation of the sixth insulating layer, the second light-transmitting region may include: a substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer disposed sequentially on the substrate.

[0226] In this example, the first signal trace connecting the first pixel circuits within adjacent display island areas may include: a first scan connection line, a second scan connection line, and a light emission control connection line located on the first conductive layer, and a first initial connection line located on the second conductive layer. The second signal trace connecting the first pixel circuits within adjacent display island areas may include: a first power connection line and a data connection line located on the transparent conductive layer.

[0227] (1-12) Forming the anode layer. In some examples, an anode thin film is deposited on the substrate on which the aforementioned pattern is formed, and the anode thin film is patterned by a patterning process to form the anode layer.

[0228] Figure 16A for Figure 5 A schematic diagram of the display substrate after the anode layer has been formed. Figure 16B for Figure 16A A schematic diagram of the intermediate anode layer. In some examples, such as... Figure 16A and Figure 16B As shown, the anode layer of a single display island area may include at least three anodes (e.g., anodes 131a, 131b, and 131c).

[0229] In some examples, anodes 131a, 131b, and 131c can have approximately the same shape, for example, all being circular or elliptical. The area of ​​anode 131a can be smaller than the area of ​​anode 131b, and smaller than the area of ​​anode 131c. The areas of anodes 131b and 131c can be approximately the same.

[0230] In some examples, an anode connection block 131a-1 may be provided on the side of anode 131a near anode 131c. The anode connection block 131a-1 may be disposed in the first pixel circuit. A first end of the anode connection block 131a-1 is connected to anode 131a, and a second end extends away from anode 131a along a first direction X. The anode connection block 131a-1 may be electrically connected to the second anode connection electrode 63a through a twenty-first via V21. The anode connection block 131a-1 and anode 131a may be an integrally connected structure.

[0231] In some examples, an anode connection block 131b-1 may be provided on the side of anode 131b near anode 131c. At least a portion of the anode connection block 131b-1 may be disposed in the second first pixel circuit. A first end of the anode connection block 131b-1 is connected to anode 131b, and a second end extends away from anode 131b along a first direction X. The anode connection block 131b-1 may be electrically connected to the second anode connection electrode 63b through a twenty-second via V22. The anode connection block 131b-1 and anode 131b may be an integral structure interconnected.

[0232] In some examples, an anode connecting block 131c-1 may be provided on the side of anode 131c near anode 131b. The anode connecting block 131c-1 may be located in the third first pixel circuit. A first end of the anode connecting block 131c-1 is connected to anode 131c, and a second end extends along the second direction Y away from anode 131c. The anode connecting block 131c-1 may be electrically connected to the second anode connecting electrode 63c via the twenty-third via V23. The anode connecting block 131c-1 and anode 131c may be an integrally connected structure.

[0233] (1-13) Forming the pixel definition layer. In some examples, a pixel definition film is coated on the substrate on which the aforementioned pattern is formed, and the pixel definition layer (PDL) is formed by masking, exposure and development processes.

[0234] In some examples, such as Figure 5 As shown, the pixel definition layer of a single display island area can form three pixel openings (e.g., including a first pixel opening OP1, a second pixel opening OP2, and a third pixel opening OP3). The first pixel opening OP1 can expose a portion of the surface of the anode 131a, the second pixel opening OP2 can expose a portion of the surface of the anode 131b, and the third pixel opening OP3 can expose a portion of the surface of the anode 131c.

[0235] In some examples, the pixel definition layer of the first display area can be made of a black material. A black pixel definition layer can absorb stray light, reducing diffraction effects and optimizing image quality. For example, the pixel definition layers of the first and second light-transmitting areas can be removed to ensure light transmittance. The pixel definition layer of the first wiring area can be retained to shield the wiring within the first wiring area, preventing diffraction during light transmission. However, this embodiment is not limited to this. In other examples, the display substrate can achieve shielding of the first wiring area by setting a black matrix (BM). In still other examples, the display substrate can be provided with a bottom shielding metal (BSM) to shield the display island area and the first wiring area; the bottom shielding metal can be located on the side of the semiconductor layer closest to the substrate.

[0236] (1-14) Forming an organic light-emitting layer, a cathode layer, and an encapsulation layer. In some examples, organic light-emitting layers can be formed within the aforementioned plurality of pixel openings, and the organic light-emitting layers are connected to the corresponding anodes. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned using a patterning process to form a cathode layer, which can be electrically connected to the organic light-emitting layer and the second power line, respectively. Subsequently, an encapsulation layer is formed on the cathode layer, and the encapsulation layer may include a stacked structure of inorganic / organic / inorganic materials.

[0237] In some examples, the first, second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of these metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The transparent conductive layer can be made of transparent conductive materials, such as indium tin oxide (ITO). The first to fourth insulating layers can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The fifth and sixth insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer can be made of reflective materials such as metal, and the cathode layer can be made of transparent conductive materials. However, this embodiment is not limited to this.

[0238] In some examples, such as Figure 1As shown, the second display area A2 may include a plurality of second pixel circuits 12 and a plurality of second light-emitting elements 14. At least one second pixel circuit 12 and at least one second light-emitting element 14 may be electrically connected, and at least one second pixel circuit 12 may be configured to drive the electrically connected at least one second light-emitting element 14 to emit light. For example, the plurality of second pixel circuits 12 and the plurality of second light-emitting elements 14 may be electrically connected in a one-to-one correspondence. The plurality of second light-emitting elements 14 in the second display area A2 may include: a second light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and a second light-emitting element emitting a third color light. The arrangement of the plurality of second light-emitting elements may be similar to the arrangement of the plurality of first light-emitting elements, and therefore will not be described in detail here. In some examples, the orthographic projection of the light-emitting area of ​​the second light-emitting element onto the substrate may overlap with the orthographic projection of the electrically connected second pixel circuit onto the substrate. In some examples, adjacent second pixel circuits in the second display area may not need to be electrically connected through traces in a transparent conductive layer, and the second display area may not need to be provided with a transparent conductive layer. The remaining film layer structure of the second display area may be similar to the film layer structure of the first display area, and therefore will not be described in detail here.

[0239] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some examples, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0240] In some implementations, a single display island in the first display area can be equipped with a first light-emitting element and a first pixel circuit, with the first pixel circuit located below the first light-emitting element to maximize the light-transmitting area. However, when a single first pixel circuit is used in the display island, the spacing between the display islands is small, limiting the winding space for the first and second signal traces electrically connecting adjacent first pixel circuits. This results in longer first and second signal traces with smaller line widths and spacing. When the first and second signal traces are made of transparent conductive materials, taking ITO as an example, the higher sheet resistance of ITO leads to a larger load on the longer first and second signal traces, affecting the display effect and causing display defects. Compared to the approach of setting a first light-emitting element and a first pixel circuit in a single display island area and having the first light-emitting element cover the first pixel circuit, the display substrate provided in this embodiment can increase the space between adjacent display island areas by centrally arranging multiple first pixel circuits and multiple first light-emitting elements in the display island area. This increases the degree of freedom in arranging the second signal traces located in the transparent conductive layer, increases the wiring space of the second signal traces, thereby increasing the linewidth of the second signal traces, reducing the resistance of the second signal traces, avoiding display defects caused by the load of the second signal traces, and supporting higher refresh rates.

[0241] In this embodiment, the first signal trace of the display substrate is made of a metallic material, which reduces the mask cost of using a transparent conductive layer and lowers the lateral display defects caused by the resistance of the first signal trace. Furthermore, by using a metallic material for the first signal trace, the spacing between adjacent display island areas in the first direction can be reduced. While maintaining the overall size of the first pixel circuit, the size of the display island area along the first direction can be increased to reduce the size along the second direction, thereby increasing the spacing between adjacent display island areas along the second direction and increasing the light transmittance of the second light-transmitting area. Moreover, by using a metallic material for the first signal trace, the drilling process between adjacent display island areas in the first direction can be avoided, reducing the space occupied by the first signal trace and lowering costs.

[0242] Furthermore, in the scheme where a first light-emitting element and a first pixel circuit are arranged in a single display island area, with the first light-emitting element covering the first pixel circuit, there are many protruding display islands and recessed slits, which can easily aggravate the light diffraction effect in the first display area and reduce the image quality. The display substrate provided in this embodiment, by centrally arranging multiple first pixel circuits in the display island area, can reduce the number of islands and slits, increase the size of the light-transmitting area between adjacent display island areas, effectively reduce the light diffraction effect, and facilitate the rounding of the edges of the display island areas.

[0243] Figure 17AThis is another schematic diagram of the first display area according to at least one embodiment of the present disclosure. In some examples, such as Figure 17A As shown, in a plane parallel to the display substrate, the first display area A1 may include an array of multiple display island areas A11. The multiple display island areas A11 may be arranged in an array along a first direction X and a second direction Y. The shapes of the multiple display island areas A11 may be approximately the same. For example, the display island areas may be irregular shapes with smooth edges. The smooth edges of the display island areas A11 can reduce light diffraction effects, thus helping to improve the shooting effect.

[0244] In some examples, such as Figure 17A As shown, a first light-transmitting area A121 can be provided between adjacent display island areas A11. The first light-transmitting area A121 can be located between adjacent display island areas A11 along the second direction Y. Multiple first light-transmitting areas A121 can be formed independently. Adjacent first light-transmitting areas A121 may not be connected. Multiple first light-transmitting areas A121 can be arranged in an array along the first direction X and the second direction Y. For example, the first light-transmitting area A121 can be elliptical, or it can be a rounded polygon or other shapes.

[0245] In some examples, such as Figure 17A As shown, a wiring area can also be provided between adjacent display island areas A11. For example, the wiring area may include: a first wiring area A131 and a second wiring area A132. The first wiring area A131 can be located between adjacent display island areas A11 along the first direction X. The second wiring area A132 can be located between adjacent first light-transmitting areas A121 along the first direction X. The first wiring area A131 and the second wiring area A132 can be connected in the second direction Y. Multiple second wiring areas A132 and multiple first light-transmitting areas A121 can be arranged at intervals along the first direction X. Adjacent display island areas A11 along the first direction X can be connected through the first wiring area A131, and adjacent display island areas A11 along the second direction Y can be connected through the second wiring area A132.

[0246] Figure 17B This is another schematic diagram of the first display area according to at least one embodiment of the present disclosure. In some examples, such as Figure 17BAs shown, in a plane parallel to the display substrate, the first display area A1 may include: a plurality of display island areas A11 arranged in an array, a first light-transmitting area A121 and a second light-transmitting area A122 located between adjacent display island areas A11, and a first wiring area A131 and a second wiring area A132 located between adjacent display island areas A11. The first light-transmitting area A121 may be located between adjacent display island areas A11 along the second direction Y, and the second light-transmitting area A122 may be located between adjacent display island areas A11 along the first direction X. The second light-transmitting area A122 may be surrounded by the first wiring area A131, or it may be surrounded by the first wiring area A131 and the display island area A11. The first light-transmitting area A121 may be surrounded by the second wiring area A132 and the display island area A11. The shapes of the first light-transmitting area A121 and the second light-transmitting area A122 may be substantially the same, for example, both may be elliptical. The area of ​​a single first light-transmitting area A121 can be larger than the area of ​​a single second light-transmitting area A122. However, this embodiment is not limited in this respect. For example, the shapes of the first and second light-transmitting areas can be different, such as different shapes with smooth edges. A description of the second light-transmitting area can be found in the foregoing embodiment.

[0247] Figure 17C This is another schematic diagram of the first display area according to at least one embodiment of the present disclosure. In some examples, such as Figure 17C As shown, in a plane parallel to the display substrate, the first display area A1 may include: a plurality of display island areas A11 arranged in an array, a first light-transmitting area A121 and a second light-transmitting area A122 located between adjacent display island areas A11, and a first wiring area A131 and a second wiring area A132 located between adjacent display island areas A11. The shapes of the first light-transmitting area A121 and the second light-transmitting area A122 may be substantially the same, for example, both may be circular. However, this embodiment is not limited to this. In other examples, the shapes of the first light-transmitting area and the second light-transmitting area may be rounded rectangles, rounded polygons, or other shapes with smooth edges. Further descriptions of the display substrate of this example can be found in the description of the foregoing embodiments.

[0248] Figure 18 for Figure 17A A partial top-view diagram of the central region S2. Figure 18 The diagram illustrates four display islands A11 arranged in a 2×2 array.

[0249] In some examples, the circuit structure layer of the first display area may include, in a direction perpendicular to the display substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. A first insulating layer may be disposed between the semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first and second conductive layers, a third insulating layer may be disposed between the second and third conductive layers, a fourth insulating layer and a fifth insulating layer may be disposed between the third and fourth conductive layers, and a sixth insulating layer may be disposed on the side of the fourth conductive layer away from the substrate.

[0250] The structure and fabrication process of the display substrate in this example are described below by way of example. In some examples, the fabrication process of the display substrate in this example may include the following operations.

[0251] (2-1) Provide a substrate.

[0252] (2-2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on a substrate, and the semiconductor thin film is patterned using a patterning process to form a semiconductor layer disposed on the substrate. In some examples, the semiconductor layer of a single display island region may include at least: a first active layer of the first transistor of the three first pixel circuits, a second active layer of the second transistor, a third active layer of the third transistor, a fourth active layer of the fourth transistor, a fifth active layer of the fifth transistor, a sixth active layer of the sixth transistor, and a seventh active layer of the seventh transistor. The description of the semiconductor layer of the display substrate in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0253] (2-3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The first conductive film is patterned by a patterning process to form a first insulating layer disposed on the semiconductor layer and a first conductive layer disposed on the first insulating layer.

[0254] Figure 19 for Figure 18 A schematic diagram of a display substrate after the first conductive layer has been formed. In some examples, such as... Figure 19As shown, the first conductive layer of a single display island area may include at least: a first scan line 31, a second scan line 32, a light emission control line 33, and a first electrode 281 of the storage capacitors for the three first pixel circuits. The first conductive layer of the first trace area between adjacent display island areas in the first direction X may include at least: a first scan connection line 71, a second scan connection line 72, and a light emission control connection line 73. The shapes of the first scan connection line 71, the second scan connection line 72, and the light emission control connection line 73 may all be straight lines with their main portions extending along the first direction X. The remaining description of the first conductive layer of the display substrate in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0255] (2-4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second conductive film is patterned by a patterning process to form a second insulating layer disposed on the first conductive layer and a second conductive layer disposed on the second insulating layer.

[0256] Figure 20 for Figure 18 A schematic diagram of a display substrate after the second conductive layer has been formed. In some examples, such as... Figure 20 As shown, the second conductive layer of a single display island area may include at least: a first initial signal line 34, and the second electrode 282 of the storage capacitors for the three first pixel circuits. The second conductive layer of the first trace area between adjacent display island areas in the first direction X may include at least: a first initial connection line 74. The description of the second conductive layer of the display substrate in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0257] (2-5) Forming a third insulating layer and a third conductive layer. In some examples, a third insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the third insulating film is patterned by a patterning process to form a third insulating layer. The third insulating layer may have multiple vias. The description of the third insulating layer in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0258] In some examples, a third conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer disposed on the third insulating layer.

[0259] Figure 21A for Figure 18 A schematic diagram of the display substrate after the third conductive layer has been formed. Figure 21B for Figure 21A A schematic diagram of the third conductive layer. In some examples, such as... Figure 21A and Figure 21BAs shown, the third conductive layer of a single display island area in the first display area may include at least: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, and a sixth connecting electrode 46. The description of the third conductive layer in this example can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0260] (2-6) Forming the fourth and fifth insulating layers. In some examples, a fourth insulating film is deposited on the substrate on which the aforementioned structure is formed, followed by coating with a fifth insulating film. The fifth and fourth insulating films are then patterned using a patterning process to form the fourth and fifth insulating layers. The fifth and fourth insulating layers may have multiple vias.

[0261] Figure 22 This is a schematic diagram of the display substrate after the fifth insulating layer has been formed, as shown in Figure 17. In some examples, the multiple vias of the fifth insulating layer in a single display island area may include at least: via V31 (thirty-first), via V32 (thirty-second), via V33 (thirty-third), and via V34 (thirty-fourth).

[0262] In some examples, the orthographic projection of the 31st via V31 onto the substrate may lie within the orthographic projection of the third connection electrode 43 onto the substrate. The fifth and fourth insulating layers within the 31st via V31 may be removed, exposing a portion of the surface of the third connection electrode 43. The 31st via V31 may be configured to allow subsequently formed data lines to connect to the third connection electrode 43 through this via.

[0263] In some examples, the orthographic projection of the 32nd via V32 onto the substrate may lie within the orthographic projection of the 44th connection electrode onto the substrate. The 5th and 4th insulating layers within the 32nd via V32 may be removed, exposing a portion of the surface of the 44th connection electrode. The 32nd via V32 may be configured to allow a subsequently formed 2nd power connection line to be connected to the 44th connection electrode through this via.

[0264] In some examples, the orthographic projection of the 33rd via V33 onto the substrate may lie within the orthographic projection of the 5th connection electrode 45 onto the substrate. The 5th and 4th insulating layers within the 33rd via V33 may be removed, exposing a portion of the surface of the 5th connection electrode 45. The 33rd via V33 may be configured to allow a subsequently formed 2nd anode connection electrode to be connected to the 5th connection electrode 45 through this via.

[0265] In some examples, the orthographic projection of the 34th via V34 onto the substrate may lie within the orthographic projection of the 6th connection electrode 46 onto the substrate. The fifth and fourth insulating layers within the 34th via V34 may be removed, exposing a portion of the surface of the 6th connection electrode 46. The 34th via V34 may be configured to allow a subsequently formed second power connection line to be connected to the 6th connection electrode 46 through this via.

[0266] (2-7) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer disposed on the fifth insulating layer.

[0267] Figure 23A for Figure 18 A schematic diagram of the display substrate after the fourth conductive layer has been formed. Figure 23B for Figure 23A A schematic diagram of the fourth conductive layer. In some examples, such as... Figure 23A and Figure 23B As shown, the fourth conductive layer of a single display island area in the first display area may include at least: three data lines (e.g., data lines 51a, 51b and 51c), three second power connection lines (e.g., second power connection lines 61a, 61b and 61c), and three second anode connection electrodes (e.g., second anode connection electrodes 63a, 63b and 63c).

[0268] In some examples, data lines 51a, 51b, and 51c can be arranged sequentially along a first direction X. The shape of data line 51a can be approximately a zigzag line with its main body extending along a second direction Y. Data line 51a can be electrically connected to the third connection electrode 43 of the first first pixel circuit through a thirty-first via V31, configured to provide a data signal to the first electrode of the fourth transistor T4 of the first first pixel circuit.

[0269] In some examples, the data line 51b may be approximately a zigzag shape with its main body extending along the second direction Y. The data line 51b may be configured to provide a data signal to the first terminal of the fourth transistor of the second first pixel circuit. A first data connection portion 51b-1 may be provided on the side of the data line 51b near the display island area of ​​the previous row. The first data connection portion 51b-1 may extend at least along the first direction X. The first data connection portion 51b-1 may extend in the first direction X toward the data line 51a. The first data connection portion 51b-1 and the data line 51b may be an integrally connected structure.

[0270] In some examples, the data cable 51b may have a second data connection portion 51b-2 on the side near the display island area of ​​the next row. The second data connection portion 51b-2 may extend along a third direction F1. The third direction F1 may intersect both the first direction X and the second direction Y. For example, the clockwise angle between the third direction F1 and the first direction X may be approximately 40 to 60 degrees, such as approximately 45 degrees. The second data connection portion 51b-2 and the data cable 51b may be an integral structure that is interconnected.

[0271] In some examples, the data line 51c can be roughly shaped as a broken line extending along the second direction Y of the main body. The data line 51c can be configured to provide a data signal to the first terminal of the fourth transistor of the third first pixel circuit. A third data connection portion 51c-1 can be provided on the side of the data line 51c near the display island area of ​​the previous row. The third data connection portion 51c-1 can extend along the third direction F1 away from the data line 51c. The third data connection portion 51c-1 and the data line 51c can be an integral structure interconnected.

[0272] In some examples, the data line 51c may have a fourth data connection portion 51c-2 on the side near the display island area of ​​the next row. The fourth data connection portion 51c-2 may extend at least along the first direction X. The fourth data connection portion 51c-2 may extend in the first direction X away from the data line 51b. The fourth data connection portion 51c-2 and the data line 51c may be an integral structure that is interconnected.

[0273] In some examples, the second power connection lines 61a, 61b, and 61c can be arranged sequentially along the first direction X. The second power connection line 61a can be located between data lines 51a and 51b, the second power connection line 61b can be located between data lines 51b and 51c, and the second power connection line 61c can be located on the side of data line 51c away from data line 51b. Within the display island area, the second power connection lines and data lines can be arranged alternately.

[0274] In some examples, the shape of the second power connection line 61a can be approximately a zigzag line extending along the second direction Y. The extension direction of the second power connection line 61a can be approximately the same as the extension direction of the data line 51a. The second power connection line 61a can be electrically connected to the fourth connection electrode 44 in the first first pixel circuit through the thirty-second via V32, and can also be electrically connected to the sixth connection electrode 46 in the first first pixel circuit through the thirty-fourth via V34. The second power connection line 61a can be configured to provide a first voltage signal to the first first pixel circuit.

[0275] In some examples, the shape of the second power connection line 61b can be approximately a zigzag line extending along the second direction Y of the main body. The extension direction of the second power connection line 61b can be approximately the same as the extension direction of the data line 51b. The second power connection line 61b can be configured to provide a first voltage signal to the second first pixel circuit.

[0276] In some examples, the second power connection line 61b may have a first power extension 61b-1 on the side near the upper row of the display island area. The first power extension 61b-1 may extend at least along the first direction X. The first power extension 61b-1 may extend towards the side near the data line 51c in the first direction X. The first data connection portion 51b-1 of the data line 51b and the first power extension 61b-1 may extend in opposite directions in the first direction X. The first power extension 61b-1 and the second power connection line 61b may be an integral structure that is interconnected.

[0277] In some examples, the second power connection line 61b may have a second power extension 61b-2 on the side near the next row of the display island area. The second power extension 61b-2 may extend along the fourth direction F2. The fourth direction F2 may intersect both the first direction X and the second direction Y. For example, the clockwise angle between the fourth direction F2 and the first direction X may be approximately 120 to 150 degrees, such as approximately 135 degrees. The fourth direction F2 may intersect the third direction F1; for example, the fourth direction F2 may be perpendicular to the third direction F1. The second power extension 61b-2 may extend along the side near the data line 51c towards the fourth direction F2. The second power extension 61b-2 and the second power connection line 61b may be an integral structure interconnected.

[0278] In some examples, the second power connection line 61c may be approximately zigzag-shaped, with the main body extending along the second direction Y. The extension direction of the second power connection line 61c may be approximately the same as the extension direction of the data line 51c. The second power connection line 61c may be configured to provide a first voltage signal to the third first pixel circuit.

[0279] In some examples, the second power connection line 61c may have a third power extension 61c-1 on the side away from the data line 51c. The third power extension 61c-1 may extend along the first direction X toward the side away from the data line 51c. The third power extension 61c-1 and the second power connection line 61c may be an integral structure that is interconnected.

[0280] In some examples, the shape of the second anode connecting electrode 63a can be approximately a zigzag shape extending along the second direction Y of the main body. The second anode connecting electrode 63a can be electrically connected to the fifth connecting electrode 45 through the thirty-third via V33. In this example, the electrical connection between the first first pixel circuit and the first first light-emitting element can be achieved through the second anode connecting electrode 63a. In this example, the position of the first light-emitting element can be changed by adjusting the shape and position of the second anode connecting electrode 63a.

[0281] In some examples, the second anode connecting electrodes 63b and 63c can have approximately the same shape, for example, both can be approximately rectangular. The second anode connecting electrode 63b can be electrically connected to the sixth transistor of the second first pixel circuit to enable subsequent electrical connection between the second first pixel circuit and the second first light-emitting element. The second anode connecting electrode 63c can be electrically connected to the sixth transistor of the third first pixel circuit to enable subsequent electrical connection between the third first pixel circuit and the third first light-emitting element.

[0282] In some examples, the fourth conductive layer of the second trace area between adjacent display island areas along the second direction Y may include at least: multiple first power connection lines (e.g., first power connection lines 76a, 76b, and 76c) and multiple data connection lines (e.g., data connection lines 75a, 75b, and 75c). The multiple data connection lines and the multiple first power connection lines may be arranged at intervals. The data connection lines 75a, 75b, and 75c, and the first power connection lines 76a, 76b, and 76c may be generally straight lines extending along the second direction Y.

[0283] In some examples, a second routing area may contain three first power connection lines and three data connection lines. For instance, the second routing area between the m-th column display island and the (m+1)-th column display island may include: a first power connection line 76b connected to the first pixel circuit of the second column in the m-th column display island; data connection lines 75c and 76c connected to the first pixel circuit of the third column in the m-th column display island; data connection lines 75a and 76a connected to the first pixel circuit of the first column in the (m+1)-th column display island; and data connection line 75b connected to the first pixel circuit of the second column in the (m+1)-th column display island. The first power connection lines 76b, 75c, 75a, 76a, and 75b within the second routing area may be arranged sequentially along a first direction X.

[0284] In some examples, data lines 51a within the adjacent display island area in the second direction Y can be connected via data connection line 75a. The first end of data connection line 75a can be connected to data line 51a within the k-th row, m-th column display island area, and the second end can be connected to data line 51a within the (k+1)-th row, m-th column display island area. Data line 51a and data connection line 75a can be an interconnected, integrated structure.

[0285] In some examples, data lines 51b within the adjacent display island area in the second direction Y can be connected via data connection line 75b. The first end of data connection line 75b can be connected to the second data connection portion 51b-2 of data line 51b within the k-th row, m-th column display island area, and the second end can be connected to the first data connection portion 51b-1 of data line 51b within the k+1-th row, m-th column display island area. Data lines 51b and data connection line 75b can be an interconnected, integrated structure.

[0286] In some examples, the data lines 51c within the adjacent display island area in the second direction Y can be connected via data connection lines 75c. The first end of the data connection line 75c can be connected to the fourth data connection portion 51c-2 of the data line 51c in the k-th row and m-th column display island area, and the second end can be connected to the third data connection portion 51c-1 of the data line 51c in the (k+1)-th row and m-th column display island area. The data lines 51c and data connection lines 75c can be an interconnected, integrated structure.

[0287] In some examples, the second power connection line 61a within the adjacent display island area in the second direction Y can be connected via the first power connection line 76a. The first end of the first power connection line 76a can be connected to the second power connection line 61a within the k-th row and m-th column display island area, and the second end can be connected to the second power connection line 61a within the (k+1)-th row and m-th column display island area. The second power connection line 61a and the first power connection line 76a can be an interconnected integral structure.

[0288] In some examples, the second power connection line 61b within the adjacent display island area in the second direction Y can be connected via the first power connection line 76b. The first end of the first power connection line 76b can be connected to the second power extension 61b-2 of the second power connection line 61b within the k-th row, m-th column display island area, and the second end can be connected to the first power extension 61b-1 of the second power connection line 61b within the k+1-th row, m-th column display island area. The second power connection line 61b and the first power connection line 76b can be an integrally connected structure.

[0289] In some examples, the second power connection line 61c within the adjacent display island area in the second direction Y can be connected via the first power connection line 76c. The first power connection line 76c extends from the second wiring area to the first wiring area between adjacent display island areas in the first direction X. The shape of the first power connection line 76c can be a zigzag line with its main body extending along the second direction Y. The portion of the first power connection line 76c in the second wiring area can be a straight line extending along the second direction Y. The first power connection line 76c can be connected to the third power extension 61c-1 of the second power connection line 61c in the first wiring area. The first power connection line 76c and the second power connection line 61c can be an integral structure interconnected.

[0290] In this example, the data line can be connected to the data connection line through data connection parts with different extension directions, and the second power connection line can be connected to the first power connection line through a power extension part with a different extension direction. This can help to smooth the edges of the display island area and improve the diffraction of the display substrate.

[0291] (2-8) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer.

[0292] Figure 24 for Figure 18 A schematic diagram of the display substrate after the formation of the sixth insulating layer. In some examples, the multiple vias of the sixth insulating layer in a single display island area may include at least: via V35 (thirty-fifth via), via V36 (thirty-sixth via), and via V37 (thirty-seventh via).

[0293] In some examples, the orthographic projection of the 35th via V35 onto the substrate may lie within the orthographic projection of the second anode connection electrode 63a onto the substrate. The sixth insulating layer within the 35th via V35 may be removed, exposing a portion of the surface of the second anode connection electrode 63a. The 35th via V35 may be configured to allow the anode of a subsequently formed first light-emitting element to be connected to the second anode connection electrode 63a through this via.

[0294] In some examples, the orthographic projection of the thirty-sixth via V36 onto the substrate may lie within the orthographic projection of the second anode connection electrode 63b onto the substrate. The sixth insulating layer within the thirty-sixth via V36 may be removed, exposing a portion of the surface of the second anode connection electrode 63b. The thirty-sixth via V36 may be configured to allow the anode of a subsequently formed first light-emitting element to be connected to the second anode connection electrode 63b through this via.

[0295] In some examples, the orthographic projection of the thirty-seventh via V37 onto the substrate may lie within the orthographic projection of the second anode connection electrode 63c onto the substrate. The sixth insulating layer within the thirty-seventh via V37 may be removed, exposing a portion of the surface of the second anode connection electrode 63c. The thirty-seventh via V37 may be configured to allow the anode of a subsequently formed first light-emitting element to be connected to the second anode connection electrode 63c through this via.

[0296] In some examples, after the formation of the sixth insulating layer, the first light-transmitting region may include: a substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer sequentially disposed on the substrate. The first wiring region may include: a substrate, a first insulating layer, a first conductive layer (e.g., including a first scan connection line 71, a second scan connection line 72, and a light-emitting control connection line 73), a second insulating layer, a second conductive layer (e.g., including a first initial connection line 74), a third insulating layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer (e.g., including a first power connection line 76c), and a sixth insulating layer sequentially disposed on the substrate. The second wiring region may include: a substrate, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer (e.g., including data connection lines 75a, 75b, and 75c, and a first power connection line 76a, 76b, and 76c), and a sixth insulating layer sequentially disposed on the substrate.

[0297] In this example, the first signal trace connecting the first pixel circuits within adjacent display island areas may include: a first scan connection line, a second scan connection line, and a light emission control connection line located on the first conductive layer, and a first initial connection line located on the second conductive layer. The second signal trace connecting the first pixel circuits within adjacent display island areas may include: a first power connection line and a data connection line located on the fourth conductive layer.

[0298] In other examples, a second light-transmitting area can be formed between adjacent display island areas along the first direction X. For example, the edge of the second light-transmitting area can be defined by a first scan connection line, a light emission control connection line, a first power connection line 76c, and a data line 51a. By bending these lines, a smooth edge of the second light-transmitting area can be achieved to improve diffraction.

[0299] (2-9) Forming the anode layer. In some examples, an anode thin film is deposited on the substrate on which the aforementioned pattern is formed, and the anode thin film is patterned by a patterning process to form the anode layer.

[0300] Figure 25 for Figure 18 A schematic diagram of a display substrate after the anode layer has been formed. In some examples, such as... Figure 25As shown, the anode layer of a single display island area may include at least three anodes (e.g., anodes 131a, 131b, and 131c).

[0301] In some examples, an anode connection block 131a-1 may be provided on the side of anode 131a near anode 131c. The anode connection block 131a-1 may be located in the first pixel circuit. A first end of the anode connection block 131a-1 is connected to anode 131a, and a second end extends away from anode 131a along a first direction X. The anode connection block 131a-1 may be electrically connected to the second anode connection electrode 63a through a thirty-fifth via V35. The anode connection block 131a-1 and anode 131a may be an integrally connected structure.

[0302] In some examples, an anode connection block 131b-1 may be provided on the side of anode 131b near anode 131c. At least a portion of the anode connection block 131b-1 may be disposed in the second first pixel circuit. A first end of the anode connection block 131b-1 is connected to anode 131b, and a second end extends away from anode 131b along a first direction X. The anode connection block 131b-1 may be electrically connected to the second anode connection electrode 63b through a thirty-sixth via V36. The anode connection block 131b-1 and anode 131b may be an integral structure interconnected.

[0303] In some examples, an anode connection block 131c-1 may be provided on the side of anode 131c near anode 131b. The anode connection block 131c-1 may be located in the third first pixel circuit. A first end of the anode connection block 131c-1 is connected to anode 131c, and a second end extends away from anode 131c along the second direction Y. The anode connection block 131c-1 may be electrically connected to the second anode connection electrode 63c via the thirty-seventh via V37. The anode connection block 131c-1 and anode 131c may be an integrally connected structure.

[0304] (2-10) The pixel definition layer, organic light-emitting layer, cathode layer, and encapsulation layer are formed sequentially. The fabrication process of the pixel definition layer, organic light-emitting layer, cathode layer, and encapsulation layer in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0305] In this embodiment, both the first and second signal traces of the display substrate are made of metal, which reduces the material and mask costs associated with using a transparent conductive layer. It also reduces lateral and longitudinal display defects caused by the high resistance of the first and second signal traces, simplifies the manufacturing process, and avoids excessive aperture operations. Furthermore, in this example, multiple first signal traces (e.g., including a first scan connection line, a second scan connection line, a light emission control connection line, and a first initial connection line) are straight lines extending along the first direction X, and multiple second signal traces (e.g., including a first power connection line and a data connection line) are straight lines extending along the second direction Y. This saves space, increases the light transmittance of the light-transmitting area, and reduces light diffraction.

[0306] The display substrate of this embodiment can reduce the number of islands and slits by arranging multiple first pixel circuits and multiple first light-emitting elements in the display island area, which can effectively reduce the light diffraction effect and facilitate the rounding of the edges of the display island area.

[0307] Figure 26 for Figure 17A Another partial top view of the central region S2. Figure 26 The diagram illustrates four display islands A11 arranged in a 2×2 array. Figure 27 for Figure 26 A schematic diagram of the display substrate after the second conductive layer has been formed. Figure 28A for Figure 26 A schematic diagram of the display substrate after the third conductive layer has been formed. Figure 28B for Figure 28A A schematic diagram of the third conductive layer in the image. Figure 29 for Figure 26 A schematic diagram of the display substrate after the fifth insulating layer has been formed. Figure 30A for Figure 26 A schematic diagram of the display substrate after the fourth conductive layer has been formed. Figure 30B for Figure 30A A schematic diagram of the fourth conductive layer in the image.

[0308] In some examples, the circuit structure layer of the first display area, in a direction perpendicular to the display substrate, may include: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. A first insulating layer may be disposed between the semiconductor layer and the first conductive layer; a second insulating layer may be disposed between the first and second conductive layers; a third insulating layer may be disposed between the second and third conductive layers; a fourth and a fifth insulating layer may be disposed between the third and fourth conductive layers; and a sixth insulating layer may be disposed on the side of the fourth conductive layer away from the substrate. The patterns of the semiconductor layer, the first conductive layer, the second conductive layer, and the third insulating layer in this example can be referenced. Figure 18The description of the embodiments shown is omitted here.

[0309] In some examples, such as Figure 28A and Figure 28B As shown, the third conductive layer of a single display island area in the first display area may include at least: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, and a data line (e.g., data line 51a). The number of first connecting electrodes 41, second connecting electrodes 42, fourth connecting electrodes 44, fifth connecting electrodes 45, and sixth connecting electrodes 46 are all three, and the number of third connecting electrodes 43 is two. The third conductive layer of a single second trace area between adjacent display island areas in the second direction Y may include at least: a data connection line (e.g., data connection line 75a). The description of the first connecting electrode 41, second connecting electrode 42, third connecting electrode 43, fifth connecting electrode 45, and sixth connecting electrode 46 in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0310] In some examples, such as Figure 27 , Figure 28A and Figure 28B As shown, all three fourth connection electrodes 44 of a single display island area can be connected to the seventh connection electrode 47. The shape of the seventh connection electrode 47 can be approximately E-shaped. The seventh connection electrode 47 can be located on the same side of the three fourth connection electrodes 44 in the second direction Y. The first end of the seventh connection electrode 47 can be electrically connected to the first fourth connection electrode 44 to achieve electrical connection with the fifth transistor and storage capacitor of the first first pixel circuit; the second end of the seventh connection electrode 47 can be electrically connected to the second fourth connection electrode 44 to achieve electrical connection with the fifth transistor and storage capacitor of the second first pixel circuit; and the third end of the seventh connection electrode 47 can be electrically connected to the third fourth connection electrode 44 to achieve electrical connection with the fifth transistor and storage capacitor of the third first pixel circuit. The seventh connection electrode 47 and the three fourth connection electrodes 44 can be an integrated structure interconnected.

[0311] In some examples, such as Figure 28A and Figure 28BAs shown, the data line 51a can be a zigzag segment extending along the second direction Y of the main body. The data line 51a can be electrically connected to the first region of the fourth active layer of the fourth transistor of the first first pixel circuit through vias formed in the third insulating layer, the second insulating layer, and the first insulating layer. The data connection line 75a can be approximately a straight line extending along the second direction Y. Data lines 51a in adjacent display island areas along the second direction Y can be connected via the data connection line 75a. For example, the first end of the data connection line 75a in the second routing area between the m-th column display island area and the (m-1)-th column display island area can be connected to the data line 51a in the m-th column, k-th row display island area, and the second end can be connected to the data line 51a in the m-th column, k+1-th row display island area. The data line 51a and the data connection line 75a can be an integrally connected structure.

[0312] In some examples, such as Figure 29 As shown, the plurality of vias in the fifth insulating layer of a single display island area may include at least: via V31 (31st), via V32 (32nd), via V33 (33rd), via V34 (34th), and via V41 (41st). The descriptions of via V31 (31st), via V32 (32nd), via V33 (33rd), and via V34 (34th) can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0313] In some examples, such as Figure 29 and Figure 28A As shown, the orthographic projection of the forty-first via V41 onto the substrate can lie within the range of the orthographic projection of the data line 51a onto the substrate. The fifth and fourth insulating layers within the forty-first via V41 can be removed, exposing a portion of the surface of the data line 51a. The forty-first via V31 can be configured to allow a subsequently formed third conductive block to connect to the data line 51a through this via.

[0314] In some examples, such as Figure 30A and Figure 30B As shown, the fourth conductive layer of a single display island area may include at least: two data lines (e.g., data lines 51b and 51c), three second power connection lines (e.g., second power connection lines 61a, 61b and 61c), three second anode connection electrodes (e.g., second anode connection electrodes 63a, 63b and 63c), and a third conductive block 64.

[0315] In some examples, such as Figures 26 to 30BAs shown, the third conductive block 64 can be roughly rectangular in shape, such as a rounded rectangle. The third conductive block 64 can be electrically connected to the data line 51a through the forty-first via V41. Connecting the third conductive block 64 in parallel with the data line 51a helps to reduce the resistance of the data line 51a. Moreover, setting the third conductive block helps to uniformize the film pattern.

[0316] In some examples, such as Figures 26 to 30B As shown, the shapes of the second power connection lines 61a, 61b, and 61c can all be zigzag lines extending along the second direction Y of the main body. The second power connection line 61a can be electrically connected to the fourth connection electrode 44 through the thirty-second via V32 located in the first first pixel circuit, and can also be electrically connected to the sixth connection electrode 46 through the thirty-fourth via V34 located in the first first pixel circuit. The second power connection line 61a can be electrically connected to the fourth and sixth connection electrodes in the second first pixel circuit. The second power connection line 61c can be electrically connected to the fourth and sixth connection electrodes in the third first pixel circuit.

[0317] In some examples, such as Figure 30A and Figure 30B As shown, a fourth power extension 61a-1 may be provided on the side of the second power connection line 61a near the data line 51a. The fourth power extension 61a-1 may extend along the first direction X toward the data line 51a. The fourth power extension 61a-1 and the second power connection line 61a may be an integral structure interconnected. A third power extension 61c-1 may be provided on the side of the second power connection line 61c away from the data line 51c. The third power extension 61c-1 may extend along the first direction X toward the side away from the data line 51c. The third power extension 61c-1 and the second power connection line 61c may be an integral structure interconnected.

[0318] In some examples, such as Figure 30A and Figure 30B As shown, the fourth conductive layer of a single second trace area between adjacent display island areas along the second direction Y may include at least: one first power connection line (e.g., first power connection line 76) and two data connection lines (e.g., data connection lines 75b and 75c). The first power connection line 76, data connection lines 75b and 75c may be generally straight lines extending along the second direction Y.

[0319] In some examples, such as Figure 26 , Figure 30A and Figure 30BAs shown, the second wiring area between the m-th column display island area and the (m+1)-th column display island area may include: a data connection line 75c electrically connected to the first pixel circuit of the third column in the m-th column display island area, a data connection line 75b electrically connected to the first pixel circuit of the second column in the (m+1)-th column display island area, a data connection line 75a electrically connected to the first pixel circuit of the first column in the (m+1)-th column display island area, and a first power connection line 76. The data connection lines 75c, 76, 75a, and 75b may be arranged sequentially along a first direction X. The first power connection line 76 may be connected to the third power extension 61c-1 of the second power connection line 61c in the m-th column display island area, and may also be connected to the fourth power extension 61a-1 of the second power connection line 61a in the (m+1)-th column display island area. The first power connection line 76 and the adjacent second power connection lines 61c and 61a may be an integrally connected structure.

[0320] In some examples, within a single display island area, the lateral transmission of the first voltage signal is achieved using the fourth connecting electrode 44 and the seventh connecting electrode 47. The lateral transmission of the first voltage signal between adjacent display island areas is achieved using the first power connection line 76, adjacent second power connection lines 61a and 61c. The vertical transmission of the first voltage signal between adjacent display island areas is achieved using the first power connection line 76. In this example, the first power connection line, second power connection line, fourth connecting electrode, and seventh connecting electrode can form a mesh-like interconnected grid structure for transmitting the first voltage signal. This not only reduces the voltage drop of the first voltage signal but also effectively improves the uniformity of the first voltage signal in the display substrate, thus improving display uniformity, display quality, and display performance. Furthermore, in this example, the second wiring area can be equipped with only three data connection lines and one first power connection line, reducing the number of connection lines and thus reducing the space occupied by the second wiring area, which is beneficial for improving the light transmittance of the first light-transmitting area.

[0321] The remaining structure of the display substrate in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0322] This embodiment also provides a display substrate, including: a first display area. The first display area includes: a plurality of display island areas arranged in an array, and a light-transmitting area located between adjacent display island areas. The light-transmitting area includes a first light-transmitting area, which is located between adjacent display island areas along a second direction. At least one of the plurality of display island areas and the first light-transmitting area are alternately arranged along the second direction. The display island area includes: a plurality of first pixel circuits and a plurality of first light-emitting elements disposed on a substrate. At least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements. At least one first pixel circuit is configured to drive the at least one first light-emitting element to emit light. The first pixel circuits in adjacent display island areas are connected in a first direction through a plurality of first signal lines, and the first pixel circuits in adjacent display island areas are connected in the second direction through a plurality of second signal lines; the first direction and the second direction intersect.

[0323] In some exemplary embodiments, the first light-transmitting area is located between a plurality of second signal traces along a first direction. For example, the plurality of second signal traces may include: a first power connection line and a data connection line.

[0324] In some exemplary embodiments, the light-transmitting area may further include a second light-transmitting area. The second light-transmitting area is located between adjacent display island areas along the first direction. The area of ​​the first light-transmitting area may be larger than the area of ​​the second light-transmitting area.

[0325] In some exemplary embodiments, the second light-transmitting area is located between the plurality of first signal lines. For example, the plurality of first signal lines may include: a first scan connection line, a second scan connection line, a light emission control connection line, and a first initial connection line.

[0326] In some exemplary embodiments, at least one of the plurality of display island areas includes: three first pixel circuits and three first light-emitting elements. The three first pixel circuits and the three first light-emitting elements are electrically connected in a one-to-one correspondence, and the three first pixel circuits are arranged sequentially along the first direction. The three first light-emitting elements include: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light. The light-emitting region of the first light-emitting element emitting the first color light, in its orthographic projection on the substrate, at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting the first color light on the substrate. The light-emitting region of the first light-emitting element emitting the second color light, in its orthographic projection on the substrate, does not overlap with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting the second color light on the substrate. The light-emitting region of the first light-emitting element emitting the third color light, in its orthographic projection on the substrate, at least partially overlaps with the orthographic projection of the first pixel circuit connected to the first light-emitting element emitting the third color light on the substrate.

[0327] The structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0328] Figure 31 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 31 As shown, this embodiment provides a display device, including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0329] In some exemplary embodiments, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be a product with image (including still images or moving images, where the moving images can be video) display capabilities. For example, the display device can be any of the following products: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device can also be any of the following products: microdisplay, VR device or AR device containing a microdisplay, etc.

[0330] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments of this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of the technical solutions of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: The first display area includes: a plurality of display island areas arranged in an array and light transmission areas between adjacent display island areas; a plurality of display island areas arranged in a first direction are a row of display island areas, and a plurality of display island areas arranged in a second direction are a column of display island areas; the light transmission area includes: a first light transmission area between adjacent display island areas in the second direction and a second light transmission area between adjacent display island areas in the first direction; the area of the first light transmission area is greater than the area of the second light transmission area; a plurality of second light transmission areas are between two adjacent columns of display island areas; The display island area includes: a plurality of first pixel circuits and a plurality of first light emitting elements arranged on the substrate, at least one first pixel circuit in the plurality of first pixel circuits is electrically connected to at least one first light emitting element in the plurality of first light emitting elements, and the at least one first pixel circuit is configured to drive the at least one first light emitting element to emit light; The first pixel circuits in adjacent display island areas are connected in the first direction by a plurality of first signal lines, and the first pixel circuits in adjacent display island areas are connected in the second direction by a plurality of second signal lines; the first direction intersects the second direction; The material of the plurality of first signal lines and the plurality of second signal lines includes a metal material; The plurality of second signal lines includes: at least one first power supply connection line for transmitting a first voltage signal to a plurality of first pixel circuits of the display island area; and the plurality of first pixel circuits of the display island area are electrically connected to the same first power supply connection line. 2.The display substrate of claim 1, wherein, The film layer where the plurality of second signal lines is located is away from the substrate on the side of the film layer where the plurality of first signal lines is located. 3.The display substrate of claim 1, wherein, The material of the plurality of first signal lines and the plurality of second signal lines includes a metal material; The plurality of second signal lines is a same-layer structure, or at least one second signal line in the plurality of second signal lines is a different-layer structure from the remaining second signal lines. 4.The display substrate of claim 3, wherein, The display substrate further includes: a first wiring area between adjacent first light transmission areas, the first wiring area being in communication with the display island area; and the plurality of second signal lines being located in the first wiring area. 5.The display substrate according to claim 3 or 4, wherein, The plurality of second signal lines further includes: a plurality of data connection lines for transmitting data signals to a plurality of first pixel circuits of the display island area, respectively. 6.The display substrate of claim 5, wherein, The plurality of first pixel circuits of the display island area are arranged in the first direction in sequence, a data connection line connected to a first first pixel circuit in the plurality of first pixel circuits is a different-layer structure from data connection lines connected to the remaining first pixel circuits. 7.The display substrate of claim 1, wherein, At least one first signal line in the plurality of first signal lines is a different-layer structure from the remaining first signal lines. 8.The display substrate of claim 7, wherein, The plurality of first signal lines includes: a first initial connection line for transmitting a first initial signal, a first scan connection line for transmitting a first scan signal, a second scan connection line for transmitting a second scan signal, and a light emitting control connection line for transmitting a light emitting control signal; The first scan connection line, the second scan connection line, and the light emitting control connection line are a same-layer structure. 9.The display substrate of claim 1, wherein, At least one of the plurality of display island regions comprises three first pixel circuits and three first light emitting elements, the three first pixel circuits and the three first light emitting elements are electrically connected one by one, and the three first pixel circuits are arranged in sequence along the first direction. 10.The display substrate of claim 9, wherein, The three first light emitting elements comprise a first light emitting element emitting first color light, a first light emitting element emitting second color light, and a first light emitting element emitting third color light. The first light emitting element emitting the first color light and the first light emitting element emitting the second color light are arranged in the same column, the first light emitting element emitting the third color light and the first light emitting element emitting the first color light are arranged in different columns, and the first light emitting element emitting the first color light, the first light emitting element emitting the second color light, and the first light emitting element emitting the third color light are arranged in different rows. 11.The display substrate of claim 10, wherein, The area of the light emitting region of the first light emitting element emitting the second color light is greater than the area of the light emitting region of the first light emitting element emitting the first color light, and the area of the light emitting region of the first light emitting element emitting the third color light is greater than the area of the light emitting region of the first light emitting element emitting the first color light. 12.The display substrate according to claim 10 or 11, wherein The light emitting region of the first light emitting element emitting the first color light at least partially overlaps the first pixel circuit connected to the first light emitting element emitting the first color light in the orthographic projection of the substrate. The light emitting region of the first light emitting element emitting the second color light does not overlap the first pixel circuit connected to the first light emitting element emitting the second color light in the orthographic projection of the substrate. The light emitting region of the first light emitting element emitting the third color light at least partially overlaps the first pixel circuit connected to the first light emitting element emitting the third color light in the orthographic projection of the substrate. 13.The display substrate of claim 12, wherein, The overlapping area of the light emitting region of the first light emitting element emitting the third color light and the first pixel circuit connected to the first light emitting element emitting the third color light is greater than the overlapping area of the light emitting region of the first light emitting element emitting the first color light and the first pixel circuit connected to the first light emitting element emitting the first color light. 14.The display substrate of claim 1, further comprising: A second display region located on at least one side of the first display region; The second display region comprises a plurality of second pixel circuits and a plurality of second light emitting elements arranged on the substrate, at least one second pixel circuit in the plurality of second pixel circuits is electrically connected to at least one second light emitting element in the plurality of second light emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light emitting element to emit light.

15. A display device comprising the display substrate according to any one of claims 1 to 14, a sensor located on the side of the non-display surface of the display substrate, and the orthographic projection of the sensor and the first display region of the display substrate overlap.

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