Method for preparing and activating getter film layer in wafer-level vacuum packaging process

Abstract

The invention provides a method for growing a chromium / gold / chromium / titanium composite film layer on a wafer-level vacuum packaging substrate slice, wherein a first chromium layer is in direct contact with substrate silicon. Wafer-level vacuum packaging is achieved through gold-silicon eutectic bonding, in the gold-silicon eutectic bonding reaction process, the Cr / Au eutectic reaction layer located at the bottom of the Cr / Ti getter layer reacts with silicon eutectic to generate liquid phase alloy, the liquid phase alloy is solidified in the cooling process, crystal lattices of the Cr / Ti getter layer on the upper layer are driven to move in the process, the pores of the Ti getter material are changed, and the vacuum packaging effect is achieved. Therefore, the air suction capacity of the titanium getter is improved, and the wafer-level packaging vacuum degree is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of wafer-level vacuum packaging, and in particular relates to a method for preparing and activating a getter film layer in a wafer-level vacuum packaging process. Background Art

[0002] With the continuous development of semiconductor technology, wafer-level vacuum packaging technology has become an important link in the manufacturing process of vacuum-packaged MEMS devices. In wafer-level vacuum packaging, the packaging vacuum directly affects the working performance of MEMS devices. The packaging vacuum can be significantly improved by preparing and activating getter materials.

[0003] In traditional wafer-level vacuum packaging technology, the getter material's getter performance depends on the porosity of the prepared getter material film. The preparation of the getter film porosity is limited by various process conditions. The prepared getter film has limited getter performance and cannot meet the high vacuum wafer-level packaging requirements. Therefore, how to improve the getter performance of metal films is an important research direction in the current field of vacuum packaging technology. Summary of the invention

[0004] The purpose of the present invention is to provide a chromium / gold chromium / titanium composite film layer grown on a wafer-level vacuum packaging substrate, wherein the first chromium layer is in direct contact with the substrate silicon. Wafer-level vacuum packaging is achieved by gold-silicon eutectic bonding. During the gold-silicon eutectic bonding reaction, the Cr / Au eutectic reaction layer at the bottom of the Cr / Ti getter layer reacts with the silicon eutectic to produce a liquid alloy, which solidifies during the cooling process. In this process, the lattice of the upper Cr / Ti getter layer is driven to move, so that the pores of the Ti getter material change, thereby improving the gettering capacity of the titanium getter.

[0005] The above-mentioned purpose of the present invention is mainly achieved through the following technical solutions:

[0006] A method for preparing a getter film layer in a wafer-level vacuum packaging process comprises the following steps:

[0007] (1) Preparing a silicon oxide insulating layer on a substrate silicon wafer for wafer-level packaging;

[0008] (2) photolithography the silicon oxide insulating layer obtained in step (1) to form a silicon oxide window to be etched, etching the silicon oxide insulating layer, removing silicon oxide in the silicon oxide window to be etched, and forming a silicon oxide window;

[0009] (3) preparing a getter mask silicon wafer containing a getter sputtering window;

[0010] (4) aligning the substrate silicon wafer obtained in step (2) and the getter mask silicon wafer obtained in step (3), fixing them with a clamp, and aligning the silicon oxide window of the substrate silicon wafer and the getter sputtering window of the getter mask silicon wafer;

[0011] (5) placing the fixture in step (4) into a magnetron sputtering table or vacuum evaporation equipment, sputtering Cr, Au, Cr, and Ti in sequence, and growing a Cr / Au eutectic reaction layer and a Cr / Ti getter layer in sequence in the silicon oxide window of the substrate silicon wafer through the getter sputtering window on the getter mask silicon wafer to obtain a getter film layer.

[0012] The getter mask silicon wafer preparation process in step (3) comprises the following steps:

[0013] (3.1) growing a first silicon oxide layer and a second silicon oxide layer on the front and back surfaces of the getter mask silicon wafer respectively by thermal oxidation;

[0014] (3.2) growing a first silicon nitride layer and a second silicon nitride layer on the front and back surfaces of the getter mask silicon wafer respectively by a PECVD method;

[0015] (3.3) patterning the first silicon oxide layer and the first silicon nitride layer on the front side of the getter mask silicon wafer by photolithography and fluorocarbon plasma dry etching of the dielectric film to form silicon oxide layer and silicon nitride layer windows;

[0016] (3.4) Anisotropically etching the getter mask silicon wafer using KOH etching solution in a 70-80°C water bath heating condition until the silicon wafer is penetrated to form a getter sputtering window;

[0017] (3.5) Use BOE or hydrofluoric acid solution to etch and remove the silicon oxide layer and silicon nitride layer on the getter mask silicon wafer.

[0018] In the KOH etching solution of step (3.4), the ratio of KOH to H2O is 900-1000g:1000ml.

[0019] In the Cr / Au eutectic reaction layer (13), the thickness of the Cr metal layer is 2-5 nm, and the thickness of the Au metal layer is 100-500 nm.

[0020] In the Cr / Ti getter layer, the thickness of the Cr metal layer is 2-5 nm, and the thickness of the Ti metal layer is 1000-2000 nm.

[0021] The getter mask silicon wafer has a thickness of 300-600 μm.

[0022] The side lengths of the Cr / Au eutectic reaction layer and the Cr / Ti getter layer are 200-2000 μm, and the Cr / Au eutectic reaction layer and the Cr / Ti getter layer are located inside the silicon oxide window.

[0023] Assuming that the thickness of the getter mask silicon wafer is H, and the side lengths of the Cr / Au eutectic reaction layer and the Cr / Ti getter layer are both L, the size of the silicon oxide layer and silicon nitride layer windows is (H*1.414+L-2W), where W is the outward expansion size of the sputtered metal layer, and its value is 50-100μm.

[0024] A method for activating a getter film layer in a wafer-level vacuum packaging process, specifically as follows: the getter film layer obtained by the above method is activated at a vacuum degree of 10 -5 The temperature is heated to 370-410° C. under the condition of less than mbar and maintained for more than half an hour to generate a eutectic reaction between the Cr / Au eutectic reaction layer and the silicon substrate layer, and at the same time, the Ti getter material in the Cr / Ti getter layer (14) is activated.

[0025] Compared with the prior art, the present invention has at least the following beneficial effects:

[0026] (1) The method for preparing and activating a getter film layer in a wafer-level vacuum packaging process of the present invention prepares a Cr / Ti getter layer on a Cr / Au eutectic reaction layer, and drives the lattice change of the getter film material through the gold-silicon eutectic reaction process, thereby significantly improving the getter performance of the metal film and meeting the high vacuum degree requirements of wafer-level packaging.

[0027] (2) The method for preparing and activating the getter film layer in the wafer-level vacuum packaging process of the present invention realizes the getter activation process through the gold-silicon eutectic reaction of wafer-level packaging, has the advantages of simple operation, low cost, and wide application range, and can be widely used in the wafer-level vacuum packaging process of MEMS device manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a process flow chart of the film layer structures on the substrate silicon wafer of wafer-level packaging, where Figure 1 a is a substrate silicon wafer including a silicon oxide insulating layer, Figure 1 b is a substrate silicon wafer including a silicon oxide window; Figure 1 c is a substrate silicon wafer including a getter film layer;

[0029] Figure 2 is a process flow chart of getter mask silicon wafer, where Figure 2 a is a getter mask silicon wafer including a silicon oxide layer, Figure 2 b is a getter mask silicon wafer including a silicon nitride layer, Figure 2 c is a getter mask silicon wafer including an oxide layer and a silicon nitride layer window, Figure 2 d is a getter mask silicon wafer forming a getter sputtering window, Figure 2 e is the finished getter mask silicon wafer. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0031] The present invention proposes a method for preparing and activating a getter film layer in a wafer-level vacuum packaging process, wherein the getter preparation process comprises the following steps:

[0032] (1) A silicon oxide insulating layer 11 is prepared on a substrate silicon wafer 1 of a wafer-level package, such as Figure 1 a;

[0033] (2) A silicon oxide window to be etched is formed by a photolithography process, and a BOE etching solution is used to etch the silicon oxide insulating layer to form a silicon oxide window 12, such as Figure 1 b;

[0034] (3) Prepare a getter mask silicon wafer 2 containing a getter sputtering window 21, such as Figure 2 e;

[0035] (4) Aligning the substrate silicon wafer 1 and the getter mask silicon wafer 2 using a photolithography machine and fixing them with a fixture, wherein the silicon oxide window 12 of the substrate silicon wafer 1 and the getter sputtering window 21 of the getter mask silicon wafer 2 are aligned in center;

[0036] (5) placing the fixture in step (4) into a magnetron sputtering table or vacuum evaporation equipment, sputtering Cr, Au, Cr and Ti in sequence, growing a Cr / Au eutectic reaction layer 13 and a Cr / Ti getter layer 14 in the silicon oxide window 12 of the substrate silicon wafer 1 through the getter sputtering window 21 on the getter mask silicon wafer 2, and forming a substrate silicon wafer for wafer-level packaging containing a getter film layer to be activated, such as Figure 1 c;

[0037] The preparation process of the getter mask silicon wafer 2 in step (3) comprises the following steps:

[0038] (3.1) On the getter mask silicon wafer 2, a first silicon oxide layer 23 and a second silicon oxide layer 24 are grown successively on the front and back sides of the silicon wafer by thermal oxidation, such as Figure 2 a;

[0039] (3.2) A first silicon nitride layer 25 and a second silicon nitride layer 26 are successively grown on the front and back sides of the getter mask silicon wafer 2 by plasma enhanced chemical vapor deposition (PECVD), as shown in FIG. Figure 2 b;

[0040] (3.3) The first silicon oxide layer 23 and the first silicon nitride layer 25 on the front side of the getter mask silicon wafer 2 are patterned by photolithography and carbon fluoride plasma dry etching of the dielectric film to form silicon oxide layer and silicon nitride layer windows 22, such as Figure 2 c;

[0041] (3.4) Using KOH etching solution (KOH: H2O = 900-1000g: 1000ml) in a 70-80°C water bath heating condition, the getter mask silicon wafer 2 is anisotropically etched until the silicon wafer is penetrated to form a getter sputtering window 21, as shown in FIG. Figure 2 d;

[0042] (3.5) BOE or hydrofluoric acid solution is used to etch and remove the silicon oxide layer and the silicon nitride layer on the getter mask silicon wafer 2, such as Figure 2 e;

[0043] The getter activation method is to use Au-Si bonding in a wafer-level vacuum packaging process, under vacuum conditions (10 -5 mbar or less) to 370-410°C and keep it for more than half an hour to generate a eutectic reaction between the Cr / Au eutectic reaction layer 13 and the silicon substrate layer, and at the same time complete the activation of the Ti getter material in the Cr / Ti getter layer 14;

[0044] The Cr / Au eutectic reaction layer 13 and the Cr / Ti getter layer 14 of the substrate silicon wafer 1 are smaller in size than the silicon oxide window 12 and are located inside the silicon oxide window 12, wherein the Cr layer is in direct contact with the silicon material on the substrate silicon wafer 1;

[0045] The Cr metal layer thickness in the Cr / Au eutectic reaction layer 13 of the substrate silicon wafer 1 is 2-5nm, the Au metal layer thickness is 100-500nm, the Cr metal layer thickness in the Cr / Ti getter layer 14 is 2-5nm, the Ti metal layer thickness is 1000-2000nm;

[0046] The thickness of the getter mask silicon wafer 2 is 300-600 μm, and the side lengths of the Cr / Au eutectic reaction layer 13 and the Cr / Ti getter layer 14 to be prepared are 200-2000 μm. Assuming that the thickness of the getter mask silicon wafer 2 is H, and the side lengths of the Cr / Au eutectic reaction layer 13 and the Cr / Ti getter layer 14 to be prepared are L, the size of the oxide layer and the silicon nitride layer window 22 in the preparation step 3-3 of the getter mask silicon wafer 2 should be designed to be (H*1.414+L-2W), wherein W is the outer expansion size of the sputtered metal layer, and its value is 50 μm to 100 μm. The actual size of this value is related to the gap between the getter mask (2) and the substrate silicon wafer (1) when they are fixed using a clamp.

[0047] Example 1

[0048] (1) Preparing a silicon oxide insulating layer 11 on a substrate silicon wafer 1 of a wafer-level package;

[0049] (2) forming a silicon oxide window to be etched by a photolithography process, and etching the silicon oxide insulating layer with a BOE etching solution to form a silicon oxide window 12;

[0050] (3) preparing a getter mask silicon wafer 2 containing a getter sputtering window 21;

[0051] (4) Aligning the substrate silicon wafer 1 and the getter mask silicon wafer 2 using a photolithography machine and fixing them with a fixture, wherein the silicon oxide window 12 of the substrate silicon wafer 1 and the getter sputtering window 21 of the getter mask silicon wafer 2 are aligned in center;

[0052] (5) placing the fixture in step (4) into a magnetron sputtering table or vacuum evaporation equipment, sputtering Cr, Au, Cr and Ti in sequence, growing a Cr / Au eutectic reaction layer 13 and a Cr / Ti getter layer 14 in the silicon oxide window 12 of the substrate silicon wafer 1 through the getter sputtering window 21 on the getter mask silicon wafer 2, and forming a substrate silicon wafer for wafer-level packaging containing a getter film layer to be activated;

[0053] Step (3) The preparation process of the getter mask silicon wafer 2 comprises the following steps:

[0054] (3.1) On the getter mask silicon wafer 2, a first silicon oxide layer 23 and a second silicon oxide layer 24 are successively grown on the front and back sides of the silicon wafer by thermal oxidation;

[0055] (3.2) growing a first silicon nitride layer 25 and a second silicon nitride layer 26 on the front and back surfaces of the getter mask silicon wafer 2 in sequence by plasma enhanced chemical vapor deposition (PECVD);

[0056] (3.3) patterning the first silicon oxide layer 23 and the first silicon nitride layer 25 on the front side of the getter mask silicon wafer 2 by photolithography and fluorocarbon plasma dry etching of the dielectric film to form silicon oxide layer and silicon nitride layer windows 22;

[0057] (3.4) using KOH etching solution (KOH: H2O = 1000g: 1000ml) to perform silicon anisotropic etching on the getter mask silicon wafer 2 under 80°C water bath heating conditions until the silicon wafer is penetrated to form a getter sputtering window 21;

[0058] (3.5) using BOE or hydrofluoric acid solution to remove the silicon oxide layer and the silicon nitride layer on the getter mask silicon wafer 2;

[0059] The getter activation method is to use Au-Si bonding in the wafer-level vacuum packaging process under vacuum conditions (10 -5 mbar or less) to 370°C and keep it for more than half an hour to generate a eutectic reaction between the Cr / Au eutectic reaction layer 13 and the silicon substrate layer, and at the same time complete the activation of the Ti getter material in the Cr / Ti getter layer 14;

[0060] The Cr / Au eutectic reaction layer 13 and the Cr / Ti getter layer 14 of the substrate silicon wafer 1 are smaller in size than the silicon oxide window 12 and are located inside the silicon oxide window 12, wherein the Cr layer is in direct contact with the silicon material on the substrate silicon wafer 1;

[0061] The Cr metal layer thickness in the Cr / Au eutectic reaction layer 13 of the substrate silicon wafer 1 is 4 nm, the Au metal layer thickness is 200 nm, and the Cr metal layer thickness in the Cr / Ti getter layer 14 is 4 nm, the Ti metal layer thickness is 1500 nm;

[0062] The thickness of the getter mask silicon wafer 2 is 500 μm, the side length of the Cr / Au eutectic reaction layer 13 and the Cr / Ti getter layer 14 to be prepared is 1000 μm, and the previous process test shows that the outer expansion size of the sputtered metal layer is about 80 μm. Therefore, the size of the oxide layer and silicon nitride layer windows 22 in the preparation step 3-3 of the getter mask silicon wafer 2 should be designed to be 1547 μm.

[0063] The present invention prepares a composite film layer of a Cr / Au eutectic reaction layer and a Cr / Ti getter layer in wafer-level vacuum packaging, adopts a gold-silicon eutectic bonding technology to achieve wafer-level packaging, and drives the lattice change of the getter film material through the gold-silicon eutectic reaction process, which can significantly improve the getter performance of the metal film and meet the high vacuum degree requirements of wafer-level packaging. The present invention realizes the getter activation process through the gold-silicon eutectic reaction of wafer-level packaging, has the advantages of simple operation, low cost, wide application range, etc., and can be widely used in the wafer-level vacuum packaging process of MEMS device manufacturing.

[0064] The above description is only the best specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

[0065] The contents not described in detail in the specification of the present invention belong to the common knowledge of the professionals in this field.

Claims

1. A method for preparing a getter film layer in a wafer-level vacuum packaging process, characterized in that: The following steps are involved: (1) preparing a silicon oxide insulating layer (11) on a substrate silicon wafer (1) for wafer-level packaging; (2) photolithographically treating the silicon oxide insulating layer (11) obtained in step (1) to form a silicon oxide window to be etched, etching the silicon oxide insulating layer, removing silicon oxide in the silicon oxide window to be etched, and forming a silicon oxide window (12); (3) preparing a getter mask silicon wafer (2) containing a getter sputtering window (21); (4) aligning the substrate silicon wafer (1) obtained in step (2) and the getter mask silicon wafer (2) obtained in step (3), fixing them with a clamp, and aligning the silicon oxide window (12) of the substrate silicon wafer (1) and the getter sputtering window (21) of the getter mask silicon wafer (2); (5) placing the fixture in step (4) into a magnetron sputtering table or vacuum evaporation equipment, sputtering Cr, Au, Cr, and Ti in sequence, and growing a Cr / Au eutectic reaction layer (13) and a Cr / Ti getter layer (14) in sequence in the silicon oxide window (12) of the substrate silicon wafer (1) through a getter sputtering window (21) on the getter mask silicon wafer (2) to obtain a getter film layer.

2. The method for preparing a getter film layer in a wafer-level vacuum packaging process according to claim 1, characterized in that: The preparation process of the getter mask silicon wafer (2) in step (3) comprises the following steps: (3.1) growing a first silicon oxide layer (23) and a second silicon oxide layer (24) on the front and back surfaces of the getter mask silicon wafer (2) respectively by thermal oxidation; (3.2) growing a first silicon nitride layer (25) and a second silicon nitride layer (26) on the front and back surfaces of the getter mask silicon wafer (2) respectively by a PECVD method; (3.3) patterning the first silicon oxide layer (23) and the first silicon nitride layer (25) on the front side of the getter mask silicon wafer (2) by photolithography and fluorocarbon plasma dry etching of the dielectric film to form silicon oxide layer and silicon nitride layer windows (22); (3.4) using KOH etching solution to anisotropically etch the getter mask silicon wafer (2) under 70-80° C. water bath heating conditions until the silicon wafer is penetrated to form a getter sputtering window (21); (3.5) Using BOE or hydrofluoric acid solution to etch and remove the silicon oxide layer and silicon nitride layer on the getter mask silicon wafer (2).

3. The method for preparing a getter film layer in a wafer-level vacuum packaging process according to claim 2, characterized in that: In the KOH etching solution of step (3.4), the ratio of KOH to H2O is 900-1000g:1000ml.

4. The method for preparing a getter film layer in a wafer-level vacuum packaging process according to claim 1, characterized in that: In the Cr / Au eutectic reaction layer (13), the thickness of the Cr metal layer is 2-5 nm, and the thickness of the Au metal layer is 100-500 nm.

5. The method for preparing a getter film layer in a wafer-level vacuum packaging process according to claim 1, characterized in that: In the Cr / Ti getter layer (14), the thickness of the Cr metal layer is 2-5 nm, and the thickness of the Ti metal layer is 1000-2000 nm.

6. The method for preparing a getter film layer in a wafer-level vacuum packaging process according to claim 1, characterized in that: The getter mask silicon wafer (2) has a thickness of 300-600 μm.

7. The method for preparing a getter film layer in a wafer-level vacuum packaging process according to claim 1, characterized in that: The side lengths of the Cr / Au eutectic reaction layer (13) and the Cr / Ti getter layer (14) are 200-2000 μm, and the Cr / Au eutectic reaction layer (13) and the Cr / Ti getter layer (14) are located inside the silicon oxide window (12).

8. The method for preparing a getter film layer in a wafer-level vacuum packaging process according to claim 1, characterized in that: Assuming that the thickness of the getter mask silicon wafer (2) is H, and the side lengths of the Cr / Au eutectic reaction layer (13) and the Cr / Ti getter layer (14) are both L, the size of the silicon oxide layer and silicon nitride layer windows (22) is (H*1.414+L-2W), where W is the outer expansion size of the sputtered metal layer, and its value is 50-100 μm.

9. A method for activating a getter film layer in a wafer-level vacuum packaging process, characterized in that: The getter film layer according to any one of claims 1 to 8, under a vacuum degree of 10 -5 The Cr / Au eutectic reaction layer (13) is heated to 370-410°C under the condition of less than mbar and maintained for more than half an hour to generate a eutectic reaction between the Cr / Au eutectic reaction layer (13) and the silicon substrate layer, and at the same time, the Ti getter material in the Cr / Ti getter layer (14) is activated.

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