Laser radar chip, operation method thereof and laser radar

Abstract

The invention discloses a laser radar chip and an operation method thereof, and a laser radar. The laser radar chip comprises a bus, a first data reading module, a first processor, a second data reading module, a second processor, a state configuration module and a function state determination module. The first processor receives and processes the data output by the first data reading module to obtain a first processing result. The state configuration module configures the second processor to be switched between a first working state and a second working state, in the first working state, the second processor receives and processes the data output by the second data reading module, in the second working state, the second processor receives and processes the data output by the first data reading module, and a verification result is obtained. The function state determination module determines whether the functions of the first processor and the second processor are normal based on the comparison result of the first processing result and the verification result. By means of the mode, the function safety requirement and the high-performance requirement can be met through one chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a laser radar chip and an operating method thereof, and a laser radar. Background Art

[0002] The laser radar chip is the core component of the laser radar, responsible for the collection, processing and transmission of all laser radar information. In the vehicle system, the laser radar chip assumes the important object sensing function. Once the function fails, the consequences will directly affect the life safety of the driver and passengers, that is, the chip needs to meet the functional safety requirements; while for some laser radars used in low-intensity application scenarios outside the vehicle system, such as the laser radar used by the sweeper, functional safety is not required, but higher computing power is required, that is, the chip needs to meet higher performance requirements. Summary of the invention

[0003] The embodiments of the present application provide a laser radar chip and an operating method thereof, and a laser radar, which can meet functional safety requirements and higher performance requirements with a single chip.

[0004] In a first aspect, an embodiment of the present application provides a laser radar chip, including a bus, a first data reading module, a first processor, a second data reading module, a second processor, a state configuration module and a functional state determination module; the first data reading module is used to obtain data from a memory; the first processor is respectively connected to the bus and the first data reading module, and is used to receive and process the data output by the first data reading module to obtain a first processing result; the second data reading module is used to obtain data from the memory; the state configuration module is used to configure the second processor to switch between a first working state and a second working state, in the first working state, the second processor is connected to the bus, the second processor is used to receive and process the data output by the second data reading module to obtain a second processing result, and output it to the bus, in the second working state, the second processor is used to receive and process the data output by the first data reading module to obtain a verification result; the functional state determination module is respectively connected to the first processor and the second processor, and the functional state determination module is used to obtain the first processing result and the verification result when the second processor is in the second working state, and determine whether the functions of the first processor and the second processor are normal based on the comparison result of the first processing result and the verification result.

[0005] Configuring the second processor to switch between the first working state and the second working state allows the lidar chip to be suitable for both application scenarios with higher performance requirements and application scenarios with functional safety requirements, thereby achieving the goal of meeting both functional safety requirements and higher performance requirements with one chip.

[0006] In one or more embodiments, the first data reading module and / or the second data reading module includes a logic circuit; the first data reading module and the second data reading module are used to read data from different address areas of the memory; the laser radar chip includes the memory, or the memory is a memory outside the laser radar chip.

[0007] In one or more embodiments, the state configuration module includes: a multiplexing module having a first input part, a second input part and a first output part, the first input part is connected to the first data reading module for receiving data output by the first data reading module, the second input part is connected to the second data reading module for receiving data output by the second data reading module, and the first output part is connected to the second processor; and a configuration register is used to configure the multiplexing module so that one of the first input part and the second input part of the multiplexing module is selected with the first output part.

[0008] In one or more embodiments, the multiplexing module includes: a first multiplexer connected to the configuration register, having a first input terminal, a second input terminal and a first output terminal, the first input terminal being connected to the first data reading module for receiving a first read instruction obtained from the memory by the first data reading module, the second input terminal being connected to the second data reading module for receiving a second read instruction obtained from the memory by the second data reading module, and the first output terminal being connected to the second processor; and a second multiplexer connected to the configuration register, having a third input terminal, a fourth input terminal and a second output terminal, the third input terminal being connected to the first data reading module for receiving a second read instruction obtained from the memory by the first data reading module. the first data received by the first multiplexer, the fourth input terminal is connected to the second data reading module for receiving the second data obtained by the second data reading module from the memory, and the second output terminal is connected to the second processor; the first input terminal and the third input terminal together constitute the first input part, the second input terminal and the fourth input terminal together constitute the second input part, and the first output terminal and the second output terminal together constitute the first output part; the configuration register is used to configure the first multiplexer and the second multiplexer so that: the first input terminal is selected with the first output terminal, and the third output terminal is selected with the second output terminal; or the second input terminal is selected with the first output terminal, and the fourth input terminal is selected with the second output terminal.

[0009] In one or more embodiments, the multiplexing module also includes a third multiplexer, which is connected to the configuration register; the third multiplexer has a fifth input terminal, a sixth input terminal and a third output terminal, the fifth input terminal is connected to the second processor, and is used to receive the second processing result or the verification result output by the second processor, the sixth input terminal is used to obtain preset information, and the third output terminal is connected to the bus; the configuration register is used to configure the third multiplexer so that: when the second processor is in the first working state, the fifth input terminal and the third output terminal are selected; and when the second processor is in the second working state, the sixth input terminal and the third output terminal are selected.

[0010] In one or more embodiments, the functional status determination module includes: a comparison unit, connected to the first processor and the second processor, respectively, to obtain the first processing result and the verification result, and output a comparison result of the first processing result and the verification result; and a status determination unit, connected to the comparison unit, for obtaining the comparison result, and determining whether the functions of the first processor and the second processor are normal based on the comparison result.

[0011] In one or more embodiments, the laser radar chip includes multiple first processors, multiple first data reading modules, multiple second processors and multiple second data reading modules, the state configuration module includes multiple multiplexing modules, and the functional state determination module includes multiple comparison units, each of the first processors corresponds to one first data reading module, one second processor, one second data reading module, one multiplexing module and one comparison unit; each of the multiplexing modules is respectively connected to the configuration register, and each of the comparison units is respectively connected to the state determination unit.

[0012] Setting up multiple first processors is beneficial to increasing the computing power of the laser radar chip and improving performance. For each first processor, a corresponding second processor is set, which can further increase the computing power of the laser radar chip or perform functional safety verification on each first processor and each second processor, so as to improve the safety and reliability of the laser radar chip. In addition, by setting up multiple second processors and switching the working state of the second processor according to the actual computing power load, it is possible to ensure that the laser radar chip can provide sufficient computing power for the actual computing power load. Moreover, on the basis of having excess computing power, the excess second processors can also be used to verify functional safety to improve the safety and reliability of the laser radar chip.

[0013] In one or more embodiments, the laser radar chip also includes a monitoring module; the monitoring module is connected to the bus and the state configuration module respectively, and the monitoring module is used to determine the current computing power load through the bus, and output a feedback signal to the state configuration module based on the current computing power load and the preset computing power load; the state configuration module is also used to control at least one of the second processors to be in the first working state when it is determined based on the feedback signal that the current computing power load is greater than or equal to the preset computing power load, and, when it is determined based on the feedback signal that the current computing power load is less than the preset computing power load, control each of the second processors to be in the second working state.

[0014] In one or more embodiments, the laser radar chip also includes a reset module; the reset module is respectively connected to the state configuration module and the second processor, and the reset module is configured to reset the second processor under the control of the state configuration module.

[0015] In a second aspect, an embodiment of the present application provides an operating method of a laser radar chip, which is applied to the laser radar chip as described above, and the method includes: determining a current computing power load of the laser radar chip; if the current computing power load is higher than a preset multiple of the total computing power of each computing processor, controlling at least one of the second processors to switch from the second working state to the first working state, so that the preset multiple of the total computing power of each computing processor is higher than the current computing power load, wherein the computing processor includes a first processor and a second processor in the first working state; if the current computing power load is lower than the preset multiple of the total computing power of each computing processor, controlling at least one of the second processors to switch from the first working state to the second working state, so that the preset multiple of the total computing power of each computing processor is still higher than the current computing power load.

[0016] In a third aspect, an embodiment of the present application provides a laser radar, including the laser radar chip as described above.

[0017] The beneficial effects of the present application are as follows: the laser radar chip of the embodiment of the present application includes a bus, a first data reading module, a first processor, a second data reading module, a second processor, a state configuration module and a functional state determination module. The first data reading module obtains data from the memory. The second data reading module obtains data from the memory. The first processor is connected to the bus and the first data reading module respectively, and the first processor receives and processes the data output by the first data reading module to obtain a first processing result. When it is necessary to meet higher performance requirements, the state configuration module configures the second processor to be in a first working state. At this time, the second processor is connected to the bus, and the second processor receives and processes the data output by the second data reading module to obtain a second processing result and output it to the bus. It can be seen that at this time, both the first processor and the second processor are used to process data to meet higher performance requirements. When functional safety requirements are required, the state configuration module configures the second processor to be in the second working state. At this time, the second processor receives and processes the data output by the first data reading module to obtain a verification result. Then, the functional state determination module obtains the first processing result and the verification result when the second processor is in the second working state, and determines whether the functions of the first processor and the second processor are normal based on the comparison result of the first processing result and the verification result, thereby meeting the functional safety requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily described by the figures in the corresponding drawings, and these exemplary descriptions are not intended to limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements.

[0019] Figure 1 This is a schematic diagram of the composition block diagram of the laser radar chip provided in the embodiment of the present application. Figure 1 ; Figure 2 yes Figure 1 The simplified block diagram of the lidar chip shown Figure 1 ; Figure 3 yes Figure 2 The simplified block diagram of the lidar chip shown Figure 2 ; Figure 4 This is a schematic diagram of the composition block diagram of the laser radar chip provided in the embodiment of the present application. Figure 2 ; Figure 5 This is a schematic diagram of the composition block diagram of the laser radar chip provided in the embodiment of the present application. Figure 3 ; Figure 6 This is a schematic diagram of the composition block diagram of the laser radar chip provided in the embodiment of the present application. Figure 4 ; Figure 7 This is a schematic diagram of the composition block diagram of the laser radar chip provided in the embodiment of the present application. Figure 5 ; Figure 8 This is a schematic diagram of the composition block diagram of the laser radar chip provided in the embodiment of the present application. Figure 6 ; Fig. 9 This is a schematic diagram of the composition block diagram of the laser radar chip provided in the embodiment of the present application. Figure 7 ; Fig.10 This is a schematic diagram of the composition block diagram of the laser radar chip provided in the embodiment of the present application. Figure 8 ; Fig.11 This is a schematic diagram of the composition block diagram of the laser radar chip provided in the embodiment of the present application. Figure 9 ; Fig.12 is a flowchart of an operating method of a laser radar chip provided in an embodiment of the present application; Fig.13 It is a schematic diagram of the structure of the laser radar provided in an embodiment of the present application applied to a vehicle. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and in detail in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0021] It should be noted that, when an element is described as being “connected to” another element, it may be directly connected to the other element, or one or more intervening elements may exist therebetween.

[0022] In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as there is no structural conflict between them.

[0023] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the block diagram of the laser radar chip provided in the embodiment of the present application. Figure 1 As shown, the laser radar chip 100 includes a bus 10, a first data reading module 20, a first processor 30, a second data reading module 40, a second processor 50, a state configuration module 60 and a functional state determination module 70.

[0024] Among them, the first data reading module 20 is used to obtain data from the memory M1. The first processor 30 is connected to the bus 10 and the first data reading module 20 respectively. The first processor 30 is used to receive and process the data D1 output by the first data reading module 20 to obtain a first processing result DA1 and output it to the bus 10. The second data reading module 40 is used to obtain data from the memory M1. The state configuration module 60 is used to configure the second processor 50 to switch between the first working state and the second working state. In the first working state, the second processor 50 is connected to the bus 10. The second processor 50 is used to receive and process the data D2 output by the second data reading module 40 to obtain a second processing result DA2 and output it to the bus 10. In the second working state, the second processor 50 is used to receive and process the data D1 output by the first data reading module 20 to obtain a verification result DB1. The functional status determination module 70 is connected to the first processor 30 and the second processor 50 respectively. The functional status determination module 70 is used to obtain the first processing result DA1 and the verification result DB1 when the second processor 50 is in the second working state, and based on the comparison result of the first processing result DA1 and the verification result DB1, determine whether the functions of the first processor 30 and the second processor 50 are normal.

[0025] The data D1 output by the first data reading module 20 and the data D2 output by the second data reading module 40 may be the same data or different data. In practical applications, the first data reading module 20 and the second data reading module 40 may read data from different address areas of the memory or from the same address area of ​​the memory. By configuring the first data reading module 20 and the second data reading module 40 to read data from different address areas of the memory, the first processor 30 and the second processor 50 may respectively process data in different address areas, which is conducive to improving work efficiency.

[0026] The processor processes the data (including the first processor 30 processing the data D1 and the second processor 50 processing the data D2) including but not limited to numerical calculation, instruction parsing, resource scheduling, error detection and recovery, etc. In some embodiments, each processor (including the first processor 30 and the second processor 50) is configured as a central processing unit (CPU).

[0027] When the state configuration module 60 configures the second processor 50 to switch to the first working state, Figure 1 The block diagram can be simplified as shown Figure 2 As shown in the block diagram. Figure 2 As shown, the first processor 30 receives and processes the data D1 output by the first data reading module 20, obtains a first processing result DA1, and outputs it to the bus 10. The second processor 50 receives and processes the data D2 output by the second data reading module 40, obtains a second processing result DA2, and outputs it to the bus 10. At this time, the first processor 30 and the second processor 50 are both used to process data, which can be applied to application scenarios with higher performance requirements.

[0028] When the state configuration module 60 configures the second processor 50 to switch to the second working state, Figure 1 The block diagram can be simplified as shown Figure 3 As shown in the block diagram. Figure 3As shown, the first processor 30 receives and processes the data D1 output by the first data reading module 20, obtains the first processing result DA1, and outputs it to the bus 10 and the function status determination module 70. The second processor 50 receives and processes the data D1 output by the first data reading module 20, obtains the verification result DB1, and outputs it to the function status determination module 70. The function status determination module 70 determines whether the functions of the first processor 30 and the second processor 50 are normal based on the comparison result between the first processing result DA1 and the verification result DB1. At this time, the first processor 30 is used to process data, and the second processor 50 is used to verify whether the functions of the first processor 30 and the second processor 50 are normal, which can be applied to application scenarios with functional safety requirements. It can be understood that in this embodiment, when the second processor 50 is in the second working state, the first processor 30 and the second processor 50 both receive data D1, and process the data D1 in exactly the same way. Based on this, if the comparison result of the first processing result DA1 and the verification result DB1 is that the first processing result DA1 and the verification result DB1 are the same, it can be determined that the functions of the first processor 30 and the second processor 50 are normal; conversely, if the comparison result of the first processing result DA1 and the verification result DB1 is that the first processing result DA1 and the verification result DB1 are different, it can be determined that the functions of the first processor 30 and / or the second processor 50 are abnormal.

[0029] In summary, for the laser radar chip 100, by configuring the second processor 50 to switch between the first working state and the second working state, it can be applied to application scenarios with higher performance requirements and functional safety requirements, that is, the functional safety requirements and higher performance requirements are met by one chip. For example, when the laser radar is a vehicle-mounted laser radar, it requires strong computing power to cope with complex and changeable scenarios; at this time, the second processor 50 can be configured to the first working state through the state configuration module 60, and the first processor 30 and the second processor 50 both act as processors that provide computing power, which is conducive to improving the overall computing power of the laser radar. When the laser radar is installed in equipment such as a sweeping robot or a food delivery robot, due to the relatively limited application scenarios, there is no need for excessive computing power for signal processing. Instead, it is necessary to ensure higher reliability to ensure that the product is safe and reliable during use. At this time, the second processor 50 can be configured to the second working state through the state configuration module 60, and the first processor 30 serves as a processor that provides computing power, and the second processor 50 serves as a functional safety processor to verify whether the first processor 30 or the second processor 50 is normal. When at least one of the first processor 30 and the second processor 50 is abnormal, an instruction indicating the abnormality of the laser radar can be uploaded to the host computer to suspend the operation of some modules or the entire laser radar.

[0030] It is understandable that in Figure 1-Figure 3In the laser radar chip 100 shown in FIG. 1 , the memory M1 is taken as an example as a memory outside the laser radar chip 100. In other embodiments, the memory M1 may also be provided in the laser radar chip 100, such as Figure 4 shown.

[0031] In some embodiments, the first data reading module and / or the second data reading module include a logic circuit. The logic circuit is an electronic circuit for processing and operating digital signals, which works based on the binary principle, that is, transmitting information through high and low levels (usually represented as 0 or 1) and performing logical operations. The core component of the logic circuit is the logic gate (such as the AND gate), which can generate corresponding output signals according to different combinations of input signals.

[0032] In some embodiments, Figure 5 As shown, the state configuration module 60 includes a multiplexing module 61 and a configuration register 62 .

[0033] The multiplexing module 61 has a first input part I1, a second input part I2 and a first output part O1. The first input part I1 is connected to the first data reading module 20, and the first input part I1 is used to receive the data D1 output by the first data reading module 20; the second input part I2 is connected to the second data reading module 40, and the second input part I2 is used to receive the data D2 output by the second data reading module 40, and the first output part O1 is connected to the second processor 50. The configuration register 62 is used to configure the multiplexing module 61 so that one of the first input part I1 and the second input part I2 of the multiplexing module 61 is selected with the first output part O1. The configuration register 62 is also connected to the second processor 50 to configure the second processor 50 to be in the first working state or the second working state.

[0034] When the configuration register 62 configures the second processor 50 to be in the first working state, the configuration register 62 configures the second input part I2 to be selected with the first output part O1, so that the second processor 50 receives and processes the data D2 output by the second data reading module 40. At this time, the second processor 50 is used to process data to improve the overall performance of the laser radar chip 100, which is conducive to meeting higher performance requirements.

[0035] When the configuration register 62 configures the second processor 50 to be in the second working state, the configuration register 62 configures the first input portion I1 and the first output portion O1 to be enabled, so that the second processor 50 receives and processes the data D1 output by the first data reading module 20. At this time, the second processor 50 is used to verify whether the functions of the first processor 30 and the second processor 50 are normal, which is conducive to meeting the functional safety requirements.

[0036] In some embodiments, Figure 6As shown, the multiplexing module 61 includes a first multiplexer 611 and a second multiplexer 612 .

[0037] The first multiplexer 611 is connected to the configuration register 62, and has a first input terminal I1_1, a second input terminal I2_1, and a first output terminal O1_1. The first input terminal I1_1 is connected to the first data reading module 20, and the first input terminal I1_1 is used to receive the first read instruction D1_1 obtained by the first data reading module 20 from the memory M1; the second input terminal I2_1 is connected to the second data reading module 40, and the second input terminal I2_1 is used to receive the second read instruction D2_1 obtained by the second data reading module 40 from the memory M1; the first output terminal O1_1 is connected to the second processor 50. The second multiplexer 612 is connected to the configuration register 62, and has a third input terminal I1_2, a fourth input terminal I2_2, and a second output terminal O1_2. The third input terminal I1_2 is connected to the first data reading module 20, and the third input terminal I1_2 is used to receive the first data D1_2 obtained by the first data reading module 20 from the memory M1; the fourth input terminal I2_2 is connected to the second data reading module 40, and the fourth input terminal I2_2 is used to receive the second data D2_2 obtained by the second data reading module 40 from the memory M1; the second output terminal O1_2 is connected to the second processor 50.

[0038] The first input terminal I1_1 and the third input terminal I1_2 together constitute the first input part I1, the second input terminal I2_1 and the fourth input terminal I2_2 together constitute the second input part I2, and the first output terminal O1_1 and the second output terminal O1_2 together constitute the first output part O1. The data D1 output by the first data reading module 20 includes the first reading instruction D1_1 and the first data D1_2; the data D2 output by the second data reading module 40 includes the second reading instruction D2_1 and the second data D2_2.

[0039] The configuration register 62 is used to configure the first multiplexer 611 and the second multiplexer 612 so that: the first input terminal I1_1 is selected with the first output terminal O1_1, and the third input terminal I1_2 is selected with the second output terminal O1_2; or the second input terminal I2_1 is selected with the first output terminal O1_1, and the fourth input terminal I2_2 is selected with the second output terminal O1_2. The first input terminal I1_1 is selected with the first output terminal O1_1, and the third input terminal I1_2 is selected with the second output terminal O1_2, corresponding to the first input part I1 and the first output part O1 are selected. At this time, the configuration register 62 configures the second processor 50 to be in the second working state; the second input terminal I2_1 is selected with the first output terminal O1_1, and the fourth input terminal I2_2 is selected with the second output terminal O1_2, corresponding to the second input part I2 and the first output part O1 are selected. At this time, the configuration register 62 configures the second processor 50 to be in the first working state.

[0040] In some embodiments, Figure 7 As shown, the multiplexing module 61 also includes a third multiplexer 613, and the third multiplexer 613 is connected to the configuration register 62. The third multiplexer 613 has a fifth input terminal I3, a sixth input terminal I4 and a third output terminal O2. The fifth input terminal I3 is connected to the second processor 50, and the fifth input terminal I3 is used to receive the second processing result DA2 or the verification result DB1 output by the second processor 50; the sixth input terminal I4 is used to obtain preset information DC1, and the preset information DC1 can be set based on the actual application scenario. The embodiment of the present application does not make specific restrictions on this. For example, in some embodiments, the preset information DC1 is configured to be 0; the third output terminal O2 is connected to the bus 10.

[0041] The configuration register 62 is used to configure the third multiplexer 613 so that: when the second processor 50 is in the first working state, the fifth input terminal I3 and the third output terminal O2 are selected; and when the second processor 50 is in the second working state, the sixth input terminal I4 and the third output terminal O2 are selected. In other words, when the second processor 50 is in the first working state, it is used to obtain the second data D2_2 through the second data reading module 40, and when the fifth input terminal I3 and the third output terminal O2 of the third multiplexer 613 are selected, the second processor 50 is connected to the bus 10, and the second processing result DA2 output by the second processor 50 is output to the bus 10. When the second processor 50 is in the second working state, it is used to obtain the first data D1_2 through the first data reading module 20. When the sixth input terminal I4 and the third output terminal O2 of the third multiplexer 613 are selected, the second processor 50 is not connected to the bus 10, and the preset information DC1 is output to the bus 10; at the same time, the verification result DB1 output by the second processor 50 is output to the functional status determination module 70.

[0042] In some embodiments, Figure 8 As shown, the functional status determination module includes a comparison unit and a status determination unit 72 .

[0043] The comparison unit 71 is connected to the first processor 30 and the second processor 50 respectively to obtain the first processing result DA1 and the verification result DB1, and output the comparison result of the first processing result DA1 and the verification result DB1. In some embodiments, the comparison unit 71 may include a comparator circuit; of course, in other embodiments of the present application, the comparison unit 71 may also be any other element capable of performing a comparison action, such as a processor, which is not limited in the present application. The state determination unit 72 is connected to the comparison unit 71, and the state determination unit 72 is used to obtain the comparison result, and determine whether the functions of the first processor 30 and the second processor 50 are normal based on the comparison result. Specifically, if the state determination unit 72 determines that the comparison result is that the first processing result DA1 is the same as the verification result DB1, it can be determined that the functions of the first processor 30 and the second processor 50 are normal; conversely, if the state determination unit 72 determines that the comparison result is that the first processing result DA1 is different from the verification result DB1, it can be determined that the functions of the first processor 30 and / or the second processor 50 are abnormal. In some embodiments, the state determination unit 72 includes a microcontroller unit (MCU); of course, in other embodiments of the present application, the state determination unit 72 may also be any other circuit element that can index or determine the corresponding state based on the input comparison result, and the present application does not limit this.

[0044] In some embodiments, after determining whether the functions of the first processor 30 and the second processor 50 are normal based on the comparison result, the status determination unit 72 can report the determination result to the upper-level device (such as the processor of the upper computer) so that the upper-level device performs corresponding operations according to the received determination result. For example, in a specific embodiment, the upper-level device determines that the function of the first processor 30 is abnormal according to the determination result, then the upper-level device controls the first processor 30 to stop working and outputs an alarm signal.

[0045] It can be understood that, when the state configuration module 60 configures the second processor 50 to be in the second working state, the comparison unit 71 works and outputs the comparison result, and the state determination unit 72 determines whether the first processor 30 and the second processor 50 are normal according to the comparison result. When the state configuration module 60 configures the second processor 50 to be in the first working state, the comparison unit 71 and the state determination unit 72 stop working.

[0046] In some embodiments, Fig. 9As shown, the laser radar chip 100 includes a plurality of first processors 30, a plurality of first data reading modules 20, a plurality of second processors 50 and a plurality of second data reading modules 40, the state configuration module 60 includes a plurality of multiplexing modules 61, and the functional state determination module 70 includes a plurality of comparison units 71, and each first processor 30 corresponds to a first data reading module 20, a second processor 50, a second data reading module 40, a multiplexing module 61 and a comparison unit 71. Each multiplexing module 61 is respectively connected to the configuration register 62, and each comparison unit 71 is respectively connected to the state determination unit 72.

[0047] Specifically, the plurality of first processors 30 include a first first processor 30, a second first processor 30, ..., and an Nth first processor 30, wherein N is an integer greater than 1. The plurality of first data reading modules 20 include a first first data reading module 20, a second first data reading module 20, ..., and an Nth first data reading module 20. The plurality of second processors 50 include a first second processor 50, a second second processor 50, ..., and an Nth second processor 50. The plurality of second data reading modules 40 include a first second data reading module 40, a second second data reading module 40, ..., and an Nth second data reading module 40. The plurality of multiplexing modules 61 include a first multiplexing module 61, a second multiplexing module 61, ..., and an Nth multiplexing module 61. The plurality of comparing units 71 include a first comparing unit 71, a second comparing unit 71, ..., and an Nth comparing unit 71.

[0048] The first first processor 30 corresponds to the first first data reading module 20, the first second processor 50, the first second data reading module 40, the first multiplexing module 61 and the first comparing unit 71; the second first processor 30 corresponds to the second first data reading module 20, the second second processor 50, the second second data reading module 40, the second multiplexing module 61 and the second comparing unit 71; ...; the Nth first processor 30 corresponds to the Nth first data reading module 20, the Nth second processor 50, the Nth second data reading module 40, the Nth multiplexing module 61 and the Nth comparing unit 71. The first multiplexing module 61, the second multiplexing module 61, ..., the Nth multiplexing module 61 are connected to the configuration register 62, and the first comparing unit 71, the second comparing unit 71, ..., the Nth comparing unit 71 are connected to the state determining unit 72. It should be noted that each multiplexing module 61 includes a third multiplexer 613, but considering that the third multiplexer 613 and the first / second multiplexers are distributed on both sides of the second processor 50, it is not convenient to show. Fig. 9 Not shown in the figure.

[0049] It is understood that, in addition to the memory M1 and the bus 10, Fig. 9 The other parts of the embodiment shown can be regarded as N such as Figure 1-Figure 8 The specific implementation process of each embodiment is the same. For example, Fig. 9 The first first processor 30, the first first data reading module 20, the first second processor 50, the first second data reading module 40, the first multiplexing module 61 and the first comparing unit 71 in the embodiment can be used as follows: Figure 1-Figure 8 For any of the embodiments shown in the figure, the specific implementation process can refer to Figure 1-Figure 8 Description.

[0050] In this embodiment, on the one hand, multiple first processors 30 are provided to increase the computing power of the laser radar chip 100 and improve the performance; on the other hand, a corresponding second processor 50 is provided for each first processor 30 to further increase the computing power of the laser radar chip 100, or functional safety verification is performed on each group of corresponding first processors 30 and second processors 50 to improve the safety and reliability of the laser radar chip 100.

[0051] It should be noted that the signals output by different first data reading modules 20 may be the same or different; the first processing results output by different first processors 30 may be the same or different; the signals output by different second data reading modules 40 may be the same or different; the second processing results output by different second processors 50 may be the same or different; the verification results output by different second processors 50 may be the same or different; and the addresses at which different data reading modules (including each first data reading module 20 and each second data reading module 40) read data from the memory M1 may be the same or different.

[0052] It should be noted that, in this embodiment, the one-to-one correspondence between the first processor 30 and the second processor 50 is taken as an example. In other embodiments, any number of first processors 30 may be set to correspond to any data of second processors. For example, in a specific embodiment, one first processor 30 is set to correspond to multiple second processors 50, and the functional safety can be verified by multiple second processors 50 together, which can more effectively improve the safety; for example, in another specific embodiment, multiple first processors 30 are set to correspond to one second processor 50, and the functions of multiple first processors 30 can be verified by one second processor 50 at the same time, so as to save costs.

[0053] In some embodiments, Fig.10As shown, the laser radar chip 100 further includes a monitoring module 80. The monitoring module 80 is connected to the bus 10 and the state configuration module 60 respectively.

[0054] The monitoring module 80 is used to determine the current computing load through the bus 10, and output a feedback signal to the state configuration module 60 based on the current computing load and the preset computing load. The state configuration module 60 is also used to control at least one second processor 50 to be in the first working state when it is determined based on the feedback signal that the current computing load is greater than or equal to the preset computing load, and to control each second processor 50 to be in the second working state when it is determined based on the feedback signal that the current computing load is less than the preset computing load.

[0055] Specifically, the current computing load is the total computing power that each first processor 30 and each second processor 50 currently needs to provide for the load. The preset computing load is the total computing power that each first processor 30 and each second processor 50 preset to provide for the preset load. For example, in some embodiments, the preset computing load may be a preset multiple of the sum of the computing powers of all first processors 30; taking the laser radar chip 100 including four first processors 30 as an example, the preset computing load may be 1 times, 0.95 times, 0.85 times, or 1.05 times, etc., of the sum of the computing powers of the four first processors 30.

[0056] If the current computing power load is greater than or equal to the preset computing power load, it is determined that the total computing power preset by each first processor 30 and each second processor 50 is less than the total computing power required by the current load, that is, the total computing power preset by each first processor 30 and each second processor 50 cannot meet the demand, and the total computing power needs to be increased. Based on this, at least one second processor 50 can be controlled to be in the first working state so that at least one second processor 50 can be used to process data, thereby increasing the total computing power to meet the total computing power required by the current load.

[0057] If the current computing load is less than the preset computing load, it is determined that the total computing power preset by each first processor 30 and each second processor 50 is greater than the total computing power required by the current load, that is, the total computing power preset by each first processor 30 and each second processor 50 can meet the demand. Based on this, each second processor 50 can be controlled to be in the second working state, so that each second processor 50 can be used to verify functional safety, thereby improving the safety and reliability of the laser radar chip 100. Specifically, if at least one second processor 50 was previously in the first working state, at least some of the second processors 50 can be switched to the second working state to perform functional safety monitoring.

[0058] It should be understood that even if the above embodiment takes the preset computing power load as a fixed value as an example to illustrate the switching principle of the second processor 50, the present application is not limited to this. In other embodiments of the present application, the preset computing power load may also be variable; for example, in some other embodiments of the present application, the preset computing power load may be a preset multiple of the sum of the computing power of all current first processors 30 and the second processor 50 in the first working state. In this way, the laser radar chip 100 can gradually switch at least one second processor 50 in the second working state to the first working state in a gradual manner, so that the total computing power of the current laser radar chip 100 is gradually increased from lower than the current computing power load to slightly higher than the current computing power load to meet the corresponding computing power requirements; or, gradually switch at least one second processor 50 in the first working state to the second working state in a gradual manner, so that the total computing power of the current laser radar is gradually reduced from significantly higher than the current computing power load to slightly higher than the current computing power load to meet the corresponding computing power requirements, while avoiding excess computing power, and can also provide higher quality functional safety monitoring.

[0059] In some embodiments, Fig.11 As shown, the laser radar chip 100 further includes a reset module 90. The reset module 90 is connected to the state configuration module 60 and the second processor 50 respectively.

[0060] Specifically, the reset module 90 is configured to reset the second processor 50 under the control of the state configuration module 60. When the state configuration module 60 configures the second processor 50 to switch from the first working state to the second working state or from the second working state to the first working state, the state configuration module 60 can control the reset module 90 to reset the second processor 50 to clear all registers, caches and other internal state information inside the second processor 50, thereby ensuring that the second processor 50 can start running from the correct state after switching the working state, thereby avoiding uncertain behavior or error state.

[0061] In some embodiments, when controlling the second processor 50 to switch from one of the first working state and the second working state to another, the state configuration module 60 may control the reset module 90 to reset the second processor 50, and the configuration register 62 controls the corresponding multiplexing module 61 to perform the corresponding selection operation according to the working state after the second processor 50 is switched; thereafter, after waiting for a preset period of time, it is determined that the reset operation of the second processor 50 has been completed, that is, all registers, caches and other internal state information inside the second processor 50 have been cleared, then the state configuration module 60 controls the reset module 90 to no longer reset the second processor 50.

[0062] In summary, for the laser radar chip 100, by configuring the second processor 50 to switch between the first working state and the second working state, the laser radar chip 100 can be applied to application scenarios with higher performance requirements and application scenarios with functional safety requirements, thereby achieving the functional safety requirements and higher performance requirements through one chip. Secondly, setting up multiple first processors 30 is conducive to increasing the computing power of the laser radar chip 100 and improving performance. Furthermore, a corresponding second processor 50 is set for each first processor 30 to further increase the computing power of the laser radar chip 100 or perform functional safety verification on each first processor 30 and each second processor 50, which is conducive to improving the safety and reliability of the laser radar chip 100. In addition, by setting up multiple second processors 50 and switching the working state of the second processor 50 according to the actual computing power load, it is possible to maintain the laser radar chip 100 to provide sufficient computing power for the actual computing power load. Furthermore, if there is excess computing power, the excess second processor 50 (i.e., the second processor 50 that does not need to provide computing power) can be used to implement the security of the verification function, so as to improve the safety and reliability of the laser radar chip 100.

[0063] Please refer to Fig.12 , Fig.12 Flow chart of the operation method of the laser radar chip provided in the embodiment of the present application. Figure 9-11 The laser radar chip 100 shown in FIG. Fig.12 As shown, the operating method of the laser radar chip includes the following method steps: Step 1201: Determine the current computing load of the lidar chip.

[0064] Step 1202: If the current computing power load is higher than a preset multiple of the total computing power of each computing processor, control at least one second processor to switch from the second working state to the first working state so that the preset multiple of the total computing power of each computing processor is higher than the current computing power load, wherein the computing processor includes a first processor and a second processor in the first working state.

[0065] Step 1203: If the current computing power load is lower than the preset multiple of the total computing power of each computing processor, control at least one second processor to switch from the first working state to the second working state so that the preset multiple of the total computing power of each computing processor is still higher than the current computing power load.

[0066] Specifically, when the current computing power load is higher than the preset multiple of the total computing power of each computing processor, the actual workload (i.e., load) allocated to each computing processor has exceeded a predetermined proportion or multiple of the maximum theoretical computing power that each computing processor can provide. This situation may lead to problems such as performance degradation, increased latency, and impaired quality of service (QoS). In this case, controlling at least one second processor to switch from the second working state to the first working state so that the preset multiple of the total computing power of each computing processor is higher than the current computing power load can alleviate the computing pressure of each computing processor, thereby enabling each computing processor to operate stably and efficiently.

[0067] When the current computing load is lower than the preset multiple of the total computing power of each computing processor, the actual workload assigned to each computing processor does not reach a predetermined ratio or multiple of the maximum theoretical computing power that each computing processor can provide, which will lead to a waste of resources. In this case, at least one second processor switches from the first working state to the second working state so that the preset multiple of the total computing power of each computing processor is still higher than the current computing load, which not only ensures that each computing processor can still operate stably and efficiently, but also utilizes the redundant second processor 50 for functional safety verification to improve the safety and reliability of the laser radar chip 100.

[0068] An embodiment of the present application also provides a laser radar, which includes the laser radar chip 100 in any embodiment of the present application.

[0069] The laser radar can be a mechanical laser radar, a solid-state laser radar, a semi-solid-state laser radar, etc., and this application does not impose any limitation on this. The laser radar can be applied to any device that requires laser detection, such as a mobile robot, a ship, or a mobile robot. Fig.13 The vehicle 1301 shown in the figure. When the laser radar 1302 is applied to the vehicle 1301, the laser radar 1302 can detect the distance and speed of the vehicle 1301 relative to the obstacle. The vehicle 1301 detects nearby moving or approaching obstacles through the laser radar 1302, such as taller vehicles, still objects on the roadside, and suddenly approaching suspended flying objects, so that the vehicle 1301 can plan a path that can avoid obstacles based on the detected information, so that the vehicle 1301 can avoid colliding with obstacles. The vehicle 1301 can be an autonomous driving vehicle or an ordinary vehicle, and this application does not make the sole limitation on this.

[0070] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

[0071] The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them. Under the idea of ​​the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. It should be understood by ordinary technicians in this field that they can still modify the technical solutions recorded in the above embodiments, or replace some of the technical features by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A laser radar chip, characterized in that: It includes a bus, a first data reading module, a first processor, a second data reading module, a second processor, a state configuration module and a function state determination module; The first data reading module is used to obtain data from the memory; The first processor is connected to the bus and the first data reading module respectively, and is used to receive and process the data output by the first data reading module to obtain a first processing result; The second data reading module is used to obtain data from the memory; The state configuration module is used to configure the second processor to switch between a first working state and a second working state. In the first working state, the second processor is connected to the bus. The second processor is used to receive and process the data output by the second data reading module to obtain a second processing result and output it to the bus. In the second working state, the second processor is used to receive and process the data output by the first data reading module to obtain a verification result. The functional status determination module is connected to the first processor and the second processor respectively. The functional status determination module is used to obtain the first processing result and the verification result when the second processor is in the second working state, and determine whether the functions of the first processor and the second processor are normal based on the comparison result between the first processing result and the verification result.

2. The laser radar chip according to claim 1, characterized in that: The first data reading module and / or the second data reading module comprises a logic circuit; The first data reading module and the second data reading module are used to read data from different address areas of the memory; The laser radar chip includes the memory, or the memory is a memory outside the laser radar chip.

3. The laser radar chip according to claim 1, characterized in that: The state configuration module includes: a multiplexing module having a first input portion, a second input portion and a first output portion, wherein the first input portion is connected to the first data reading module for receiving data output by the first data reading module, the second input portion is connected to the second data reading module for receiving data output by the second data reading module, and the first output portion is connected to the second processor; and The configuration register is used to configure the multiplexing module so that one of the first input part and the second input part of the multiplexing module is connected to the first output part.

4. The laser radar chip according to claim 3, characterized in that: The multiplexing module comprises: a first multiplexer connected to the configuration register, having a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is connected to the first data reading module and is used to receive a first read instruction acquired from the memory by the first data reading module, the second input terminal is connected to the second data reading module and is used to receive a second read instruction acquired from the memory by the second data reading module, and the first output terminal is connected to the second processor; and a second multiplexer connected to the configuration register, having a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal is connected to the first data reading module and is used to receive the first data acquired from the memory by the first data reading module, the fourth input terminal is connected to the second data reading module and is used to receive the second data acquired from the memory by the second data reading module, and the second output terminal is connected to the second processor; The first input end and the third input end together constitute the first input part, the second input end and the fourth input end together constitute the second input part, and the first output end and the second output end together constitute the first output part; The configuration register is used to configure the first multiplexer and the second multiplexer so that: The first input terminal is connected to the first output terminal, and the third output terminal is connected to the second output terminal; or, The second input terminal is gated to the first output terminal, and the fourth input terminal is gated to the second output terminal.

5. The laser radar chip according to claim 3, characterized in that: The multiplexing module further comprises a third multiplexer, wherein the third multiplexer is connected to the configuration register; The third multiplexer has a fifth input terminal, a sixth input terminal and a third output terminal, the fifth input terminal is connected to the second processor and is used to receive the second processing result or the verification result output by the second processor, the sixth input terminal is used to obtain preset information, and the third output terminal is connected to the bus; The configuration register is used to configure the third multiplexer so that: When the second processor is in the first working state, the fifth input terminal and the third output terminal are switched on; as well as When the second processor is in the second working state, the sixth input terminal and the third output terminal are selected.

6. The laser radar chip according to claim 3, characterized in that: The functional status determination module includes: a comparison unit, connected to the first processor and the second processor respectively, to obtain the first processing result and the verification result, and output a comparison result between the first processing result and the verification result; and A state determination unit is connected to the comparison unit, and is used to obtain the comparison result, and determine whether the functions of the first processor and the second processor are normal based on the comparison result.

7. The laser radar chip according to claim 6, characterized in that: The laser radar chip includes a plurality of the first processors, a plurality of the first data reading modules, a plurality of the second processors and a plurality of the second data reading modules, the state configuration module includes a plurality of the multiplexing modules, the functional state determination module includes a plurality of comparison units, and each of the first processors corresponds to a first data reading module, a second processor, a second data reading module, a multiplexing module and a comparison unit; Each of the multiplexing modules is connected to the configuration register respectively, and each of the comparing units is connected to the state determining unit respectively.

8. The laser radar chip according to claim 7, characterized in that: The laser radar chip also includes a monitoring module; The monitoring module is connected to the bus and the state configuration module respectively, and the monitoring module is used to determine the current computing load through the bus, and output a feedback signal to the state configuration module based on the current computing load and the preset computing load; The state configuration module is also used to control at least one of the second processors to be in the first working state when it is determined based on the feedback signal that the current computing power load is greater than or equal to the preset computing power load, and to control each of the second processors to be in the second working state when it is determined based on the feedback signal that the current computing power load is less than the preset computing power load.

9. The laser radar chip according to claim 3, characterized in that: The laser radar chip also includes a reset module; The reset module is connected to the state configuration module and the second processor respectively, and the reset module is configured to be controlled by the state configuration module to reset the second processor.

10. A method for operating a laser radar chip, characterized in that: Applied to the laser radar chip as claimed in claim 7 or 8, the method comprises: Determining the current computing load of the lidar chip; If the current computing power load is higher than a preset multiple of the total computing power of each computing processor, control at least one of the second processors to switch from the second working state to the first working state, so that the preset multiple of the total computing power of each computing processor is higher than the current computing power load, wherein the computing processor includes a first processor and a second processor in the first working state; If the current computing power load is lower than a preset multiple of the total computing power of each computing processor, control at least one of the second processors to switch from the first working state to the second working state so that the preset multiple of the total computing power of each computing processor is still higher than the current computing power load.

11. A laser radar, characterized in that: Comprising a laser radar chip as described in any one of claims 1 to 9.

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