Fast charging protocol control device compatible with multiple fast charging protocols

Abstract

The invention discloses a fast charging protocol control device compatible with multiple fast charging protocols, and the device is characterized in that a Type-C controller is connected with a tested fast charging power supply and a main DSP controller, and achieves the control modes of PD2.0 and PD3.0 fast charging protocols of the tested fast charging power supply; the ADC1 and the ADC2 are respectively connected with the tested fast charging power supply and the main DSP controller, the main DSP controller is connected with the electronic load, and a control mode of ID identification of the tested fast charging power supply is realized; the DAC1 and the DAC2 are respectively connected with the tested fast charging power supply and the main DSP controller, the main DSP controller is connected with the electronic load, and the control mode of QC2.0 and QC3.0 fast charging protocols of the tested fast charging power supply is realized; and the Timer is connected with the main DSP controller and the tested fast charging power supply to realize a control mode of AFC, FCP and SCP fast charging protocols of the tested fast charging power supply.

Description

Technical Field

[0001] The present invention relates to the field of charging technology, and in particular to a fast charging protocol control device compatible with multiple fast charging protocols. Background Art

[0002] Electronic loads have been widely used in the power supply industry and are an indispensable part of power supply industry test automation. However, electronic loads can only control the load conditions of the power supply under test and can only adapt to traditional fixed-output power supplies, but are difficult to meet the testing requirements of fast-charging power supplies. Fast-charging power supplies require a variety of protocols to control the output status of fast-charging power supplies.

[0003] There are many popular fast charging protocols on the market, and they are constantly being updated. The application of power supply testing has strong universal requirements and needs to be compatible with most communication protocols, which poses a severe challenge to fast charging electronic loads. Summary of the invention

[0004] Technical purpose: In view of the defects in the prior art, the present invention discloses a fast charging protocol control device that is compatible with multiple fast charging protocols, which can realize matching and communication with the fast charging power source under test based on multiple fast charging protocols when the output characteristics of the fast charging power source under test are tested through an electronic load, thereby realizing control of the output voltage and current characteristics of the fast charging power source under test, as well as detection of the types of protocols supported by the fast charging power source under test and the adjustable methods.

[0005] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0006] A fast charging protocol control device compatible with multiple fast charging protocols includes a main DSP controller, ADC1, ADC2, ADC3, DAC1, DAC2, Timer, UART, a Type-C controller supporting the PD protocol, a voltage signal conditioning circuit, and an electronic load; the Type-C controller is connected to a fast charging power source under test and the main DSP controller to implement the PD2.0 and PD3.0 fast charging protocol control modes of the fast charging power source under test; ADC1 and ADC2 are respectively connected to the fast charging power source under test and the main DSP controller, and the main DSP controller is connected to the electronic load. Used to implement the control mode of ID identification of the fast-charging power supply under test; DAC1 and DAC2 are respectively connected to the fast-charging power supply under test and the main DSP controller, and the main DSP controller is connected to the electronic load, which is used to implement the control mode of QC2.0 and QC3.0 fast charging protocols of the fast-charging power supply under test; Timer is connected to the main DSP controller and the fast-charging power supply under test, which is used to implement the control mode of AFC, FCP, and SCP fast charging protocols of the fast-charging power supply under test; UART is connected to the main DSP controller and the fast-charging power supply under test, which is used to implement the control mode of UFCS fast charging protocol of the fast-charging power supply under test.

[0007] Furthermore, the main DSP controller is connected to the electronic load through the CAN bus, and the main DSP controller controls the Type-C controller that supports the PD protocol through the IIC bus. The CC1 signal terminal and CC2 signal terminal of the Type-C controller are connected one by one with the CC1 signal terminal and CC2 signal terminal of the fast charging power supply under test.

[0008] Furthermore, in the control mode of PD2.0 and PD3.0 fast charging protocols, the main DSP controller sends instructions to the Type-C controller that supports the PD protocol through the IIC bus, instructing it to communicate with the fast charging power supply under test through the CC1 signal terminal and the CC2 signal terminal to inquire whether it supports the PD2.0 or PD3.0 fast charging protocol. The Type-C controller that supports the PD protocol transmits the information to the main DSP controller through the IIC bus. The main DSP controller determines whether the output specifications of the fast charging power supply under test required by the electronic load match the information based on the information. If they match, the Type-C controller that supports the PD protocol communicates with the fast charging power supply under test through the IIC bus command, and the fast charging power supply under test adjusts its output state to the output state specified by the electronic load, that is, controls the output voltage and maximum output current of the fast charging power supply under test, thereby completing the PD2.0 or PD3.0 fast charging protocol control of the fast charging power supply under test.

[0009] Furthermore, ADC1 is connected to the fast-charging power supply under test, and is used to receive a first analog signal output from the D+ signal terminal of the fast-charging power supply under test. ADC1 performs analog-to-digital conversion on the first analog signal and outputs a first digital signal to the main DSP controller; ADC2 is connected to the fast-charging power supply under test, and is used to receive a second analog signal output from the D- signal terminal of the fast-charging power supply under test. ADC2 performs analog-to-digital conversion on the second analog signal and outputs a second digital signal to the main DSP controller; the main DSP controller completes voltage detection of the D+ signal terminal and the D- signal terminal of the fast-charging power supply under test through ADC1 and ADC2, and realizes ID identification of the fast-charging power supply under test according to the voltage detection result.

[0010] Furthermore, in the control mode of ID identification, the main DSP controller performs analog-to-digital conversion on the first analog signal at the D+ signal end of the fast charging power supply under test through ADC1 to obtain a first digital signal V_D+; the main DSP controller performs analog-to-digital conversion on the second analog signal at the D- signal end of the fast charging power supply under test through ADC2 to obtain a second digital signal V_D-. The main DSP controller uploads the first digital signal V_D+ and the second digital signal V_D- to the electronic load through the CAN bus, and performs ID legitimacy judgment on the first digital signal V_D+ and the second digital signal V_D- based on preset maximum and minimum values.

[0011] Furthermore, DAC1 is connected to the main DSP controller, and is used to receive the third digital signal of the main DSP controller, and output the third analog signal after digital-to-analog conversion, so as to control the D+ signal terminal of the fast charging power supply under test; DAC2 is connected to the main DSP controller, and is used to receive the fourth digital signal of the main DSP controller, and output the fourth analog signal after digital-to-analog conversion, so as to control the D- signal terminal of the fast charging power supply under test; the main DSP controller completes the adjustment of the D+ signal terminal and D- signal terminal of the fast charging power supply under test by controlling DAC1 and DAC2, thereby realizing the analysis and control of QC2.0 and QC3.0 fast charging protocols.

[0012] Furthermore, in the control mode of QC2.0 or QC3.0 fast charging protocol, the electronic load obtains the fast charging protocol matched by the fast charging power supply under test, that is, QC2.0 or QC3.0, and according to the set output voltage and maximum output current of the power supply under test, the output voltage combination of D+ and D- signals is obtained by looking up the table according to the protocol content, and the main DSP controller is notified through the CAN bus. The main DSP controller controls the voltage of the D+ signal end at the corresponding value obtained by looking up the table through DAC1, and the main DSP controller controls the voltage of the D- signal end at the corresponding value obtained by looking up the table through DAC2, thereby allowing the fast charging power supply under test to output the set voltage and maximum current, completing the fast charging protocol control of QC2.0 or QC3.0.

[0013] Furthermore, one end of the Timer is connected to the main DSP controller, and the other end is connected to the D-signal end of the fast charging power supply under test. Under the control mode of AFC, FCP, and SCP fast charging protocols, the electronic load obtains and controls the fast charging protocol matched by the fast charging power supply under test, namely AFC, FCP or SCP, and according to the set output voltage and maximum output current of the power supply under test, the command word obtained by looking up the table according to the protocol content is encoded by the main DSP controller through the control of the Timer to control the D-signal end of the fast charging power supply under test to receive the preset pulse.

[0014] Furthermore, the UART is connected to the main DSP controller, the D+ signal terminal of the fast-charging power supply under test, and the D- signal terminal of the fast-charging power supply under test. The main DSP controller completes serial communication with the fast-charging power supply under test through the UART, and completes the parsing and control of the UFCS fast charging protocol; in the UFCS fast charging protocol control mode, the main DSP controller enables the UART and communicates with the fast-charging power supply under test through the serial port. The electronic load obtains and controls the UFCS fast charging protocol matched by the fast-charging power supply under test, and transmits the voltage and maximum output current required to be output by the power supply under test to the main DSP controller through the CAN bus. The main DSP controller transmits them to the fast-charging power supply under test through the UART, and the fast-charging power supply under test adjusts its output voltage and maximum output current according to the protocol.

[0015] Beneficial effects: 1. When the present invention tests the output characteristics of the fast-charge power source under test through an electronic load, it matches and communicates with the fast-charge power source under test based on multiple fast-charge protocols to achieve control of the output voltage and current characteristics of the fast-charge power source under test, as well as detection of the protocol types and adjustable modes supported by the fast-charge power source under test; 2. The present invention can support fast charging protocols such as PD2.0, PD3.0, QC2.0, QC3.0, PE1.0, PE2.0, AFC, FCP, SCP, UFCS, etc.; 3. The present invention can query and display all fast charging protocols supported by the fast charging power source under test, as well as the optional options of its output specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the structure of a fast charging protocol control device compatible with multiple fast charging protocols according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a Type-C controller supporting the PD protocol according to an embodiment of the present invention; Figure 3 This is an example diagram of PE fast charging protocol control according to an embodiment of the present invention; Figure 4 This is an example diagram of AFC, FCP, and SCP fast charging protocol control according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] It should be noted that the terms used herein are only for describing specific implementation methods, and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the unit form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or their combinations.

[0019] As attached Figure 1As shown, a fast charging protocol control device compatible with multiple fast charging protocols in this embodiment includes: a main DSP controller, ADC1, ADC2, ADC3, DAC1, DAC2, Timer, UART, a Type-C controller supporting the PD protocol, a voltage signal conditioning circuit, and an electronic load; the Type-C controller is connected to the fast charging power supply under test and the main DSP controller to implement the PD2.0 and PD3.0 fast charging protocol control modes of the fast charging power supply under test; ADC1 and ADC2 are respectively connected to the fast charging power supply under test and the main DSP controller, and the main DSP controller is connected to the electronic The load is connected to realize the control mode of ID identification of the fast-charging power supply under test; DAC1 and DAC2 are respectively connected to the fast-charging power supply under test and the main DSP controller, and the main DSP controller is connected to the electronic load to realize the control mode of QC2.0 and QC3.0 fast charging protocols of the fast-charging power supply under test; Timer is connected to the main DSP controller and the fast-charging power supply under test to realize the control mode of AFC, FCP, and SCP fast charging protocols of the fast-charging power supply under test; UART is connected to the main DSP controller and the fast-charging power supply under test to realize the control mode of UFCS fast charging protocol of the fast-charging power supply under test.

[0020] Specifically, ADC1, ADC2, ADC3, DAC1, DAC2, Timer, UART, Type-C controller, and voltage signal conditioning circuit are connected to the fast charging power supply under test, the voltage signal conditioning circuit is connected to the main DSP controller through ADC3, the main DSP controller is connected to ADC1, ADC2, ADC3, DAC1, DAC2, Timer, UART, Type-C controller and electronic load, wherein ADC1, ADC2, DC1, DAC2, Timer, and UART are connected to the main DSP controller through an internal bus, the main DSP controller is connected to the electronic load through a CAN bus, the main DSP controller controls the Type-C controller supporting the PD protocol through an IIC bus, the CC1 signal terminal and CC2 signal terminal of the Type-C controller are connected one-to-one with the CC1 signal terminal and CC2 signal terminal of the fast charging power supply under test, and the Type-C controller supporting the PD protocol completes the parsing and control of the PD2.0 and PD3.0 fast charging protocols of the fast charging power supply under test.

[0021] As attached Figure 2As shown, in the control mode of PD2.0 and PD3.0 fast charging protocols, the main DSP controller sends instructions to the Type-C controller supporting the PD protocol through the IIC bus, so that it communicates with the fast charging power supply under test through the CC1 signal terminal and the CC2 signal terminal to query whether it supports the PD2.0 or PD3.0 fast charging protocol. If it does, query which output specifications the fast charging power supply under test supports. The Type-C controller supporting the PD protocol transmits this information to the main DSP controller through the IIC bus. The main DSP controller determines whether the output specifications of the fast charging power supply under test required by the electronic load match the above information based on this information, that is, the output specifications of the fast charging power supply under test are set through the electronic load, and the output voltage of the fast charging power supply under test is controlled through the fast charging protocol. If it matches, the Type-C controller supporting the PD protocol is commanded to communicate with the fast charging power supply under test through the IIC bus, so that the fast charging power supply under test adjusts its output state to the output state specified by the electronic load, that is, controls the output voltage and maximum output current of the fast charging power supply under test, thereby completing the PD2.0 or PD3.0 fast charging protocol control of the fast charging power supply under test. The output voltage and maximum output current of the fast charging power supply under test correspond to the output specifications of the fast charging power supply under test, such as 5V / 3A, 12V / 2A, etc.

[0022] As attached Figure 2 As shown, the Type-C controller includes a control chip U1, and the model of the control chip U1 is FUSB302B; pin 1 and pin 14 of the control chip U1 are connected to connect to the CC2 signal end; pin 10 and pin 11 of the control chip U1 are connected to connect to the CC1 signal end; pin 2 of the control chip U1 outputs a VBUS signal, pin 6 and pin 7 of the control chip U1 output an SCL signal and an SDA signal respectively, and pin 5 of the control chip U1 outputs an INT signal. The Type-C controller communicates with the main DSP controller through the IIC bus, that is, through the three signals of INT signal, SCL signal and SDA signal.

[0023] ADC1 is an analog-to-digital conversion module, which is connected to the fast-charging power supply under test and is used to receive a first analog signal output from the D+ signal terminal of the fast-charging power supply under test. ADC1 performs analog-to-digital conversion on the first analog signal and outputs a first digital signal to the main DSP controller. ADC2 is an analog-to-digital conversion module, which is connected to the fast-charging power supply under test and is used to receive a second analog signal output from the D- signal terminal of the fast-charging power supply under test. ADC2 performs analog-to-digital conversion on the second analog signal and outputs a second digital signal to the main DSP controller. The main DSP controller completes voltage detection of the D+ signal terminal and the D- signal terminal of the fast-charging power supply under test through ADC1 and ADC2, and realizes ID identification of the fast-charging power supply under test according to the voltage detection results.

[0024] In the control mode of ID identification, the main DSP controller performs analog-to-digital conversion on the first analog signal of the D+ signal end of the tested fast charging power source through ADC1, and obtains the voltage of the D+ signal end, that is, the first digital signal V_D+; the main DSP controller performs analog-to-digital conversion on the second analog signal of the D- signal end of the tested fast charging power source through ADC2, and obtains the voltage of the D- signal end, that is, the second digital signal V_D-. The main DSP controller uploads the first digital signal V_D+ and the second digital signal V_D- to the electronic load through the CAN bus. The electronic load displays the size of the first digital signal V_D+ and the second digital signal V_D- in real time on the human-machine interface. It can also perform ID legitimacy judgment on the first digital signal V_D+ and the second digital signal V_D- according to the preset maximum and minimum values, and can also be uploaded to the host computer software for ID legitimacy judgment. ID legitimacy judgment is to measure and determine whether the voltage combination on D+ and D- is consistent with the combination corresponding to the preset ID. The combination corresponding to the preset ID can be the voltage combination provided by the manufacturer.

[0025] DAC1 is a digital-to-analog conversion module, which is connected to the main DSP controller, used to receive the third digital signal of the main DSP controller, output the third analog signal after digital-to-analog conversion, and control the D+ signal end of the fast-charging power supply under test; DAC2 is a digital-to-analog conversion module, which is connected to the main DSP controller, used to receive the fourth digital signal of the main DSP controller, output the fourth analog signal after digital-to-analog conversion, and control the D- signal end of the fast-charging power supply under test; the main DSP controller completes the adjustment of the D+ signal end and the D- signal end of the fast-charging power supply under test by controlling DAC1 and DAC2, thereby realizing the analysis and control of QC2.0 and QC3.0 fast charging protocols.

[0026] In the control mode of QC2.0 or QC3.0 fast charging protocol, the electronic load obtains the fast charging protocol matched by the fast charging power supply under test from the human-machine interface or the upper computer software, that is, QC2.0 or QC3.0, and obtains the output voltage combination of D+ and D- signals according to the set output voltage and maximum output current of the power supply under test and the protocol content, and then notifies the main DSP controller through the CAN bus. The main DSP controller controls the voltage of the D+ signal end at the corresponding value obtained by the table lookup through DAC1, and the main DSP controller controls the voltage of the D- signal end at the corresponding value obtained by the table lookup through DAC2, thereby allowing the fast charging power supply under test to output the set voltage and maximum current, completing the fast charging protocol control of QC2.0 or QC3.0. The output voltage combination is as follows:

[0027] Timer is a timer, one end of which is connected to the main DSP controller, and the other end is connected to the D- signal end, ADC2, DAC2, and UART of the fast charging power supply under test; As attached Figure 4 As shown, the main DSP controller controls the output level and duration of the D-signal terminal by operating the Timer, that is, communicates through the D-signal terminal to realize the encoding and control of the AFC, FCP, and SCP fast charging protocols.

[0028] In the control mode of AFC, FCP, and SCP fast charging protocols, the electronic load obtains the fast charging protocol matched by the fast charging power supply under test from the human-machine interface or the host computer software, i.e., AFC, FCP, or SCP, and according to the set output voltage and maximum output current of the power supply under test, the command word obtained by the table lookup according to the protocol content is encoded by the main DSP controller through the control of the Timer to control the D-signal end of the fast charging power supply under test to receive the preset pulse. When each bit of the command word is high, a high level with a duration of 160uS is output, and when each bit of the command word is low, a low level with a duration of 160uS is output. In addition to completing the encoding of the Timer, the main DSP controller decodes the Timer. Every time a high level is detected for 160uS, it is decoded as 1, and every time a low level is detected for 160uS, it is decoded as 0. The synchronization signal of the data is a 40uS pulse. That is to say, the main DSP controller controls the output of the Timer and uses a 40uS pulse to determine the start and end of the communication. Every time a 1 is output, the level of the D-signal terminal is pulled up for 160uS, and every time a 0 is output, the level of the D-signal terminal is pulled down for 160uS. The output of the Timer is a digital signal, which has only two states: high level and low level. The Timer can detect and control its duration. Figure 4 As shown, attached Figure 4 It shows the process of encoding and decoding the Timer by the main DSP controller.

[0029] The UART is connected to the main DSP controller, the D+ signal terminal of the fast-charging power supply under test, and the D- signal terminal of the fast-charging power supply under test. The main DSP controller completes serial communication with the fast-charging power supply under test through the UART, and completes the analysis and control of the UFCS fast-charging protocol.

[0030] In the UFCS fast-charge protocol control mode, the main DSP controller enables UART and communicates with the fast-charge power supply under test through the serial port, that is, through the D+ signal terminal and the D- signal terminal. The electronic load obtains the UFCS fast-charge protocol that matches the fast-charge power supply under test from the human-machine interface or the host computer software, and transmits the voltage and maximum output current required by the power supply under test to the main DSP controller through the CAN bus. The main DSP controller transmits it to the fast-charge power supply under test through UART. The fast-charge power supply under test adjusts its output voltage and maximum output current according to the protocol. UART is a digital signal TTL level, which is only distinguished by high level and low level. UART is a serial communication protocol that automatically encodes and decodes at a fixed baud rate.

[0031] The electronic load is connected to the main DSP controller, human-machine interface, and host computer software. The electronic load receives the fast charging protocol selection information, output voltage, maximum output current and other information input by the human-machine interface or host computer software, and transmits it to the main DSP controller through the CAN bus. The main DSP controller completes the matching and control of the fast charging protocol.

[0032] As attached Figure 3 As shown in the figure, the electronic load also realizes the analysis and control of PE1.0 or PE2.0 fast charging protocol by controlling the timing of loading current and unloading current. Figure 3 This is a schematic diagram of the PE fast charging protocol control. It is different from other protocols. It does not communicate through the CC line or the D+ and D- signals. Instead, it uses the electronic load to load the pulse current of the output of the fast charging power supply under test to achieve encoding and decoding. The electronic load controls the duration and sequence of the loading and unloading currents to achieve the encoding and decoding of the PE protocol.

[0033] In the control mode of PE1.0 or PE2.0 fast charging protocol, the electronic load obtains the fast charging protocol matched by the fast charging power supply under test from the human-machine interface or the host computer software, that is, PE1.0 or PE2.0, and according to the set output voltage and maximum output current of the power supply under test, the current pulse waveform required by the electronic load is obtained by looking up the table according to the protocol content. Then the electronic load works in CC mode and performs waveform simulation according to the current pulse waveform obtained by looking up the table.

[0034] The electronic load is connected to the host computer software through the RS232 communication interface and the SCPI protocol, receives the instructions of the host computer software, realizes various working modes of the electronic load and the loading of specified parameters, and feeds back the measured electrical parameters and working status to the host computer software, thereby realizing remote control and electrical parameter monitoring of the electronic load, as well as the linkage between the electronic load and other instruments, thereby realizing automatic detection of the power supply under test.

[0035] The voltage signal conditioning circuit is connected to the fast charging power supply under test and ADC3, and is used to collect the voltage V_Bus of the fast charging power supply under test. The voltage V_Bus of the fast charging power supply under test is amplified by the voltage signal conditioning circuit and then outputs the voltage reference value Vf. Vf is sent to ADC3 for analog-to-digital conversion to complete the voltage measurement and is used to implement closed-loop confirmation of the adjustment result of the fast charging protocol. ADC3 is an analog-to-digital converter. In other words, ADC3 and the voltage signal conditioning circuit detect the output voltage of the fast charging power supply under test, confirm whether the control instructions of the fast charging protocol are effectively completed, and implement closed-loop control. The voltage signal conditioning circuit can be a voltage sampling circuit with a resistor divider, which is an existing technical means and will not be elaborated here.

[0036] The Type-C controller is implemented by chip U1. The model of chip U1 is FUSB302B. The circuit connection diagram is as follows: Figure 2 As shown, chip U1 completes the PD2.0 or PD3.0 fast charging protocol parsing and control of the fast charging power supply under test through CC1 and CC2, and transmits the information of the fast charging power supply under test to the main DSP controller through the IIC bus, and receives the matching fast charging protocol and control information of the output specifications of the fast charging power supply under test from the main DSP controller.

[0037] In some embodiments of the present invention, ADC1, ADC2, ADC3, DAC1, DAC2, Timer, and UART are all peripheral devices embedded in an MCU. The MCU can adopt STM32G431CBTX of ST Corporation. The analog inputs of ADC1, ADC2, and ADC3 in the peripheral devices are all input pins and are in a high-impedance state. The analog outputs of DAC1 and DAC2 can be disabled and set to a high-impedance state. The Timer can be used as both input and output. Its output state can be disabled and set to a high-impedance state. The RX pin of UART is an input pin and is in a high-impedance state. The TX pin of UART is an output pin, and its output state can be disabled and set to a high-impedance state.

[0038] As is generally understood, electronic loads can operate in multiple operating modes such as CC, CV, CP, CR, etc., which will not be elaborated here.

[0039] A fast charging protocol control device compatible with multiple fast charging protocols in the present invention can be embedded in an electronic load, communicate with the electronic load through a CAN bus, and thus constitute a complete fast charging electronic load. The fast charging electronic load can not only match and control the output characteristics of the fast charging power source under test while the electronic load tests the output characteristics of the fast charging power source under test according to the fast charging protocol, but also can flexibly scan and detect the output capacity and working condition of the fast charging power source under test, thereby realizing systematic detection and closed-loop control of the fast charging power source under test.

[0040] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A fast charging protocol control device compatible with multiple fast charging protocols, characterized in that: It includes a main DSP controller, ADC1, ADC2, ADC3, DAC1, DAC2, Timer, UART, a Type-C controller supporting the PD protocol, a voltage signal conditioning circuit, and an electronic load; the Type-C controller is connected to the fast-charging power supply under test and the main DSP controller to realize the control mode of the PD2.0 and PD3.0 fast-charging protocols of the fast-charging power supply under test; ADC1 and ADC2 are respectively connected to the fast-charging power supply under test and the main DSP controller, and the main DSP controller is connected to the electronic load to realize the control mode of the ID identification of the fast-charging power supply under test; DAC1 and DAC2 are respectively connected to the fast-charging power supply under test and the main DSP controller, and the main DSP controller is connected to the electronic load to realize the control mode of the QC2.0 and QC3.0 fast-charging protocols of the fast-charging power supply under test; the Timer is connected to the main DSP controller and the fast-charging power supply under test to realize the control mode of the AFC, FCP, and SCP fast-charging protocols of the fast-charging power supply under test; the UART is connected to the main DSP controller and the fast-charging power supply under test to realize the control mode of the UFCS fast-charging protocol of the fast-charging power supply under test.

2. A fast charging protocol control device compatible with multiple fast charging protocols according to claim 1, characterized in that: The main DSP controller is connected to the electronic load through the CAN bus. The main DSP controller controls the Type-C controller that supports the PD protocol through the IIC bus. The CC1 signal terminal and CC2 signal terminal of the Type-C controller are connected one by one with the CC1 signal terminal and CC2 signal terminal of the fast charging power supply under test.

3. A fast charging protocol control device compatible with multiple fast charging protocols according to claim 2, characterized in that: In the control mode of PD2.0 and PD3.0 fast charging protocols, the main DSP controller sends instructions to the Type-C controller that supports the PD protocol through the IIC bus, instructing it to communicate with the fast charging power supply under test through the CC1 signal terminal and the CC2 signal terminal to query whether it supports the PD2.0 or PD3.0 fast charging protocol. The Type-C controller that supports the PD protocol transmits the information to the main DSP controller through the IIC bus. The main DSP controller determines whether the output specifications of the fast charging power supply under test required by the electronic load match the information based on the information. If they match, the Type-C controller that supports the PD protocol communicates with the fast charging power supply under test through the IIC bus command, and the fast charging power supply under test adjusts its output state to the output state specified by the electronic load, that is, controls the output voltage and maximum output current of the fast charging power supply under test, thereby completing the PD2.0 or PD3.0 fast charging protocol control of the fast charging power supply under test.

4. The fast charging protocol control device compatible with multiple fast charging protocols according to claim 1, characterized in that: ADC1 is connected to the fast-charging power source under test, and is used for receiving a first analog signal output from the D+ signal terminal of the fast-charging power source under test. ADC1 performs analog-to-digital conversion on the first analog signal and outputs a first digital signal to the main DSP controller; ADC2 is connected to the fast-charging power source under test, and is used for receiving a second analog signal output from the D- signal terminal of the fast-charging power source under test. ADC2 performs analog-to-digital conversion on the second analog signal and outputs a second digital signal to the main DSP controller; the main DSP controller completes voltage detection of the D+ signal terminal and the D- signal terminal of the fast-charging power source under test through ADC1 and ADC2, and realizes ID identification of the fast-charging power source under test according to the voltage detection result.

5. A fast charging protocol control device compatible with multiple fast charging protocols according to claim 4, characterized in that: In the control mode of ID identification, the main DSP controller performs analog-to-digital conversion on the first analog signal at the D+ signal end of the fast charging power supply under test through ADC1 to obtain a first digital signal V_D+; the main DSP controller performs analog-to-digital conversion on the second analog signal at the D- signal end of the fast charging power supply under test through ADC2 to obtain a second digital signal V_D-. The main DSP controller uploads the first digital signal V_D+ and the second digital signal V_D- to the electronic load through the CAN bus, and makes ID legitimacy judgment on the first digital signal V_D+ and the second digital signal V_D- according to the preset maximum and minimum values.

6. The fast charging protocol control device compatible with multiple fast charging protocols according to claim 1, characterized in that: DAC1 is connected to the main DSP controller, and is used to receive the third digital signal of the main DSP controller, output the third analog signal after digital-to-analog conversion, and control the D+ signal end of the fast-charging power supply under test; DAC2 is connected to the main DSP controller, and is used to receive the fourth digital signal of the main DSP controller, output the fourth analog signal after digital-to-analog conversion, and control the D- signal end of the fast-charging power supply under test; the main DSP controller completes the adjustment of the D+ signal end and D- signal end of the fast-charging power supply under test by controlling DAC1 and DAC2, thereby realizing the analysis and control of QC2.0 and QC3.0 fast charging protocols.

7. A fast charging protocol control device compatible with multiple fast charging protocols according to claim 6, characterized in that: In the control mode of QC2.0 or QC3.0 fast charging protocol, the electronic load obtains the fast charging protocol matched by the fast charging power supply under test, that is, QC2.0 or QC3.0, and according to the set output voltage and maximum output current of the power supply under test, the output voltage combination of D+ and D- signals is obtained by looking up the table according to the protocol content, and the main DSP controller is notified through the CAN bus. The main DSP controller controls the voltage of the D+ signal end at the corresponding value obtained by looking up the table through DAC1, and the main DSP controller controls the voltage of the D- signal end at the corresponding value obtained by looking up the table through DAC2, thereby allowing the fast charging power supply under test to output the set voltage and maximum current, completing the fast charging protocol control of QC2.0 or QC3.

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8. The fast charging protocol control device compatible with multiple fast charging protocols according to claim 1, characterized in that: One end of the Timer is connected to the main DSP controller, and the other end is connected to the D-signal end of the fast-charging power supply under test. Under the control mode of AFC, FCP, and SCP fast-charging protocols, the electronic load obtains and controls the fast-charging protocol matched by the fast-charging power supply under test, namely AFC, FCP or SCP, and according to the set output voltage and maximum output current of the power supply under test, the command word obtained by looking up the table according to the protocol content is encoded by the main DSP controller through the control of the Timer to control the D-signal end of the fast-charging power supply under test to receive the preset pulse.

9. The fast charging protocol control device compatible with multiple fast charging protocols according to claim 1, characterized in that: The UART is connected to the main DSP controller, the D+ signal end of the fast-charging power supply under test, and the D- signal end of the fast-charging power supply under test. The main DSP controller completes serial communication with the fast-charging power supply under test through the UART, and completes the parsing and control of the UFCS fast-charging protocol. In the UFCS fast-charging protocol control mode, the main DSP controller enables the UART and communicates with the fast-charging power supply under test through the serial port. The electronic load obtains and controls the UFCS fast-charging protocol matched by the fast-charging power supply under test, and transmits the voltage and maximum output current required by the power supply under test to the main DSP controller through the CAN bus. The main DSP controller transmits them to the fast-charging power supply under test through the UART, and the fast-charging power supply under test adjusts its output voltage and maximum output current according to the protocol.

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