Data output method of distributed control system and related device

Abstract

The invention discloses a data output method of a distributed control system and a related device, and relates to the field of industrial control, and the method comprises the steps: setting data areas with different output periods in a shared memory, configuring different spin locks for the different data areas, processing obtained target output data by a first core, and outputting the target output data to a second core; and obtaining the spin lock of the target output data area in the shared memory. And writing the target output data into a target output data area, and releasing the spin lock. And an output data notification is sent to the second core, and the second core responds to the notification to obtain the spin lock of the target output data area, reads the data in the target output data area and sends the data to the corresponding IO module through the CAN bus controller. Therefore, according to the scheme, the output data of different periods in the shared memory are protected through different spin locks, the waiting time for obtaining the spin locks is avoided, and the real-time performance of data output is improved. Meanwhile, the utilization rate of SoC resources is improved.

Description

Technical Field

[0001] The present application relates to the field of industrial control technology, and in particular to a data output method and related devices for a distributed control system. Background Art

[0002] The controller of a distributed control system (DCS) is usually composed of a system on chip (SoC). For example, a controller includes a single-core SoC and a dual-core SoC. Data exchange between different SoCs is achieved through shared memory. In order to prevent simultaneous read and write operations on the shared memory, a single spin lock is used to protect the entire data area.

[0003] However, this design has obvious disadvantages: software arbitration has low efficiency in processing data. When data outputs of different cycles exist simultaneously in the controller, there will be many invalid waiting for arbitration, that is, waiting for the party currently reading data to release the spin lock, resulting in waste of SoC resources and loss of output data. Summary of the invention

[0004] In view of the above problems, the present application provides a data output method and related device of a distributed control system to achieve the purpose of... The specific scheme is as follows:

[0005] In a first aspect, the present application provides a data output method of a distributed control system, which is applied to a controller of a distributed control system, wherein the controller includes a system-level chip, the system-level chip includes a first core and a second core, and a shared memory of the first core and the second core includes a first output data area and a second output data area, the first output data area is used to store first output data and is configured with a first spin lock, and the second output data area is used to store second output data and is configured with a second spin lock; the method includes:

[0006] The first core obtains target output data, the target output data is first output data or second output data, the output cycle of the first output data is a first cycle, the output cycle of the second output data is a second cycle, and the first cycle is different from the second cycle;

[0007] The first core acquires a spin lock corresponding to a target output data area in the shared memory area, where the target output data area is used to store the target output data;

[0008] The first core writes the target output data into the target output data area, releases the spin lock of the target output data area, and sends a notification to the second core that the output data is written into the target output data area of ​​the shared memory area;

[0009] The second core responds to the notification, obtains the spin lock of the target output data area, reads the target output data of the target output data area and writes it into the target message buffer of the CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer to the target IO module.

[0010] In a possible implementation, the CAN bus controller sends the target output data in the target message buffer to the target IO module, including:

[0011] After the CAN bus controller determines that multiple IO modules share one target message buffer and the output data of the target IO module is greater than the storage data volume of the target message buffer, the output data in the target message buffer is sent to the target IO module until all the output data of the target IO module is sent.

[0012] In a possible implementation, the CAN bus controller includes a plurality of message buffers, and a corresponding priority is configured for each message buffer;

[0013] The CAN bus controller sends the output data in the message buffer to be sent, including:

[0014] The CAN bus controller determines the message buffer to be sent this time according to the order of priority of the message buffer to be sent from high to low, and sends the output data in the message buffer to be sent this time to the corresponding IO module.

[0015] In a possible implementation, the method further includes:

[0016] After the second core detects that the MB to be sent has timed out and the priority of the MB to be sent has timed out, and that the priority of the MB to be sent has timed out is lower than the preset priority, the second core increases the priority of the MB to be sent with timed out to the preset priority.

[0017] In a possible implementation, the reading the target output data in the target output data area and writing the target message buffer of the CAN bus controller includes:

[0018] After the second core determines that the valid flag of the target data area is set, the target output data in the target data area is read and written into a second output buffer corresponding to the second core;

[0019] The second core reads output data corresponding to the target IO module from the second output buffer, and writes the output data into a target message buffer corresponding to the target IO module.

[0020] In a possible implementation, the second core reads output data corresponding to the target IO module from the second output buffer and writes the output data into a target message buffer corresponding to the target IO module, including:

[0021] The second core traverses the IO modules in ascending order of the serial numbers of the IO modules;

[0022] After the output flag of the currently traversed IO module is set and the remaining data length corresponding to the currently traversed IO module is non-zero, determining the target message buffer corresponding to the currently traversed IO module;

[0023] After determining that there is no data in the target message buffer, the target output data in the first output buffer corresponding to the currently traversed IO module is written into the target message buffer, and the target message buffer is activated as a message buffer to be sent, so that the CAN bus controller sends the output data in the message buffer to be sent.

[0024] In a possible implementation manner, the first core acquires a spin lock corresponding to a target output data area in the shared memory area, including:

[0025] After the first core determines that the output cycle of the target output data is the first cycle, acquiring the spin lock corresponding to the first output data area;

[0026] After determining that the output cycle of the target output data is the second cycle, the first core acquires the spin lock corresponding to the second output data area.

[0027] A second aspect of the present application provides a data output device of a distributed control system, which is applied to a controller of a distributed control system, wherein the controller includes a system-level chip, the system-level chip includes a first core and a second core, the shared memory of the first core and the second core includes a first output data area and a second output data area, the first output data area is used to store first output data and is configured with a first spin lock, and the second output data area is used to store second output data and is configured with a second spin lock; the device includes:

[0028] an output data acquisition module, configured to enable the first core to obtain target output data, wherein the target output data is the first output data or the second output data, the output cycle of the first output data is the first cycle, the output cycle of the second output data is the second cycle, and the first cycle is different from the second cycle;

[0029] A first spin lock acquisition module, used to enable the first core to acquire a spin lock corresponding to a target output data area in the shared memory area, where the target output data area is used to store the target output data;

[0030] A first data writing module, configured to enable the first core to write the target output data into the target output data area and release the spin lock of the target output data area;

[0031] a notification sending module, configured to enable the first core to send a notification to the second core that output data is written into a target output data area of ​​the shared memory area;

[0032] A data output module is used for the second core to respond to the notification, obtain the spin lock of the target output data area, read the target output data of the target output data area and write it into the target message buffer of the CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer to the target IO module.

[0033] A third aspect of the present application provides a controller of a distributed control system, characterized in that it includes at least one processor and a memory connected to the processor, wherein:

[0034] The memory is used to store computer programs;

[0035] The processor is used to execute the computer program so that the controller can implement the data output method of the distributed control system as described in any one of the first aspects.

[0036] The fourth aspect of the present application provides a computer storage medium, characterized in that the storage medium carries one or more computer programs, and when the one or more computer programs are executed by an electronic device, the electronic device can implement the data output method of the distributed control system as described in any one of the first aspects.

[0037] The data output method of the distributed control system provided in this embodiment can realize data interaction through shared memory for different cores in the same SoC in the controller. Data areas of different output cycles are set in the shared memory, and different spin locks are configured for different data areas, for example, a first spin lock is configured for the output data area of ​​the first cycle, and a second spin lock is configured for the output data area of ​​the second cycle. After the first core processes the target output data obtained, the spin lock of the output data area for storing the target output data in the shared memory is obtained. The target output data is written into the target output data area, and the spin lock is released. Then, an output data notification is sent to the second core, and the second core responds to the notification to obtain the spin lock of the target output data area, reads the data in the target output data area and writes it into the MB of the CAN bus controller, and the CAN bus controller sends the data in the MB to the corresponding IO module. It can be seen that when the scheme is applied to the data output of different cycles in the controller at the same time, the output data of different cycles in the shared memory can be protected by different spin locks respectively, avoiding the waiting time for obtaining the spin lock and improving the real-time performance of the data output. At the same time, the utilization rate of SoC resources is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0039] Figure 1 is a schematic diagram of a distributed control system provided by the present application;

[0040] Figure 2 It is a schematic diagram of a controller in a distributed control system provided by the present application;

[0041] Figure 3 is a schematic diagram of another controller in a distributed control system provided by the present application;

[0042] Figure 4 It is a flow chart of a data output method of a distributed control system provided by the present application;

[0043] Figure 5 is a flow chart of another data output method of a distributed control system provided by the present application;

[0044] Figure 6 It is a structural schematic diagram of a distributed control system data output device provided in this application. DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0046] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0047] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0048] First, some terms in the embodiments of the present application are explained to facilitate understanding by those skilled in the art.

[0049] Spin lock: It is a non-blocking lock. It is implemented by using a busy-wait method to achieve synchronization in a multi-threaded environment. That is, the thread will not be suspended when requesting the lock, but will repeatedly check whether the lock is available in a loop. When a thread acquires the lock, other threads will continue to try to acquire the lock until the thread that acquires the lock actively releases the lock. Only then can other threads continue to execute.

[0050] Controller Area Network (CAN) bus controller: is a digital circuit or microprocessor specially designed to implement the CAN bus communication protocol. It is responsible for converting the data sent by the CPU (or microprocessor) into a format that complies with the CAN bus standard and sending it out through the CAN bus. At the same time, it can also receive data from the CAN bus, convert it into a format that the CPU can recognize, and pass it to the CPU for processing. In short, the CAN bus controller is a bridge connecting the CPU and the CAN bus, realizing the data exchange between the CPU and the CAN bus.

[0051] like Figure 1As shown, a distributed control system provided by the present application may include a host computer, a control station and input / output devices, wherein the input / output devices may include controlled devices and acquisition devices, such as various switching devices (such as output valves) and acquisition devices (such as instruments, sensors, etc.).

[0052] like Figure 1 As shown, the number of host computers, control stations and input / output devices in a distributed control system is usually n, where n is an integer greater than 1.

[0053] The control station usually includes a controller and an IO module, and the controller can be connected to the host computer through a redundant process control network. The controller can include multiple system-level chips (System on Chip, SoC), where multiple can be two or more. This example takes the controller as an example including two SoCs, SoC1 and SoC2. Each SoC can be a single-core or multi-core chip, and the multi-core can be two or more cores, which is not limited in this application.

[0054] The controller can receive program instructions or data sent by the host computer. For example, the host computer can send hardware configuration information and program instructions to the controller.

[0055] The controller configures the corresponding hardware according to the hardware configuration information, such as configuring the scheduling cycle of the IO module. In addition, the controller performs corresponding operations and processing on the received data (such as data collected by the acquisition device received by the IO module) by running the program instructions issued by the host computer to obtain corresponding output data, which can be called IO module output data, and the output data can be control instructions or data. The controller can send data to the corresponding IO module via the CAN bus. Furthermore, after receiving the output data, the IO module sends it to the input / output device connected to the IO module.

[0056] For example, when the controller detects that one of the switch devices is in the on state, it controls the other switch device to be turned off. Specifically, when the controller receives a sampling value of ON from an input channel of a certain IO module, it outputs an OFF control instruction to an output channel of another IO module.

[0057] The data output method of the distributed control system provided in the present application is a process in which the controller executes the user program and outputs the corresponding output data. Figure 2 The figure shows a schematic diagram of the internal structure of a controller in a distributed control system provided by the present application.

[0058] This application takes a dual-core SoC as an example to illustrate that data interaction is achieved between different cores through shared memory, for example, Figure 2In the embodiment, the SoC in the controller may include Core0 and Core1, wherein Core0 is responsible for data calculation and processing, and Core1 is responsible for interacting with the IO module and recording basic events. Core0 and Core1 interact with data through shared memory, and Core0 and Core1 can communicate through inter-core interrupts.

[0059] The host computer can configure the first cycle IO module, the second cycle IO module and the program instructions in the hardware configuration.

[0060] The first-cycle IO module is an IO module with a first cycle, such as 5ms, 10ms or 20ms. The second-cycle IO module is an IO module with a second cycle, such as 100ms, 200ms or 500ms. For example, a control station includes 64 IO modules, of which IO modules 1-16 use the first cycle (such as 20ms) for output, and the remaining IO modules 17-64 use the second cycle (such as 100ms) for output.

[0061] The shared memory is a memory area in the SoC that can be read and written by both Core 0 and Core 1. In this embodiment, the shared memory may include a spin lock data area, a first output data area, a second output data area, and a diagnostic information data area.

[0062] The spin lock data area is used to store the basic data structure of the spin lock, such as n spin locks, and the size of the data area can be n×the length of the basic data structure of the spin lock.

[0063] The first output data area is used to store data output by the IO module using the first cycle.

[0064] The second output data area is used to store data output by the IO module using the second cycle.

[0065] The diagnostic information data area is used to store the status information of Core0 and Core1, and may also include the scheduling plan of the IO module.

[0066] Core0 in the controller can download hardware configuration data and program instructions from the host computer, configure the hardware accordingly according to the hardware configuration data, and run the program instructions to perform corresponding operations and processing on the data.

[0067] Core1 can read and write the IO module through the CAN bus controller. The CAN bus controller can be regarded as a peripheral of Core1. Exemplarily, the CAN bus controller can adopt a FlexCan controller, which includes multiple message buffers (MB). Core1 can write the data to be output into the MB of the FlexCan controller, and the FlexCan controller sends the data in the MB to the corresponding IO module through the CAN bus.

[0068] See also Figure 3 , shows a schematic diagram of the structure of another controller of a distributed control system provided by the present application, in Figure 2 The controller shown further includes a first output buffer and a second output buffer, wherein the first output buffer is the output buffer of Core0, that is, only Core0 can read and write the buffer, and the second output buffer is the output buffer of Core1, that is, only Core1 can read and write the buffer.

[0069] The main thread of Core0 will write the output data into the first output buffer after obtaining it, and the buffer read and write thread is responsible for reading the output data from the first output buffer and writing it into the first output data area of ​​the shared memory. That is, the processing, calculation process and writing sharing process can be run simultaneously using different threads.

[0070] The main thread of Core1 reads the output data from the first output data area of ​​the shared memory and writes it into the second output buffer, and the buffer read and write thread of Core1 is responsible for reading the output data from the second output buffer and writing it into the corresponding MB. That is, the process of reading data from the shared memory and reading data from the second output buffer can be executed simultaneously by different threads.

[0071] The following will be combined Figure 2 This section describes the processing of Core0 and Core1 before outputting real-time data to the IO module:

[0072] After Core0 downloads the hardware configuration data from the host computer, before running the new configuration for the first time, it first polls to obtain the spin lock of the original IO output data area, and detects that the status of the IO output data area is invalid, indicating that Core1 has taken the output data in the data area. After that, Core0 reallocates the data area protected by the spin lock, where the first data area in the shared memory is used to store the output data of IO modules 1-16, and Core0 allocates the first spin lock protection to the first data area. The second data area in the shared memory is used to store the output data of IO modules 17-64, and Core0 allocates the second spin lock protection to the second data area.

[0073] In some embodiments, the spin lock data structure may include an 8-byte array and two 2-byte cycle times. Each bit of the 8-byte array represents the output cycle of an IO module. For example, a bit position of 1 indicates that the corresponding IO module adopts the first cycle scheduling, and a bit position of 0 indicates that the corresponding IO module adopts the second cycle scheduling. The spin locks allocated by one of the two 2-byte data areas and the second data area are stored in the spin lock data area of ​​the shared memory.

[0074] In addition, the spin lock data area can also store spin locks of other data areas in the shared memory, which will not be described in detail in this application.

[0075] After Core0 updates the spin locks of the first and second data areas, it sends an interrupt notification to Core1 through an inter-core interrupt to notify that the content of Core1's diagnostic information data area has been updated. The updated content of the diagnostic information data area may include the IO module scheduling cycle configuration information, that is, the scheduling cycle of each IO module, and Core0 reallocates the spin locks for the first data area and the second data area.

[0076] After receiving the interrupt, Core1 updates the spin lock protection data area scheme. The first spin lock protects the first data area, and the second spin lock protects the second data. At the same time, the MB allocation scheme of the output data is updated, that is, MB is reallocated to each IO module according to the cycle configuration of the IO module, and the execution result is returned to Core0 as a reply. The execution result shows that Core1 has correctly received the IO module scheduling cycle configuration information issued by Core0, and has re-established the MB allocation table corresponding to the IO module.

[0077] After Core0 confirms the reply command from Core1, it starts to schedule program instructions, such as performing corresponding operations and processing on the received data to obtain the output data of the IO module. According to the cycle of the obtained output data, the output data is written into the corresponding output data area in the shared memory. For example, if the cycle of the output data obtained this time is the first cycle, the output data is written into the first data area of ​​the shared memory, and Core1 is notified to read the data. Core1 reads the output data from the first data area and writes it into the MB corresponding to the IO module of the output data, and waits for the FlexCan controller to send the data in the MB to the corresponding IO module.

[0078] In some embodiments, the process of Core1 reallocating MB of the FlexCan controller to the IO module is as follows:

[0079] The FlexCan controller can be regarded as a peripheral of Core1. The FlexCan controller includes multiple MBs, such as 64. The FlexCan controller can configure each MB to send or receive. For example, 32 MBs can be configured to send and receive, such as MB1-32 for sending MBs and MB33-64 for receiving MBs. Among them, MB1-3 are used to send broadcast frames, management message frames, and synchronization frames in CAN data, respectively, and MB4-32 is used to send output data frames.

[0080] Generally, the number of available sending MBs may be less than the actual sending demand, and the sending MBs may be allocated according to the ratio of the IO modules of the first cycle to the IO modules of the second cycle.

[0081] For example, the number of MBs to be sent allocated to the IO module in the first cycle is P f as follows:

[0082]

[0083] The number of transmit MBs P allocated to the IO module for the second cycle n as follows:

[0084]

[0085] Where m represents the number of IO modules in the first cycle, n represents the number of IO modules in the second cycle, and T fast represents the scheduling period of the first cycle, T normal represents the scheduling period of the second cycle, S MB Indicates the number of transmit MBs that can be allocated.

[0086] If P calculated according to the above formula f , P n If the number is not an integer, it is rounded down. And, an MB sequence number table corresponding to the IO module is established, that is, an array whose dimension is consistent with the number of IO modules, and each element represents the MB sequence number corresponding to an IO module. For example, IO modules 17-20 share MB4, and the values ​​corresponding to the 17th to 20th elements in the array are all 4.

[0087] The following will be combined Figure 4 and Figure 5 The present invention introduces the data output method flow of the distributed control system provided by the present application.

[0088] See also Figure 4 , shows a flow chart of a data output method of a distributed control system of the present application, which can be applied to a controller in a distributed control system. In this embodiment, the first core and the second core are different cores in the same SoC. Figure 4As shown, the method may include the following steps:

[0089] S101: The first core runs a first program to obtain target output data.

[0090] The target output data may be data obtained by the first core through operation and processing of the received IO module input data, and these data may be sent to a corresponding controlled device, such as a switch device, through the IO module.

[0091] In the present application, the output data may include output data of the first cycle or output data of the second cycle.

[0092] S102: The first core obtains a target spin lock corresponding to target output data.

[0093] The first core sets different spin locks for the data areas in the shared memory used to store different output cycles. For example, Figure 2 In the example shown, a first spin lock is set for a first output data area in the shared memory, and a second spin lock is set for a second output data area.

[0094] After the first core determines the output cycle of the output data this time, it obtains the spin lock corresponding to the corresponding output data area in the shared memory. For example, when outputting the data of the first cycle this time, the first spin lock is obtained, and when outputting the data of the second cycle this time, the second spin lock is obtained.

[0095] S103, the first core writes the target output data into the target output data area of ​​the shared memory and releases the target spin lock.

[0096] When the target output data is data of the first cycle, the data is written into the first output data area. When the target output data is data of the second cycle, the data is written into the second output data area.

[0097] S104: The first core sends a data output notification to the second core.

[0098] After the first core writes the output data of this time into the shared memory, an inter-core interrupt is initiated, and the interrupt is used to notify the second core that the content of the output data area of ​​the shared memory has been updated.

[0099] S105, the second core responds to the data output notification and acquires the target spin lock.

[0100] After receiving the data output interrupt event initiated by the first core, the second core can parse the interrupt event to obtain the area with updated data content, such as the first output data area or the second output data area in the shared memory, and further try to obtain the spin lock of the data area until the spin lock is obtained.

[0101] S106, the second core reads the target output data in the target output data area in the shared memory, and writes the target output data into the target sending MB of the CAN bus controller.

[0102] After the second core obtains the spin lock of the target output data area, it reads the output data of the target output data area and writes the output data into the sending MB of the IO module corresponding to the target output data.

[0103] In some embodiments, after reading the target output data, the second core determines the IO module number corresponding to the target output data, further determines the MB number corresponding to the IO module number according to the MB allocation table corresponding to the IO module, and finally writes the target output data into the determined sending MB.

[0104] S107, the second core determines the priority of the target sending MB according to the period of the target data, and activates the target sending MB to be sent.

[0105] After the second core writes the target output data into the corresponding sending MB, the priority of the sending MB is further configured according to the period of the target output data. For example, the priority of the sending MB can be configured according to the pre-configured priority configuration information of each type of data transmission. For example, if the output period of the target output data is the first period, the priority of the target sending MB is set to level 4. For another example, if the output period of the target output data is the second period, the priority of the target sending MB is set to level 5.

[0106] S108, the CAN bus controller reads the data in the MB to be sent in descending order of priority of the MB to be sent.

[0107] In some embodiments, the CAN bus controller (such as the FlexCan controller) supports configuring different priorities for MBs. Core1 can write different types of frames into MBs of different priorities. In this embodiment, data frames with different output cycles can be written into different MBs. The FlexCan controller can arbitrate the MBs to be sent this time according to the priority of each MB.

[0108] Exemplarily, the priority of the MB can be indicated by 3 bits, and the 3 bits correspond to a maximum of 8 priorities, such as priority 0-7. Among them, the priority allocation of the MB corresponding to the broadcast frame, management message frame, and synchronization frame is configured as priority 0-2. The broadcast frame is used for communication diagnosis and detection between the controller and the IO module on the bus. The controller sends a data packet every 25ms, so the broadcast frame has the highest priority, which is priority 0. The MB corresponding to the IO module of the first cycle can be configured as priority 4, and the MB corresponding to the IO module of the second cycle can be configured as priority 5.

[0109] When there may be multiple MBs waiting to be sent in the CAN bus controller, they are sent in descending order of priority. For example, if there are data frames with priority 4 and 5, the data frames with priority 4 are sent first, and the data frames with priority 5 are sent only after all the data frames with priority 4 are sent.

[0110] S109, the CAN bus controller sends the read data in the MB to be sent to the corresponding IO module through the CAN bus.

[0111] The CAN bus controller converts the data format of the output data read from the MB to be sent into a format that complies with the CAN bus standard and sends it to the CAN bus, and finally transmits it to the IO module corresponding to the output data.

[0112] The data output method of the distributed control system provided in this embodiment can realize data interaction through shared memory for different cores in the same SoC in the controller. Data areas of different output cycles are set in the shared memory, and different spin locks are configured for different data areas, for example, a first spin lock is configured for the output data area of ​​the first cycle, and a second spin lock is configured for the output data area of ​​the second cycle. After the first core processes the target output data obtained, the spin lock of the output data area for storing the target output data in the shared memory is obtained. The target output data is written into the target output data area, and the spin lock is released. Then, an output data notification is sent to the second core, and the second core responds to the notification to obtain the spin lock of the target output data area, reads the data in the target output data area and writes it into the MB of the CAN bus controller, and the CAN bus controller sends the data in the MB to the corresponding IO module. It can be seen that when the scheme is applied to the data output of different cycles in the controller at the same time, the output data of different cycles in the shared memory can be protected by different spin locks respectively, avoiding the waiting time for obtaining the spin lock and improving the real-time performance of the data output. At the same time, the utilization rate of SoC resources is improved.

[0113] See also Figure 5 , shows a flow chart of another data output method of a distributed control system provided by an embodiment of the present application, the method is applied to Figure 3 In the distributed control system shown in Figure 5 As shown, the method may include the following steps:

[0114] S201, the first core runs a program to obtain target output data.

[0115] S202: The first core writes target output data into a first output buffer corresponding to the first core.

[0116] In some embodiments, in order to improve data output efficiency, a corresponding output buffer, namely, a first output buffer, is allocated to the first core, that is, the buffer only supports the first core to perform read and write operations. In this way, the main thread of the first core can write the output data obtained by the operation processing into the first output buffer, and then the write data thread reads the output data from the first output buffer and writes it to the target output data area of ​​the shared memory. The main thread and the write data thread can run in parallel, thereby improving data output efficiency.

[0117] S203, the first core obtains a target spin lock corresponding to a data area for target output data in the shared memory.

[0118] S204, the first core determines whether there is data in the target output data area in the shared memory; if yes, execute S204 after a delay of a preset time (such as 1ms); if not, execute S205.

[0119] The first core obtains the spin lock of the target output data area in the shared memory, and determines whether the valid flag bit of the target output data area is invalid. If invalid, it indicates that there is no data in the target output data area. If it is set, it indicates that there is data in the target output data area to be read by the second core.

[0120] S205, the first core writes the target output data into the target output data area of ​​the shared memory, releases the target spin lock, and sets the valid flag bit of the target output data area.

[0121] If the first core determines that there is no data in the target output data area in the shared memory that has not been read by the second core, the target output data can be written into the target output data area and the valid flag of the target output data area is set to indicate that there is data to be read in the target output data area.

[0122] S206: The first core sends a data output notification to the second core.

[0123] S207, the second core responds to the data output notification and acquires the target spin lock.

[0124] S208, the second core determines whether there is data in the target output data area of ​​the shared memory; if yes, execute S209; if not, return to execute S208 after delaying for a preset time.

[0125] After the second core obtains the spin lock of the target output data area in the shared memory, it first determines whether the valid flag bit of the target output data area is invalid (such as 0). If it is invalid, it indicates that there is no data in the target output data area. If the valid flag bit is set (such as 1), it indicates that there is data in the target output data area.

[0126] S209, the second core reads the data in the target output data area in the shared memory, writes the data into the output buffer corresponding to the second core (ie, the second output buffer), and sets the output flag of the corresponding IO module.

[0127] In some embodiments, in order to improve data output efficiency, a corresponding output buffer, namely, a second output buffer, is allocated to the second core, that is, the buffer only supports the second core to perform read and write operations. In this way, the main thread of the second core reads the target output data from the target output data area and writes it into the second output buffer, and then another thread reads the output data from the second output buffer and writes it into the corresponding MB. The main thread and the other thread can run in parallel, thereby improving data output efficiency.

[0128] S210, the second core traverses the IO modules to determine a target IO module whose output flag is set and whose corresponding output buffer has remaining data.

[0129] After the second core writes the data read from the shared memory into the second output buffer, it traverses the IO modules in ascending order according to the serial numbers, and determines that the IO module whose output flag is set (such as 1) and the remaining data length in the output buffer corresponding to the serial number is non-zero is the target IO module.

[0130] The output flag of the IO module is set to indicate that the IO module has data to output, and the remaining data corresponding to the IO module in the second output buffer is non-zero, indicating that the IO module has data to be sent. In other words, this step is to search for IO modules that have data to output in ascending order of the IO module numbers.

[0131] S211, the second core obtains the target sending MB corresponding to the target IO module.

[0132] The second core may search the sequence number of the sending MB corresponding to the sequence number of the target IO module according to the MB allocation table, and determine it as the target sending MB.

[0133] S212, the second core determines whether the target sending MB is idle; if yes, executes S213, if not, delays for a preset time and then returns to execute S212.

[0134] After the second core determines the sending MB corresponding to the target IO module, it first determines whether there is no data in the sending MB. If there is no data, it indicates that the sending MB is in an idle state.

[0135] S213, the second core determines the sending MB priority according to the cycle of the output data, writes the output data corresponding to the target IO module in the second output buffer into the target sending MB, and activates the target sending MB to be sent.

[0136] For example, the output data of the first cycle corresponds to priority 4, and the output data of the second cycle corresponds to priority 5.

[0137] After the output data is written to the target MB, the target sending MB is activated to be in a waiting-to-send state, that is, there is data in the sending MB waiting to be sent by the CAN bus control.

[0138] S214, the CAN bus controller reads the data in the MB to be sent in descending order of priority of the MB to be sent.

[0139] S215, the CAN bus controller sends the read data in the MB to be sent to the target IO module through the CAN bus.

[0140] S216, when there are multiple IO modules sharing one sending MB, and the output data of the IO modules is greater than the storage data volume of one sending MB, the second core continuously reads the output data of the target IO module from the second output buffer until all the data of the target IO module is written into the MB.

[0141] In order to ensure that the output data frames of the same IO module are continuously sent, when the second core writes the output data in the second output buffer into the sending MB, if it detects that the output data volume of a certain IO module is greater than the data volume of one MB, the output data of the IO module will be written into the same MB multiple times until all the data of the IO module is written into the MB, and then the data of the next IO module is read. In this way, the data frames of the same IO module can be continuously sent, and the real-time performance of the IO module output can be improved.

[0142] S217, the second core traverses the MBs to be sent to determine that there are MBs to be sent whose sending has timed out, and raises the priority of the MBs to be sent whose sending has timed out to the reserved priority.

[0143] S218, the CAN bus controller resends the MB to be sent according to the updated priority.

[0144] The CAN bus controller sends the MBs to be sent in order of priority from high to low. When the MBs to be sent with high priority are densely packed, the MBs to be sent with low priority may not be sent and cause a sending timeout. In this scenario, a reserved priority can be set. When a MB to be sent with a sending timeout is detected, the priority of the MB to be sent can be adjusted to the reserved priority. The data in the MB to be sent will be sent according to the reallocated priority when it is sent next time. By dynamically adjusting the priority of the MB to be sent with a sending timeout, the waiting time for retransmission of data transmission failure can be shortened, and the data output efficiency can be improved.

[0145] For example, the reserved priority is level 3, and Core1 can traverse all MBs to be sent at regular intervals. When there is an MB with a sending timeout, the priority of the MB to be sent is increased to level 3, and the MB to be sent is sent according to the reconfigured priority at the next sending.

[0146] The data output method of the distributed control system provided in this embodiment protects the output data of different cycles in the shared memory through different spin locks, avoids the waiting time for acquiring the spin lock, and improves the real-time performance of the data output. At the same time, the utilization rate of the SoC resources is improved. Moreover, when it is detected that the output data volume of a certain IO module is greater than the data volume of one MB, the output data of the IO module is written into the same MB in multiple times until all the data of the IO module is written into the MB, and then the data of the next IO module is read. In this way, the data frames of the same IO module can be continuously sent, and the real-time performance of the IO module output can be improved.

[0147] Furthermore, after detecting that a low-priority MB to be sent has timed out, the priority of the MB to be sent that has timed out is dynamically adjusted to shorten the waiting time for retransmission of data transmission failure and improve data output efficiency.

[0148] See also Figure 6 , shows a schematic diagram of the structure of a data output device of a distributed control system provided by an embodiment of the present application, the device is applied to a controller of a distributed control system, the controller includes a system-level chip, the system-level chip includes a first core and a second core, the shared memory of the first core and the second core includes a first output data area and a second output data area, the first output data area is used to store the first output data and is configured with a first spin lock, the second output data area is used to store the second output data and is configured with a second spin lock. Figure 6 As shown, the device comprises:

[0149] The output data acquisition module 101 is used to enable the first core to obtain target output data, where the target output data is the first output data or the second output data, the output cycle of the first output data is the first cycle, the output cycle of the second output data is the second cycle, and the first cycle is different from the second cycle.

[0150] The first spin lock acquisition module 102 is used to enable the first core to acquire a spin lock corresponding to a target output data area in the shared memory area, where the target output data area is used to store target output data.

[0151] In a possible implementation, the first spin lock acquisition module is specifically used for:

[0152] After the first core determines that the output cycle of the target output data is the first cycle, acquiring the spin lock corresponding to the first output data area;

[0153] After determining that the output cycle of the target output data is the second cycle, the first core acquires the spin lock corresponding to the second output data area.

[0154] The first data writing module 103 is used to enable the first core to write the target output data into the target output data area and release the spin lock of the target output data area.

[0155] The notification sending module 104 is used to enable the first core to send a notification to the second core that output data is written into the target output data area of ​​the shared memory area.

[0156] The data output module 105 is used for the second core response notification, obtains the spin lock of the target output data area, reads the target output data in the target output data area and writes it into the target message buffer of the CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer to the target IO module.

[0157] In a possible implementation, the data output module is used to enable the CAN bus controller to send the target output data in the target message buffer to the target IO module, including:

[0158] After the CAN bus controller determines that multiple IO modules share one target message buffer and the output data of the target IO module is greater than the storage data volume of the target message buffer, the output data in the target message buffer is sent to the target IO module until all the output data of the target IO module is sent.

[0159] In a possible implementation, the CAN bus controller includes a plurality of message buffers, and a corresponding priority is configured for each message buffer; and the data output module is used to enable the CAN bus controller to send output data in the to-be-sent message buffer, specifically to:

[0160] The CAN bus controller determines the message buffer to be sent this time according to the order of priority of the message buffer to be sent from high to low, and sends the output data in the message buffer to be sent this time to the corresponding IO module.

[0161] In a possible implementation, the data output module is further used to: upon detecting that the MB to be sent has timed out and whose priority is lower than a preset priority, increase the priority of the MB to be sent with timed out to the preset priority.

[0162] In a possible implementation, the data output module is specifically used to:

[0163] After determining that the valid flag of the target data area is set, reading the target output data in the target data area and writing the target output data into a second output buffer corresponding to the second core;

[0164] The output data corresponding to the target IO module is read from the second output buffer, and written into a target message buffer corresponding to the target IO module.

[0165] In a possible implementation, when the data output module is used to read the output data corresponding to the target IO module from the second output buffer and write the output data into the target message buffer corresponding to the target IO module, it is specifically used to:

[0166] Traverse the IO modules in ascending order of their serial numbers;

[0167] After the output flag of the currently traversed IO module is set and the remaining data length corresponding to the currently traversed IO module is non-zero, determining the target message buffer corresponding to the currently traversed IO module;

[0168] After determining that there is no data in the target message buffer, the target output data in the first output buffer corresponding to the currently traversed IO module is written into the target message buffer, and the target message buffer is activated as a message buffer to be sent, so that the CAN bus controller sends the output data in the message buffer to be sent.

[0169] The data output device of the distributed control system provided in this embodiment is applied to the controller when data output of different cycles exists at the same time. Different spin locks can be used to protect the output data of different cycles in the shared memory, thereby avoiding the waiting time for acquiring the spin lock and improving the real-time performance of the data output. At the same time, the utilization rate of SoC resources is improved.

[0170] An embodiment of the present application also provides a computer program product including computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements any distributed control system data output method provided in the embodiment of the present application.

[0171] A computer-readable storage medium is also provided in an embodiment of the present application. The storage medium carries one or more computer programs. When one or more computer programs are executed by an electronic device, the electronic device can implement any distributed control system data output method provided in an embodiment of the present application.

[0172] It should also be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiments provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

[0173] Through the description of the above implementation mode, the technicians in the field can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better implementation mode in more cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a ROM, a RAM, a disk or an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a training device, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0174] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0175] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a training device, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, training device, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

Claims

1. A data output method for a distributed control system, characterized in that: A controller applied to a distributed control system, the controller comprising a system-on-chip, the system-on-chip comprising a first core and a second core, the shared memory of the first core and the second core comprising a first output data area and a second output data area, the first output data area being used to store first output data and being configured with a first spin lock, the second output data area being used to store second output data and being configured with a second spin lock; the method comprising: The first core obtains target output data, the target output data is first output data or second output data, the output cycle of the first output data is a first cycle, the output cycle of the second output data is a second cycle, and the first cycle is different from the second cycle; The first core acquires a spin lock corresponding to a target output data area in the shared memory area, where the target output data area is used to store the target output data; The first core writes the target output data into the target output data area, releases the spin lock of the target output data area, and sends a notification to the second core that the output data is written into the target output data area of ​​the shared memory area; The second core responds to the notification, obtains the spin lock of the target output data area, reads the target output data of the target output data area and writes it into the target message buffer of the CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer to the target IO module.

2. The method according to claim 1, characterized in that: The CAN bus controller sends the target output data in the target message buffer to the target IO module, including: After the CAN bus controller determines that multiple IO modules share one target message buffer and the output data of the target IO module is greater than the storage data volume of the target message buffer, the output data in the target message buffer is sent to the target IO module until all the output data of the target IO module is sent.

3. The method according to claim 1, characterized in that The CAN bus controller includes a plurality of message buffers, and a corresponding priority is configured for each message buffer; The CAN bus controller sends the output data in the message buffer to be sent, including: The CAN bus controller determines the message buffer to be sent this time according to the order of priority of the message buffer to be sent from high to low, and sends the output data in the message buffer to be sent this time to the corresponding IO module.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: After the second core detects that the MB to be sent has timed out and the priority of the MB to be sent has timed out, and that the priority of the MB to be sent has timed out is lower than the preset priority, the second core increases the priority of the MB to be sent with timed out to the preset priority.

5. The method according to claim 1, characterized in that The step of reading the target output data in the target output data area and writing the target output data in the target message buffer of the CAN bus controller comprises: After the second core determines that the valid flag of the target data area is set, the target output data in the target data area is read and written into a second output buffer corresponding to the second core; The second core reads output data corresponding to the target IO module from the second output buffer, and writes the output data into a target message buffer corresponding to the target IO module.

6. The method according to claim 5, characterized in that The second core reads output data corresponding to the target IO module from the second output buffer and writes the output data into a target message buffer corresponding to the target IO module, including: The second core traverses the IO modules in ascending order of the serial numbers of the IO modules; After the output flag of the currently traversed IO module is set and the remaining data length corresponding to the currently traversed IO module is non-zero, determining the target message buffer corresponding to the currently traversed IO module; After determining that there is no data in the target message buffer, the target output data in the first output buffer corresponding to the currently traversed IO module is written into the target message buffer, and the target message buffer is activated as a message buffer to be sent, so that the CAN bus controller sends the output data in the message buffer to be sent.

7. The method according to claim 1, characterized in that The first core acquires a spin lock corresponding to a target output data area in the shared memory area, including: After the first core determines that the output cycle of the target output data is the first cycle, acquiring the spin lock corresponding to the first output data area; After determining that the output cycle of the target output data is the second cycle, the first core acquires the spin lock corresponding to the second output data area.

8. A data output device for a distributed control system, characterized in that: A controller applied to a distributed control system, the controller comprising a system-level chip, the system-level chip comprising a first core and a second core, the shared memory of the first core and the second core comprising a first output data area and a second output data area, the first output data area being used to store first output data and being configured with a first spin lock, the second output data area being used to store second output data and being configured with a second spin lock; the device comprising: an output data acquisition module, configured to enable the first core to obtain target output data, wherein the target output data is the first output data or the second output data, the output cycle of the first output data is the first cycle, the output cycle of the second output data is the second cycle, and the first cycle is different from the second cycle; A first spin lock acquisition module, used to enable the first core to acquire a spin lock corresponding to a target output data area in the shared memory area, where the target output data area is used to store the target output data; A first data writing module, configured to enable the first core to write the target output data into the target output data area and release the spin lock of the target output data area; a notification sending module, configured to enable the first core to send a notification to the second core that output data is written into a target output data area of ​​the shared memory area; A data output module is used for the second core to respond to the notification, obtain the spin lock of the target output data area, read the target output data of the target output data area and write it into the target message buffer of the CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer to the target IO module.

9. A controller for a distributed control system, characterized in that: The method comprises at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is used to execute the computer program so that the controller can implement the data output method of the distributed control system according to any one of claims 1 to 7.

10. A computer storage medium, characterized in that: The storage medium carries one or more computer programs, and when the one or more computer programs are executed by an electronic device, the electronic device is enabled to implement the data output method of the distributed control system as described in any one of claims 1 to 7.

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