Data output method of a distributed control system and related device

Abstract

The application discloses a data output method of a distributed control system and related devices, and relates to the field of industrial control, and comprises the following steps: setting data areas with different output periods in shared memory, and configuring different spin locks for different data areas; after obtaining target output data by a first core, acquiring a spin lock of a target output data area in the shared memory; writing the target output data into the target output data area, and releasing the spin lock; sending an output data notification to a second core; in response to the notification, the second core acquires the spin lock of the target output data area, reads data in the target output data area, and sends the data to a corresponding IO module through a CAN bus controller. It can be seen that the scheme protects output data with different periods in the shared memory through different spin locks respectively, avoids waiting time for acquiring the spin lock, improves real-time performance of data output, and improves utilization of SoC resources.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of industrial control, and particularly relates to a data output method of a distributed control system and a related device. BACKGROUND

[0002] A controller of a distributed control system (DCS) is usually composed of a system on chip (SoC), for example, a controller includes a single-core SoC and a dual-core SoC, and data interaction between different SoCs is realized through shared memory. In order to prevent simultaneous read and write operations on the shared memory, a single spin lock is used to protect the entire data area.

[0003] However, this design has obvious disadvantages: the software arbitration processing data efficiency is low, and when there are different periods of data output in the controller at the same time, there are many invalid waiting arbitration cases, that is, waiting for the party currently reading the data to release the spin lock, thereby causing waste of SoC resources and loss of output data. SUMMARY

[0004] In view of the above problems, the present application provides a data output method of a distributed control system and a related device to improve the data output efficiency. The specific scheme is as follows:

[0005] The first aspect of the present application provides a data output method of a distributed control system, applied to a controller of a distributed control system, wherein the controller includes a system on chip, the system on chip includes a first core and a second core, a shared memory of the first core and the second core includes a first output data area and a second output data area, the first output data area is used to store first output data and is configured with a first spin lock, and the second output data area is used to store second output data and is configured with a second spin lock; the method comprises:

[0006] The first core obtains target output data, the target output data is first output data or second output data, the output period of the first output data is a first period, the output period of the second output data is a second period, and the first period and the second period are different;

[0007] The first core acquires a spin lock corresponding to a target output data area in the shared memory area, and the target output data area is used to store the target output data;

[0008] The first core writes the target output data into the target output data area, releases the spin lock of the target output data area, and sends a notification to the second core that the output data is written into the target output data area of the shared memory area;

[0009] The second core acquires the spin lock of the target output data area in response to the notification, reads the target output data in the target output data area, and writes the target output data into the target message buffer of the CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer to the target IO module.

[0010] In a possible implementation, the CAN bus controller sending the target output data in the target message buffer to the target IO module comprises:

[0011] The CAN bus controller determines that a plurality of IO modules share one target message buffer, and when the output data of the target IO module is greater than the storage data amount of the target message buffer, the CAN bus controller sends the output data in the target message buffer to the target IO module until all the output data of the target IO module is sent.

[0012] In a possible implementation, the CAN bus controller comprises a plurality of message buffers, and each message buffer is configured with a corresponding priority.

[0013] The CAN bus controller sending the output data in the to-be-sent message buffer comprises:

[0014] The CAN bus controller determines the to-be-sent message buffer to be sent this time in the order from high to low of the priorities of the to-be-sent message buffers, and sends the output data in the to-be-sent message buffer to be sent this time to the corresponding IO module.

[0015] In a possible implementation, the method further comprises:

[0016] When the second core detects a to-be-sent MB that is sent with a timeout, and the priority of the to-be-sent MB that is sent with a timeout is lower than a preset priority, the second core raises the priority of the to-be-sent MB that is sent with a timeout to the preset priority.

[0017] In a possible implementation, the reading of the target output data in the target output data area and the writing of the target output data into the target message buffer of the CAN bus controller comprises:

[0018] When the second core determines that the valid flag of the target data area is set, the second core reads the target output data in the target data area and writes the target output data into the second output buffer corresponding to the second core.

[0019] The second core reads the output data corresponding to the target IO module from the second output buffer and writes the output data into a target message buffer corresponding to the target IO module.

[0020] In a possible implementation, the second core reads the output data corresponding to the target IO module from the second output buffer and writes the output data into a target message buffer corresponding to the target IO module, including:

[0021] The second core traverses the IO modules in ascending order of the serial numbers of the IO modules.

[0022] After the output flag of the currently traversed IO module is set and the remaining data length corresponding to the currently traversed IO module is nonzero, a target message buffer corresponding to the currently traversed IO module is determined.

[0023] After it is determined that the target message buffer is empty, the target output data corresponding to the currently traversed IO module in the first output buffer is written into the target message buffer, and the target message buffer is activated as a to-be-sent message buffer, so that the CAN bus controller sends the output data in the to-be-sent message buffer.

[0024] In a possible implementation, the first core acquires a spin lock corresponding to a target output data area in the shared memory area, including:

[0025] After the first core determines that the output period of the target output data is the first period, the first core acquires the spin lock corresponding to the first output data area.

[0026] After the first core determines that the output period of the target output data is the second period, the first core acquires the spin lock corresponding to the second output data area.

[0027] The second aspect of the present application provides a data output device of a distributed control system, applied to a controller of the distributed control system, the controller including a system-level chip, the system-level chip including a first core and a second core, and a shared memory of the first core and the second core including a first output data area and a second output data area, the first output data area being configured with a first spin lock and used for storing first output data, and the second output data area being configured with a second spin lock and used for storing second output data; the device including:

[0028] an output data obtaining module, configured to enable the first core to obtain target output data, the target output data being first output data or second output data, an output period of the first output data being a first period, an output period of the second output data being a second period, and the first period being different from the second period;

[0029] a first spin lock obtaining module, configured to enable the first core to obtain a spin lock corresponding to a target output data area in the shared memory area, the target output data area being configured to store the target output data;

[0030] a first data writing module, configured to enable the first core to write the target output data into the target output data area, and release the spin lock of the target output data area;

[0031] a notification sending module, configured to enable the first core to send a notification to the second core that output data is written into the target output data area of the shared memory area;

[0032] a data output module, configured to enable the second core to, in response to the notification, obtain the spin lock of the target output data area, read the target output data of the target output data area, and write the target output data into a target message buffer area of a CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer area to a target IO module.

[0033] The third aspect of the present application provides a controller of a distributed control system, comprising at least one processor and a memory connected to the processor, wherein:

[0034] the memory is configured to store a computer program;

[0035] the processor is configured to execute the computer program, so that the controller can implement the data output method of the distributed control system according to any one of the first aspect.

[0036] The fourth aspect of the present application provides a computer storage medium, wherein the storage medium carries one or more computer programs, and when the one or more computer programs are executed by an electronic device, the electronic device can implement the data output method of the distributed control system according to any one of the first aspect.

[0037] The data output method of the distributed control system provided by the embodiment can realize data interaction between different cores in the same SoC in the controller through shared memory. Data areas with different output periods are set in the shared memory, and different spin locks are configured for different data areas, for example, a first spin lock is configured for the output data area of the first period, and a second spin lock is configured for the output data area of the second period. After the first core processes the target output data obtained, the spin lock of the output data area in the shared memory for storing the target output data is acquired. The target output data is written into the target output data area, and the spin lock is released. Then, the output data notification is sent to the second core, and the second core acquires the spin lock of the target output data area in response to the notification, reads the data in the target output data area and writes the data into the MB of the CAN bus controller, and the CAN bus controller sends the data in the MB to the corresponding IO module. It can be seen that when the scheme is applied to the controller in which data output with different periods exists at the same time, different spin locks can be used to protect the output data with different periods in the shared memory, so that the waiting time for acquiring the spin lock is avoided, and the real-time performance of data output is improved. At the same time, the utilization rate of SoC resources is improved. BRIEF DESCRIPTION OF DRAWINGS

[0038] The above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent by describing in detail the following specific embodiments thereof with reference to the attached drawings. Throughout the drawings, the same or similar reference numerals refer to the same or similar elements. It should be understood that the drawings are schematic, and the original and elements are not necessarily drawn according to the scale.

[0039] Figure 1 is a schematic diagram of a distributed control system provided by the present application;

[0040] Figure 2 is a schematic diagram of a controller in a distributed control system provided by the present application;

[0041] Figure 3 is a schematic diagram of another controller in a distributed control system provided by the present application;

[0042] Figure 4 is a flowchart of a data output method of a distributed control system provided by the present application;

[0043] Figure 5 is a flowchart of another data output method of a distributed control system provided by the present application;

[0044] Figure 6 is a structural schematic diagram of a data output device of a distributed control system provided by the present application. DETAILED DESCRIPTION

[0045] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The terms used in the embodiment part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0046] The embodiments of the present application will be described below in conjunction with the drawings. It is known to those skilled in the art that as technology develops and new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0047] The terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, and this is only a way of distinguishing the objects with the same attributes used in the description of the embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that the processes, methods, systems, products or equipment containing a series of units do not have to be limited to those units, but can include other units not clearly listed or inherent to these processes, methods, products or equipment.

[0048] First, some of the terms used in the embodiments of the present application are explained and described, so as to facilitate the understanding of those skilled in the art.

[0049] Spin lock: a non-blocking lock, which is implemented in a multi-threaded environment using busy waiting to achieve synchronization, that is, the thread will not be suspended when requesting a lock, but will repeatedly check whether the lock is available in a loop. When a thread acquires the lock, other threads will continue to try to acquire the lock until the thread that acquires the lock voluntarily releases the lock, and then other threads can continue to execute.

[0050] Controller Area Network (CAN) bus controller: a digital circuit or microprocessor specially designed to implement the CAN bus communication protocol, which is responsible for converting the data sent by the CPU (or microprocessor) into a format that conforms to the CAN bus standard and sending it out through the CAN bus; at the same time, it can also receive data from the CAN bus, convert it into a format that the CPU can recognize, and pass it to the CPU for processing. In short, the CAN bus controller is a bridge connecting the CPU and the CAN bus, realizing the data exchange between the CPU and the CAN bus.

[0051] As Figure 1As shown, a distributed control system provided by the present application may include a host computer, a control station and input / output devices, wherein the input / output devices may include controlled devices and acquisition devices, such as various switching devices (such as output valves) and acquisition devices (such as instruments, sensors, etc.).

[0052] like Figure 1 As shown, the number of host computers, control stations and input / output devices in a distributed control system is usually n, where n is an integer greater than 1.

[0053] A control station typically includes a controller and I / O modules. The controller can be connected to a host computer via a redundant process control network. The controller can include multiple system-on-chips (SoCs). The term "multiple" can mean two or more. This example uses a controller consisting of two SoCs, SoC1 and SoC2. Each SoC can be single-core or multi-core, and multi-core can be two or more cores, though this application does not impose any restrictions.

[0054] The controller can receive program instructions or data from the host computer. For example, the host computer can send hardware configuration information and program instructions to the controller.

[0055] The controller configures the corresponding hardware based on the hardware configuration information, such as configuring the scheduling period for the I / O module. Furthermore, the controller executes program instructions issued by the host computer to perform corresponding operations and processing on received data (such as data collected by the I / O module and the data acquisition device), generating corresponding output data. This output data can be referred to as I / O module output data and can be control instructions or data. The controller can send data to the corresponding I / O module via the CAN bus. Furthermore, the I / O module sends the received output data to the input / output device connected to the I / O module.

[0056] For example, when the controller detects that one of the switch devices is in the on state, it controls the other switch device to be closed. Specifically, when the controller receives the sampling value of an IO module input channel as ON, it outputs an OFF control instruction to the output channel of another IO module.

[0057] The data output method of the distributed control system provided by this application is a process in which the controller executes the user program and outputs the corresponding output data. Figure 2 , which is a schematic diagram of the internal structure of a controller in a distributed control system provided by the present application.

[0058] This application takes a dual-core SoC as an example to illustrate that data interaction is achieved between different cores through shared memory, for example, Figure 2In the controller, the SoC can include Core0 and Core1, wherein Core0 is responsible for data operation processing, and Core1 is responsible for interaction with the IO module and basic event record transaction, Core0 and Core1 interact data through shared memory, and Core0 and Core1 can communicate through inter-core interruption.

[0059] The host computer can configure the first periodic IO module, the second periodic IO module and the program instruction in the hardware configuration.

[0060] The first periodic IO module is an IO module with a first periodic scheduling period, for example, the first period can include 5ms, 10ms or 20ms, etc. The second periodic IO module is an IO module with a second periodic scheduling period, and the second period can include 100ms, 200ms or 500ms, etc. For example, a control station includes 64 IO modules, wherein IO modules 1-16 use a first period (such as 20ms) for output, and the remaining IO modules 17-64 use a second period (such as 100ms) for output.

[0061] The shared memory is a memory area in the SoC that can be read and written by Core0 and Core1 simultaneously. In the embodiment, the shared memory can include a spin lock data area, a first output data area, a second output data area and a diagnostic information data area.

[0062] The spin lock data area is used to store the basic data structure of the spin lock, such as n spin locks, and the size of the data area can be n x the length of the spin lock basic data structure.

[0063] The first output data area is used to store data output by the IO module using the first period.

[0064] The second output data area is used to store data output by the IO module using the second period.

[0065] The diagnostic information data area is used to store the state information of Core0 and Core1, and can also include the scheduling scheme of the IO module.

[0066] Core0 in the controller can download hardware configuration data and program instructions from the host computer, and configure the hardware according to the hardware configuration data, and run the program instructions to perform corresponding operations and processing on the data.

[0067] The Core 1 can read and write the IO module through the CAN bus controller. The CAN bus controller can be regarded as a peripheral of the Core 1. For example, the CAN bus controller can adopt a FlexCan controller, and the FlexCan controller includes a plurality of message buffers (MBs). The Core 1 can write the data to be output into the MB of the FlexCan controller, and the FlexCan controller sends the data in the MB to the corresponding IO module through the CAN bus.

[0068] Please refer to Figure 3 , which shows a structure schematic diagram of a controller of another distributed control system provided in the present application, based on the controller shown in Figure 2 , further comprising a first output buffer and a second output buffer. The first output buffer is the output buffer of the Core 0, that is, only the Core 0 can read and write the buffer. The second output buffer is the output buffer of the Core 1, that is, only the Core 1 can read and write the buffer.

[0069] The main thread of the Core 0 writes the output data into the first output buffer after obtaining the output data, and the buffer read-write thread is responsible for reading the output data from the first output buffer and writing the output data into the first output data area of the shared memory. That is, the processing and operation process and the writing shared process can be simultaneously performed by different threads.

[0070] The main thread of the Core 1 reads the output data from the first output data area of the shared memory and writes the output data into the second output buffer, and the buffer read-write thread of the Core 1 is responsible for reading the output data from the second output buffer and writing the output data into the corresponding MB. That is, the process of reading data from the shared memory and reading data from the second output buffer can be simultaneously performed by different threads.

[0071] The processing process of the Core 0 and the Core 1 before outputting real-time data to the IO module will be introduced below in combination with Figure 2

[0072] After the Core 0 downloads the hardware configuration data from the upper computer, before running the new configuration for the first time, the Core 0 first polls the spin lock of the original IO output data area and detects that the state of the IO output data area is invalid, indicating that the Core 1 has taken away the output data in the data area. Thereafter, the Core 0 reassigns the data area protected by the spin lock. The first data area in the shared memory is used to store the output data of the IO modules 1-16, and the Core 0 allocates the first spin lock to protect the first data area. The second data area in the shared memory is used to store the output data of the IO modules 17-64, and the Core 0 allocates the second spin lock to protect the second data area.

[0073] ​In some embodiments, the spin lock data structure can be an 8-byte array and two 2-byte period times. Each bit of the 8-byte array represents the output period of an IO module, for example, bit position 1 indicates that the corresponding IO module adopts the first period scheduling, and bit position 0 indicates that the corresponding IO module adopts the second period scheduling. One of the two 2-byte is used to indicate the specific time of the first period, and the other is used to indicate the specific time of the second period. The spin lock allocated by Core0 for the first data area and the second data area is stored in the spin lock data area of the shared memory.

[0074] In addition, the spin lock data area can also store the spin lock of other data areas in the shared memory, which is not described in detail in this application.

[0075] After Core0 updates the spin lock of the first and second data areas, it sends an interrupt to Core1 through the inter-core interrupt to inform Core1 that the diagnostic information data area content has been updated. The updated content of the diagnostic information data area can include the IO module scheduling period configuration information, i.e., the scheduling period of each IO module, and the spin lock allocated by Core0 for the first data area and the second data area.

[0076] After receiving the interrupt, Core1 updates the spin lock protection data area. The first spin lock protects the first data area, and the second spin lock protects the second data, and the MB allocation scheme of the output data is updated, i.e., the MB is allocated to each IO module according to the period configuration of the IO module, and the execution result is returned as a reply to Core0. The execution result indicates that Core1 has correctly received the IO module scheduling period configuration information issued by Core0, and has re-established the MB allocation table corresponding to the IO module.

[0077] After Core0 confirms the reply command of Core1, it starts the scheduling program instruction, such as performing corresponding operation and processing on the received data to obtain the output data of the IO module. According to the period of the obtained output data, the output data is written into the corresponding output data area in the shared memory, for example, if the period of the obtained output data is the first period, the output data is written into the first data area of the shared memory, and Core1 is notified to read the data. Core1 reads the output data from the first data area and writes it into the MB corresponding to the IO module of the output data, and waits for the FlexCan controller to send the data in the MB to the corresponding IO module.

[0078] In some embodiments, the process of Core1 reallocating the MB of the FlexCan controller for the IO module is as follows:

[0079] The FlexCan controller can be regarded as a peripheral of the Core 1, and the FlexCan controller includes a plurality of MBs, such as 64 MBs. The FlexCan controller can configure each of the MBs to be a sending MB or a receiving MB, for example, 32 sending MBs and 32 receiving MBs can be configured, for example, MBs 1-32 are sending MBs, and MBs 33-64 are receiving MBs. Among them, MBs 1-3 are respectively used to send broadcast frames, management message frames, and synchronization frames in CAN data, and MBs 4-32 are used to send output data frames.

[0080] Generally, the number of available sending MBs can be less than the actual sending demand, and the sending MBs can be allocated according to the proportion of the IO modules of the first period to the IO modules of the second period.

[0081] For example, the number of sending MBs allocated to the IO modules of the first period P f As follows:

[0082] (1)

[0083] The number of sending MBs allocated to the IO modules of the second period P n As follows:

[0084] (2)

[0085] Wherein, m represents the number of IO modules of the first period, n represents the number of IO modules of the second period, T fast represents the scheduling period of the first period, T normal represents the scheduling period of the second period, S MB represents the number of allocatable sending MBs.

[0086] If the P f , P n calculated according to the above formula is not an integer, it is rounded down. And a MB serial number table corresponding to the IO module is established, that is, an array, the dimension of the array is consistent with the number of IO modules, and each element represents the MB serial number corresponding to an IO module, for example, the sending MBs 4 are shared by the IO modules 17-20, and therefore the values corresponding to the 17th-20th elements in the array are all 4.

[0087] The data output method of the distributed control system provided in the present application will be described below in combination with Figure 4 and Figure 5 .

[0088] Please refer to Figure 4 , which shows a flowchart of the data output method of the distributed control system, which can be applied to the controller in the distributed control system, and the first core and the second core in the embodiment are different cores in the same SoC. As shown inFigure 4 As shown, the method can include the following steps:

[0089] S101, the first core runs the first program to obtain target output data.

[0090] The target output data can be data obtained by the first core operating and processing the received IO module input data, which can be sent to the corresponding controlled device, such as a switch device, through the IO module.

[0091] In this application, the output data can include first-period output data or second-period output data.

[0092] S102, the first core obtains a target spin lock corresponding to the target output data.

[0093] The first core sets different spin locks for different data areas in the shared memory for storing different output periods. For example, Figure 2 In the example shown, a first spin lock is set for a first output data area in the shared memory, and a second spin lock is set for a second output data area.

[0094] After the first core determines the output period of the current output data, it obtains the spin lock corresponding to the corresponding output data area in the shared memory. For example, the first spin lock is obtained when the first-period data is output, and the second spin lock is obtained when the second-period data is output.

[0095] S103, the first core writes the target output data into the target output data area of the shared memory and releases the target spin lock.

[0096] When the target output data is first-period data, the data is written into the first output data area. When the target output data is second-period data, the data is written into the second output data area.

[0097] S104, the first core sends a data output notification to the second core.

[0098] After the first core writes the current output data into the shared memory, it initiates an inter-core interrupt, which is used to notify the second core that the content of the output data area of the shared memory has been updated.

[0099] S105, the second core responds to the data output notification and obtains the target spin lock.

[0100] After the second core receives the data output interrupt event initiated by the first core, it can parse the interrupt event to obtain the area of data content update, such as the content of the first output data area or the second output data area in the shared memory being updated. Further, it attempts to obtain the spin lock of the data area until the spin lock is obtained.

[0101] S106, the second core reads the target output data in the target output data area in the shared memory and writes the target output data into the target sending MB of the CAN bus controller.

[0102] After the second core obtains the spin lock of the target output data area, the second core reads the output data in the target output data area and writes the output data into the sending MB of the IO module corresponding to the target output data.

[0103] In some embodiments, after the second core reads the target output data, the second core determines the IO module number corresponding to the target output data, further determines the MB number corresponding to the IO module number according to the MB allocation table corresponding to the IO module, and finally writes the target output data into the determined sending MB.

[0104] S107, the second core determines the priority of the target sending MB according to the period of the target data and activates the target sending MB to be sent.

[0105] After the second core writes the target output data into the corresponding sending MB, the second core further configures the priority of the sending MB according to the period of the target output data. For example, the priority of the sending MB can be configured according to the pre-configured priority configuration information of each type of data transmission. For example, if the output period of the target output data is the first period, the priority of the target sending MB is set to level 4. For example, if the output period of the target output data is the second period, the priority of the target sending MB is set to level 5.

[0106] S108, the CAN bus controller reads the data in the sending MB in the order from high to low according to the priority of the sending MB.

[0107] In some embodiments, the CAN bus controller (such as FlexCan controller) supports configuring different priorities for MBs, and Core1 can write different types of frames into MBs with different priorities. In this embodiment, data frames with different output periods can be written into different MBs. The FlexCan controller can arbitrate the MBs to be sent according to the priority of each MB.

[0108] For example, the priority of the MB can be indicated by 3 bits, and the 3 bits correspond to 8 priorities at most, such as priorities 0-7. The priorities of the MBs corresponding to broadcast frames, management message frames and synchronization frames are configured as priorities 0-2. The broadcast frame is used for communication diagnosis and detection between the controller and the IO module on the bus, and the controller sends a data packet every 25 ms, so the priority of the broadcast frame is the highest, which is priority 0. The MB corresponding to the IO module of the first period can be configured as priority 4, and the MB corresponding to the IO module of the second period can be configured as priority 5.

[0109] When there are multiple to-be-sent MBs in the CAN bus controller at the same time, the multiple to-be-sent MBs are sent in order from high to low priority. For example, when there are data frames of priority 4 and 5 at the same time, the data frames of priority 4 are sent first, and after all the data frames of priority 4 are sent, the data frames of priority 5 are sent.

[0110] S109, the CAN bus controller sends the data in the read to-be-sent MB to the corresponding IO module through the CAN bus.

[0111] The CAN bus controller converts the data format of the output data read from the to-be-sent MB into a format conforming to the CAN bus standard and sends it to the CAN bus, and finally transmits it to the IO module corresponding to the output data.

[0112] The data output method of the distributed control system provided in the embodiment can realize data interaction between different cores in the same SoC in the controller through shared memory. Different data regions of different output periods are set in the shared memory, and different spin locks are configured for different data regions, for example, a first spin lock is configured for the output data region of the first period, and a second spin lock is configured for the output data region of the second period. After the first core processes the target output data, the spin lock of the output data region in the shared memory for storing the target output data is acquired. The target output data is written into the target output data region, and the spin lock is released. Then, an output data notification is sent to the second core, and the second core acquires the spin lock of the target output data region in response to the notification, reads the data in the target output data region, and writes the data into the MB of the CAN bus controller. The CAN bus controller sends the data in the MB to the corresponding IO module. It can be seen that when different periods of data output exist in the controller at the same time, the scheme can protect different periods of output data in the shared memory through different spin locks respectively, avoid the waiting time for acquiring the spin lock, and improve the real-time performance of data output. At the same time, the utilization rate of SoC resources is improved.

[0113] Please refer to Figure 5 , which shows a flowchart of another data output method of a distributed control system provided in the embodiment. The method is applied to Figure 3 , as shown in Figure 5 , the method can include the following steps:

[0114] S201, the first core running the program obtains target output data.

[0115] S202, the first core writes the target output data into the first output buffer corresponding to the first core.

[0116] In some embodiments, in order to improve the data output efficiency, a corresponding output buffer is allocated for the first core, i.e., the first output buffer, which only supports the first core to perform read and write operations. In this way, the main thread of the first core can write the output data obtained by operation processing into the first output buffer, and then the write data thread reads the output data from the first output buffer and writes the output data into the target output data area of the shared memory. The main thread and the write data thread can run in parallel, thereby improving the data output efficiency.

[0117] In S203, the first core acquires the target spin lock corresponding to the data area for the target output data in the shared memory.

[0118] In S204, the first core determines whether there is data in the target output data area in the shared memory; if yes, the process returns to S204 after a preset time period (e.g., 1 ms); if no, the process proceeds to S205.

[0119] The first core acquires the spin lock of the target output data area in the shared memory, and determines whether the valid flag of the target output data area is invalid. If the valid flag is invalid, it indicates that there is no data in the target output data area. If the valid flag is set, it indicates that there is data in the target output data area to be read by the second core.

[0120] In S205, the first core writes the target output data into the target output data area in the shared memory, releases the target spin lock, and sets the valid flag of the target output data area.

[0121] If the first core determines that there is no data in the target output data area in the shared memory that has not been read by the second core, the target output data can be written into the target output data area, and the valid flag of the target output data area is set, indicating that there is data in the target output data area to be read.

[0122] In S206, the first core sends a data output notification to the second core.

[0123] In S207, the second core acquires the target spin lock in response to the data output notification.

[0124] In S208, the second core determines whether there is data in the target output data area in the shared memory; if yes, the process proceeds to S209; if no, the process returns to S208 after a preset time period.

[0125] After the second core acquires the spin lock of the target output data area in the shared memory, it first determines whether the valid flag of the target output data area is invalid (e.g., 0). If the valid flag is invalid, it indicates that there is no data in the target output data area. If the valid flag is set (e.g., 1), it indicates that there is data in the target output data area.

[0126] S209, the second core reads data in the target output data area in the shared memory and writes the data into the output buffer corresponding to the second core (i.e., the second output buffer), and sets the output flag of the corresponding IO module.

[0127] In some embodiments, in order to improve the data output efficiency, the second core is allocated a corresponding output buffer, i.e., the second output buffer, which means that the buffer only supports the read and write operations of the second core. In this way, the main thread of the second core reads the target output data from the target output data area and writes the data into the second output buffer, and then another thread reads the output data from the second output buffer and writes the data into the corresponding MB. The main thread and the other thread can run in parallel, thereby improving the data output efficiency.

[0128] S210, the second core traverses the IO modules to determine the target IO module whose output flag is set and which has remaining data in the corresponding output buffer.

[0129] After the second core writes the data read from the shared memory into the second output buffer, the second core traverses the IO modules in the order of the sequence number from small to large to determine the target IO module whose output flag is set (e.g., 1) and which has a non-zero length of remaining data in the output buffer corresponding to the sequence number.

[0130] The set output flag of the IO module indicates that the IO module has data to be output, and the non-zero length of the remaining data in the second output buffer corresponding to the IO module indicates that the IO module has data to be sent. In other words, this step is to find the IO module which has data to be output in the order of the sequence number from small to large.

[0131] S211, the second core obtains the target sending MB corresponding to the target IO module.

[0132] The second core can find the sequence number of the sending MB corresponding to the sequence number of the target IO module according to the MB allocation table to determine the target sending MB.

[0133] S212, the second core determines whether the target sending MB is idle; if yes, S213 is performed, and if no, the second core continues to return to execute S212 after delaying for a preset time length.

[0134] After the second core determines the sending MB corresponding to the target IO module, the second core first determines whether the sending MB has no data, which indicates that the sending MB is in an idle state.

[0135] S213, the second core determines the priority of the sending MB according to the period of the output data, writes the output data corresponding to the target IO module in the second output buffer into the target sending MB, and activates the target sending MB to be sent.

[0136] For example, the output data of the first cycle corresponds to priority 4, and the output data of the second cycle corresponds to priority 5.

[0137] After the output data is written into the target MB, the target sending MB is activated to be in a state of being ready to be sent, that is, the sending MB has data waiting to be sent to the CAN bus.

[0138] S214, the CAN bus controller reads the data in the ready-to-send MB in order of high to low priority of the ready-to-send MB.

[0139] S215, the CAN bus controller sends the read data in the ready-to-send MB to the target IO module through the CAN bus.

[0140] S216, when there are multiple IO modules sharing one sending MB, and the output data of the IO module is greater than the storage data amount of one sending MB, the second core continuously reads the output data of the target IO module from the second output buffer until all the data of the target IO module is written into the MB.

[0141] In order to ensure the continuous delivery of the output data frame of the same IO module, when the second core writes the output data in the second output buffer into the sending MB, it detects that the output data amount of a certain IO module is greater than the data amount of one MB, and then writes the output data of the IO module into the same MB multiple times until all the data of the IO module is written into the MB, and then reads the data of the next IO module. In this way, the continuous delivery of the data frame of the same IO module can be ensured, and the real-time performance of the IO module output can be improved.

[0142] S217, the second core traverses the ready-to-send MB to determine that there is a ready-to-send MB with a sending timeout, and the priority of the ready-to-send MB with the sending timeout is raised to a reserved priority.

[0143] S218, the CAN bus controller re-sends the ready-to-send MB according to the updated priority.

[0144] The CAN bus controller sends the ready-to-send MB in order of high to low priority, and when the high-priority ready-to-send MB is dense, it may cause the low-priority ready-to-send MB to be always not sent, resulting in a sending timeout. In this scenario, a reserved priority can be set, and when a ready-to-send MB with a sending timeout is detected, the priority of the ready-to-send MB can be adjusted to the reserved priority, and the data in the ready-to-send MB is sent according to the re-allocated priority next time. By dynamically adjusting the priority of the ready-to-send MB with the sending timeout, the waiting time for data sending failure and retransmission is shortened, and the data output efficiency is improved.

[0145] For example, the reserved priority is level 3, and Core 1 can traverse all to-be-sent MBs at intervals, when there is an MB whose sending time is out, the priority of the to-be-sent MB is raised to level 3, and the to-be-sent MB is sent according to the reconfigured priority next time.

[0146] The data output method of the distributed control system provided by the embodiment protects different periods of output data in the shared memory by different spin locks, avoids the waiting time for obtaining the spin lock, and improves the real-time performance of data output. Meanwhile, the utilization rate of SoC resources is improved. Moreover, when it is detected that the output data volume of an IO module is greater than the data volume of one MB, the output data of the IO module is written into the same MB for multiple times until all data of the IO module is written into the MB, and then the data of the next IO module is read. In this way, the data frame of the same IO module can be continuously sent out, and the real-time performance of the IO module output is improved.

[0147] Further, after detecting that a to-be-sent MB of low priority is sent out for a long time, the priority of the to-be-sent MB whose sending time is out is dynamically adjusted, the waiting time for data sending failure and retransmission is shortened, and the data output efficiency is improved.

[0148] Please refer to Figure 6 , which shows a structure schematic diagram of a data output device of a distributed control system provided by an embodiment of the application. The device is applied to a controller of a distributed control system. The controller includes a system on chip, the system on chip includes a first core and a second core, and the shared memory of the first core and the second core includes a first output data area and a second output data area. The first output data area is used for storing first output data and is configured with a first spin lock, and the second output data area is used for storing second output data and is configured with a second spin lock. As shown in Figure 6 , the device includes:

[0149] The output data obtaining module 101 is configured to enable the first core to obtain target output data. The target output data is the first output data or the second output data. The output period of the first output data is a first period, and the output period of the second output data is a second period. The first period and the second period are different.

[0150] The first spin lock obtaining module 102 is configured to enable the first core to obtain a spin lock corresponding to a target output data area in the shared memory area. The target output data area is used for storing the target output data.

[0151] In a possible implementation manner, the first spin lock obtaining module is specifically configured to:

[0152] After the first core determines that the output period of the target output data is the first period, the first core obtains the spin lock corresponding to the first output data area.

[0153] The first core determines that an output period of the target output data is a second period, and acquires a spin lock corresponding to the second output data area.

[0154] The first data writing module 103 is configured to enable the first core to write the target output data into the target output data area, and release the spin lock of the target output data area.

[0155] The notification sending module 104 is configured to enable the first core to send a notification to the second core that the target output data is written into the target output data area of the shared memory area.

[0156] The data output module 105 is configured to enable the second core to acquire the spin lock of the target output data area, read the target output data of the target output data area, and write the target output data into a target message buffer area of the CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer area to the target IO module.

[0157] In a possible implementation, the data output module is configured to enable the CAN bus controller to send the target output data in the target message buffer area to the target IO module, including:

[0158] The CAN bus controller determines that a plurality of IO modules share one target message buffer area, and the output data of the target IO module is greater than a storage data amount of the target message buffer area, and sends the output data in the target message buffer area to the target IO module until all the output data of the target IO module is sent.

[0159] In a possible implementation, the CAN bus controller includes a plurality of message buffer areas, and each message buffer area is configured with a corresponding priority; the data output module is configured to enable the CAN bus controller to send the output data in the to-be-sent message buffer area, and specifically configured to:

[0160] The CAN bus controller determines the to-be-sent message buffer area to be sent this time according to the priorities of the to-be-sent message buffer areas from high to low, and sends the output data in the to-be-sent message buffer area to be sent this time to the corresponding IO module.

[0161] In a possible implementation, the data output module is further configured to: when detecting that a to-be-sent MB is sent in timeout, and a priority of the to-be-sent MB sent in timeout is lower than a preset priority, the priority of the to-be-sent MB sent in timeout is raised to the preset priority.

[0162] In a possible implementation, the data output module is specifically configured to:

[0163] After determining that the target data area valid flag is set, reading the target output data in the target data area and writing the target output data into a second output buffer corresponding to the second core;

[0164] reading the output data corresponding to the target IO module from the second output buffer and writing the output data into a target message buffer corresponding to the target IO module.

[0165] In a possible implementation, the data output module is configured to read the output data corresponding to the target IO module from the second output buffer and write the output data into a target message buffer corresponding to the target IO module, and specifically configured to:

[0166] traversing the IO modules in ascending order of the serial numbers of the IO modules;

[0167] after determining that the output flag of the currently traversed IO module is set and the remaining data length corresponding to the currently traversed IO module is non-zero, determining a target message buffer corresponding to the currently traversed IO module;

[0168] after determining that the target message buffer is empty, writing the target output data corresponding to the currently traversed IO module in the first output buffer into the target message buffer, and activating the target message buffer as a to-be-sent message buffer, so that the CAN bus controller sends the output data in the to-be-sent message buffer.

[0169] The data output device of the distributed control system provided in the embodiment can protect the output data of different periods in the shared memory through different spin locks when different periods of data output exist in the controller at the same time, avoids the waiting time for obtaining the spin lock, and improves the real-time performance of data output. Meanwhile, the utilization rate of SoC resources is improved.

[0170] In the embodiment, a computer program product is further provided, which includes computer readable instructions. When the computer readable instructions run on an electronic device, the electronic device can implement any of the data output methods of the distributed control system provided in the embodiments.

[0171] In the embodiment, a computer readable storage medium is further provided, which carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement any of the data output methods of the distributed control system provided in the embodiments.

[0172] It should be noted that the apparatus embodiments described above are merely illustrative, and the units described as separate units can or can not be physically separate, and the units displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the connection relationship between the modules in the apparatus embodiment provided in the present application indicates that there is a communication connection between them, which can be implemented as one or more communication buses or signal lines.

[0173] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be realized by means of software and the necessary general hardware, and of course can also be realized by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. Generally, functions completed by computer programs can be easily realized by corresponding hardware, and the specific hardware structure for realizing the same function can also be various, such as analog circuit, digital circuit or special circuit, etc. However, for the present application, software program implementation is a better embodiment. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products, which are stored in readable storage media, such as computer floppy disks, U disks, mobile hard disks, ROM, RAM, magnetic or optical disks, etc., including a plurality of instructions for making a computer device (which can be a personal computer, a training device, or a network device, etc.) execute the methods described in various embodiments of the present application.

[0174] In the above embodiments, all or part can be realized by software, hardware, firmware or any combination thereof. When realized by software, it can be realized in the form of a computer program product in whole or in part.

[0175] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, training device or data center to another website, computer, training device or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be stored by the computer or a data storage device such as a training device, a data center, etc. integrated with one or more available media sets. The available media can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

Claims

1. A data output method for a distributed control system, characterized in that: A controller for a distributed control system, the controller comprising a system-on-chip, the system-on-chip comprising a first core and a second core, the shared memory of the first core and the second core comprising a first output data area and a second output data area, the first output data area being used to store first output data and being configured with a first spin lock, the second output data area being used to store second output data and being configured with a second spin lock; the method comprising: The first core obtains target output data, where the target output data is first output data or second output data, an output cycle of the first output data is a first cycle, an output cycle of the second output data is a second cycle, and the first cycle is different from the second cycle; The first core acquires a spin lock corresponding to a target output data area in the shared memory area, where the target output data area is used to store the target output data; The first core writes the target output data into the target output data area, releases the spin lock of the target output data area, and sends a notification to the second core that the output data is written into the target output data area of ​​the shared memory area; The second core responds to the notification, obtains the spin lock of the target output data area, reads the target output data of the target output data area and writes it into the target message buffer of the CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer to the target IO module.

2. The method according to claim 1, characterized in that The CAN bus controller sends the target output data in the target message buffer to the target IO module, including: After the CAN bus controller determines that multiple IO modules share one target message buffer and the output data of the target IO module is greater than the storage data capacity of the target message buffer, the output data in the target message buffer is sent to the target IO module until all output data of the target IO module is sent.

3. The method according to claim 1, characterized in that The CAN bus controller includes multiple message buffers, and each message buffer is configured with a corresponding priority; The CAN bus controller sends the target output data in the target message buffer to the target IO module, including: The CAN bus controller determines the target message buffer for this transmission according to the order of priority of the multiple message buffers from high to low, and sends the output data in the target message buffer for this transmission to the corresponding IO module.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: After the second core detects that the MB to be sent has timed out and the priority of the MB to be sent has timed out is lower than the preset priority, the second core increases the priority of the MB to be sent to the preset priority.

5. The method according to claim 1, wherein The step of reading the target output data in the target output data area and writing the data into the target message buffer of the CAN bus controller includes: After the second core determines that the valid flag of the target output data area is set, the second core reads the target output data in the target output data area and writes the target output data into a second output buffer corresponding to the second core; The second core reads output data corresponding to the target IO module from the second output buffer, and writes the output data into a target message buffer corresponding to the target IO module.

6. The method according to claim 5, characterized in that The second core reads output data corresponding to the target IO module from the second output buffer and writes the output data into a target message buffer corresponding to the target IO module, including: The second core traverses the IO modules in ascending order of the IO module numbers; After the output flag of the currently traversed IO module is set and the remaining data length corresponding to the currently traversed IO module is non-zero, determining the target message buffer corresponding to the currently traversed IO module; After determining that there is no data in the target message buffer, the target output data corresponding to the currently traversed IO module in the first output buffer is written into the target message buffer, and the target message buffer is activated as a message buffer to be sent, so that the CAN bus controller sends the output data in the message buffer to be sent.

7. The method according to claim 1, characterized in that The first core acquires a spin lock corresponding to a target output data area in the shared memory area, including: After determining that the output cycle of the target output data is the first cycle, the first core acquires a spin lock corresponding to the first output data area; After determining that the output cycle of the target output data is the second cycle, the first core acquires a spin lock corresponding to the second output data area.

8. A data output device for a distributed control system, characterized in that: A controller for a distributed control system, the controller comprising a system-on-chip (SoC), the SoC comprising a first core and a second core, the shared memory of the first core and the second core comprising a first output data area and a second output data area, the first output data area being used to store first output data and being configured with a first spin lock, the second output data area being used to store second output data and being configured with a second spin lock; the device comprising: an output data acquisition module, configured to enable the first core to obtain target output data, where the target output data is first output data or second output data, the output period of the first output data is a first period, the output period of the second output data is a second period, and the first period is different from the second period; a first spin lock acquisition module, configured to enable the first core to acquire a spin lock corresponding to a target output data area in the shared memory area, wherein the target output data area is used to store the target output data; a first data writing module, configured to enable the first core to write the target output data into the target output data area and release the spin lock of the target output data area; a notification sending module, configured to enable the first core to send a notification to the second core that output data has been written into a target output data area of ​​the shared memory area; A data output module is used for the second core to respond to the notification, obtain the spin lock of the target output data area, read the target output data of the target output data area and write it into the target message buffer of the CAN bus controller, so that the CAN bus controller sends the target output data in the target message buffer to the target IO module.

9. A controller for a distributed control system, characterized in that: comprising at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is configured to execute the computer program so as to enable the controller to implement the data output method of the distributed control system according to any one of claims 1 to 7.

10. A computer storage medium, characterized in that The storage medium carries one or more computer programs, and when the one or more computer programs are executed by an electronic device, the electronic device is enabled to implement the data output method of the distributed control system as described in any one of claims 1 to 7.

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