Low dropout linear regulator with embedded reference high loop gain, method of regulating

Abstract

The application provides a low-dropout linear voltage regulator with embedded reference high loop gain, and a voltage stabilizing method. The low-dropout linear voltage regulator comprises an adjusting power tube, a source electrode of the adjusting power tube is connected with a voltage input end for providing an input voltage, and a drain electrode of the adjusting power tube is connected with a voltage output end for outputting a voltage; a first loop is electrically connected with a gate electrode of the adjusting power tube, and is used for forming a pseudo push-pull stage; and a second loop is electrically connected with the drain electrode of the adjusting power tube, and is used for forming a bias circuit of the adjusting power tube by the output voltage. The second loop makes the high DC gain of the whole circuit, thereby improving the linearity, load regulation rate and low-frequency PSR, and the pseudo push-pull output stage is realized at the gate electrode of the adjusting power tube, so that the static current of the whole circuit is only in the nA level, and the low-dropout linear voltage regulator has the characteristics of compact structure, no amplifier, low power consumption and high gain.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, and in particular relates to a low dropout linear regulator with embedded reference high loop gain and a voltage regulation method. Background Technology

[0002] The growing demand for the Internet of Things (IoT) necessitates the use of self-powered, fully integrated System-on-Chip (SoC) designs to ensure sensing and computing on a single chip. Therefore, in sub-1V systems with low supply voltages, sensor nodes must have long operating lifetimes. Low-dropout linear regulators (LDOs) have always been an integral part of power management systems. For fully integrated SoCs, LDOs require on-chip load capacitance ranging from zero to hundreds of pF. Meanwhile, most advanced or traditional LDO architectures require a voltage reference (VR) (bandgap- or CMOS-based), a differential-to-single-ended error amplifier (EA), and power transistors to support varying load currents. However, due to the low supply voltage, it is difficult to design compact and high-loop-gain LDOs at sub-1V supply voltages, resulting in weaker linearity, load regulation, and power supply rejection ratio (PSR). Therefore, architectural changes are essential to ensure excellent DC performance of sub-1V LDOs. Traditional LDOs with embedded references rely solely on the reference for loop gain, which is insufficient to guarantee excellent DC performance.

[0003] Therefore, it is necessary to study a compact, amplifier-free, low-power, high-gain LDO with an embedded reference. Summary of the Invention

[0004] The purpose of this application is to provide a low-dropout linear regulator with embedded high-loop-gain reference and a voltage regulation method, so as to solve at least one technical problem in the prior art.

[0005] The technical solution of this application is:

[0006] A low-dropout linear regulator with embedded reference and high loop gain includes:

[0007] Adjust the power transistor so that its source is connected to the voltage input terminal used to provide the input voltage, and its drain is connected to the voltage output terminal used to provide the output voltage.

[0008] The first loop is electrically connected to the gate of the regulating power transistor to form a pseudo push-pull stage, which can achieve fast transient response to small step load current and provide DC gain.

[0009] The second loop is electrically connected to the drain of the regulating power transistor and is used to form a bias circuit for the regulating power transistor consisting of the output voltage.

[0010] The first loop includes:

[0011] Eighth power transistor;

[0012] A common-gate module is disposed between the drain of the eighth power transistor and the gate of the adjustment power transistor;

[0013] The eleventh power transistor is disposed between the source of the eighth power transistor and the gate of the adjustment power transistor.

[0014] The source of the eleventh power transistor is connected in parallel with the source of the adjustable power transistor and then connected to the voltage input terminal.

[0015] The drain of the eleventh power transistor is connected to the gate of the adjustment power transistor.

[0016] The common gate module includes:

[0017] The drain of the ninth power transistor is electrically connected to the drain of the eighth power transistor.

[0018] The tenth power transistor has its drain connected to the gate of the regulating power transistor;

[0019] The gate of the ninth power transistor is electrically connected to that of the tenth power transistor, and the drain of the eighth power transistor is electrically connected to that of the tenth power transistor.

[0020] The sources of both the ninth and tenth power transistors are electrically connected to the drain of the adjustment power transistor.

[0021] A common drain module is also provided between the source of the tenth power transistor and the drain of the adjustment power transistor;

[0022] The common-drain module includes:

[0023] The source of the twelfth power transistor is electrically connected to the drain of the regulating power transistor;

[0024] The drain of the thirteenth power transistor is electrically connected to the drain of the twelfth power transistor.

[0025] The gate of the twelfth power transistor is connected to the voltage input terminal;

[0026] The gates of all thirteenth power transistors are connected to the voltage output terminals.

[0027] A series module is provided between the gate of the twelfth power transistor and the voltage input terminal;

[0028] The series module includes:

[0029] The first power transistor has its drain electrically connected to the power input terminal;

[0030] The drain of the second power transistor is electrically connected to the source of the first power transistor.

[0031] The source of the third power transistor is electrically connected to the gate of the twelfth power transistor.

[0032] The gates of the first power transistor, the second power transistor, and the third power transistor are connected in parallel and then electrically connected to the gate of the twelfth power transistor.

[0033] The gate of the thirteenth power transistor is electrically connected to the gate of the fifth power transistor.

[0034] The source of the fifth power transistor is connected to the voltage output terminal, and its drain is connected to the drain of the sixth power transistor.

[0035] The source of the sixth power transistor is connected to the voltage input terminal, and the gate of the sixth power transistor is connected to the gate of the seventh power transistor.

[0036] The drain of the seventh power transistor is electrically connected to the gate of the eighth power transistor, and the source of the seventh power transistor is connected to the voltage input terminal.

[0037] The second loop includes:

[0038] A load series module is electrically connected to the voltage output terminal;

[0039] The fourth power transistor has its source connected to the output terminal of the load series module;

[0040] The gate of the fourth power transistor is connected to the voltage output terminal;

[0041] The drain of the fourth power transistor is electrically connected to the load series module to form a bias circuit for the adjusting power transistor consisting of the output voltage.

[0042] The load series module includes:

[0043] The source of the first load transistor is electrically connected to the drain of the regulating power transistor;

[0044] The drain of the second load transistor is electrically connected to the drain of the first load transistor.

[0045] The source of the second load transistor is connected to the voltage output terminal.

[0046] A low-dropout linear regulator method with embedded reference high-loop gain, based on the aforementioned low-dropout linear regulator with embedded reference high-loop gain, includes:

[0047] By using the eighth, ninth, tenth, and eleventh power transistors in the low-dropout linear regulator with embedded high-loop gain reference, a pseudo-push-pull stage is formed at the gate of the adjusting power transistor to form the first loop, thereby increasing the slew rate.

[0048] A second loop is constructed by using the first load transistor, the second load transistor, and the fourth power transistor in a low dropout linear regulator with embedded high loop gain and a reference, so that the output voltage is directly biased by the second loop and the output voltage is insensitive to PVT changes.

[0049] The transfer function for the global loop is as follows:

[0050]

[0051] The overall DC gain is:

[0052]

[0053] The poles are:

[0054]

[0055]

[0056] Zero point is:

[0057]

[0058] Where, ω p1 Principal pole, ω p2 For the secondary pole, ω p3 With ω p4 Other poles outside the bandwidth, z1 is a zero, ω p3 With ω p4 Located outside the bandwidth, it does not affect the phase margin; where β is the voltage division coefficient of the feedback resistor, g mi For MOSFET M i transconductance, g di For MOSFET M i The conductivity, C out For the output capacitor, C x To compensate for the capacitance, C P C is the gate capacitance of the power transistor MP. m For Miller compensation capacitor, A ns For pseudo-push-pull stage gain, R b R is the equivalent resistance of the bias current source. o2 R is the equivalent output resistance of the pseudo-push-pull stage. L Let be the load resistance, and s be the Laplace transform parameter.

[0059] Application of a low-dropout linear regulator with embedded reference and high loop gain, as described above, in IoT devices.

[0060] The beneficial effects of this application include at least the following:

[0061] The low-dropout linear regulator with embedded reference and high loop gain described in this application forms a first loop by forming a pseudo-push-pull stage at the gate of the adjustment power transistor through the eighth, ninth, tenth, and eleventh power transistors. The first load transistor, second load transistor, and fourth power transistor in the low-dropout linear regulator form a second loop, resulting in high overall DC gain, thereby improving linearity, load regulation, and low-frequency PSR. Furthermore, the pseudo-push-pull output stage is implemented at the gate of the power transistors, making the overall circuit's quiescent current only in the nA range. It features a compact structure, no amplifier, low power consumption, and high gain. Attached Figure Description

[0062] Figure 1 It is a traditional low-dropout linear regulator with an embedded 5-tube reference;

[0063] Figure 2 It is an adaptive substrate bias circuit in the prior art;

[0064] Figure 3 This is a circuit diagram of the low-dropout linear regulator with embedded reference and high loop gain described in this invention.

[0065] Figure 4 yes Figure 3 Small-signal analysis diagram of the LDO circuit shown;

[0066] Figure 5 yes Figure 3 Loop stability simulation of the circuit diagram shown, IL = 25mA;

[0067] Figure 6 yes Figure 3 The transient response simulation diagram of the circuit shown is given, with IL = 1mA ~ 25mA and tr = 100ns. Detailed Implementation

[0068] The present application will now be further described with reference to the accompanying drawings.

[0069] To provide a more detailed explanation of this application, a detailed description of the prior art is required.

[0070] like Figure 1It is a traditional low-dropout linear regulator with an embedded 5-transistor reference. The VR is integrated with the flip-flop voltage follower (FVF) output stage to form a dual-loop structure. This ensures that the LDO has a high DC loop gain, thus providing excellent linearity and load regulation for the proposed design. The embedded reference design also ensures tighter integration of reference and regulation, as the LDO output is directly controlled by the VR module without the need for an EA.

[0071] VR is composed of devices M1-M5. Transistors M3-M5 improve line sensitivity by ensuring a fixed DC voltage across M1 and reducing drain-induced barrier lowering (DIBL), thereby improving the reference DC PSR. The subthreshold current source M1 and the bottom current sink M2 have the same drain current. When placed in negative feedback, M2 generates a specific VGS2 to carry the required drain current. For a proper M1 to M2 size ratio, VGS2 can be made temperature insensitive, therefore VGS2 = VREF, and its output voltage formula is...

[0072]

[0073] In this structure, VR acts as a single-stage common-source amplifier for the small-signal gain from gate to drain in M2. Considering the inverting gain provided by VR, an FVF is chosen as the pass stage of the LDO to ensure dual-loop regulation at the output node. The advantage of this structure is low output impedance and the bias flexibility achieved through M7. However, the overall DC gain is not high, and this architecture does not offer advantages in linearity, load regulation, or PSR compared to LDO architectures with amplifiers. Furthermore, the lack of an amplifier results in a low gate slew rate (SR) for the LDO power transistor, affecting transient response. Because loop L1 has a small UGB (0.2kHz under nominal conditions), the transient recovery of VOUT is slow (on the order of milliseconds). Since the recovery of VOUT after a load change depends primarily on the bandwidth of the operating loop, an adaptive substrate bias circuit is added to address the slow transient response.

[0074] like Figure 2 This is an existing adaptive substrate biasing circuit. The gate of MB2 is connected to VBIAS, where MB2 is only 1 / 16 of Ib to reduce power consumption. MB2 is connected to the diode-connected PMOS device MB1. As the load current increases, Vin-Vbulk begins to increase, and the VTH of MP decreases due to the body effect. The reduced VTH causes the VG of MP to decrease as IL increases. The source-body voltage of MP gradually becomes positive, and the source-body leakage current flowing to the body terminal also increases accordingly. However, the self-biasing circuit design is complex and carries the risk of diode current leakage from the source to the body of MP. It also has relatively high power consumption.

[0075] It is evident that existing LDOs with an exponential gain (EA) in the sub-1V range struggle to achieve high DC gain within a limited voltage margin. While cascading two gain stages can improve gain, this comes at the cost of increased quiescent power consumption and reduced stability. Alternatively, transistors with lower threshold voltages can be used, but this requires additional mask layers, increasing manufacturing costs. Furthermore, existing LDO architectures with embedded references omit the EA for a low-voltage, compact design, but the DC gain remains insufficient, resulting in lower linearity, load regulation, and PSR performance. Additionally, the lack of the EA leads to a lower SR in the power transistors, meaning that compared to LDO architectures with EAs, transient response remains inferior under the same bandwidth conditions. Using a high-power adaptive substrate bias to increase SR is detrimental to achieving a longer operating life for sensor nodes in IoT systems. Specific Implementation Example 1:

[0077] This invention provides an embodiment:

[0078] To address the issue of low DC gain in LDOs with embedded references and no feedback exchange (EA), this invention proposes a low-dropout linear regulator with embedded references and high loop gain, featuring multiple feedback loops, high gain, and low power consumption; for example... Figure 3 As shown, the LDO core consists of two loops: LOOP2 provides excellent DC regulation performance such as linearity and load regulation, while LOOP1 provides fast transient response.

[0079] like Figure 3 A low-dropout linear regulator with embedded high-loop-gain reference is described below: An adjustable power transistor MP has its source connected to a voltage input terminal for providing the input voltage, and its drain connected to a voltage output terminal for providing the output voltage; a first loop is electrically connected to the gate of the adjustable power transistor MP to form a pseudo-push-pull stage, enabling fast transient response to small step load currents and providing DC gain; a second loop is electrically connected to the drain of the adjustable power transistor MP to form a bias circuit for the adjustable power transistor MP composed of the output voltage.

[0080] Specifically, in the first loop, a common-gate module is disposed between the drain of the eighth power transistor M8 and the gate of the adjusting power transistor MP; an eleventh power transistor M11 is disposed between the source of the eighth power transistor M8 and the gate of the adjusting power transistor MP; the source of the eleventh power transistor M11 is connected in parallel with the source of the adjusting power transistor MP and then connected to the voltage input terminal; the drain of the eleventh power transistor M11 is connected to the gate of the adjusting power transistor MP.

[0081] Preferably, the common-gate module includes: a ninth power transistor M9 and a tenth power transistor M10; wherein the drain of the ninth power transistor M9 is electrically connected to the drain of the eighth power transistor M8; the drain of the tenth power transistor M10 is connected to the gate of the adjusting power transistor MP; the gates of the ninth power transistor M9 and the tenth power transistor M10 are electrically connected, and are also electrically connected to the drain of the eighth power transistor M8; the sources of both the ninth power transistor M9 and the tenth power transistor M10 are electrically connected to the drain of the adjusting power transistor MP.

[0082] Specifically, a common drain module is provided between the source of the tenth power transistor M10 and the drain of the adjustment power transistor MP;

[0083] The common-drain module includes: a twelfth power transistor M12 and a thirteenth power transistor M13; wherein, the source of the twelfth power transistor M12 is electrically connected to the drain of the adjusting power transistor MP; the drain of the thirteenth power transistor M13 is electrically connected to the drain of the twelfth power transistor M12; the gate of the twelfth power transistor M12 is connected to the voltage input terminal; and the gates of the thirteenth power transistor M13 are all connected to the voltage output terminal. A series module is provided between the gate of the twelfth power transistor M12 and the voltage input terminal.

[0084] Preferably, the series module includes: a first power transistor M1, a second power transistor M2, and a third power transistor M3; wherein, the drain of the first power transistor M1 is electrically connected to the power input terminal; the drain of the second power transistor M2 is electrically connected to the source of the first power transistor M1; the source of the third power transistor M3 is electrically connected to the gate of the twelfth power transistor M12; the gates of the first power transistor M1, the second power transistor M2, and the third power transistor M3 are connected in parallel and then electrically connected to the gate of the twelfth power transistor M12. The gate of the thirteenth power transistor M13 is electrically connected to the gate of the fifth power transistor M5; the source of the fifth power transistor M5 is connected to the voltage output terminal, and its drain is connected to the drain of the sixth power transistor M6; the source of the sixth power transistor M6 is connected to the voltage input terminal, and the gate of the sixth power transistor M6 is connected to the gate of the seventh power transistor M7; the drain of the seventh power transistor M7 is electrically connected to the gate of the eighth power transistor M8, and the source of the seventh power transistor M7 is connected to the voltage input terminal.

[0085] The second loop includes: a load series module and a fourth power transistor M4; wherein, the load series module is electrically connected to the voltage output terminal; the source of the fourth power transistor M4 is connected to the output terminal of the load series module; the gate of the fourth power transistor M4 is connected to the voltage output terminal; the drain of the fourth power transistor M4 is electrically connected to the load series module, for forming a bias circuit composed of the output voltage for the adjusting power transistor MP.

[0086] Preferably, the load series module includes: a first load transistor Mf1 and a second load transistor Mf2; wherein, the source of the first load transistor Mf1 is electrically connected to the drain of the regulating power transistor MP; the drain of the second load transistor Mf2 is electrically connected to the drain of the first load transistor Mf1; and the source of the second load transistor Mf2 is connected to the voltage output terminal.

[0087] This embodiment describes a low-dropout linear regulator with embedded reference and high loop gain, capable of providing ultra-low IQ and high load current drive capability. However, this requirement can be reduced in load transient performance due to poor SR at the power transistor gates. This limitation is caused by the large gate capacitances of MP and the nA constant current sources Ib1 and Ib2. To overcome this drawback, this embodiment adds a slew rate enhancement feedback loop LOOP1, forming a pseudo-push-pull stage at the MP gate, composed of the eighth power transistor M8, the ninth power transistor M9, the tenth power transistor M10, and the eleventh power transistor M11. For small step load currents, this loop shortens the recovery time to tens of microseconds, thereby achieving a fast transient response. Simultaneously, LOOP1 provides the main DC gain for the overall loop, approximately 90 dB. Furthermore, due to the small parasitic capacitances at each node and the low overall power consumption, most of the poles generated by these nodes are outside the bandwidth and do not affect loop stability. The high DC gain Loop1 ensures good linearity, load regulation, and low-frequency PSR performance of the LDO.

[0088] For LOOP2, it can be seen that LOOP2 directly biases VOUT, rather than using a current mirror method based on a single-transistor controlled FVF. Therefore, the output voltage directly depends on VR, and thus the LDO's output voltage is insensitive to changes in PVT.

[0089] For overall small signal analysis, such as Figure 4 For simplicity, the channel length modulation effect of the MOSFET is ignored here (ro12≈∞). Therefore, looking from Vout towards the drain of M12, the gain can be simplified to...

[0090]

[0091] Therefore, gm12B can be simplified to

[0092]

[0093] The transfer function for the global loop is as follows:

[0094]

[0095] The overall DC gain is

[0096]

[0097] The poles are:

[0098]

[0099]

[0100] Zero point is:

[0101]

[0102] Where, ω p1 Principal pole, ω p2 For the secondary pole, ω p3 With ω P4 For other poles outside the bandwidth, z1 is a zero, and z1 is located at ω. p1 With ω p2 Then ensure good phase margin (PM). Additionally, ω p3 With ω p4 Located outside the bandwidth, ω should be ensured during circuit design. p3 It should not be too close to z1, otherwise PM will drop significantly, leading to loop instability. At the same time, Ib2 should not be too small, otherwise it will cause ω to degrade under light load. p4 Too close to z1.

[0103] However, since the embedded VR only carries a pA-level quiescent current, the effective resistance at the drain of M4 is in the hundreds of MΩ. Due to this large impedance, the dominant left-half-plane pole of Loop1 is at ω. p1 = gds4 / Cx (for all process angles <1kHz), therefore, at ω p1 Subsequently, due to the decrease in loop gain, the effective output impedance at VOUT will increase, causing the PSR to begin to decrease. However, due to the high overall DC gain, the PSR still performs well in the 1–100 Hz range.

[0104] Compared to a low-dropout linear regulator with an embedded 5-transistor reference, this embodiment achieves better transient response without requiring an adaptive substrate bias circuit, significantly reducing power consumption. The combination of high-bandwidth, high-gain LOOP1 and LOOP2 improves the overall gain, ensuring good linearity, load regulation, and low-frequency PSR for the LDO. Furthermore, the pseudo-push-pull stage increases the slew rate at the MP gate, further enhancing the transient response.

[0105] Compared to low-dropout linear regulators with an embedded 5-transistor reference, load regulation, line regulation, and PSR are all improved. Furthermore, compared to traditional LDOs, the elimination of the need for an amplifier significantly reduces power consumption.

[0106] The DC gain in this embodiment is:

[0107]

[0108] The DC gain of the low-dropout linear regulator with an embedded 5-tube reference is:

[0109]

[0110] At low frequencies, the DC gain of this invention is approximately 150 dB, while the DC gain of the low-dropout linear regulator with an embedded 5-transistor reference is approximately 60 dB. It can be seen that the DC gain of this invention is significantly improved. Below is a comparison of various data from the loop stability simulation and transient simulation of this invention, as well as the data from the low-dropout linear regulator with an embedded 5-transistor reference. Figure 5 and 6 Specific data are shown in Table 1.

[0111] Table 1 Data Comparison

[0112]

[0113] In summary, this invention proposes a low-dropout linear regulator with multi-loop control and embedded reference, which achieves high gain and good transient response without the use of an amplifier, and has a more compact structure. Specific Implementation Example 2:

[0115] The present invention also provides an embodiment:

[0116] A low-dropout linear regulator with embedded reference high loop gain, based on the low-dropout linear regulator with embedded reference high loop gain described in Specific Embodiment 1, includes: forming a first loop by using the eighth power transistor M8, the ninth power transistor M9, the tenth power transistor M10, and the eleventh power transistor M11 in the low-dropout linear regulator with embedded reference high loop gain to form a pseudo push-pull stage at the gate of the adjusting power transistor MP, thereby increasing the slew rate; and constructing a second loop by using the first load transistor Mf1, the second load transistor Mf2, and the fourth power transistor M4 in the low-dropout linear regulator with embedded reference high loop gain, so that the second loop directly biases the output voltage, making the output voltage insensitive to PVT changes. Specific Implementation Example 3:

[0118] This application also provides an embodiment:

[0119] An electronic device includes: a storage medium and a processing unit; wherein the storage medium is used to store a computer program, and the processing unit exchanges data with the storage medium for executing the computer program during linear voltage regulation to perform the steps of the low dropout linear voltage regulation method with embedded reference high loop gain as described in Specific Embodiment 2. Specific Implementation Example 4:

[0121] A computer-readable storage medium storing a computer program; when the computer program is run, it performs the steps of the low-dropout linear voltage regulation method with embedded reference high loop gain as described in Specific Embodiment 2.

[0122] In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0123] The above disclosures are merely a few specific implementation scenarios of this application; however, this application is not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of this application. The above application serial numbers are for descriptive purposes only and do not represent the superiority or inferiority of the implementation scenarios.

Claims

1. A low-dropout linear regulator with embedded reference and high loop gain, characterized in that, include: Adjust the power transistor so that its source is connected to the voltage input terminal used to provide the input voltage, and its drain is connected to the voltage output terminal used to provide the output voltage. The first loop is electrically connected to the gate of the regulating power transistor to form a pseudo push-pull stage, which can achieve fast transient response to small step load current and provide DC gain. The second loop is electrically connected to the drain of the regulating power transistor and is used to form a bias circuit for the regulating power transistor consisting of the output voltage, so as to improve the DC regulation performance. The first loop includes: Eighth power transistor; A common-gate module is disposed between the drain of the eighth power transistor and the gate of the adjustment power transistor; The eleventh power transistor is disposed between the source of the eighth power transistor and the gate of the adjustment power transistor. The source of the eleventh power transistor is connected to the voltage input terminal; The drain of the eleventh power transistor is connected to the gate of the adjustment power transistor. The common gate module includes: The drain of the ninth power transistor is electrically connected to the drain of the eighth power transistor. The tenth power transistor has its drain connected to the gate of the regulating power transistor; The gate of the ninth power transistor is electrically connected to that of the tenth power transistor, and the drain of the eighth power transistor is electrically connected to that of the tenth power transistor. The sources of the ninth power transistor and the tenth power transistor are both electrically connected to the drain of the adjustment power transistor. The second loop includes: A load series module is electrically connected to the voltage output terminal; The fourth power transistor has its source connected to the output terminal of the load series module; The gate of the fourth power transistor is connected to the voltage output terminal; The drain of the fourth power transistor is electrically connected to the load series module, which is used to form a bias circuit for the adjustment power transistor consisting of the output voltage. The load series module includes: The first load transistor has its gate and drain grounded; The drain and gate of the second load transistor are both connected to the source of the first load transistor. The source of the second load transistor is connected to the voltage output terminal.

2. The low-dropout linear regulator with embedded reference and high loop gain according to claim 1, characterized in that, A common drain module is also provided between the source of the tenth power transistor and the drain of the adjustment power transistor; The common-drain module includes: The source of the twelfth power transistor is electrically connected to the drain of the regulating power transistor; The drain of the thirteenth power transistor is electrically connected to the drain of the twelfth power transistor. The gate of the twelfth power transistor is connected to the voltage input terminal; The gate and drain of the thirteenth power transistor are both connected to the voltage output terminal.

3. The low-dropout linear regulator with embedded reference and high loop gain according to claim 2, characterized in that: A series module is provided between the gate of the twelfth power transistor and the voltage input terminal; The series module includes: The first power transistor has its drain electrically connected to the power input terminal; The drain of the second power transistor is electrically connected to the source of the first power transistor. The source of the third power transistor is electrically connected to the gate of the twelfth power transistor. The gates of the first power transistor, the second power transistor, and the third power transistor are all electrically connected to the gate of the twelfth power transistor.

4. The low-dropout linear regulator with embedded reference and high loop gain according to claim 2, characterized in that: The gate of the thirteenth power transistor is electrically connected to the gate of the fifth power transistor. The source of the fifth power transistor is connected to the voltage output terminal, and its drain is connected to the drain of the sixth power transistor. The source of the sixth power transistor is connected to the voltage input terminal, and the gate of the sixth power transistor is connected to the gate of the seventh power transistor. The drain of the seventh power transistor is electrically connected to the gate of the eighth power transistor, and the source of the seventh power transistor is connected to the voltage input terminal.

5. An Internet of Things (IoT) device, characterized in that: The IoT device employs a low-dropout linear regulator with embedded reference high loop gain as described in any one of claims 1-4.

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