An n-dimensional discrete hyperchaotic pseudo-random number generator and its generation method

Abstract

The present invention provides a n The invention discloses a 3D discrete hyperchaotic pseudo-random number generator and a generating method thereof, comprising a plurality of operation circuits, wherein the operation circuit comprises an adder, the adder is connected to a first register, the first register is connected to a multiplier, the multiplier is connected to a second register, and the second register is connected to an output module and a circulation module. The circuit structure of the invention is simple and occupies FPGA Very few resources, showing high utilization, low hardware power consumption, and the pseudo-random number rate generated can reach 8*n Gbps The pseudo-random number sequence generated can pass various well-known randomness tests, can meet most encryption needs, and can also be used for enterprise or higher-demand military purposes. Its equations are simple, the algorithm is easy to implement, the hardware resource occupancy rate is extremely low, and it has a very high speed. Whether it is low cost, low power consumption or high throughput, it far exceeds the limits that can be achieved by existing pseudo-random number algorithms.

Description

Technical Field

[0001] The present invention belongs to the field of communication security technology and relates to a n dimensional discrete hyperchaotic pseudo-random number generator and its generation method. Background Art

[0002] In today's information age, random numbers have been widely used in many fields. The main methods for generating random numbers include algorithmic pseudo-random number generation, physical entropy source true random number generation, and chaotic circuit generation. Among them, the methods of algorithmic pseudo-random number generation and physical entropy source true random number generation are feasible, but have fatal disadvantages such as platform limitations, susceptibility to environmental interference, and high cost. Currently, the chaotic circuit pseudo-random number generation has the following main characteristics: the traditional chaotic model is implemented using an exclusive-OR circuit. Although this model is small in scale and has low resource utilization, the random numbers it generates are not random and require post-processing, with a rate of only 7.38 Mbit / s; the model using an enhanced low-dimensional chaotic system plus sin operation can be miniaturized and chip-based, but the complex algorithm results in a low generation rate; finally, the pseudo-random number generator produced by Agilent Technologies in the United States, although it has been mass-produced, is prohibitively expensive. Summary of the Invention

[0003] The purpose of the present invention is to provide a n dimensional discrete hyperchaotic pseudo-random number generator and its generation method.

[0004] To this end, the present invention adopts the following technical solutions:

[0005] A sort of n The invention discloses a 3D discrete hyperchaotic pseudo-random number generator, comprising a plurality of operation circuits, wherein the operation circuit comprises an adder, the adder is connected to a multiplier, the multiplier is connected to an output module for outputting random numbers and a circulation module, the circulation module is used to input the random numbers back to the adder for cyclic calculation.

[0006] Furthermore, the adder is connected to the multiplier through a first register.

[0007] Furthermore, the multiplier is connected to the output module and the circulation module through a second register.

[0008] Furthermore, the adder is 64 bit Input to the unsigned adder.

[0009] Furthermore, the multiplier is 64 bit Enter the unsigned multiplier.

[0010] Furthermore, there are at least three operation circuits.

[0011] The present invention also provides a n dimensional discrete hyperchaotic pseudorandom number generation method, using the above n The method comprises the following steps:

[0012] (1) Enter multiple initial values kn m , and bring the initial value into n The intermediate value is calculated in the dimensional chaos model, and then the modulus operation is performed on the intermediate value to obtain the calculated value. kn m+1 , n The dimensional chaos model is as follows:

[0013]

[0014] In the formula a n is the coefficient, and a n Is a positive number.

[0015] Furthermore, in the calculation process of step (1), n The modulo operation is performed on 1 in the dimensional chaotic model, and the modulo operation is to truncate the integer bits of the intermediate value and take 64 bit Decimal gets calculated value kn m+1 Output, clear the integer of the intermediate value, and then intercept 4 bit Integer and 60 bit Bringing back the decimals n Iterative calculation is performed in a 3D chaos model.

[0016] Furthermore, the initial value in step (1) kn m 64 bit Fixed-point number, where the high 4 bit Indicates the integer part, low 60 bit Indicates the decimal part.

[0017] The beneficial effects of the present invention are:

[0018] (1) The circuit structure of this generator is simple, it occupies very little FPGA resources, shows a high utilization rate, low hardware power consumption, and the pseudo-random number rate generated can reach 8*nGbps, which can meet most encryption needs and can also be used for enterprise or higher-demand military purposes. Its equations are simple, the algorithm is easy to implement, the hardware resource occupancy rate is extremely low, and it has a very high speed. Compared with the existing random number generator, the generation rate is the same while the cost is greatly reduced, which improves FPGAThe resource utilization efficiency is improved while the power consumption is reduced. Whether it is low cost, low power consumption or high throughput, it far exceeds the limit that can be achieved by existing pseudo-random number algorithms.

[0019] (2) The pseudo-random numbers generated have high enough randomness to pass strict and high-standard randomness tests without any additional operations, and the generated sequence has high complexity and can pass the internationally renowned NIST 、 TestU 01 and Dieharder test.

[0020] (3) The pseudo-random numbers generated by the present invention only rely on FPGA The chip costs less than 5,000 yuan and is FPGA The usage of internal resources is extremely low, for a single FPGA The chip can output pseudo-random numbers through multiple channels to further improve throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 For the present invention n Schematic diagram of the structure of the 3D random number generator;

[0022] Figure 2 For the present invention n Schematic diagram of the dimensional chaos model;

[0023] Figure 3 This is a schematic diagram of the structure of a random number generator when the present invention adopts three-dimensional discrete hyperchaos;

[0024] Figure 4 Schematic diagram of the three-dimensional chaotic model of the present invention;

[0025] Figure 5 is the 2D phase diagram output by the three-dimensional chaos model algorithm k1, k2 of the present invention;

[0026] Figure 6 It is the 2D phase diagram output by the three-dimensional chaos model algorithm k2, k3 of the present invention;

[0027] Figure 7 It is the 2D phase diagram output by the three-dimensional chaos model algorithm k1, k3 of the present invention;

[0028] Figure 8 is a 3D phase diagram of the three-dimensional chaos model algorithm of the present invention;

[0029] Figure 9 This is a Lyapunov exponent diagram of the three-dimensional chaos model algorithm coefficient a1 when it changes;

[0030] Figure 10This is a Lyapunov exponent diagram when the coefficient a2 of the three-dimensional chaos model algorithm of the present invention changes;

[0031] Figure 11 The Lyapunov exponent diagram of the three-dimensional chaos model algorithm coefficient a3 when it changes;

[0032] Figure 12 This is a comparison chart of the sample entropy when the present invention adopts the three-dimensional chaos model and the sample entropy of other chaos models;

[0033] Figure 13 This is a comparison chart of the permutation entropy when the present invention adopts a three-dimensional chaotic model and the permutation entropy of other chaotic models;

[0034] In the figure, 1-adder, 2-first register, 3-multiplier, 4-second register, 5-output module, 6-loop module. DETAILED DESCRIPTION

[0035] The present invention is described in detail below in conjunction with embodiments:

[0036] A sort of n dimensional discrete hyperchaotic pseudo-random number generator, the structure of the hardware circuit is as follows Figure 1 As shown, it includes multiple operation circuits, specifically no less than three operation circuits, the operation circuit includes an adder 1, the adder 1 is used to add and sum two initial values, and the adder 1 adopts 64 bit Input unsigned adder, since the initial value is a fixed-point decimal after modulo 1, there is no need to consider the carry, set 64 bit Output, in this embodiment, adder 1 can be used for two 64 bit The initial value is added and then a 64 bit The value of adder 1 is 64 bit Initial value and 64 bit The output values are all expressed in fixed-point numbers. bit For integer digits, the last 60 bit For decimal places, adder 1 is connected to a first register 2, which is used to store a pre-stored value (the value stored before the operation starts) or the value output after the adder 1 operates. The first register 2 is connected to a multiplier 3, and the value output by the first register 2 can be input into the multiplier 3 and multiplied by a coefficient through the multiplier 3. a n , multiplier 3 uses 64 bit Input unsigned multiplier, which can be implemented by cascading DSP hard cores inside FPGA or using LUT Resource construction, after multiplication by multiplier 3, a 128 bit The value of the obtained value is a fixed point number, where the first 8 bit120 after the integer bit For decimal places, the multiplier 3 is connected to the second register 4, the second register 4 is used to store the pre-stored value (the value stored before the operation starts) or the value output by the multiplier 3 after the operation (i.e., the intermediate value). The first register 2 and the second register 4 are used to split the combinational logic to realize two-stage pipeline operation, and at the same time, two groups of number operations can be performed alternately. The second register 4 is connected to the output module 5 and the loop module 6. The output module 5 and the loop module 6 can be used to perform a modulo operation on 1. Specifically, the value in the second register 4 can be divided into two paths. One path is truncated with the integer bit through the output module 5 and takes 64 bit The decimal is used as the output, that is, the output module 5 takes the [119:56] bits of the second register 4 [127:0] as the output, and the other way clears the integer through the loop module 6, intercepting 4 bit Integer and 60 bit The decimals constitute a fixed-point number as the next round of input, that is, the loop module 6 takes the second register 4 [127:0] [119:60] as the 60-bit decimal, and the high bit is spliced with 4 bits of zero to form the next round of input. bit For integer digits, the last 60 bit The decimal place is input back to the adder 1 in the corresponding operation circuit to perform a new round of cyclic operation.

[0037] When the present invention is used, a pre-stored value is first stored in the first register 2 and the second register 4. Specifically, the first register 2 stores 64 bit The pre-stored value is input to the multiplier 3 and multiplied by the corresponding coefficient, and the multiplied value is sent to the input port of the second register 4. The second register 4 also stores 128 bit The pre-stored value is divided into two paths. One path passes through output module 5 to truncate the integer bit and take the 64-bit decimal as output. The other path passes through loop module 6 to clear the integer, and then truncates the 4-bit integer and 60-bit decimal to form the next round of input. The next round of input is divided into two paths and enters adder 1 in the specific operation circuit to sum with the other inputs. The resulting value is sent to the input port of the first register 2. When the clock rises, the first register 2 and the second register 4 simultaneously latch the data at their input ports, completing the first operation. As the clock rises, the first register 2 and the second register 4 automatically latch the values at the input ports without reloading the pre-stored values. The circuit repeats the above steps to perform two sets of number operations alternately.

[0038] The present invention also provides a n dimensional discrete hyperchaotic pseudorandom number generation method, using the above n The method comprises the following steps:

[0039] Enter multiple 64 bit Initial value of kn m , specifically, the initial value kn m 64 bit Fixed-point number, where the high 4 bit Indicates the integer part, low 60 bit Indicates the decimal part and brings the initial value into n The intermediate value is calculated in the dimensional chaos model, and then the modulus operation is performed on the intermediate value to obtain the calculated value. kn m+1 , calculated value kn m+1 64 bit Numerical value, n The dimensional chaos model is as follows:

[0040]

[0041] In the formula a n is the coefficient, and a n is a positive number, specifically a 1 、 a 2 and a 3 are also coefficients. In order to prevent negative numbers from appearing in the modulo operation results, in addition, during the calculation process, n The modulo operation of 1 is also performed in the dimensional chaos model, and the modulo operation of 1 can be directly expressed as truncating the integer bits of the fixed-point number. Specifically, the modulo operation is to truncate the integer bits of the intermediate value and take 64 bit Decimal gets calculated value kn m+1 Output, clear the integer of the intermediate value, and then intercept 4 bit Integer and 60 bit The decimal is brought back into the n-dimensional chaos model for iterative calculation. The structural diagram of the model is as follows: Figure 2 As shown, the equations constructed by the model are very simple, the calculation steps are few, and the algorithm is easy to implement. The model algorithm is implemented in FPGA. In order to improve the sequence complexity and suppress chaotic degradation, the overall operation of the present invention in the FPGA circuit adopts 64 bit Fixed-point design, i.e. high 4 bit Indicates the integer part, low 60 bit The algorithm adopts a two-stage pipeline design to improve the accuracy while suppressing the chaotic degradation, and also improves the output bandwidth and throughput, and makes the output sequence obtain better chaotic characteristics, which provides a guarantee for further applications (such as encryption, etc.). nIn the dimensional chaos model, the initial value is first kn m Add and then add the coefficient a n Multiplication, that is, for the operation within the modulo brackets, the coefficients are taken out, the addition within the brackets is calculated first, and then the multiplication is calculated, which reduces the more time-consuming multiplication steps:

[0042]

[0043] In the formula a is the coefficient ， That is, adder 1 can be used to add two 64 bit Initial value of kn m Add.

[0044] The following is an example of a three-dimensional discrete hyperchaotic pseudo-random number generator with three operation circuits, and then the three-dimensional chaotic model (such as Figure 3 Specifically, the three-dimensional chaos model is as follows (as shown in Figure 4 shown):

[0045]

[0046] in, k 1. k 2. k 3 represents the output of three dimensions, a 1. a 2 and a 3 are constant coefficients, let the coefficients a 1. a 2 and a 3 are 14.2, 15.1, 15.7 respectively, the initial values k 1 m 、 k 2 m and k 3 m are 0.2, 0.1, and 0.7 respectively (in this embodiment, the first register 2 and the second register 4 input the same set of initial values), and a pre-stored value is stored in the first register 2 of each operation circuit, that is, the pre-stored values are k1 m +k2 m 、k2 m +k3 m and k1 m +k3 m (i.e. k1 m +k2 m The value of k2 is 0.3, m +k3 m The value of k1 is 0.8, m +k3 mThe value is 0.9), a pre-stored value is stored in the second register 4 of each operation circuit, that is, the pre-stored values are (k1 m +k2 m )* a 1.(k2 m +k3 m )* a 2 and (k1 m +k3 m ) * a 3 (i.e. (k1 m +k2 m )* a The value of 1 is 4.26, (k2 m +k3 m )* a The value of 2 is 12.08, (k1 m +k3 m ) * a 3 is 14.13), and then the operation is performed. Specifically, the 128 in the second register 4 bit The pre-stored value is divided into two paths after the loop module 6, k1 m+1 and k2 m+1 The sum is performed by adder 1 of the first operation circuit, k2 m+1 and k3 m+1 The sum is performed by adder 1 of the second operation circuit, and k1 m+1 and k3 m+1 The sum is performed through adder 1 of the third operation circuit to obtain k1 m+1 +k2 m+1 、k2 m+1 +k3 m+1 and k1 m+1 +k3 m+1 , the value obtained after the summation is completed is input into the first register 2. At the same time, the pre-stored value in the first register 2 is directly input into the multiplier 3 and multiplied with the corresponding coefficient, and the intermediate value obtained after the multiplication is transmitted to the second register 4. At the same time, the pre-stored value in the second register 4 is divided into two paths, and a modulo 1 operation is performed. One path truncates the integer bit through the output module 5 and takes the 64-bit decimal as the output, and the other path clears the integer through the loop module 6, and then truncates the 4-bit integer and the 60-bit decimal to form the next round of input. When 50,000 data points are calculated, the 2D and 3D phase diagrams are shown in Figures 5-8. It can be seen from the phase diagram that the distribution is very uniform. In addition, let one of the coefficients change from 0 to 50 to obtain the Lyapunov exponent (such as Figure 9-11As shown in Figure 2), it can be seen that as the coefficient increases from 0, the system quickly enters the hyperchaotic state and takes a larger Lyapunov exponent. In addition, by changing a3 from 0 to 1, the sample entropy graph and the permutation entropy graph are obtained, which are compared with the sample entropy and permutation entropy of other chaotic models. Figure 12 , Figure 13 It can be seen that the chaos model algorithm (NDSHS) proposed in the present invention is far superior to the existing algorithm, and if the pseudo-random number generator proposed in this embodiment is input with two sets of different initial values for calculation at the same time, better chaos performance can be obtained.

[0047] The three-dimensional chaos model of the present invention is implemented in FPGA. The main resource occupancy rates in FPGA are shown in Table 1. The FPGA model selected is Xilinx Kintex-7 xc7k325tffg900-2:

[0048] Table 1

[0049]

[0050] It can be seen from Table 1 that the consumption of FPGA resources is extremely low.

[0051] The power consumption of the invention is 267mw and the efficiency is 10pJ / b, which is extremely low compared with the random number generators available on the market.

[0052] And the timing analysis shows that the generator operates at a maximum frequency of 136Mhz and a rate of about 24Gbps (since the rate increases linearly with the increase of the dimension, n The circuit speed is approximately n *8 Gbps ), which can meet most daily needs, such as image and video encryption. Taking high-bandwidth video as an example (after H.264 encoding): video (4K60P) 20-50Mbps, video (8K60P) 80-200Mbps, it can also meet the requirements of Gbps rates for enterprises or higher purposes. Whether it is low cost, low power consumption or high throughput, it far exceeds the limits of existing pseudo-random number algorithms. At the same time, the generated sequence complexity is high and can pass internationally renowned randomness standard tests such as NIST, TestU01 and Dieharder.

[0053] In addition to its performance advantages, the present invention also has significant cost advantages. Pseudo-random code generators with the same performance on the current market are usually priced at hundreds of thousands of RMB. For example, Agilent's 3.35 Gb / s pseudo-random code generator (81134A) costs about 500,000 RMB per unit, while the true random password module and true random password generator developed by Taiyuan University of Technology cost only about 50,000 RMB per unit. The pseudo-random numbers generated by the present invention rely solely on FPGA chips, costing less than 5,000 RMB, and using very little internal FPGA resources. Therefore, for a single FPGA chip, multiple channels can be used to output pseudo-random numbers, further improving throughput and reducing costs.

Claims

1. A n dimensional discrete hyperchaotic pseudorandom number generator, characterized by: The invention comprises a plurality of operation circuits, wherein the operation circuit comprises an adder, wherein the adder is used to add and sum two initial values inputted, the adder is connected to a first register, wherein the first register is used to store a pre-stored value or a value outputted by the adder, the first register is connected to a multiplier, wherein the multiplier is used to multiply the value outputted by the first register by a coefficient, the multiplier is connected to a second register, wherein the second register is used to store a pre-stored value or a value outputted by the multiplier, the second register is connected to an output module and a circulation module for outputting a random number, the second register can input a value into the output module and the circulation module, and the circulation module is used to input the output random number back to the adder in the corresponding operation circuit for circulation calculation.

2. A method according to claim 1 n dimensional discrete hyperchaotic pseudorandom number generator, characterized by: The adder is 64 bit Input to the unsigned adder.

3. A method according to claim 1 n dimensional discrete hyperchaotic pseudorandom number generator, characterized by: The multiplier is 64 bit Enter the unsigned multiplier.

4. A method according to claim 1 n dimensional discrete hyperchaotic pseudorandom number generator, characterized by: There are at least three operation circuits.

5. A n A method for generating discrete hyperchaotic pseudo-random numbers, comprising: n dimensional discrete hyperchaotic pseudorandom number generator, characterized by: The following steps are involved: (1) Enter multiple initial values kn m , and bring the initial value into n The intermediate value is calculated in the dimensional chaos model, and then the modulus operation is performed on the intermediate value to obtain the calculated value. kn m+1 , n The dimensional chaos model is as follows: In the formula a n is the coefficient, and a n Is a positive number.

6. A method according to claim 5 n The method for generating dimensional discrete hyperchaotic pseudorandom numbers is characterized by: The modulo operation is n 1 is performed in the dimensional chaos model, specifically by truncating the intermediate value to an integer and taking 64 bit Decimal gets calculated value kn m+1 Output, clear the integer of the intermediate value, and then intercept 4 bit Integer and 60 bit Bringing back the decimals n Iterative calculation is performed in a 3D chaos model.

7. A method according to claim 5 n The method for generating dimensional discrete hyperchaotic pseudorandom numbers is characterized by: The initial value in step (1) kn m 64 bit Fixed-point number, where the high 4 bit Indicates the integer part, low 60 bit Indicates the decimal part.

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