Instruction cache prefetching method and device and storage medium

Abstract

The embodiment of the invention provides an instruction cache prefetching method and device and a storage medium, and relates to the technical field of storage. The method comprises the following steps: sending a first instruction fetching request to a prefetching unit through an instruction fetching unit; the prefetching unit obtains a first instruction code from the instruction storage unit according to the first instruction fetching request, then sends the first instruction code to the instruction fetching unit and prefetches a second instruction code from the instruction storage unit in the next time period, and the instruction fetching unit sends the first instruction code to the execution unit to be executed; the second instruction code and the first instruction code are continuous instruction codes; and after the fetch unit sends the second fetch request to the prefetch unit, the prefetch unit sends the second instruction code to the fetch unit, and the fetch unit sends the second instruction code to the execution unit for execution. Through the method provided by the invention, the instruction fetch unit can obtain the instruction code in a shorter time period, so that the instruction fetch and execution operation efficiency is greatly improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to an instruction cache prefetching method, device and storage medium. Background Art

[0002] The instruction fetch unit is the module in the central processing unit responsible for fetching instructions. Its main function is to obtain instruction codes from the instruction memory. After fetching the instruction, the instruction fetch unit sends instruction information to the execution unit. The execution unit executes the instruction according to the instruction code information and submits and retires the instruction. In this way, an instruction is considered completed.

[0003] In the prior art, when the instruction fetch unit sends an instruction to the execution unit, it also calculates the instruction fetch address of the next instruction, sends it to the instruction memory to retrieve the instruction code of the next instruction, and then sends it to the execution unit for execution. That is, the next instruction also repeats the instruction fetch execution process of the previous instruction, so that the processor can process instructions continuously.

[0004] It takes a full clock cycle for the instruction fetch unit to read instructions from the instruction storage unit. However, due to the poor timing of obtaining data from the instruction storage unit, it takes two clocks from issuing the instruction fetch address to obtaining the instruction code, and the instruction fetch request can only be issued after obtaining the instruction code data. Therefore, it takes two clock cycles to obtain the instruction code. Then, even in the case of continuous instruction fetching, two clock cycles are required between two adjacent instruction fetch requests. Therefore, the instruction / cycle can only reach 1 / 2, which is less efficient.

[0005] At the same time, in the process of instruction fetching and execution of the pipeline, since the execution unit may be paused, the instruction fetch unit cannot issue a new instruction fetch request due to the pause of the execution unit. If the instruction fetch unit and the memory access unit share the bus, when data contention occurs in the access, the priority of instruction fetching is higher than that of data fetching. The data fetch request of the execution unit may be stopped and cause a pause because the instruction fetch unit cannot issue a request, thus causing deadlock, which seriously affects the normal operation of instruction fetching and execution. Summary of the invention

[0006] In order to solve one of the above-mentioned technical defects, an instruction cache prefetching method, device and storage medium are provided in an embodiment of the present application.

[0007] According to a first aspect of an embodiment of the present application, an instruction cache prefetching method is provided, the method comprising: Sending a first instruction fetch request to the prefetch unit through the instruction fetch unit; The prefetch unit obtains the first instruction code from the instruction storage unit according to the first instruction fetch request and sends it to the instruction fetch unit, and prefetches the second instruction code from the instruction storage unit in the next time cycle, and the instruction fetch unit sends the first instruction code to the execution unit for execution; the second instruction code and the first instruction code are consecutive instruction codes; After the instruction fetch unit sends the second instruction fetch request to the prefetch unit, the prefetch unit sends the second instruction code to the instruction fetch unit, and the instruction fetch unit sends the second instruction code to the execution unit for execution.

[0008] In an optional embodiment of the present application, the pre-fetch unit stores the acquired first instruction code and second instruction code into a cache, and the pre-fetch unit sends the first instruction code and the second instruction code to the instruction fetch unit through the cache.

[0009] In an optional embodiment of the present application, after the prefetch unit obtains the first instruction code from the instruction storage unit according to the first instruction fetch request, the prefetch unit sends the first instruction code to the instruction fetch unit and prefetches the second instruction code from the instruction storage unit, and the step of the instruction fetch unit sending the first instruction code to the execution unit for execution further includes: The pre-fetch unit obtains the second instruction code according to the instruction fetch width of the first instruction fetch request.

[0010] In an optional embodiment of the present application, after the instruction fetch unit sends the second instruction fetch request to the prefetch unit, the prefetch unit sends the second instruction code to the instruction fetch unit, and the instruction fetch unit sends the second instruction code to the execution unit for execution, the step further includes: The instruction fetch unit performs instruction fetch width alignment after receiving the second instruction code.

[0011] In an optional embodiment of the present application, the method further includes: The pre-fetch unit continuously fetches the second instruction code until a non-continuous instruction fetch request is received.

[0012] In an optional embodiment of the present application, the step of the prefetch unit continuously prefetching the second instruction code further includes: The second instruction code is continuously acquired at continuous time periods.

[0013] In an optional embodiment of the present application, the step of the prefetch unit continuously prefetching the second instruction code further includes: The non-consecutive instruction fetch request is reused as the first instruction fetch request.

[0014] In an optional embodiment of the present application, the first instruction fetch request is a jump instruction fetch request.

[0015] According to a second aspect of an embodiment of the present application, there is provided a computer device, including: a memory; A processor; and a computer program; wherein the computer program is stored in a memory and is configured to be executed by the processor to implement the steps of any method of the first aspect of the embodiment of the present application.

[0016] According to a third aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored; the computer program is executed by a processor to implement the steps of any method of the first aspect of an embodiment of the present application.

[0017] The instruction cache prefetching method provided in the embodiment of the present application has the following beneficial effects: Through the method of the present application, the prefetch unit will send the first instruction fetch request to the instruction storage unit when receiving the first instruction fetch request from the instruction fetch unit. In the next time cycle, the instruction fetch unit cannot issue the instruction fetch request for the next instruction, but the prefetch unit can still issue the next instruction fetch request without receiving the request from the instruction fetch unit. Based on this, the instruction fetch unit only needs one clock cycle to obtain the instruction code, which greatly improves the efficiency of instruction fetch and execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A flowchart of the instruction cache prefetching method provided in an embodiment of the present application; Figure 2 It is a structural diagram of an instruction acquisition system in the prior art; Figure 3 is a timing diagram without using the prefetch unit; Figure 4 A structural diagram of a pre-fetch unit provided in an embodiment of the present application; Figure 5 A timing diagram of using a pre-fetch unit provided in an embodiment of the present application; Figure 6 A structural diagram of an instruction cache prefetch system provided in an embodiment of the present application; Figure 7 A schematic diagram of the computer device structure provided for one embodiment of the present application.

[0019] Reference numerals: 10: instruction fetch module; 20: prefetch module; 30: instruction storage module; 40: execution module. DETAILED DESCRIPTION

[0020] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0021] The instruction fetch unit (IFU) is a module in the central processing unit (CPU) responsible for fetching instructions. Its main function is to fetch instruction codes from the instruction memory. After fetching the instruction, the instruction fetch unit sends instruction information to the execution unit (EXU). The execution unit executes the instruction according to the instruction code information, and commits and retires the instruction. In this way, an instruction is considered completed. While sending instructions to the execution unit EXU, the instruction fetch unit IFU will also calculate the instruction fetch address of the next instruction, send it to the instruction memory to retrieve the instruction code of the next instruction, and then send it to the execution unit for execution. That is, the next instruction also repeats the instruction fetch execution process of the previous instruction, so that the processor can continuously process instructions.

[0022] The inventors of the present application discovered that it takes a full clock cycle for the instruction fetch unit to read instructions from the static random access memory (SRAM) of the instruction storage unit. However, in reality, due to the poor timing of obtaining data from the SRAM, a trigger must be used to store data for one beat before it can be used. Therefore, it takes two clocks for the instruction fetch to go from issuing the instruction fetch address to obtaining the instruction code. The instruction fetch unit needs to obtain the instruction code of the current instruction before it can give the instruction fetch address of the next instruction based on the current instruction information. Therefore, the instruction fetch request can only be issued after obtaining the instruction code data. It takes two clock cycles for the instruction fetch to obtain the instruction code. Even in the case of continuous instruction fetching, two clock cycles are required between two adjacent instruction fetch requests. Therefore, the number of instructions executed in each clock cycle, i.e., instruction / cycle (Instruction Per Clock, IPC), can only reach 1 / 2, and the ideal performance close to IPC=1 cannot be achieved.

[0023] At the same time, in the process of instruction fetching and execution of the pipeline, since the execution unit may be paused, the instruction fetch unit cannot issue a new instruction fetch request due to the pause of the execution unit. If the instruction fetch unit and the execution unit share a bus, because the instruction fetch pipeline is earlier, when data contention occurs in the access, the priority of instruction fetching is higher than that of data fetching. The data fetch request of the execution unit may be stopped and cause a pause because the instruction fetch unit cannot issue a request. This pause is exactly the reason why the instruction fetch unit cannot issue a request, so a deadlock will occur.

[0024] Based on this, see Figure 1 : Example 1

[0025] The instruction cache prefetching method provided in this embodiment includes: S1, sending a first instruction fetch request to a prefetch unit through an instruction fetch unit; S2, after the pre-fetch unit obtains the first instruction code from the instruction storage unit according to the first instruction fetch request, it sends it to the instruction fetch unit, and pre-fetches the second instruction code from the instruction storage unit in the next time period, and the instruction fetch unit sends the first instruction code to the execution unit for execution; the second instruction code and the first instruction code are consecutive instruction codes; S3. After the instruction fetch unit sends the second instruction fetch request to the prefetch unit, the prefetch unit sends the second instruction code to the instruction fetch unit, and the instruction fetch unit sends the second instruction code to the execution unit for execution.

[0026] In the embodiment of the present application, the prefetch unit is a structure between the instruction fetch unit and the instruction storage unit, which is used to receive the instruction fetch request of the instruction fetch unit, obtain the instruction code from the instruction storage unit and forward it to the instruction fetch unit.

[0027] In a specific implementation, the instruction fetch unit sends a first instruction fetch request to the prefetch unit. After receiving the first request from the instruction fetch unit, the prefetch unit sends the request to the instruction storage unit, and issues a prefetch sequential instruction fetch request in the next cycle. The instruction code returned by the instruction storage unit is cached in the cache module of the prefetch unit. When the instruction fetch unit sends the next request, the cache module directly sends the instruction code to the instruction fetch unit. As long as the cache module is not full, the prefetch unit can continuously send continuous instruction fetch requests, and the instruction fetch unit can continuously obtain the instruction code for sequential instruction fetch. That is, in this embodiment, data needs to pass through the prefetch unit before it is obtained from the instruction storage unit.

[0028] Specifically, when the prefetch unit receives the first instruction fetch request (i.e., the first instruction fetch request) from the instruction fetch unit, it sends a corresponding instruction fetch request to the instruction storage unit. In the next time cycle, the instruction fetch unit cannot issue an instruction fetch request for the next instruction because it has not received the fetched instruction code. The prefetch unit still issues the next instruction fetch request without receiving the request from the instruction fetch unit. After two cycles, the instruction fetch unit obtains the first instruction code from the prefetch unit and issues a second instruction fetch request accordingly. The instruction prefetch unit has obtained the second instruction code in the previous time cycle, i.e., the instruction fetch unit can directly obtain the second instruction code from the prefetch unit, i.e., the instruction fetch unit only needs one clock cycle to obtain the second instruction code.

[0029] See also Figure 2 , Figure 3 The storage structure and its corresponding timing diagram in the prior art shown in the prior art, in the case of no pre-fetch unit, the instruction fetch unit sends a data acquisition request when the zeroth clock cycle (Clock, CLK) is 0, and the program counter value at this time is assumed to be equal to a, then the instruction storage unit receives the data required during the period when the corresponding instruction counter (Program Counter, PC) value = a in the second cycle, and in the same cycle, the instruction fetch unit calculates the address of the second instruction fetch based on the obtained instruction code and sends the second instruction request, taking the PC value plus 4 as an example, at this time PC = a + 4. That is, at this time, the IPC can only reach 1 / 2, and it is impossible to achieve the ideal performance close to IPC = 1.

[0030] In this embodiment, if Figure 4 , Figure 5 As shown in the figure, when there is a prefetch unit, the prefetch unit will send an instruction fetch request with PC=a to the instruction storage unit when it receives the first instruction fetch request from the instruction fetch unit (CLK=0). When CLK=1, the instruction fetch unit cannot issue an instruction fetch request for the next instruction because it has not received the fetched instruction code. However, the prefetch unit can still issue the next instruction fetch request (PC=a+4) without receiving the request from the instruction fetch unit. After two cycles when CLK=2, the instruction fetch unit obtains the instruction code with PC=a from the prefetch unit and issues an instruction fetch request with PC=a+4, while the instruction prefetch unit has issued an instruction fetch request with PC=a+4 when CLK=1. When CLK=3, the instruction fetch unit can obtain the instruction code with PC=a+4 from the prefetch unit. Therefore, the instruction fetch unit only needs one clock cycle to obtain the instruction code. Example 2

[0031] On the basis of the above-mentioned embodiment, the pre-fetch unit in this embodiment stores the acquired first instruction code and second instruction code into a cache, and the pre-fetch unit sends the first instruction code and the second instruction code to the instruction fetch unit through the cache.

[0032] Specifically, there is a cache module in the pre-fetch unit, the pre-fetch unit stores the acquired first instruction code and second instruction code in the cache module, and the pre-fetch unit sends the first instruction code and the second instruction code to the instruction fetch unit through the cache module.

[0033] Based on this, the instruction prefetch unit, when configured with a prefetch cache, can issue the next continuous instruction fetch request as long as it receives a new instruction code. Therefore, the cache of the instruction prefetch unit can always receive instruction codes from the instruction storage unit without worrying about whether the instruction fetch unit is ready to receive new instruction codes, and there is no need to worry about the pause of the instruction execution unit. Therefore, the instruction fetch request is decoupled from the instruction fetch unit and the execution unit, and there is no need to worry about the deadlock problem of instruction fetching and data fetching on the bus. Example 3

[0034] On the basis of the above-mentioned embodiment, the prefetch unit in this embodiment prefetches the second instruction code with the instruction fetch width of the first instruction fetch request.

[0035] In a specific implementation, when the pre-fetch unit pre-fetches the second instruction code from the instruction storage unit, since the instruction fetch unit does not issue a clear second instruction fetch request, it is easy for the pre-fetch unit to pre-fetch the second instruction code from the instruction storage unit. Based on this, in this embodiment, the second instruction code is pre-fetched with the instruction fetch width of the first instruction fetch request, which can overcome the technical problem of inaccurate instruction fetching and pre-fetch the second instruction code with a relatively accurate instruction fetch address. Specifically, the instruction fetch width is fixed. This embodiment takes 32 bits as an example. The retrieved 32-bit instruction code is not the instruction code that is actually executed in the end, because the instruction code has two types, 32 and 16 bits. The low-order information position of the current instruction is determined according to the previous instruction, and it can be obtained whether the instruction is 32 or 16 bits, and then it is cut. The unused excess instruction code will be temporarily stored and spliced ​​with the 32-bit instruction code sent back later.

[0036] Specifically, when the instruction fetch width of the first instruction fetch request is 32 bits, the second instruction code is pre-fetched with 32 bits. Example 4

[0037] On the basis of the above-mentioned embodiment, the instruction fetch unit in this embodiment performs instruction fetch width alignment after receiving the second instruction code.

[0038] In a specific implementation, although the second instruction code can be pre-fetched with a relatively accurate instruction fetch address, there is a certain discrepancy with the actual instruction fetch width. To overcome this technical problem, in this embodiment, after pre-fetching the second instruction code with the instruction fetch width of the first instruction fetch request, the instruction fetch unit receives the second instruction code and then performs instruction fetch width alignment.

[0039] Specifically, when the instruction fetch width of the first instruction fetch request is 32 bits, the second instruction code is pre-fetched with 32 bits; at this time, if the actual instruction fetch width of the second instruction fetch request is inconsistent with it (taking 16 bits as an example in this embodiment), only 16 bits of instruction data are sent for execution, and the remaining 16 bits of instruction data are stored, and so on. Based on this, the above technical problems can be overcome, more accurate instruction fetch width matching can be achieved, the fluency of instruction fetch and execution operation can be improved, and instruction fetch obstacles caused by mismatch of instruction fetch width can be avoided. Example 5

[0040] On the basis of the above-mentioned embodiment, the prefetch unit in this embodiment prefetches the second instruction code continuously until a non-continuous instruction fetch request is received.

[0041] In a specific implementation, the non-continuous instruction fetch request includes but is not limited to a jump instruction fetch request, a debug instruction fetch request, and an exception instruction fetch request.

[0042] Specifically, there is a control module in the prefetch unit, which determines whether the instruction to be fetched is a non-continuous instruction fetch through part of the decoded data obtained from the instruction fetch unit, and enables the prefetch unit to only receive non-continuous instruction fetch requests from the instruction fetch unit.

[0043] In a specific implementation, when the prefetch unit cache is not full, the prefetch unit will continuously issue continuous instruction fetch requests, even if the upstream instruction fetch unit is not yet ready to issue the next sequential instruction fetch, which is not conducive to further optimizing efficiency. Based on this, in this embodiment, the prefetch unit uses part of the decoding data obtained from the instruction fetch unit to determine whether the instruction to be fetched is a non-continuous instruction fetch, so that the prefetch unit only receives non-continuous instruction fetch requests from the instruction fetch unit, which can further improve the instruction fetch operation efficiency.

[0044] In a specific implementation, based on the continuous acquisition of the second instruction code in this embodiment, subsequent continuous instruction fetches can retrieve instructions in a shorter cycle. Based on this, in this embodiment, except for the first two cycles where no data is received, other clock cycles can obtain a corresponding data in a continuous shorter time period, further improving the IPC. The more continuous instructions there are, the closer the IPC is to 1.

[0045] In this embodiment, when performing continuous instruction fetching, if a non-continuous instruction fetching request is received, the instruction fetching is no longer performed continuously. Based on this, the problem of large deviation in obtaining the second instruction code can be overcome, and operation confusion caused by large deviation can be avoided. Example 6

[0046] Based on the above-mentioned embodiment, in this embodiment, the second instruction code is pre-fetched continuously in a continuous time period.

[0047] In the specific implementation, further Figure 5 As shown, in this embodiment, the second instruction code is continuously acquired in a continuous time cycle, that is, the second instruction code is acquired once in each subsequent time cycle, that is, the instruction fetch unit can obtain the instruction code of PC=a+4 from the pre-fetch unit when CLK=3, so the instruction fetch unit only needs one clock cycle to obtain the instruction code, and in this embodiment, the subsequent continuous instruction fetches can retrieve the instruction in one cycle. Based on this, in this embodiment, except that no data is received in the first two cycles, the other clock cycles can obtain a corresponding data in each clock cycle. Then, if there are 100 consecutive instructions, IPC is equal to 98 / 100, and so on. When there are 1000 consecutive instructions, IPC is equal to 998 / 1000. Therefore, based on this embodiment, the more consecutive instructions there are, the closer the IPC is to 1. Example 7

[0048] On the basis of the above-mentioned embodiment, in this embodiment, the non-continuous instruction fetch request is re-used as the first instruction fetch request.

[0049] In a specific implementation, when continuous instruction fetching is performed, if a non-continuous instruction fetch request is received, instruction fetching will no longer be performed continuously, and in this embodiment, the non-continuous instruction fetch request will be re-used as the first instruction fetch request to fetch the instruction. This can overcome the problem of large deviations in the acquisition of the second instruction code while taking instruction prefetching into account, and as long as continuous instruction fetching can be continued subsequently, its IPC is greater than 1 / 2 of the prior art, and it still has a relatively high efficiency. Example 8

[0050] On the basis of the above-mentioned embodiment, in this embodiment, the first instruction fetch request is a non-continuous instruction fetch request.

[0051] Jump instruction, also known as jump instruction, is a type of instruction that changes the execution order of the program. It unconditionally jumps to the specified location and starts executing the instructions at the new location.

[0052] In this embodiment, when performing a jump instruction fetch, if a jump instruction fetch request is received, the instruction fetch is no longer continued. Based on this, the problem of a large deviation in the acquisition of the second instruction code can be overcome, and operation confusion due to a large deviation can be avoided.

[0053] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0054] See also Figure 6 One embodiment of the present application provides an instruction cache prefetch system based on the above-mentioned embodiments 1-8, including: Instruction fetch module 10 , execution module 40 , pre-fetch module 20 and instruction storage module 30 ; the instruction fetch module 10 is connected to the execution module 40 and the pre-fetch module 20 respectively; the instruction storage module 30 is connected to the pre-fetch module 20 .

[0055] In this embodiment, the instruction fetch module 10 and the prefetch module 20 are configured as follows: The instruction fetch module 10 sends a first instruction fetch request to the prefetch module 20. After the prefetch module 20 obtains the first instruction code from the instruction storage module 30 according to the first instruction fetch request, it sends it to the instruction fetch module 10 and prefetches the second instruction code from the instruction storage module 30. After the instruction fetch module 10 sends a second instruction fetch request to the prefetch module 20, the prefetch module 20 sends the second instruction code to the instruction fetch module 10. That is, in this embodiment, data needs to pass through the prefetch module 20 before being obtained from the instruction storage module 30.

[0056] In this embodiment, the execution module 40 is configured to: Receive and execute the first instruction code and the second instruction code sent by the instruction fetch module 10.

[0057] Each module in the above instruction cache prefetch system can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each of the above units.

[0058] For the specific limitations of the above-mentioned instruction cache prefetch system, please refer to the limitations of the instruction cache prefetch method in the above text, which will not be repeated here.

[0059] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0060] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 7 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an instruction cache prefetch method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the above video signal processing method is implemented.

[0061] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above instruction cache prefetching method can be implemented.

[0062] Those skilled in the art will appreciate that the embodiments of the present application may be provided as systems, methods, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program codes. The scheme in the embodiments of the present application may be implemented in various computer languages, for example, C language, VHDL language, Verilog language, object-oriented programming language Java, and literal scripting language JavaScript, etc.

[0063] The present application is described with reference to the flowcharts and / or block diagrams of the systems, methods, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0064] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0065] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0066] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0067] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0068] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An instruction cache prefetching method, characterized in that: include: Sending a first instruction fetch request to the prefetch unit through the instruction fetch unit; After the pre-fetch unit obtains the first instruction code from the instruction storage unit according to the first instruction fetch request, it sends the first instruction code to the instruction fetch unit, and pre-fetches the second instruction code from the instruction storage unit in the next time period, and the instruction fetch unit sends the first instruction code to the execution unit for execution; the second instruction code and the first instruction code are consecutive instruction codes; After the instruction fetch unit sends the second instruction fetch request to the prefetch unit, the prefetch unit sends the second instruction code to the instruction fetch unit, and the instruction fetch unit sends the second instruction code to the execution unit for execution.

2. The instruction cache prefetching method according to claim 1, characterized in that: The pre-fetch unit stores the acquired first instruction code and the second instruction code into a cache, and the pre-fetch unit sends the first instruction code and the second instruction code to the instruction fetch unit through the cache.

3. The instruction cache prefetching method according to claim 2, characterized in that: After the prefetch unit obtains the first instruction code from the instruction storage unit according to the first instruction fetch request, the prefetch unit sends the first instruction code to the instruction fetch unit and prefetches the second instruction code from the instruction storage unit, and the step of the instruction fetch unit sending the first instruction code to the execution unit for execution also includes: The prefetch unit prefetches the second instruction code with the instruction fetch width of the first instruction fetch request.

4. The instruction cache prefetching method according to claim 3, characterized in that: After the instruction fetch unit sends the second instruction fetch request to the prefetch unit, the prefetch unit sends the second instruction code to the instruction fetch unit, and the instruction fetch unit sends the second instruction code to the execution unit for execution, the step further includes: The instruction fetch unit performs instruction fetch width alignment after receiving the second instruction code.

5. The instruction cache prefetching method according to claim 4, characterized in that: The method further comprises: The prefetch unit prefetches the second instruction code continuously until receiving the non-continuous instruction fetch request.

6. The instruction cache prefetching method according to claim 5, characterized in that: The step of the prefetch unit continuously prefetching the second instruction code further comprises: The second instruction code is pre-fetched continuously at continuous time periods.

7. The instruction cache prefetching method according to claim 5, characterized in that: The step of the prefetch unit continuously prefetching the second instruction code further comprises: The non-continuous instruction fetch request is reused as the first instruction fetch request.

8. The instruction cache prefetching method according to any one of claims 1 to 7, characterized in that: The first instruction fetch request is a jump instruction fetch request.

9. A computer device, characterized in that: include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and is configured to be executed by the processor to implement the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon; the computer program is executed by a processor to implement the method according to any one of claims 1 to 8.

Images