Apparatus and method for direct refresh management attack recognition

Abstract

The invention relates to a device and method for direct refresh management attack recognition. Memory device direct refresh management DRFM aggression recognition. The DRFM logic circuit receives the DRFM aggressor address and compares it to a previous DRFM aggressor address. And if not, performing a DRFM operation. If matched, the DRFM operation may be skipped. This may prevent repeated DRFM operations from being performed on the same DRFM aggressor address.

Description

Technical Field

[0001] The present disclosure relates to an apparatus and method for direct refresh management attack identification. Background Art

[0002] Information may be stored on memory cells of a memory device. Memory cells may be organized at the intersection of word lines (rows) and bit lines (columns). Information in a memory cell may decay over time. For example, information may be stored as a charge on a capacitor, which may decay over time. A memory device may perform a refresh operation to restore information and prevent information loss.

[0003] Certain access patterns can cause an increased rate of information decay in nearby memory cells (e.g., memory cells along nearby word lines). The memory can use various schemes to identify which memory cells are affected by such patterns so that a targeted refresh operation can be performed before those memory cells lose their information. The controller of the memory can also monitor the access pattern and instruct the memory to refresh certain word lines. However, this process itself can be used to generate a pattern that causes information decay. The memory may be required to monitor a refresh address provided by the controller. Summary of the invention

[0004] In one aspect, the present disclosure provides an apparatus comprising: a direct refresh management (DRFM) logic circuit configured to latch a row address as a DRFM aggressor address in response to receiving a sample command, wherein the DRFM logic circuit is configured to provide a valid skip signal if the DRFM aggressor address matches a previous DRFM aggressor address; and a refresh state control circuit configured to perform a DRFM operation by performing a target refresh operation based on the DRFM aggressor address in response to a DRFM refresh command when the skip signal is invalid, or to skip performing the DRFM operation if the skip signal is valid.

[0005] On the other hand, the present disclosure provides an apparatus comprising: a first latch circuit configured to store a row address as a direct refresh management (DRFM) aggressor address in response to a sampling signal; a second latch circuit configured to store a previous DRFM aggressor address; a comparator circuit configured to provide a match signal if the DRFM aggressor address matches the previous DRFM aggressor address; and a DRFM control circuit configured to provide a DRFM skip signal based in part on the match signal, wherein a DRFM operation is skipped based in part on the DRFM skip signal.

[0006] In yet another aspect, the present disclosure provides a method comprising: receiving a direct refresh management (DRFM) aggressor address as part of a DRFM operation; comparing the DRFM aggressor address to a previous DRFM aggressor address; and skipping the DRFM operation if the DRFM address matches the previous DRFM address. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 is a block diagram of a portion of a memory according to some embodiments of the present disclosure.

[0009] Figure 3 is a block diagram of a DRFM logic circuit according to some embodiments of the present disclosure.

[0010] Figure 4 is a table of example patterns for DRFM addresses according to some embodiments of the present disclosure.

[0011] Figure 5 is a timing diagram of an example operation of a refresh control circuit according to some embodiments of the present disclosure.

[0012] Figure 6 is a schematic diagram of a DRFM logic circuit with two comparators according to some embodiments of the present disclosure.

[0013] Figure 7 is a flowchart of a method of determining whether to skip a DRFM operation according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The description of certain embodiments below is merely exemplary in nature and is by no means intended to limit the scope of the present disclosure or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof, and the accompanying drawings are shown by way of illustrative specific embodiments in which the described system and method can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the purpose of clarity, the detailed description of certain features will not be discussed when it is obvious to those skilled in the art, so as not to obscure the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0015] Information in a memory array may be accessed through one or more access operations, such as read or write operations. During an example access operation, a word line may be activated based on a row address, and then selected memory cells along the active word line may have their information read or written based on which bit lines are accessed, which may be based on a column address. The memory array may be refreshed row by row (e.g., as part of an auto-refresh and / or self-refresh mode), where the memory cells along each row are periodically refreshed. The speed at which a row is refreshed (e.g., the maximum time any given row experiences between refreshes) may be determined based on an expected rate of information decay.

[0016] Various access patterns to rows (aggressor rows) can result in increased information decay rates in nearby memory cells (e.g., along victim rows). For example, "row hammering" can involve repeated accesses to an aggressor row, which can increase decay rates in adjacent rows (and / or rows further away). Therefore, it may be important to track the number of accesses to each row to determine if it is an aggressor, so that victim rows can be identified and refreshed as part of a targeted refresh operation. For example, each word line may have an associated count value that is used to determine how many times the word line has been accessed. Based on those access counts, rows for a targeted refresh operation may be identified and stored in a target refresh queue or an aggressor queue.

[0017] The memory may determine when to perform a targeted refresh operation based on internal logic. In addition to the internal logic, (or alternatively) the controller may issue a refresh management (RFM) command. In response to the RFM command, the memory may perform one or more targeted refresh operations based on the addresses in the target refresh queue. The controller may also monitor access operations and provide direct RFM (DRFM) commands, where the controller specifies an aggressor address and instructs the memory to perform a targeted refresh on the victim of the aggressor. However, it may happen that if many DRFM commands are executed on the same aggressor, then repeated refreshes of the same victim word lines may in turn cause those victim word lines to become aggressors again, resulting in an increased rate of information decay in word lines outside the victim range refreshed by the address specified by the DRFM command. Since this may result in loss of information, it may be important to track the address specified by the DRFM command in order to prevent repeated refreshes of the address.

[0018] The present disclosure relates to apparatus, systems and methods for direct refresh management attack identification. A memory device receives a DRFM command and a DRFM aggressor address. The DRFM logic circuit compares the DRFM aggressor address with a stored previous DRFM aggressor address. If there is no match, a target refresh operation is performed on the victim of the DRFM aggressor address, and the DRFM aggressor address is stored as the previous DRFM aggressor address. If there is a match, the DRFM operation can be skipped.

[0019] In some embodiments, the DRFM logic circuit may skip N repeated DRFM commands in a row with the same DRFM aggressor address, and then allow M of those operations before again skipping N repeated addresses. For example, if a single DRFM address is constantly provided, the DRFM logic may perform one DRFM operation, skip 3, then perform one DRFM operation, skip 3, and so on. In some embodiments, the DRFM logic circuit may implement different skip logic for different victim address calculations. For example, the DRFM logic circuit may apply different values ​​of N and M for different victim address calculations. In an example implementation, if the same address is provided, refresh operations for victims that are closer to the DRFM aggressor (e.g., + / - 1 refresh) may occur more frequently than refresh operations for victims that are farther away (e.g., + / - 3 refreshes). In other words, the more distant victim addresses may be skipped more frequently.

[0020] In some embodiments, when a DRFM operation is skipped, the memory may instead perform some other actions. For example, in response to the DRFM operation starting to be skipped, the memory may perform a target refresh (eg, a normal RFM operation) on a victim of an address stored in a target refresh queue.

[0021] In some embodiments, the DRFM aggressor address may be captured from the row address bus in response to a DRFM sample command, and then the address may be refreshed in response to a DRFM refresh command. In some embodiments, the controller may issue these as separate commands. In some embodiments, the controller may issue a single command, and the memory may generate the sample and refresh commands. In response to the DRFM sample command, the current address along the row address bus is stored in a first register and compared to the previous DRFM address in a second register, the result of the comparison determining what occurs in response to the DRFM refresh command. Figure 1 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. Also shown is a controller 150 that can operate memory device 100. Controller 150 may represent a processor or other unit that stores and retrieves data from memory device 100. In some embodiments, controller 150 and memory 100 may be integrated into a single circuit or chip. In some embodiments, controller 150 and memory 100 may be separate components. Memory 100 and controller 150 are arranged along Figure 1 Multiple buses (such as a data bus, a clock bus, and a command / address bus) not shown are communicatively coupled.

[0022] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown as including a plurality of memory banks. Figure 1 In the embodiment of the present invention, the memory array 118 is shown to include eight memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL (rows), a plurality of bit lines BL (columns), and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL.

[0023] The selection of the word line WL is performed by the row decoder 108, and the selection of the bit line BL is performed by the column decoder 110. Figure 1 In the embodiment of the present invention, the row decoder 108 includes a corresponding row decoder for each memory bank, and the column decoder 110 includes a corresponding column decoder for each memory bank. The bit line BL is coupled to a corresponding sense amplifier (SAMP). The data read from the bit line BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 120 through the complementary local data line (LIOT / B), the transfer gate (TG) and the complementary main data line (MIOT / B). Conversely, the write data output from the read / write amplifier 120 is transmitted to the sense amplifier SAMP through the complementary main data line MIOT / B, the transfer gate TG and the complementary local data line LIOT / B, and is written into the memory cell MC coupled to the bit line BL.

[0024] The semiconductor device 100 may employ a plurality of external terminals, including a command and address terminal coupled to a command and address (C / A) bus to receive a command and address and a CS signal, a clock terminal for receiving clocks CK and / CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. One or more of the external terminals may be coupled to the controller 150.

[0025] The clock terminal is supplied with external clocks CK and / CK provided to the input circuit 112 by the controller 150. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 110 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of the circuit included in the input / output circuit 122, for example, to the data receiver to time the reception of the write data.

[0026] The C / A terminal may be supplied with a memory address by the controller 150. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies the decoded row address XADD to the row decoder 108, and supplies the decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded memory bank address BADD, which may indicate the memory bank of the memory array 118 containing the decoded row address XADD and the column address YADD. The C / A terminal may be supplied with a command. Command examples include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., a read command for performing a read operation and a write command for performing a write operation), and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and memory bank addresses BADD to indicate the memory cell(s) to be accessed.

[0027] The commands may be provided as internal command signals to a command decoder 106 via the command / address input circuit 102. The command decoder 106 includes circuitry for decoding the internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0028] The device 100 may receive an access command as a read command. In response to the read command, data is read out from the memory array 118 to the data terminal DQ. Data is read out from the memory cell in the memory body specified by BADD at the intersection of the word line specified by XADD and the bit line specified by YADD. The read command is received by the command decoder 106, which provides internal commands such as a row activation signal ACT and a read signal R. In response to ACT and the row address XADD, the row decoder 108 activates the specified word line, and in response to R and the column address YADD, the column decoder 110 couples the sense amplifier coupled to the specified bit line to the read / write amplifier 120 to read the values ​​along those bit lines from the memory cells at the intersection with the active word line as read data to the IO circuit 122. The read data is output to the outside from the data terminal DQ via the input / output circuit 122. The precharge command Pre precharges the word line and deactivates (or turns it off).

[0029] The device 100 may receive an access command as a write command. In response to the write command, data received along the DQ terminal is written to the memory array 118. The data is written to the memory cell in the memory bank specified by BADD at the intersection of the word line specified by XADD and the bit line specified by YADD. The read command is received by the command decoder 106, which provides an internal command such as ACT and a write signal W. The IO circuit 122 receives data from the DQ terminal, which is provided to the read / write amplifier 120. In response to ACT, the row decoder activates the word line specified by XADD, and in response to W, the column decoder 110 couples the write data from the read / write amplifier 120 to the bit line specified by YADD, where the sense amplifier amplifies the write data so that it is written to the memory cell at the intersection with the active word line. Precharge Pre turns off the word line.

[0030] The device 100 may also receive a command from the controller 150 to cause the device 100 to perform a refresh operation. For example, the memory controller 150 may place the device 100 in an auto-refresh mode and provide a refresh signal REF. The device 100 may also enter a self-refresh mode in which a refresh signal is generated internally. The controller 150 may also provide an RFM or DRFM command that causes the memory 100 to perform a target refresh operation, as described in more detail herein.

[0031] The refresh signal REF is supplied to the refresh address control circuit 116. The refresh address control circuit 116 supplies the refresh row address RXADD to the row decoder 108, which refreshes the memory cells along the word line WL identified by the refresh row address RXADD. The refresh control circuit 116 may perform a sequential or normal refresh operation, in which the refresh address RXADD is generated based on the sequential logic of the refresh control circuit 116, or may perform a targeted refresh operation, in which the refresh address RXADD is based on an identified aggressor address stored in the aggressor queue of the refresh control circuit 116.

[0032] During a sequential or normal refresh operation, the refresh control circuit 116 may use sequence logic to determine the next RXADD. For example, RXADD may be based on a previous value of RXADD (e.g., RXADD(i+1)=RXADD(i)+1). A counter circuit may be used to generate a sequential refresh address. During a target refresh operation, the refresh control circuit 116 may generate RXADD based on an identified aggressor address. For example, a refresh address may represent a word line that is physically adjacent to a word line associated with an aggressor address. In some embodiments, a sequential refresh address may be associated with more word lines than a target refresh address. During an internally directed target refresh operation or a target refresh operation performed based on an RFM command, the aggressor address is an address identified by the refresh control circuit 118. During a target refresh operation performed based on a DRFM command, the aggressor address is a DRFM aggressor address provided by the controller.

[0033] When the refresh control circuit 116 receives the refresh signal REF, it can perform a set of refresh operations and can determine whether those refresh operations are sequential or targeted refresh operations based on internal logic. For example, in response to REF, the refresh control circuit can perform a set of refresh operations and can perform one or more targeted refresh operations for every N sequential refresh operations. When the refresh control circuit 116 receives the RFM signal from the RFM timing circuit 132, it performs one or more targeted refresh operations.

[0034] The refresh control circuit 116 uses one or more criteria to identify the aggressor address. For example, the access pattern to different addresses can be used. Figure 1 In the example of , an aggressor detection scheme using per row access count or per row hammer tracking (PRHT) is shown. However, other schemes for detecting aggressor addresses may be used in other example embodiments instead of or in addition to PRHT.

[0035] As part of PRHT Figure 1 In an example of , each word line includes a plurality of counter memory cells 126 that store a count value XCount associated with the word line. The count value XCount may represent the number of times the word line has been accessed. When a row is accessed (e.g., by ACT and XADD), the count value XCount is read out and updated (e.g., by incrementing). If the updated count value has crossed a threshold, the row address XADD is determined to be an aggressor and is added to an aggressor queue. When an address is added to the queue, the count value in the counter memory cell 126 may be reset. If the count has not crossed a threshold, the updated count value is written back to the counter memory cell 126.

[0036] Controller 150 may also perform its own tracking of aggressor addresses. For example, controller 150 may include targeted refresh or row hammer refresh (RHR) logic 152 that monitors addresses provided to memory 100 and determines whether they are aggressor addresses. If the address is determined to be an aggressor, RHR logic 152 may issue a DRFM command to memory 100. The DRFM command may specify a DRFM aggressor address and instruct memory 100 to perform one or more targeted refresh operations based on the DRFM aggressor address. For example, controller 150 may provide a DRFM command when a DRFM aggressor address is provided along the C / A bus (e.g., as part of an access operation), and command decoder 106 may cause refresh control circuit 116 to sample (or latch) the DRFM aggressor address.

[0037] When the refresh control circuit 116 receives the DRFM aggressor address, it compares the DRFM aggressor address with the previous DRFM aggressor address. If there is no match, then the target refresh operation in response to the DRFM command can be performed on the DRFM aggressor address. If there is a match, then the target refresh operation on the DRFM aggressor address can be skipped. In this way, the refresh control circuit 116 can prevent multiple consecutive DRFM operations from being performed on the same DRFM aggressor address. In some embodiments, the refresh control circuit 116 can include a counter and can count the number of times the DRFM aggressor address matches the previous address. When the counter has a certain value or multiple values, the counter can allow all or part of the normal DRFM operation to continue. In an example embodiment, the counter can be incremented each time the address matches, and can count from 0 to 3 before resetting back to 0. When the counter is 0 or 1, the DRFM logic can skip the operation, but allows operation on 2 and 3. Other example embodiments can be used in other embodiments.

[0038] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminal. The internal potential VPP is mainly used in the row decoder 108, the internal potential VARY is mainly used in the sense amplifier SAMP included in the memory array 118, and the internal potential VPERI is used in many other peripheral circuit blocks.

[0039] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0040] Figure 2 is a block diagram of a portion of a memory according to some embodiments of the present disclosure. Figure 2 An example of a portion of memory associated with a refresh operation is shown. Figure 2 In some embodiments, the memory 200 may be implemented in some embodiments. Figure 1 A portion of the memory device 100.

[0041] Figure 2 The memory 200 of FIG. 1 shows a DRAM interface 240, which represents various components of the memory, which provide signals such as row address XADD, row activation signal ACT and refresh signal REF and RFM command RFM. Refresh control circuit 216 (e.g., Figure 1 In response to the signal REF or RFM, the refresh control circuit 216 provides a refresh address RXADD, and the row decoder 208 (eg, Figure 1 108) to the array 218 (eg, Figure 1 A refresh operation is performed on the memory cell 118).

[0042] The DRAM interface 240 also provides signals related to DRFM operations. The DRAM interface 240 provides a DRFM refresh signal DRFM and a DRFM sampling signal DRFM_Samp. In some embodiments, both signals may be provided in response to a DRFM command from a controller (e.g., by a command decoder). The DRFM logic circuit 260 receives the DRFM sampling command DRFM_Samp and stores the row address XADD as a DRFM aggressor address DRFMXADD. The DRFM logic circuit 260 determines whether a DRFM skip signal DRFM_Skip should be provided based on a comparison of the sampled address with a previously sampled address. In response to the DRFM refresh signal DRFM, the refresh control circuit 216 performs a target refresh based on DRFMXADD unless the signal DRFM_Skip is valid, in which case the operation is skipped (or a different type of target refresh operation is performed).

[0043] The refresh control circuit 216 includes a refresh state control circuit 242, which determines whether a target refresh operation or a sequential refresh operation will be performed by issuing an internal refresh signal IREF and / or a target refresh signal RHR. In response to the refresh signal IREF / RHR, the refresh address generator circuit 250 provides a refresh address RXADD. The refresh control circuit 216 also includes an aggressor detector circuit 217, which identifies an aggressor address and stores it in an aggressor queue 244. When the refresh state control circuit 242 signals a target refresh operation (e.g., by providing RHR), the refresh address generator circuit 250 generates the refresh address RXADD using one of the addresses in the aggressor queue 244. When the refresh state control circuit 242 indicates a DRFM operation, the refresh address generator 250 generates RXADD using the address DRFMXADD.

[0044] exist Figure 2 , dashed boxes are used to represent components that may be repeated on a bank-by-bank basis within the memory. For example, each bank may have its own row decoder 208, refresh control circuit 216, and memory array 218. In other example embodiments, other arrangements in which components are repeated on a bank-by-bank basis and shared by multiple banks may be used.

[0045] The refresh state control circuit 242 controls which refresh operations are performed and how many refresh operations are performed in response to the signal REF and / or RFM / DRFM. The refresh state control circuit 242 provides an internal refresh signal IREF and a target refresh signal RHR. The signal IREF can indicate a sequential refresh operation, and RHR can indicate a target refresh operation. In some embodiments, IREF alone can indicate a sequential or normal refresh operation, and IREF and RHR simultaneously effectively indicate a target refresh operation. In some embodiments, IREF and RHR can be effective alone to indicate different types of refresh operations.

[0046] In response to the refresh signal REF, the refresh state control circuit 242 may perform multiple refresh operations or pumps. For example, the number of activations of IREF. In response to REF, the refresh state control circuit 242 may perform a mixture of sequential refresh operations and target refresh operations based on internal logic. For example, a certain number N of sequential refresh operations (e.g., by providing IREF) may be performed together with a certain number M of target refresh operations (e.g., by providing RHR). For example, the refresh state control circuit 242 may perform four pumps, two of which are normal refresh operations and two of which are target refresh operations. In response to the signal RFM, the refresh state control circuit 242 performs multiple target refresh operations (e.g., two or four target refresh operations) by providing the signal RHR.

[0047] In response to a DRFM operation, as indicated by a DRFM refresh signal DRFM when a DRFM skip signal DRFM_Skip is inactive, the refresh state control circuit 242 performs one or more target refresh operations. The refresh state control circuit 242 may provide a signal such as DRFM to a refresh address generator (e.g., instead of or in addition to the signal RHR) to indicate that a refresh address RXADD should be generated based on the DRFM aggressor address DRFMXADD. In response to a skipped DRFM operation, as indicated by the signal DRFM and the signal DRFM_Skip being active, the refresh state control circuit 242 may skip the DRFM operation. In some embodiments, the refresh state control circuit 242 may perform other refresh operations, such as target refresh operations, during the time when a DRFM operation has been performed. For example, when DRFM_Skip is active, the refresh state control circuit 242 may provide IREF and / or RHR in response to the signal DRFM without providing DRFM.

[0048] The refresh address generator circuit 250 includes a sequential refresh address generator circuit 252 that provides a sequential refresh address as RXADD in response to IREF (or only in response to IREF). The sequential refresh address generator circuit 252 generates the refresh address based on sequence logic. For example, the refresh address may be generated based on an address provided as part of a previous sequential refresh operation.

[0049] The refresh address generator circuit 250 includes a target refresh address generator circuit 254 that provides a target refresh address as RXADD in response to RHR and an identified aggressor address HitXADD from the aggressor queue 244, or provides RXADD based on DRFMXADD in response to a signal DRFM (or DRFM and RHR together). Since the logic for generating the target refresh address can be similar except for the source of the aggressor address for the target refresh operation, the operation of the target refresh address generator circuit 254 will be described overall with respect to HitXADD, however, in the case of DRFM operation, DRFMXADD can be replaced.

[0050] The target refresh address generator circuit 254 generates a refresh address based on the aggressor address HitXADD. For example, the refresh address RXADD may represent a word line adjacent to the word line represented by HitXADD (e.g., RXADD=HitXADD+ / -1). In other example embodiments, other relationships between refresh addresses and aggressor addresses may be used (e.g., HitXADD+ / -2, + / -3, etc.). In some embodiments, multiple target refresh operations may be performed on a single aggressor address to capture multiple victims (e.g., refresh addresses may be generated for + / -1, + / -2, etc.).

[0051] Refresh control circuit 216 includes aggressor detector circuit 217 that determines whether the accessed address XADD should be added as an aggressor address HitXADD to aggressor queue 244. Various schemes may be used to determine whether an address should be added to a queue. Figure 2 The counter memory unit 226 (eg, Figure 1 126) in an example embodiment of the PRHT. Other aggressor tracking schemes may be used in other example embodiments.

[0052] When a row is accessed, its count value XCount is read out from the counter memory unit 226 to the aggressor detector 217. The counter circuit 246 updates the count value to an updated count value XCount'. In some embodiments, the counter circuit 246 can update the count value by incrementing XCount (e.g., XCount'=XCount+1). The aggressor detector circuit 217 includes a comparator circuit 248 that compares the updated count value XCount' with a threshold. If the count has not crossed the threshold (e.g., is less than the threshold), the updated count value is written back to the counter memory unit 226. If the count has crossed the threshold (e.g., is greater than or equal to the threshold), the aggressor detector circuit provides a signal AGG to indicate that the current row address is an aggressor. The updated count value is reset (e.g., reset to an initial value such as 0) and written back to the counter memory unit 226.

[0053] In some embodiments, the threshold value may represent the maximum value of the binary number of the count value. The count value may cross the threshold value by "rolling" from the maximum value to the minimum value. In such embodiments, comparator 248 may be omitted, and counter 246 may send signal AGG when the count rolls over.

[0054] In response to signal AGG, aggressor queue 244 adds the current row address XADD to the queue. Aggressor queue 244 may be a register comprising a plurality of slots, each slot storing a row address. Each slot comprises a plurality of latch circuits, such as content addressable memory (CAM) cells or other types of latches, which store the bits of the address stored in that slot. The number of slots in the queue may generally be referred to as the "depth" of aggressor queue 244.

[0055] In response to the signal RHR, the aggressor queue 244 provides the address to the target refresh address generator circuit 254 as the aggressor address HitXADD. After providing the address, the address is removed from the queue (or the slot is marked as empty so that it can be overwritten). The queue 244 can use various logics to determine which address to provide. For example, it can act as a FIFO queue. In some embodiments, if the queue 244 is full when the signal AGG is received, the refresh control circuit 216 can provide a signal to indicate an alarm. In some embodiments, the controller can issue an RFM command sequence to clear the queue in response to the queue full alarm. In response to the signal AGG, the aggressor queue 244 can search for an open slot (e.g., a slot that does not store an address or a slot where an address has been provided as HitxADD), and store the current address XADD in the open slot.

[0056] The DRFM logic circuit 260 determines whether the DRFM operation should be skipped based on a comparison between the current DRFM aggressor address and the previous DRFM aggressor address. In response to the DRFM sampling command DRFM_Samp, the DRFM logic 260 stores the address XADD in the latch 262 and compares it with the previous DRFM address. If there is a match, the signal DRFM_Skip is provided at an active level. If there is no match, the signal DRFM_Skip is not provided, and the address is stored as the previous address for the next comparison.

[0057] In some embodiments, the DRFM logic circuit 260 may include a counter circuit that counts the number of times DRM_Skip is provided. When the counter reaches a threshold, it is reset and the DRFM_Skip signal is not provided even if the sampled address and the previous address match. The counter may also be reset when the sampled address changes (e.g., when there is no match). In some embodiments, certain values ​​of the counter may cause the DRFM logic circuit 260 to skip a DRFM operation, while other values ​​may cause the DRFM logic circuit 260 to allow a DRFM operation.

[0058] In some embodiments, the DRFM logic circuit 260 may employ different logic (e.g., different counters) for different calculations of the refresh address. For example, if there is a mismatch, then the refresh address generator 250 may provide DRFMXADD+ / -1, + / -2, + / -3, and + / -4 as refresh addresses (e.g., 8 refresh addresses) as part of the DRFM operation. The DRFM logic circuit 260 may use different counter logic to skip some of those victim calculations compared to other victim calculations. In some embodiments, different logic may be applied to groups away from the aggressor. For example, all refreshes (+ / -1, + / -2, + / -3, + / -4) may be skipped at a first rate, + / -2, + / -3, and + / -4 may be skipped at a second rate, + / -3 and + / -4 may be skipped at a third rate, and + / -4 may be skipped at a fourth rate. Other groups of address calculations and rates may be used in other example embodiments. In an example implementation, a four-bit counter may be used and incremented each time an address matches. With values ​​of 0 and 1, all refreshes may be skipped. When the value is 2 and 3, + / -1 and + / -2 refreshes are performed, and + / -3 and + / -4 are skipped. When there is no match, all refreshes are performed.

[0059] Figure 3 is a block diagram of a DRFM logic circuit according to some embodiments of the present disclosure. In some embodiments, the DRFM logic circuit 300 may implement Figure 23. The DRFM logic circuit 260 of FIG. 300 includes one or more address management circuits 310 and a DRFM control circuit 308. The address management circuits 310 each store a previous DRFM aggressor address and compare the current address with the address stored in the address management circuit. Each DRFM logic circuit includes a first register 302, a second register, and a comparator circuit 304. Based on the output from the address management circuit 310, the DRFM control circuit 308 determines whether to provide a DRFM skip signal DRFM_Skip.

[0060] Because the DRFM address management circuits 310 may generally be similar to each other, only a single address management circuit is described in detail herein. In some embodiments, only a single address management circuit may be used. In some embodiments, multiple address management circuits may be used, such as two, three, or more address management circuits. Each address management circuit allows the DRFM logic circuit 300 to track additional previous DRFM aggressor addresses.

[0061] In an example embodiment having a single address tracking circuit 310, in response to a DRFM sampling signal (eg, Figure 2 The address XADD is stored in the first register 302. The comparator circuit 304 compares the address stored in the first register 302 with the address stored in the second register 306. If they match, the comparator provides a skip signal SameSkip to the control circuit 308. If they do not match, the comparator circuit 304 provides a reset signal NotSameReset to the control circuit 308.

[0062] In response to a DRFM refresh signal (eg, Figure 2 The address from the first register 302 is moved to the second register 306. In this way, the second register 306 stores the previous DRFM address.

[0063] The control circuit 308 changes the count value in response to SameSkip (e.g., by incrementing the count value). If the count value is below the threshold, the control circuit 308 provides the DRFM skip signal DRFM_Skip at an active level. If the count value is at the threshold, the count value is reset, and the signal DRFM_Skip is not provided in response to the signal SameSkip. In some embodiments, the count value may reach a maximum value and "roll over" to an initial value, and when the count value rolls over, it may act as if the count reaches the threshold. For example, if the counter is a two-bit counter, DRFM_Skip may be provided for three of every four activations of SameSkip (assuming NotSameReset is not provided). When the control circuit 308 receives the reset signal NotSameReset, the count value is reset to the initial value, and the signal DRFM_Skip is not provided.

[0064] In some embodiments, there may be multiple address tracking circuits 310. For example, in an embodiment with two address tracking circuits, there may be two comparators 304 and two second registers 306. When an address is sampled, the two comparators compare the sampled address with its corresponding second register. Each comparator separately provides a signal SameSkip or NotSameReset based on the comparison. The control circuit 308 receives the signal and determines what to do based on the signal. For example, if the sampled address does not match the stored address (e.g., both signals are NotSameReset), then one of the two second registers is reset and the sampled address is written to the register. For example, the older of the two stored addresses may be overwritten. If one of the signals SameSkip is valid, the control circuit may update the count value associated with the address tracking circuit and provide a DRFM_Skip signal until the counter reaches a threshold or is reset.

[0065] In some embodiments, the first latch 302 may be shared by multiple address tracking circuits 310 so that the same DRFM aggressor address is provided to each comparator.

[0066] Figure 4 is a table of example modes of DRFM addresses according to some embodiments of the present disclosure. Table 400 represents four different address modes provided as part of DRFM operation. Three different addresses are shown, labeled A, B, and C. Table 400 shows the DRFM logic circuit (e.g. Figure 2 260 and / or Figure 3 The behavior represented by table 400 is only one example of how the DRFM logic circuit may respond to an address pattern, and different operations may be used in other example embodiments. Figure 4The example of represents the operation of a DRFM logic circuit with two address tracking circuits, each associated with a two-bit counter (e.g., threshold 4). The modes and which addresses are skipped are based on the circuit initialization just before the first address shown in each example mode. The skipped addresses are shown in the boxes.

[0067] Table 400 shows four example address modes. In the first mode, the sequence of DRFM addresses AAB is repeated over and over. In this mode, the memory performs a target refresh operation on address A, skips the next DRFM operation (on A), and then performs the next DRFM operation on B and A, then skips the second DRFM operation on A, and so on.

[0068] In the second mode, address A is repeatedly received as a DRFM address. In this mode, a DRFM operation is performed the first time address A is received. The next three DRFM operations on A are skipped (e.g., when the counter is incremented). When A is provided for the fifth time, the counter is reset and a DRFM operation is performed on A again.

[0069] In a third mode, address AB is repeated repeatedly. When A is provided for the first time, it is stored in the first address management circuit and DRFM is performed on A. When B is provided for the first time, it is stored in the second address management circuit and DRFM is performed on B. When A is provided for the second time, it is compared with the first and second management circuits, and because it matches, DRFM is skipped on A. When B is provided for the second time, it is compared with the address management circuit and matches the second circuit, but not the first circuit, which resets the first address management circuit (and associated counter). Because it matches the second circuit, DRFM is skipped on B. When A is received for the third time since the first address management circuit was reset, DRFM is performed on A and the second DRFM address management circuit is reset. When B is received for the third time, DRFM is performed on B, and so on.

[0070] In the fourth example mode, address ABC is received repeatedly. Since this mode resets both address management circuits each time, the DRFM operation is not skipped.

[0071] Figure 5 is a timing diagram of an example operation of a refresh control circuit according to some embodiments of the present disclosure. In some embodiments, timing diagram 500 may be implemented by one or more of the devices or systems described herein. For example, the timing diagram may represent Figure 1 The refresh control circuit 116 and / or Figure 2 The timing diagram 500 shows the operation of the DRFM logic circuit (e.g. Figure 2 The DRFM logic circuit 260 and / or Figure 3300) in the memory.

[0072] exist Figure 5 In the example of FIG. 1 , as part of performing a DRFM operation, the refresh control circuit performs a total of four refresh operations, two of which are DRFM operations and two of which are target refresh operations (e.g., using addresses from an aggressor queue). The timing diagram shows four consecutive DRFM operations, each of which may be associated with the same DRFM aggressor address (e.g., Figure 4 4) is associated with the mode 2 of Table 400 of FIG. At some time before the initial time t0, the address is provided together with the sampling signal. At the first time t0, the DRFM command is received and four refresh pumps RRAST are generated. The first two pumps are DRFM pumps DRFMpump. The next two pumps are target update pumps RHRpump. At the next three times t1, t2 and t3 after the DRFM refresh command is received, the skip signal is valid and thus four refresh pumps are still generated, but all four pumps are target refresh pumps because the target refresh operation is replacing the skipped DRFM operation.

[0073] Figure 6 is a schematic diagram of a DRFM logic circuit with two comparators according to some embodiments of the present disclosure. In some embodiments, Figure 6 The DRFM logic circuit 600 may be implemented Figure 2 The DRFM logic circuit 260 and / or Figure 3 300. Specifically, Figure 6 DRFM logic circuit 600 represents an example embodiment in which there are two address management circuits, each of which compares a received DRFM aggressor address to a first or second previous DRFM aggressor address, respectively.

[0074] The DRFM logic circuit 600 includes a DRFM control circuit 630 (eg, Figure 3 308) and two comparator circuits 610 and 620 (e.g., Figure 3 The comparator circuit 304 in the first and second address management circuits 310 of FIG. 310 ). The latch is not shown, for example Figure 3 However, the DRFM logic circuit 600 may include three latches, one for storing the currently sampled DRFM address DRFM_ADDR_SAMP, one for storing the first previous DRFM address DRFM_ADDR_Flush, and one for storing the second previous DRFM address DRFM_ADDR_Flush2nd.

[0075] Each comparator circuit 610 and 620 may be similar in operation except for the signals it receives. Both comparators 610 and 620 receive system power, such as VPERI, and a DRFM aggressor address DRFM_ADDR_SAMP (and its inverse DRFM_ADDRF_SAMP, which inverts all bits), as well as a control signal tmfzDRFMSkipCtrl that determines whether the DRFM skip logic is enabled, a block enable signal BlockEn that determines whether the operation of the comparator is blocked, a compare enable signal CompareEn that causes the comparator to perform its compare function, and a DRFM signal DrfmrisePulse that determines whether a DRFM operation is performed. The first comparator 610 receives a first previous address DRFM_ADDR_Flush (and its inverse address) and a first reset signal rst3, and the second comparator 620 receives a second previous address DRFM_ADDR_Flus2nd (and its inverse address) and a second reset signal rst4.

[0076] The comparator circuit may be operable when tmfzDRFMSkipCtrl is valid (e.g., the DRFM skip feature is enabled in settings such as a fuse array and / or a mode register of a memory) and the signal CompareEn is valid and the signal BlockEn is invalid. When in operation (e.g., CompareEn is valid), if the address DRFM_ADDR_Flush matches DRFM_ADDR_SAMP, the first comparator 610 provides a first match signal Match. When in operation (e.g., CompareEn is valid), if the address DRFM_ADDR_Flush2nd matches DRFM_ADDR_SAMP, the second comparator 620 provides a second match signal Match2nd.

[0077] The control circuit 630 receives a plurality of input signals, such as fnCbrCntRstBuf, DRFM, DRFM_FLAG_OUT, and tmfzDRFMSkipCtrl, which indicates that the device is valid and in a DRFM mode that enables skip DRFM operations. The control circuit 630 receives a DRFM sampling signal ArmSampleD that indicates when a new DRFM address is sampled. The control circuit 630 also receives two match signals Match and Match2nd output from the two comparators 610 and 620.

[0078] The control circuit 630 provides reset signals rst3 and rst4, and a signal to reset the two comparators rst_tot. The control circuit 630 provides a block enable signal BlockEn and a comparison enable signal CompareEn. The control circuit 630 also provides DRFM control signals DrfmallPulse, DrfmrisePulse, DrfmfallPulse, and DrfmfallPusleDD. The control circuit also provides a skip signal SameAddrDrfm.

[0079] During example operation, the signal ArmSampleD indicates that the new DRFM aggressor address has been sampled as DRFM_ADDR_SAMP. The control circuit 630 provides the signal CompareEn to cause the two comparators 610 and 620 to compare the address DRFM_ADDR_SAMP with its corresponding previous DRFM address. The control circuit 630 receives the signals Match and Match2nd, which indicate whether either of the two comparators 610 and 620 has found a match. If not, the control circuit 630 provides a DRFM signal such as DRFMallPulse to indicate that a DRFM refresh operation should be performed. If not, a reset signal such as rst3 or rst4 may be sent to indicate that one of the comparators 610 or 620 applies a new previous address reset, and the current address DRFM_ADDR_SAMP may be saved as DRFM_ADDR_Flush or DRFM_ADDR_Flush2nd. For example, the control circuit 630 may keep track of which of the stored previous addresses is older and replace the older address first.

[0080] If there is a match and Match or Match2nd is valid, the control circuit 630 may provide a skip signal SameAddrDrfm.

[0081] Figure 7 700 is a flow chart of a method for determining whether to skip a DRFM operation according to some embodiments of the present disclosure. In some embodiments, method 700 may be implemented by one or more of the devices or systems described herein. For example, method 700 may be implemented by Figure 1 The memory device 100, Figure 2 200 Figure 3 The DRFM logic circuit 300 and / or Figure 6 of 600 to execute.

[0082] Method 700 may begin at block 710, which describes receiving a DRFM aggressor address as part of a DRFM operation. Method 700 may include receiving a DRFM aggressor address from a controller of a memory, and receiving a DRFM aggressor address at the memory. For example, the method may include the controller providing an address along an address bus, and latching the address out of the address bus as a DRFM aggressor address in response to a DRFM sampling command. The method may include receiving a DRFM sampling command from a controller or generating a DRFM sampling command in response to a DRFM command from a controller.

[0083] Block 710 may be followed by block 720, which depicts comparing the DRFM aggressor address to a previous DRFM aggressor address. For example, a comparator (e.g., Figure 3 304 and / or Figure 6 610 / 620) can be compared. The DRFM aggressor address can be stored in a first latch (e.g., Figure 3 302), and the previous DRFM aggressor address may be stored in a second latch (eg, Figure 3 306). Block 720 is followed by block 730, which describes determining whether there is a match between the DRFM aggressor address and the previous DRFM aggressor address. If there is a match, then the method continues to block 740. If there is no match, then the method 700 continues to block 750.

[0084] Block 740 depicts skipping the DRFM operation if the address matches. For example, the method may include providing a DRFM skip signal, and skipping the DRFM operation in response to the DRFM skip signal. In some embodiments, the method may include counting the number of times the DRFM operation is skipped, and performing the DRFM operation even if the address matches when the count reaches a threshold (e.g., block 750). For example, the method may include performing 1 out of every N DRFM operations when the address matches. In some embodiments, the method 700 may include tracking the aggressor address (e.g., in e.g., Figure 2 244 aggressor queues) and performs a target refresh operation on the aggressor address from the queue instead of a skipped DRFM operation.

[0085] Block 750 depicts performing a DRFM operation if the addresses do not match. Performing a DRFM operation may include generating one or more refresh addresses based on the DRFM aggressor address and performing a refresh operation on a word line associated with the refresh address. Method 700 may include receiving a DRFM refresh signal (e.g., from a controller) or generating a DRFM refresh signal (e.g., based on a DRFM command from a controller) and performing a DRFM operation in response to a DRFM refresh command (e.g., when a DRFM skip signal is deasserted).

[0086] In some embodiments, method 700 may include determining whether to skip DRFM operations on a victim address by victim address calculation basis. For example, method 700 may include determining that a DRFM aggressor address matches a previous DRFM aggressor address, and performing some DRFM operations while skipping other DRFM operations. For example, method 700 may include refreshing victims that are closer to a word line associated with the DRFM aggressor address while skipping victims that are further away from the DRFM aggressor address. For example, if block 750 generally involves performing DRFM operations on a first number of refresh addresses, block 740 may involve performing DRFM operations on a second number of refresh addresses that is less than the first number.

[0087] It should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or separated and / or performed in a separate device or device portion according to the present systems, devices, and methods.

[0088] Finally, the above discussion is intended to be illustrative only of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the present system has been described in particular detail with reference to exemplary embodiments, it should also be understood that numerous modifications and alternative embodiments may be devised by one of ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as subsequently set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: a direct refresh management (DRFM) logic circuit configured to latch a row address as a DRFM aggressor address in response to receiving a sample command, wherein the DRFM logic circuit is configured to provide a valid skip signal if the DRFM aggressor address matches a previous DRFM aggressor address; and A refresh state control circuit is configured to perform a DRFM operation by performing a target refresh operation based on the DRFM aggressor address in response to a DRFM refresh command when the skip signal is invalid, or to skip performing the DRFM operation if the skip signal is valid.

2. The apparatus of claim 1 , wherein the DRFM logic circuit is configured to compare the DRFM aggressor address to a first previous DRFM aggressor address and a second previous DRFM aggressor address and to provide the valid skip signal if the DRFM aggressor address matches the first previous DRFM aggressor address or the second previous DRFM aggressor address.

3. The apparatus of claim 1, wherein the DRFM logic circuit is configured to store the DRFM aggressor address as the previous DRFM aggressor address in response to performing the target refresh operation based on the DRFM aggressor address.

4. The apparatus according to claim 1, further comprising: an aggressor detector circuit configured to identify the address as an aggressor address; an aggressor queue configured to store the identified aggressor addresses, Wherein the refresh state control circuit is configured to perform a target refresh operation based on the identified aggressor address in the aggressor queue in response to a refresh management (RFM) signal.

5. The apparatus of claim 4, wherein the refresh state control circuit is configured to perform a target refresh operation based on the identified aggressor address in the aggressor queue in response to skipping performing the DRFM operation.

6. The apparatus of claim 1 , wherein the DRFM logic circuit comprises: a first latch configured to store the DRFM aggressor address; a second latch configured to store the previous DRFM aggressor address; and A comparator circuit is configured to compare the DRFM aggressor address in the first latch with the previous DRFM aggressor address in the second latch and provide a match signal if the DRFM aggressor address matches the previous DRFM aggressor address, wherein the valid skip signal is provided based in part on the match signal.

7. The apparatus of claim 6, further comprising a DRFM control circuit configured to change a count value in response to the match signal and to provide the valid skip signal based on the changed count value.

8. A device comprising: a first latch circuit configured to store a row address as a direct refresh management DRFM aggressor address in response to a sampling signal; a second latch circuit configured to store a previous DRFM aggressor address; a comparator circuit configured to provide a match signal if the DRFM aggressor address matches the previous DRFM aggressor address; and A DRFM control circuit is configured to provide a DRFM skip signal based in part on the match signal, wherein a DRFM operation is skipped based in part on the DRFM skip signal.

9. The apparatus of claim 8, further comprising a refresh state control circuit configured to perform a DRFM operation in response to a DRFM refresh command when the DRFM skip signal is not provided, and configured to skip performing the DRFM operation in response to the DRFM refresh command when the DRFM skip signal is provided.

10. The apparatus of claim 9, further comprising: a refresh address generator configured to generate a refresh address based on the DRFM aggressor address in response to the refresh state control circuit performing the DRFM operation; and A row decoder is configured to refresh one or more word lines based on the refresh address.

11. The apparatus of claim 10, further comprising an aggressor queue configured to store aggressor addresses, wherein the refresh state control circuit is configured to perform a target refresh operation in response to skipping the DRFM operation, and Wherein the refresh address generator is configured to generate the refresh address based on the aggressor address in the aggressor queue in response to the target refresh operation.

12. The apparatus of claim 8, wherein the DRFM control circuit is configured to change a count value in response to the match signal, and is configured to not provide the DRFM skip signal and reset the count value in response to the count value reaching a threshold.

13. The apparatus of claim 8, further comprising: a third latch circuit configured to store a second previous DRFM address; and a second comparator circuit configured to provide a second match signal if the DRFM aggressor address matches the second previous DRFM address, Wherein the DRFM control circuit is configured to provide the DRFM skip signal based in part on the match signal and the second match signal.

14. The apparatus of claim 8, wherein the DRFM control circuit is configured to store the DRFM aggressor address from the first latch as the previous DRFM aggressor address in the second latch in response to a DRFM refresh signal when the DRFM skip signal is not provided.

15. A method comprising: receiving a direct refresh management DRFM aggressor address as part of a DRFM operation; comparing the DRFM aggressor address with a previous DRFM aggressor address; and If the DRFM address matches the previous DRFM address, then the DRFM operation is skipped.

16. The method of claim 15, further comprising refreshing one or more word lines as part of the DRFM operation based on the DRFM aggressor address if the DRFM operation is not skipped.

17. The method according to claim 15, further comprising: Counting the number of times the DRFM operation is skipped; and When the count reaches a threshold, the DRFM operation is performed even if the DRFM address matches the previous DRFM address.

18. The method of claim 15, further comprising storing the DRFM aggressor address in a latch as the previous DRFM aggressor if the DRFM operation is not skipped.

19. The method of claim 15, further comprising: comparing the DRFM aggressor address to a second previous DRFM aggressor address; and If the DRFM address matches the first or second previous DRFM aggressor address, then the DRFM operation is skipped.

20. The method of claim 15, further comprising: identifying an aggressor address and storing the identified aggressor address in an aggressor queue; and In response to skipping the DRFM operation, a target refresh operation is performed on the aggressor address from the aggressor queue.

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