A high-speed data exchange method and system for embedded heterogeneous platforms

Abstract

The present invention relates to the technical field of data transmission, and discloses a high-speed data exchange method and system for an embedded heterogeneous platform, in which a DDR module is mapped to a shared memory of a CPU module and a DSP module; when a data sender in the CPU module and the DSP module writes data to the shared memory, an interrupt signal triggered to a data responder in the CPU module and the DSP module is generated according to the written data and the written address; according to the response signal of the data responder to the interrupt signal, it is determined whether the data responder needs to read the written data, thereby managing the read and write permissions of the CPU module and the DSP module to the write address respectively; and the write status of the shared memory is synchronized to the CPU module and the DSP module respectively. The present invention is conducive to providing a simple and efficient direct sharing mechanism for the data interaction process between the DSP and the CPU in an embedded heterogeneous platform.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a high-speed data exchange method and system for embedded heterogeneous platforms. Background Art

[0002] An embedded heterogeneous platform is a system that integrates multiple different types of processors or computing units, each with different architectures and features, designed to meet the needs of specific applications by leveraging the advantages of each part. This type of platform is usually used in applications that require high performance, low power consumption, and high flexibility, such as industrial control systems, automotive electronics, medical equipment, and communication infrastructure.

[0003] The embedded heterogeneous platform combines three different types of processing units: FPGA (field programmable gate array), DSP (digital signal processor) and CPU (central processing unit), aiming to use their respective advantages to meet the needs of complex applications. This combination can provide strong support for high-performance computing, real-time data processing and flexible algorithm implementation.

[0004] However, this embedded heterogeneous platform combining FPGA, DSP and CPU also has some problems and defects, which are mainly reflected in: there is no high-speed channel between DSP and CPU, and the data transmission efficiency is low; in addition, synchronization and coordination between DSP and CPU are difficult. Specifically, when DSP and CPU need to interact with each other, one of DSP and CPU needs to provide data to the other for data processing, and the party that receives and processes data needs to receive data in time for data processing. If the data is not received in time, data will be lost. In other words, when DSP and CPU interact with each other, data cannot be shared, and there is a lack of a simple and efficient direct sharing mechanism. If data sharing is required between the two, it is usually necessary to use a complex software layer to achieve data synchronization and coordination, which not only increases the difficulty and workload of software development, but also easily introduces synchronization errors and data inconsistency due to the complexity of software design.

[0005] Therefore, it is necessary to propose a new high-speed data exchange method and system for embedded heterogeneous platforms to solve the technical problems of low data transmission efficiency between DSP and CPU in existing embedded heterogeneous platforms, and lack of a simple and efficient direct sharing mechanism in the data interaction process. Summary of the invention

[0006] The main purpose of the present invention is to provide a high-speed data exchange method and system for embedded heterogeneous platforms, aiming to solve the technical problems of low data transmission efficiency between DSP and CPU and lack of a simple and efficient direct sharing mechanism in the data interaction process between DSP and CPU in existing embedded heterogeneous platforms.

[0007] To achieve the above object, the present invention provides a high-speed data exchange method for embedded heterogeneous platforms, which is applied to an embedded heterogeneous platform system. The embedded heterogeneous platform system includes an FPGA module and a CPU module and a DSP module respectively connected to the FPGA module for communication; the FPGA module is connected to a DDR module; the method includes the following steps:

[0008] Establish a high-speed PCIe data channel between the FPGA module and the CPU module, and establish a high-speed SRIO data channel between the FPGA module and the DSP module;

[0009] The DDR module is constructed as the shared memory of the CPU module and the DSP module, and the shared memory is memory-mapped to the CPU module and the DSP module respectively;

[0010] When the data senders in the CPU module and the DSP module write data to the shared memory, an interrupt signal is generated to trigger the data responders in the CPU module and the DSP module according to the written data and the written address;

[0011] According to the response signal of the data responder to the interrupt signal, it is determined whether the data responder needs to read the written data, so as to manage the read and write permissions of the CPU module and the DSP module to the write address respectively;

[0012] The write status of the shared memory is synchronized to the CPU module and the DSP module respectively.

[0013] Optionally, the step of constructing the DDR module as a shared memory of the CPU module and the DSP module, and performing memory mapping on the shared memory to the CPU module and the DSP module respectively includes:

[0014] Build the DDR module as the shared memory of the CPU module and the DSP module;

[0015] Dividing the shared memory into a plurality of first shared partitions and a plurality of second shared partitions;

[0016] Dividing the first shared partition into a plurality of first atomic operation blocks, and dividing the second shared partition into a plurality of second atomic operation blocks;

[0017] Map the shared memory to the CPU module and DSP module respectively;

[0018] The first shared partition is write-only for the CPU module and read-only for the DSP module, and the second shared partition is read-only for the CPU module and write-only for the DSP module.

[0019] Optionally, when the data senders in the CPU module and the DSP module write data to the shared memory, the step of generating an interrupt signal triggered to the data responders in the CPU module and the DSP module according to the written data and the written address includes:

[0020] When the data sender in the CPU module and the DSP module writes data to the shared memory, the atomic operation block to be controlled corresponding to the write data sent by the data sender to the shared memory and the write address of the write data is obtained;

[0021] Generate an interrupt signal triggered to a data responder according to the written data and the atomic operation block to be controlled;

[0022] The step of determining whether the data responder needs to read the written data according to the response signal of the data responder to the interrupt signal, thereby managing the read and write permissions of the CPU module and the DSP module to the write address respectively, includes:

[0023] When the data responder responds to the interrupt signal with the signal that data needs to be read or written, the atomic operation block to be controlled is locked;

[0024] After detecting that the data responder has successfully read and written data from the atomic operation block to be controlled, unlocking the locked atomic operation block to be controlled;

[0025] When the data responder responds to the interrupt signal with the signal that there is no need to read or write data, the atomic operation block to be controlled is not locked.

[0026] Optionally, the method further includes:

[0027] Allocate initial quota values ​​to the CPU module and the DSP module respectively, wherein the initial quota value of the CPU module is equal to the number of the first atomic operation blocks initially allocated, and the initial quota value of the DSP module is equal to the number of the second atomic operation blocks initially allocated;

[0028] Whenever a CPU module or DSP module uses a corresponding atomic operation block, the corresponding quota value is reduced;

[0029] According to the current quota values ​​of the CPU module and the DSP module, flow control is performed between the CPU module and the DSP module, thereby avoiding data congestion between the CPU module and the DSP module.

[0030] Optionally, the method further includes:

[0031] Adaptively match the check strength of the data to be transmitted based on the importance and content of the data to be transmitted.

[0032] Optionally, the method further includes:

[0033] According to the customized data packet header format, the data format of the data to be transmitted is optimized to achieve efficient data transmission between the CPU module and the DSP module, wherein the customized data packet header format includes: source address, destination address, data length, data type and check field.

[0034] Optionally, the method further includes:

[0035] According to the source, purpose and type of the data to be transmitted, an idle data channel is selected to transmit the data sent by one of the CPU module and the DSP module to the other through the selected data channel.

[0036] To achieve the above object, the present invention further proposes an embedded heterogeneous platform system, applying the high-speed data exchange method for embedded heterogeneous platforms; the embedded heterogeneous platform system includes an FPGA module and a CPU module and a DSP module respectively connected to the FPGA module for communication, and the FPGA module is connected to a DDR module;

[0037] The FPGA module includes a memory sharing module, and the memory sharing module includes a permission control unit, a memory management unit, a synchronization mechanism unit and a memory mapping unit;

[0038] The memory management unit is used to build the DDR module as a shared memory for the CPU module and the DSP module;

[0039] The authority control unit is used to generate an interrupt signal triggered to the data responder in the CPU module and the DSP module according to the written data and the written address when the data sender in the CPU module and the DSP module writes data to the shared memory; according to the response signal of the data responder to the interrupt signal, determine whether the data responder needs to read the written data, so as to manage the read and write permissions of the CPU module and the DSP module to the write address respectively;

[0040] The memory mapping unit is used to map the shared memory to the CPU module and the DSP module respectively;

[0041] The synchronization mechanism unit is used to synchronize the write status of the shared memory to the CPU module and the DSP module respectively.

[0042] Optionally, the FPGA module further includes a data conversion module, a data routing module, and a custom high-efficiency transmission protocol module;

[0043] The data conversion module is used to convert the data to be transmitted according to the requirements of the processor receiving the data according to the preset conversion rules, so that the data to be transmitted can be correctly transmitted and processed between the CPU module and the DSP module;

[0044] The data routing module is used to select an idle data transmission channel according to the source, purpose and type of the data to be transmitted, so as to transmit the data to be transmitted between the CPU module and the DSP module;

[0045] The custom high-efficiency transmission protocol module is used to provide a custom high-efficiency transmission protocol for embedded heterogeneous platforms. According to the custom data packet header format, the data format of the transmitted data is optimized to achieve efficient data transmission between the CPU module and the DSP module. The custom data packet header format includes: source address, destination address, data length, data type and check field.

[0046] Optionally, the CPU module includes an application control module and a data exchange driver module;

[0047] The application control module is used to analyze, process and control data according to the application scenario of the embedded system;

[0048] The data exchange driver module is used to communicate with the FPGA module on the PCIe data channel to implement data read and write operations, flow control, and error handling;

[0049] The DSP module includes a data processing module and a data exchange interface module;

[0050] The data processing module is used to implement digital signal processing algorithms according to application requirements;

[0051] The data exchange interface module is used to implement data request, send, receive and process functions according to the customized efficient transmission protocol of the SRIO data channel, and to exchange data with the FPGA module through the high-speed SRIO data channel to achieve fast data transmission.

[0052] The technical solution of the present invention provides a simple and efficient direct sharing mechanism in an embedded heterogeneous platform, specifically: the CPU module and the DSP module are respectively connected to the FPGA module for communication, and a high-speed data channel between the CPU module and the DSP module is established through the FPGA module; the FPGA module maps the DDR module connected to itself as a shared memory of the CPU module and the DSP module; when one of the CPU module and the DSP module writes data to the shared memory, the FPGA generates an interrupt signal triggered to the data responder in the CPU module and the DSP module according to the written data and the write address, so as to inform the data responder through the interrupt signal that data is written to the shared memory, obtain the response signal of the data responder to the interrupt signal, determine whether the data responder needs to read the written data, manage the read and write permissions of the CPU module and the DSP module to the write address according to whether the data responder needs to read the written data, and synchronize the write status of the shared memory to the CPU module and the DSP module respectively. Therefore, in an embedded heterogeneous platform, when there is interactive data between the CPU module and the DSP module, the interactive data can be stored in a shared memory, and the information that the data is written into the shared memory can be notified to the system, so that the data responder can read the data in the shared memory. Thus, the problem that the interactive data in the CPU module and the DSP module cannot be received in time is solved, and the data loss caused by the failure to receive data in time is solved. Therefore, the technical solution of the present invention provides a simple and efficient direct sharing mechanism in an embedded heterogeneous platform. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is a block diagram of the composition of the embedded heterogeneous platform system of the present invention;

[0054] Figure 2 This is a schematic diagram of shared memory data exchange in the FPGA module of the present invention;

[0055] Figure 3 FIG. 1 is a flow chart of the first embodiment of the present invention.

[0056] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0057] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0058] In the following description, suffixes such as "unit", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings. Therefore, "unit", "component" or "unit" can be used in a mixed manner.

[0059] See also Figures 1 to 3In a first embodiment of the present invention, a high-speed data exchange method for an embedded heterogeneous platform is provided. The embedded heterogeneous platform system includes an FPGA module and a CPU module and a DSP module respectively connected to the FPGA module for communication; the FPGA module is connected to a DDR module; the method includes the following steps:

[0060] Step S10, establishing a high-speed PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) data channel between the FPGA module and the CPU module, and establishing a high-speed SRIO (Serial RapidIO, a high-speed serial interconnect technology designed for high-performance embedded systems) data channel between the FPGA module and the DSP module;

[0061] Step S20, constructing the DDR module as a shared memory of the CPU module and the DSP module, and performing memory mapping on the shared memory to the CPU module and the DSP module respectively;

[0062] Step S30, when the data senders in the CPU module and the DSP module write data to the shared memory, an interrupt signal is generated to trigger the data responders in the CPU module and the DSP module according to the written data and the written address;

[0063] Step S40, determining whether the data responder needs to read the written data according to the response signal of the data responder to the interrupt signal, thereby managing the read and write permissions of the CPU module and the DSP module to the write address respectively;

[0064] Step S50, synchronizing the write status of the shared memory to the CPU module and the DSP module respectively.

[0065] The technical solution of the present invention provides a simple and efficient direct sharing mechanism in an embedded heterogeneous platform, specifically: the CPU module and the DSP module are respectively connected to the FPGA module for communication, and a high-speed data channel between the CPU module and the DSP module is established through the FPGA module; the FPGA module maps the DDR module connected to itself as a shared memory of the CPU module and the DSP module; when one of the CPU module and the DSP module writes data to the shared memory, the FPGA generates an interrupt signal triggered to the data responder in the CPU module and the DSP module according to the written data and the write address, so as to inform the data responder through the interrupt signal that data is written to the shared memory, obtain the response signal of the data responder to the interrupt signal, determine whether the data responder needs to read the written data, manage the read and write permissions of the CPU module and the DSP module to the write address according to whether the data responder needs to read the written data, and synchronize the write status of the shared memory to the CPU module and the DSP module respectively. Therefore, in an embedded heterogeneous platform, when there is interactive data between the CPU module and the DSP module, the interactive data can be stored in a shared memory, and the information that the data is written into the shared memory can be notified to the system, so that the data responder can read the data in the shared memory. Thus, the problem that the interactive data in the CPU module and the DSP module cannot be received in time is solved, and the data loss caused by the failure to receive data in time is solved. Therefore, the technical solution of the present invention provides a simple and efficient direct sharing mechanism in an embedded heterogeneous platform.

[0066] The technical solution of the present invention utilizes the parallel real-time processing characteristics of FPGA to build a transparent high-speed data transmission channel between DSP and CPU, realizes fast and stable data sharing through a shared memory mechanism, effectively solves data synchronization and coordination problems, and improves system reliability and stability.

[0067] Specifically, step S10 to step S50 may be executed by an FPGA module.

[0068] Furthermore, the type of data transmitted in the embedded heterogeneous platform of the present invention is not limited, for example, it can be image data, radar data, or other types of data.

[0069] Based on the first embodiment of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, in the second embodiment of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, step S20 includes:

[0070] Step S21, constructing the DDR module as a shared memory of the CPU module and the DSP module;

[0071] Step S22, dividing the shared memory into a plurality of first shared partitions and a plurality of second shared partitions;

[0072] Step S23, dividing the first shared partition into a plurality of first atomic operation blocks, and dividing the second shared partition into a plurality of second atomic operation blocks;

[0073] Step S24, memory mapping the shared memory to the CPU module and the DSP module respectively;

[0074] The first shared partition is write-only for the CPU module and read-only for the DSP module, and the second shared partition is read-only for the CPU module and write-only for the DSP module.

[0075] Specifically, the shared memory is divided into a plurality of first shared partitions and a plurality of second shared partitions. Figure 2 In the figure, M_A is the first shared partition, M_B is the second shared partition, in the first shared partition, the CPU module only has write permission, and the DSP module only has read permission, on the contrary, in the second shared partition, the DSP module only has write permission, and the CPU module only has read permission, so when the CPU module writes data to the shared memory, it will only write to the first shared partition, and when the DSP module writes data to the shared memory, it will only write to the second shared partition, thus realizing partition writing of the CPU module and the DSP module and avoiding data overwriting errors.

[0076] Furthermore, the first shared partition is divided into several first atomic operation blocks, and the second shared partition is divided into several second atomic operation blocks, which is beneficial for managing the written shared partitions according to the atomic operation blocks when the CPU module and the DSP module write data to the shared memory respectively.

[0077] Specifically, the number of the first shared partitions and the number of the second shared partitions may be one or more, respectively. Further, the number of the first atomic operation blocks in the first shared partition may be equal to or unequal to the number of the second atomic operation blocks in the second shared partition.

[0078] Different serial numbers may be assigned to each first atomic operation block and each second atomic operation block, so that the atomic operation block and the storage partition corresponding to the atomic operation block can be located by the serial number.

[0079] A memory sharing module is built inside the FPGA module, which has a high-speed read / write interface and a flexible memory management unit. The memory management unit is responsible for partitioning the shared memory, allocating independent read / write areas for the DSP module and the CPU module, and setting corresponding access rights and synchronization mechanisms. An efficient memory mapping scheme is designed so that the DSP module and the CPU module can access the shared memory of the FPGA module as easily as accessing local memory.

[0080] Based on the second embodiment of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, in a third embodiment of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, step S30 includes:

[0081] Step S31, when the data sender in the CPU module and the DSP module writes data to the shared memory, the write data sent by the data sender to the shared memory and the atomic operation block to be controlled corresponding to the write address of the write data are obtained;

[0082] Step S32, generating an interrupt signal triggered to the data responder according to the written data and the atomic operation block to be controlled;

[0083] The step S40 comprises:

[0084] Step S41, when the data responder's response signal to the interrupt signal is that data needs to be read or written, the atomic operation block to be controlled is locked;

[0085] Step S42, after detecting that the data responder has successfully read and written data from the atomic operation block to be controlled, unlocking the locked atomic operation block to be controlled;

[0086] Step S43: When the data responder responds to the interrupt signal with the signal that there is no need to read or write data, the atomic operation block to be controlled is not locked.

[0087] When one of the CPU module and the DSP module writes data to the corresponding shared memory, the atomic operation block corresponding to the write address assigned to the write data is used as the atomic operation block to be controlled. For example, when the CPU module writes data to the shared memory, the write data is written to a first atomic operation block in the first shared partition. At this time, the first atomic operation block is the atomic operation block to be controlled.

[0088] Specifically, the interrupt signal may include: the atomic operation block sequence number and the written data content, and may also include the written data address and length.

[0089] When writing data, the FPGA module generates an interrupt signal to the data responder. The data responder obtains the content of the written data and the written atomic operation block according to the interrupt signal. Thus, according to the content of the written data, the data responder can make a judgment and generate a response signal. The response signal can be: immediate reading, delayed reading, or no reading. When the response signal is that the written data needs to be read, the data responder can read the written data from the corresponding atomic operation block through the atomic operation block serial number recorded in the interrupt signal. At the same time, if the response signal indicates that the written data needs to be read, the atomic operation block to be controlled will be locked until the data responder successfully reads the written data, and then the atomic operation block to be controlled will be unlocked. If the written data does not need to be read, the atomic operation block to be controlled will not be locked directly.

[0090] In a shared partition where the CPU module or DSP module has write permission, the write permission of the atomic operation block is closed by locking the atomic operation block to prevent the data to be read from being overwritten by subsequent write data. By unlocking the atomic operation block, the write permission of the atomic operation block can be released. The technical solution of the present invention realizes transparent high-speed transmission of data. In order to ensure the consistency and integrity of the data, the atomic operation and cache consistency protocol are introduced in the read and write operations of the shared memory to prevent other parties from performing operations at the same time and avoid data conflicts.

[0091] Based on the second to third embodiments of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, in a fourth embodiment of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, the method further includes:

[0092] Step S60, allocating initial quota values ​​to the CPU module and the DSP module respectively, wherein the initial quota value of the CPU module is equal to the number of the first atomic operation blocks initially allocated, and the initial quota value of the DSP module is equal to the number of the second atomic operation blocks initially allocated;

[0093] Step S70, whenever the CPU module or the DSP module uses a corresponding atomic operation block, the corresponding quota value is reduced;

[0094] Step S80, performing flow control between the CPU module and the DSP module according to the current quota values ​​of the CPU module and the DSP module, thereby avoiding data congestion between the CPU module and the DSP module.

[0095] In this embodiment, a flow control mechanism based on quota value allocation is adopted. The FPGA module allocates an initial quota value to the CPU module and the DSP module. Each time the CPU module or the DSP module uses a corresponding atomic operation block, the quota value decreases accordingly. When the quota value is exhausted, it is necessary to wait for the FPGA module to replenish the quota value before continuing to send, thereby effectively avoiding data congestion.

[0096] The initial quota value indicates the number of atomic operation blocks initially available to the CPU module and the DSP module. According to the current quota values ​​corresponding to the CPU module and the DSP module respectively, the number of atomic operation blocks locked by the two in the corresponding storage partitions can be determined. According to the number of locked atomic operation blocks, it can be determined whether the corresponding operating states of the two are busy or idle. If they are idle, the excess resources can be transferred to perform other processing tasks. If they are busy, other resources can be used to process the current task, thereby realizing flow control between the CPU module and the DSP module according to the current quota value, thereby avoiding data congestion between the CPU module and the DSP module.

[0097] Based on the first to fourth embodiments of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, in a fifth embodiment of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, the method further includes:

[0098] Step S90, adaptively matching the verification strength of the data to be transmitted according to the importance and transmission content of the data to be transmitted.

[0099] Specifically, an adaptive error checking strategy is introduced to dynamically adjust the check strength according to the importance of the data to be transmitted and the content of the transmission. For key control data, a high-intensity multiple check is used, such as a combination of CRC check and parity check. For general data, a simple check method is used to reduce the check overhead. At the same time, when an error is detected, the error position can be quickly located according to the check result, and corresponding retransmission or error correction operations can be performed.

[0100] Based on the first to fifth embodiments of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, in a sixth embodiment of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, the method further includes:

[0101] Step S100, optimizing the data format of the data to be transmitted according to the customized data packet header format, so as to perform efficient data transmission between the CPU module and the DSP module, wherein the customized data packet header format includes: source address, destination address, data length, data type and check field.

[0102] The data transmission efficiency in existing embedded heterogeneous platforms is low. Traditional embedded heterogeneous platform data exchange solutions often rely on general data transmission interfaces and protocols. These general protocols need to take into account multiple scenarios when designed, resulting in a large amount of redundant information and complex interaction processes in specific embedded heterogeneous platforms. The effective data transmission ratio is reduced, and the data transmission bandwidth is wasted, which seriously restricts the performance improvement of the entire embedded system.

[0103] The present invention designs a concise and targeted data packet header format, which only includes the necessary source address, destination address, data length, data type and checksum field. This embodiment designs a custom high-efficiency transmission protocol for embedded heterogeneous platforms, optimizes the data transmission format and process, improves data transmission efficiency, and reduces transmission delay to meet the needs of embedded application scenarios with high real-time requirements.

[0104] Based on the first to sixth embodiments of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, in a seventh embodiment of the high-speed data exchange method for embedded heterogeneous platforms of the present invention, the method further includes:

[0105] Step S110, selecting an idle data channel according to the source, destination and type of the data to be transmitted, so as to transmit the data sent by one of the CPU module and the DSP module to the other through the selected data channel.

[0106] The hardware resources in the existing embedded heterogeneous platforms are not fully utilized. The FPGA modules, DSP modules and CPU modules in the embedded heterogeneous platforms each have unique hardware resource advantages, but the existing data exchange methods fail to fully tap these advantages. The potential of the FPGA module's parallel processing capabilities in data routing and conversion has not been effectively utilized, resulting in bottlenecks when data is transmitted between different processors, resulting in low hardware resource utilization of the entire platform, and increasing system cost and energy consumption.

[0107] In this embodiment, the parallel processing capability of the FPGA module is utilized to design a flexible data routing module. The module can automatically select an idle data transmission channel according to the source, purpose and type of the data, and quickly route the data from one processor to another. In the data routing process, the FPGA module also undertakes the task of data conversion. Since different processors may have differences in data formats and encoding methods, the FPGA module can perform operations such as format conversion and encoding conversion on the data according to pre-set conversion rules to ensure that the data can be correctly transmitted and processed between different processors. For example, the image data sent by the CPU module that conforms to a certain specific format is converted into a format that can be directly processed by the DSP module to improve data processing efficiency.

[0108] Furthermore, in the present invention, the command signal between the CPU module and the DSP module is sent through the serial port, and the data to be transmitted between the CPU module and the DSP module is written into the shared memory so as to be read by accessing the shared memory.

[0109] Fully utilize the hardware resource advantages of each processor in the embedded heterogeneous platform, improve the hardware resource utilization of the entire platform through reasonable data exchange methods and platform architecture design, reduce system costs and energy consumption, and enhance the overall performance of the system.

[0110] To achieve the above object, the present invention further proposes an embedded heterogeneous platform system, applying the high-speed data exchange method for embedded heterogeneous platforms; the embedded heterogeneous platform system includes an FPGA module and a CPU module and a DSP module respectively connected to the FPGA module for communication, and the FPGA module is connected to a DDR module;

[0111] The FPGA module includes a memory sharing module, and the memory sharing module includes a permission control unit, a memory management unit, a synchronization mechanism unit and a memory mapping unit;

[0112] The memory management unit is used to build the DDR module as a shared memory for the CPU module and the DSP module;

[0113] The authority control unit is used to generate an interrupt signal triggered to the data responder in the CPU module and the DSP module according to the written data and the written address when the data sender in the CPU module and the DSP module writes data to the shared memory; according to the response signal of the data responder to the interrupt signal, determine whether the data responder needs to read the written data, so as to manage the read and write permissions of the CPU module and the DSP module to the write address respectively;

[0114] The memory mapping unit is used to map the shared memory to the CPU module and the DSP module respectively;

[0115] The synchronization mechanism unit is used to synchronize the write status of the shared memory to the CPU module and the DSP module respectively.

[0116] Optionally, the FPGA module further includes a data conversion module, a data routing module, and a custom high-efficiency transmission protocol module;

[0117] The data conversion module is used to convert the data to be transmitted according to the requirements of the processor receiving the data according to the preset conversion rules, so that the data to be transmitted can be correctly transmitted and processed between the CPU module and the DSP module;

[0118] The data routing module is used to select an idle data transmission channel according to the source, purpose and type of the data to be transmitted, so as to transmit the data to be transmitted between the CPU module and the DSP module;

[0119] The custom high-efficiency transmission protocol module is used to provide a custom high-efficiency transmission protocol for embedded heterogeneous platforms. According to the custom data packet header format, the data format of the transmitted data is optimized to achieve efficient data transmission between the CPU module and the DSP module. The custom data packet header format includes: source address, destination address, data length, data type and check field.

[0120] The FPGA module includes a function module for customizing efficient transmission protocols, a shared memory module, a data routing module, and a data conversion module. As the core of data exchange, the FPGA module is responsible for data routing and caching, unpacking, decoding, and error detection and correction to ensure data accuracy and integrity. It has high-speed parallel processing capabilities and can quickly transfer data from one processor to another.

[0121] The processor in the present invention refers to a CPU module or a DSP module.

[0122] Optionally, the CPU module includes an application control module and a data exchange driver module;

[0123] The application control module is used to analyze, process and control data according to the application scenario of the embedded system;

[0124] The data exchange driver module is used to communicate with the FPGA module on the PCIe data channel to implement data read and write operations, flow control, and error handling; for example, in the intelligent early warning system, it performs target detection and recognition on video data, and performs corresponding alarm or control operations based on the results;

[0125] The DSP module includes a data processing module and a data exchange interface module;

[0126] The data processing module is used to implement digital signal processing algorithms according to application requirements; such as audio filtering, video encoding, detection and tracking algorithms, etc.

[0127] The data exchange interface module is used to implement data request, send, receive and process functions according to the customized efficient transmission protocol of the SRIO data channel, and to exchange data with the FPGA module through the high-speed SRIO data channel to achieve fast data transmission.

[0128] The main beneficial effects of the present invention are as follows:

[0129] First, by customizing the efficient transmission protocol, the redundant information in the data packet header is reduced, the data transmission process is optimized, and the effective load rate of data transmission is improved. At the same time, the flow control mechanism based on the quota value and the adaptive error checking strategy are adopted to effectively avoid data congestion and error retransmission, greatly improving the data transmission efficiency.

[0130] Second, the shared memory mechanism of the FPGA module is used to achieve transparent high-speed data transmission between the DSP module and the CPU module, avoiding complex software synchronization operations and reducing the probability of data inconsistency and synchronization errors. By introducing atomic operations and cache consistency protocols in shared memory read and write operations, data consistency and integrity are ensured, improving the reliability and stability of the system.

[0131] Third, the hardware resource advantages of FPGA modules, DSP modules and CPU modules in the embedded heterogeneous platform are fully utilized. Through reasonable data exchange methods and architecture design, efficient data routing and conversion are achieved, avoiding idleness and waste of hardware resources. The parallel processing capabilities of the FPGA module are fully utilized in the data routing and conversion process, which improves the hardware resource utilization of the entire platform, reduces system costs and energy consumption, and enhances the overall performance of the system.

[0132] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a computer-readable storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for enabling a terminal device to enter the method described in each embodiment of the present invention.

[0133] In the description of this specification, the description with reference to the terms "an embodiment", "another embodiment", "other embodiments", or "first embodiment to Xth embodiment" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, method steps or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0134] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0135] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0136] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high-speed data exchange method for embedded heterogeneous platforms, characterized in that: The method is applied to an embedded heterogeneous platform system, wherein the embedded heterogeneous platform system comprises an FPGA module and a CPU module and a DSP module respectively connected to the FPGA module for communication; the FPGA module is connected to a DDR module; and the method comprises the following steps: Establish a high-speed PCIe data channel between the FPGA module and the CPU module, and establish a high-speed SRIO data channel between the FPGA module and the DSP module; The DDR module is constructed as the shared memory of the CPU module and the DSP module, and the shared memory is memory-mapped to the CPU module and the DSP module respectively; When the data senders in the CPU module and the DSP module write data to the shared memory, an interrupt signal is generated to trigger the data responders in the CPU module and the DSP module according to the written data and the written address; According to the response signal of the data responder to the interrupt signal, determine whether the data responder needs to read the written data, so as to manage the read and write permissions of the CPU module and the DSP module to the write address respectively, including: when the response signal of the data responder to the interrupt signal is that the written data needs to be read, the atomic operation block to be controlled is locked; after detecting that the data responder successfully reads the written data from the atomic operation block to be controlled, the locked atomic operation block to be controlled is unlocked; when the response signal of the data responder to the interrupt signal is that the written data does not need to be read, the atomic operation block to be controlled is not locked, wherein, when one of the CPU module and the DSP module writes data to the corresponding shared memory, the atomic operation block corresponding to the write address assigned to the write data is used as the atomic operation block to be controlled; according to the number of atomic operation blocks locked by the CPU module and the DSP module respectively, it is judged whether the corresponding running states of the CPU module and the DSP module are busy or idle; The write status of the shared memory is synchronized to the CPU module and the DSP module respectively.

2. The high-speed data exchange method for embedded heterogeneous platforms according to claim 1, characterized in that: The step of constructing the DDR module as a shared memory of the CPU module and the DSP module, and performing memory mapping on the shared memory to the CPU module and the DSP module respectively comprises: Build the DDR module as the shared memory of the CPU module and the DSP module; Dividing the shared memory into a plurality of first shared partitions and a plurality of second shared partitions; Dividing the first shared partition into a plurality of first atomic operation blocks, and dividing the second shared partition into a plurality of second atomic operation blocks; Map the shared memory to the CPU module and DSP module respectively; The first shared partition is write-only for the CPU module and read-only for the DSP module, and the second shared partition is read-only for the CPU module and write-only for the DSP module.

3. The high-speed data exchange method for embedded heterogeneous platforms according to claim 2, characterized in that: The step of generating an interrupt signal triggered to the data responders in the CPU module and the DSP module according to the written data and the written address when the data senders in the CPU module and the DSP module write data to the shared memory comprises: When the data sender in the CPU module and the DSP module writes data to the shared memory, the atomic operation block to be controlled corresponding to the write data sent by the data sender to the shared memory and the write address of the write data is obtained; An interrupt signal is generated to trigger the data responder according to the written data and the atomic operation block to be managed.

4. The high-speed data exchange method for embedded heterogeneous platforms according to claim 2, characterized in that: The method further comprises: Allocate initial quota values ​​to the CPU module and the DSP module respectively, wherein the initial quota value of the CPU module is equal to the number of the first atomic operation blocks initially allocated, and the initial quota value of the DSP module is equal to the number of the second atomic operation blocks initially allocated; Whenever a CPU module or DSP module uses a corresponding atomic operation block, the corresponding quota value is reduced; According to the current quota values ​​of the CPU module and the DSP module, flow control is performed between the CPU module and the DSP module, thereby avoiding data congestion between the CPU module and the DSP module.

5. The high-speed data exchange method for embedded heterogeneous platforms according to claim 1, characterized in that: The method further comprises: Adaptively match the check strength of the data to be transmitted based on the importance and content of the data to be transmitted.

6. The high-speed data exchange method for embedded heterogeneous platforms according to claim 1, characterized in that: The method further comprises: According to the customized data packet header format, the data format of the data to be transmitted is optimized to achieve efficient data transmission between the CPU module and the DSP module, wherein the customized data packet header format includes: source address, destination address, data length, data type and check field.

7. The high-speed data exchange method for embedded heterogeneous platforms according to claim 6, characterized in that: The method further comprises: According to the source, purpose and type of the data to be transmitted, an idle data channel is selected to transmit the data sent by one of the CPU module and the DSP module to the other through the selected data channel.

8. An embedded heterogeneous platform system, characterized in that: The high-speed data exchange method for embedded heterogeneous platforms as described in any one of claims 1 to 7 is applied; the embedded heterogeneous platform system comprises an FPGA module and a CPU module and a DSP module respectively connected to the FPGA module for communication, and the FPGA module is connected to a DDR module; The FPGA module includes a memory sharing module, and the memory sharing module includes a permission control unit, a memory management unit, a synchronization mechanism unit and a memory mapping unit; The memory management unit is used to build the DDR module as a shared memory for the CPU module and the DSP module; The permission control unit is used to generate an interrupt signal triggered to the data responder in the CPU module and the DSP module according to the written data and the written address when the data sender in the CPU module and the DSP module writes data to the shared memory; according to the response signal of the data responder to the interrupt signal, determine whether the data responder needs to read the written data, so as to manage the read and write permissions of the CPU module and the DSP module to the write address respectively, including: when the response signal of the data responder to the interrupt signal is that the written data needs to be read, the atomic operation block to be controlled is locked; after detecting that the data responder successfully reads the written data from the atomic operation block to be controlled, the locked atomic operation block to be controlled is unlocked; when the response signal of the data responder to the interrupt signal is that the written data does not need to be read, the atomic operation block to be controlled is not locked; wherein, when one of the CPU module and the DSP module writes data to the corresponding shared memory, the atomic operation block corresponding to the write address assigned to the write data is used as the atomic operation block to be controlled; according to the number of atomic operation blocks locked by the CPU module and the DSP module respectively, it is judged whether the corresponding running status of the CPU module and the DSP module is busy or idle; The memory mapping unit is used to map the shared memory to the CPU module and the DSP module respectively; The synchronization mechanism unit is used to synchronize the write status of the shared memory to the CPU module and the DSP module respectively.

9. The embedded heterogeneous platform system according to claim 8, characterized in that: The FPGA module also includes a data conversion module, a data routing module, and a custom high-efficiency transmission protocol module; The data conversion module is used to convert the data to be transmitted according to the requirements of the processor receiving the data according to the preset conversion rules, so that the data to be transmitted can be correctly transmitted and processed between the CPU module and the DSP module; The data routing module is used to select an idle data transmission channel according to the source, purpose and type of the data to be transmitted, so as to transmit the data to be transmitted between the CPU module and the DSP module; The custom high-efficiency transmission protocol module is used to provide a custom high-efficiency transmission protocol for embedded heterogeneous platforms. According to the custom data packet header format, the data format of the transmitted data is optimized to achieve efficient data transmission between the CPU module and the DSP module. The custom data packet header format includes: source address, destination address, data length, data type and check field.

10. The embedded heterogeneous platform system according to claim 8 or 9, characterized in that: The CPU module includes an application control module and a data exchange driver module; The application control module is used to analyze, process and control data according to the application scenario of the embedded system; The data exchange driver module is used to communicate with the FPGA module on the PCIe data channel to implement data read and write operations, flow control, and error handling; The DSP module includes a data processing module and a data exchange interface module; The data processing module is used to implement digital signal processing algorithms according to application requirements; The data exchange interface module is used to implement data request, send, receive and process functions according to the customized efficient transmission protocol of the SRIO data channel, and to exchange data with the FPGA module through the high-speed SRIO data channel to achieve fast data transmission.

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