Processor for writing memory from non-compliant memory tag extension devices using default tags and related methods

Abstract

The invention relates to a processor and a related method for writing memory from a device that does not conform to memory tag extension using default tags. A processor including a memory flag extension (MTE) provides default flag bits that will be used when an external device that does not comply with the MTE accesses memory circuitry (e.g., employing direct memory access (DMA)). The default flag bit is stored in the memory together with the data as a first flag bit. The processing circuitry may include a mode indicator indicating whether to use a default flag bit. In the first mode, the default flag bit is not used, and an abnormal signal can be immediately generated to respond to mismatch between the first flag bit and the second flag bit in the memory instruction. In the second mode, in response to a mismatch, the first flag bit is further compared to the default flag bit, and an error may be generated in response to a mismatch between the first flag bit and the default flag bit.

Description

Technical Field

[0001] The disclosed technology relates to a computing system that employs a memory system that employs a memory tagging function. Background Art

[0002] The Internet provides access to millions of computing devices for personal, business and government applications, cloud computing and cloud storage. Personal, financial and medical information of individuals as well as confidential information of businesses, governments and other non-governmental organizations are stored online with the expectation that it will be readily accessible to authorized personnel when needed. At the same time, there is an expectation that this information will be protected to prevent any unauthorized access attempts. Unfortunately, unauthorized access has been achieved in many ways. One way to gain unauthorized access to online data is to exploit weaknesses in the computing devices used to access, process and store the data. A well-known example of such a weakness is the ability to gain unauthorized access to memory locations. Specifically, malicious programs can exploit unintended features present in the instructions and architecture of processing devices to access memory locations that are not accessible without permission. Designers of processing devices and their architectures have developed many techniques and mechanisms to prevent unauthorized or accidental access to memory locations. An example of such a technique is the ARM Ltd.-based A class of processors in the Intel FPGA Architecture, called the memory tagging extension (MTE), is designed to detect memory safety violations. MTE employs "tag" bits stored in memory associated with memory addresses. However, some devices coupled to the same memory as a processing device that includes MTE may not be compliant with the MTE standard. Summary of the invention

[0003] Aspects disclosed herein include a processor that uses a default tag to write to memory from a device that does not comply with a memory tag extension (MTE). A related method for using a default tag to write to memory from a device that does not comply with MTE is also disclosed. In a processor including MTE, executing a memory access instruction to access a target memory address in a memory circuit includes obtaining a first tag bit associated with the memory address from the memory circuit and comparing the first tag bit with a second tag bit in the memory access instruction. The first tag bit can be accessed together with the data in a memory access operation. If an external device that stores data in a memory circuit (e.g., via direct memory access (DMA)) does not maintain the first tag bit, the memory circuit cannot remain compliant with MTE. An exemplary processor disclosed herein provides a default tag bit that is used when an external device that does not implement MTE accesses a memory circuit. In this case, the default tag bit is stored with the data (e.g., in a metadata field). During the execution of a memory access instruction, the first tag bit is compared with the second tag bit, and when there is a mismatch, the first tag bit can be compared with the default tag bit. In some examples, the processing circuit includes a mode indicator that indicates whether the default tag bit is adopted. In a first mode indicated by the mode indicator, in which the default mark bit is not adopted, an exception signal may be generated in response to a mismatch between the first mark bit and the second mark bit. In a second mode indicated by the mode indicator, in which the default mark bit is adopted, in response to a mismatch between the first mark bit and the second mark bit, the first mark bit is further compared with the default mark bit, and an exception signal may be generated in response to a mismatch between the first mark bit and the default mark bit.

[0004] In this regard, in an exemplary aspect, a system including a memory circuit is provided. The system also includes a processing circuit coupled to the memory circuit and configured to execute a memory access instruction to access a first memory address of the memory circuit. In response to the processing circuit executing the memory access instruction, the processing circuit is further configured to receive a first flag bit associated with the first memory address from the memory circuit; determine that the first flag bit is different from a second flag bit in the memory access instruction; and in response to a mode indicator indicating a first mode, compare the first flag bit with a default flag bit.

[0005] In another exemplary aspect, a processing circuit is configured to be coupled to a memory circuit and is configured to execute a memory access instruction to access a first memory address of the memory circuit. In response to the processing circuit executing the memory access instruction, the processing circuit is further configured to receive a first flag bit associated with the first memory address from the memory circuit; determine that the first flag bit is different from a second flag bit in the memory access instruction; and in response to a mode indicator indicating a first mode, compare the first flag bit with a default flag bit.

[0006] In another exemplary aspect, a method is provided in a system including a processing circuit coupled to a memory circuit. The method includes executing a memory access instruction to access a first memory address of the memory circuit. In response to the processing circuit executing the memory access instruction, the method also includes accessing a first flag bit associated with the first memory address; determining that the first flag bit is different from a second flag bit in the memory access instruction; and, in response to a mode indicator indicating a first mode, comparing the first flag bit to a default flag bit.

[0007] Those skilled in the art will understand the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0009] Figure 1 is a schematic diagram of an exemplary system including a processing circuit configured to access a memory circuit, wherein one of a first tag bit and a default tag bit is associated with each memory location and compared to an address tag bit in a memory instruction;

[0010] Figure 2 is a schematic diagram of a memory circuit, wherein a flag bit stored in association with each memory address may correspond to an address flag bit or a default flag bit;

[0011] Figure 3 is a flow chart of a method for determining whether a tag bit associated with a memory address matches an address tag bit or a default tag bit;

[0012] Figure 4 is a schematic diagram of an exemplary processing circuit configured to couple to a memory circuit and compare a tag bit associated with an accessed memory address to an address tag bit or a default tag bit; and

[0013] Figure 5 is a block diagram of an exemplary computer system that includes a processor including multiple CPU cores coupled to peripheral devices and other resources including a memory system, wherein each CPU core includes processing circuitry configured to determine whether a tag bit associated with a memory location matches an address tag bit or a default tag bit. DETAILED DESCRIPTION

[0014] With reference now to the drawings, several exemplary aspects of the present disclosure are described. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0015] Aspects disclosed herein include a processor that uses a default tag to write to memory from a device that does not comply with a memory tag extension (MTE). A related method for using a default tag to write to memory from a device that does not comply with MTE is also disclosed. In a processor including MTE, executing a memory access instruction to access a target memory address in a memory circuit includes obtaining a first tag bit associated with the memory address from the memory circuit and comparing the first tag bit with a second tag bit in the memory access instruction. The first tag bit can be accessed together with the data in a memory access operation. If an external device that stores data in a memory circuit (e.g., via direct memory access (DMA)) does not retain the first tag bit, the memory circuit cannot remain compliant with MTE. An exemplary processor disclosed herein provides a default tag bit that is used when an external device that does not implement MTE accesses a memory circuit. In this case, the default tag bit is stored with the data (e.g., in a metadata field). During the execution of a memory access instruction, the first tag bit is compared with the second tag bit, and when there is a mismatch, the first tag bit can be compared with the default tag bit. In some examples, the processing circuit includes a mode indicator that indicates whether the default tag bit is used. In a first mode indicated by the mode indicator, wherein the default flag bit is not adopted, an exception signal may be generated in response to a mismatch between the first flag bit and the second flag bit. In a second mode indicated by the mode indicator, wherein the default flag bit is adopted, in response to a mismatch between the first flag bit and the second flag bit, the first flag bit is further compared with the default flag bit, and an exception signal may be generated in response to a mismatch between the first flag bit and the default flag bit.

[0016] The architecture of the processor and processing circuit has been developed to include a memory tag function, which may be referred to as a memory tag extension (MTE) to improve data security in various devices and computing systems. Processors and processing circuits including MTE include processors and processing circuits with certain architectures provided by ARM Ltd., which may be referred to as "ARM architectures". MTE is an acronym that can be used specifically to refer to the ARM architecture, but is not intended to be so limited in this context, and generally refers to the memory tag function described herein. That is, although the acronym "MTE" may be used herein, other memory tag functions of designers or providers of ARM Ltd. or other processors, processing circuits and / or architectures are also included in the scope of the acronym MTE used herein. MTE includes the use of a "tag" or "tag bit" (e.g., metadata) associated with each cache line address in a memory circuit ("memory"). The tag bit can be used to verify whether access to a memory address is authorized. When a memory address is allocated for data storage, the tag bit can be determined by a tag creation circuit in a processor or memory controller. For example, the use of the tag bit can be determined by each process. Alternatively, or in addition, certain regions of memory may be provided with an additional level of data security implemented by MTE. However, even those regions that do not include additional data security may implement a tag bit in the processing circuitry that employs MTE.

[0017] Once the value of the tag bit is determined, two copies are retained. The first tag bit (the memory tag bit) is stored in association with a memory address in the memory circuit. MTE-specific instructions are used to set or modify the first tag bit. In addition, the second tag bit (the address tag bit) is tracked by the software that allocates the memory region and is used to obtain access to the data at the memory address. As described in more detail below, each time data in a cache line (e.g., at that memory address) is accessed (read or written), the first tag bit is retrieved along with the data (e.g., from the memory circuit). The second tag bit is included in the memory address of the memory access instruction. MTE improves data security because during a memory access instruction, the first tag bit stored in the memory circuit is compared with the second tag bit included in the target memory address of the memory access instruction. In this way, the tag bit can be used to verify whether the software thread or process attempting to access the data has the right or authorization to access the data. This feature prevents a memory access instruction directed to a first cache line from overlapping a second protected cache line. The "tag" used in MTE is a specific bit pattern (sometimes called a "color") attached to a specific memory region (a 16B aligned block in the specific case of the ARM MTE architecture). In this way, different data blocks belonging to one process and stored in adjacent memory locations can be marked with corresponding "colors" (tags) to ensure that the process does not access the wrong data. For example, data belonging to a first memory allocation block and stored in a first memory location can be marked with a "color" (tag) associated with the allocation block to ensure that a memory access intended to access a second allocation block with a different color will not succeed.

[0018] Figure 1 1 is a schematic diagram of a system 100 including a processing circuit 102 and a memory circuit 104 that employs a memory access extension (MTE). The processing circuit 102 is configured to execute a memory access instruction 106 to access a memory address in the memory circuit 104, and also access a first memory tag bit 108 associated with the memory address, the memory address corresponding to one of cache lines 110(0)-110(M). The processing circuit 102 may use the first memory tag bit 108 to determine whether the memory address is a cache line or not based on the MTE (e.g., The MTE of the architecture improves the security of data stored in the memory circuit 104. The memory access instruction 106 represents any type of memory access instruction executed by the processing circuit 102 for reading existing data 112 from the memory circuit 104 or writing new data 113 to the memory circuit 104. Regardless of whether the memory access instruction 106 is configured to read or write data at a memory address, execution of the memory access instruction first includes reading the first memory flag bit 108. The memory write instruction may also include reading the existing data 112 stored at the memory address before writing the new data 113 to the memory circuit 104.

[0019] System 100 includes memory control circuitry 114 ("memory controller 114") coupled between memory circuitry 104 and processing circuitry 102. Memory controller 114 also includes an interface 116 configured to couple to one of a plurality of external devices 118(1)-118(D) that are capable of using direct memory access (DMA) functionality to access data 112 in memory circuitry 104 without involvement of processing circuitry 102. In this regard, memory controller 114 may include DMA control circuitry (not shown). In an example not shown, memory controller 114 may include a plurality of interfaces 116, each interface 116 configured to couple to one of external devices 118(1)-118(D).

[0020] Figure 1 The memory circuits 104 in may be organized according to cache lines 110(0)-110(M), each cache line having a number X of bytes for storing data 112, where M may be any integer depending on the size of the memory circuits 104, and X may be driven by design choices, such as the number of instructions to be stored in each cache line 110(0)-110(M). Cache line 110(A) is described herein as a representative example of cache lines 110(0)-110(M). In addition to data 112, the X bytes of cache line 110(A) include at least one or more additional bytes to store parity and / or error correction control (ECC) bits 120 ("error control bits 120"). Figure 1 In the example of FIG. 1 , cache line 110(A) further includes a field 122 for storing memory flag bits 108. In some examples, the number of error control bits 120 stored in each cache line 110(0)-110(M) is reduced to make room for memory flag bits 108. This reduction in error control bits 120 may reduce data reliability in memory circuit 104. The first flag bits are located at the same location as the data, so they are always accessed along with the data. Therefore, DMA writes to the memory location are detected because they may overwrite the first flag bit.

[0021] In this regard, a brief reference Figure 2 , memory circuit 200 is another example of supporting MTE and can be used to replace Figure 1 Memory circuit 104 in system 100. Memory circuit 200 includes cache lines 202(0)-202(N). Memory circuit 200 differs from memory circuit 104 in the storage of memory flag bit 204, which corresponds to Figure 1Here, in order to maintain a certain level of error correction capability, the memory circuit 200 includes an additional storage circuit 206 that includes fields 208(0)-208(N), each of which provides storage for the memory flag bit 204 associated with one of the cache lines 202(0)-202(N), rather than occupying storage space that could alternatively be used for the error control bit 120. In an example where the system 100 is modified to include the memory circuit 200, there may be more than one embodiment of the present invention. Figure 1 In some examples, a corresponding one of fields 208(0)-208(N) is accessed in parallel with data 112 of an associated one of cache lines 202(0)-202(N). Alternatively, fields 208(0)-208(N) may be accessed individually.

[0022] Back to Figure 1 , an external device 118(1)-118(D) coupled to the memory circuit 104 may not support the MTE employed in the processing circuit 102. In addition, although not shown here, other internal devices may access the memory circuit 104, but are configured for MTE. Therefore, when data 112 is written to the memory circuit 104 from one of the external devices 118(1)-118(D), the memory flag bit 108 may remain unchanged or may be updated to have a value unknown to the software or process that has access to such data 112. Subsequently, if a memory access instruction employing MTE accesses the cache line 110(A), and the memory flag bit 108 is compared to the second address flag bit 124 included in the target memory address 126 of the memory access instruction 106 used to access the cache line 110(A), there may be a mismatch, resulting in the generation of an exception signal 128. The exception signal 128 may be a fault indication, an exception, or any other type of signal indicating that the first memory flag bit 108 has an unexpected value. However, the exemplary processing circuit 102 also includes a default flag register 130, which includes a default flag bit 132 and a default flag mode indicator 134, which is referenced in response to a mismatch between the memory flag bit 108 and the second address flag bit 124. That is, in response to determining that the memory flag bit 108 is different from the address flag bit 124, the processing circuit 102 checks the default flag mode indicator 134 to indicate the first mode or the second mode. It should be understood that the default flag register 130 is merely an example of a circuit for storing the default flag bit 132 and the default flag mode indicator 134, which can be stored in different registers or memory locations.

[0023] Figure 1The default mark mode indicator 134 in the byte indicates one of a first mode of the processing circuit 102 and a second mode of the processing circuit 102, wherein the default mark bit 132 is used in the first mode and the default mark bit 132 is not used in the second mode. In other words, Figure 1 The default flag mode indicator 134 in the second mode indicates whether the default flag mode in the processing circuit 102 is enabled or disabled, which determines whether the memory flag bit 108 is compared with the default flag bit 132. In some examples, the memory flag bit 108 can always be compared with the default flag bit 132, and the result of the comparison is ignored in the second mode.

[0024] The value or state of the default tag mode indicator 134 is provided to the memory controller 114. When the memory controller 114 receives new data 113 to be stored in the memory circuit 104 from one of the external devices 118(1)-118(D), and the default tag mode indicator 134 indicates that the processing circuit 102 is operating in the first mode (e.g., the default tag bit is enabled), the memory controller 114 sets the memory tag bit 108 in the field 122 of the accessed cache line 110(A) to the value of the default tag bit 132. As noted, in this example, the default tag bit 132 is stored in the default tag register 130, and thus the value of the default tag bit 132 may be configurable, including but not limited to being determined by firmware writing to the default tag register 130. For example, in system 100, memory flag bits 108 may be four (4) (or more or less) binary bits having any binary value from b'0000' (decimal 0) to b'1111 (decimal 15), and default flag bits 132 may be set to one of these values, such as b'1111'. Alternatively, when default flags are enabled, default flag bits 132 may be a predetermined (e.g., hardwired) value (e.g., a combination of binary digits) that is always used in the first mode. In the first mode, processing circuit 102 may not use the value of default flag bits 132 as one of the values ​​of memory flag bits 108 in field 122 in cache lines 110(0)-110(M).

[0025] In some architectures implementing MTE, monitoring software identifies a flag that is either available or unavailable. In the processing circuit 102, in the first mode, the value selected as the default flag may be identified as also being unavailable.

[0026] In this example, in response to executing the memory access instruction 106, the processing circuit 102 receives the memory flag bits 108 stored in the memory circuit 104 associated with the cache line 110 (A) at the memory address 126 that is the target of the memory access instruction 106. The processing circuit 102 determines whether the memory flag bits 108 match the address flag bits 124 in the memory access instruction 106. The processing circuit 102 also compares the memory flag bits 108 with the default flag bits 132 in the default flag register 130 in response to an indication of being in the first mode (e.g., an indication provided by the default flag mode indicator 134). The processing circuit 102 generates the exception signal 128 based on whether the memory flag bits 108 match one of the address flag bits 124 and the default flag bits 132.

[0027] In more detail, if the memory flag bit 108 matches the address flag bit 124, the memory access instruction is completed normally. If the memory flag bit 108 does not match the address flag bit 124, the indication of the default tag mode indicator 134 is checked, and in response to the indication of the first mode, the memory flag bit 108 is compared with the default tag bit 132. In the first mode, if the memory flag bit 108 matches the default tag bit 132, the memory access instruction can be completed normally. In addition, or alternatively, an alarm can be generated to note that a default tag bit is used in the target memory location. In the first mode, if the memory flag bit 108 is different from the default tag bit 132, an exception signal 128 is generated.

[0028] If the memory flag bits 108 do not match the address flag bits 124, and the default flag mode indicator 134 indicates that the processing circuit 102 is in the second mode, an exception signal 128 is generated independently of the default flag bits 132. In some examples, it is determined whether the memory flag bits 108 match the default flag bits 132 only in the first mode. In other examples, such a determination is made during each memory access operation, but the result can be ignored in the second mode. For example, the second mode can be adopted when the system 100 is not coupled to any external device or is not coupled to any device that does not comply with MTE.

[0029] In the first mode, if the memory flag bits 108 do not match the address flag bits 124, but the memory flag bits 108 match the default flag bits 132, then no exception signal 128 is generated. However, as described above, an alarm may be generated to track memory locations where the default flag bits 132 have been employed.

[0030] An example of where the memory flag bits 108 may not match the address flag bits 124 is when the data 112 accessed by the memory access instruction 106 executed in the processing circuit 102 was originally stored in the memory circuit 104 by one of the external devices 118(1)-118(D) that does not support MTE. When the data is written by one of the external devices 118(1)-118(D), the memory controller 114 stores the value of the default flag bits 132 as the memory flag bits 108 in the field 122. Therefore, based on the fact that the memory flag bits 108 do not match the address flag bits 124 but match the default flag bits 132, the memory controller 114 identifies the instance of data written to the memory circuit 104 by the external device 118(1)-118(D) and processes the data 112 rather than generating an exception. As described above, an alert may be generated in this case for tracking purposes.

[0031] Figure 3 is a flow chart illustrating a method 300 in a system 100 including a processing circuit 102 coupled to a memory circuit 104. The method 300 includes executing a memory access instruction 106 to access a first memory address 126 of the memory circuit 104 (block 302). The method 300 also includes, in response to executing the memory access instruction 106 (block 304), accessing a first flag bit 108 associated with the first memory address 126 (block 306) and determining that the first flag bit 118 is different from a second flag bit in the memory access instruction 106 (block 308). The method 300 also includes, in response to a mode indication indicating a first mode, comparing the first flag bit 108 to a default flag bit 132 (block 310).

[0032] Figure 4 is a schematic diagram of a processing circuit 400, which may be Figure 1 The processing circuit 102 in FIG. Figure 1 The description is presented to provide a non-limiting example of circuitry in processing circuit 400 that may be used to implement the default marking mode. Figure 1 and Figure 4 The common features can be found in Figure 4 Medium Figure 1 The processing circuit 400 includes an execution circuit 402 configured to execute or process instructions, including a memory access instruction 404 for accessing the memory circuit 104. The processing circuit 400 includes a default tag register 406 configured to store and Figure 14 and 5. The default mark mode indicator 408 and the default mark bit 410 corresponding to the default mark mode indicator 134 and the default mark bit 132 in the memory circuit 104 are shown in FIG. The default mark mode indicator 408 indicates one of a first mode (in which the use of the default mark bit 132 is enabled) and a second mode (in which the use of the default mark bit 132 is disabled). In the first mode, when data is stored in the memory circuit 104 by an external device that does not comply with the MTE standard (e.g., through a DMA operation), the memory controller 114 will use the default mark bit 410, as described above. In the second mode, the memory controller 114 does not use the default mark bit 410.

[0033] The default flag bit 410 and the default flag mode indicator 408 are provided to the memory controller 114 via outputs 412(B) and 412(I) from the processing circuit 400. The processing circuit 400 also includes a memory interface 414 configured to couple to the Figure 1 In response to executing the memory access instruction 404, whether data is read from the memory circuit 104 or written to the memory circuit 104, and according to the MTE, the memory tag bit 108 associated with the cache line 110 (A) at the target memory address 126 can be read from the memory circuit 104 through the memory interface 414.

[0034] The processing circuit 400 includes a tag checking circuit 418, which includes a first comparator circuit 422, which is configured to compare the memory tag bit 108 received from the memory circuit 104 with a second address tag bit 420, the second address tag bit 420 corresponding to Figure 1 The address marker in is 124. Although Figure 4 4. The default tag register 406 is shown to be within the tag check circuit 418, but in some examples, the default tag mode register 406 can be outside the tag check circuit 418. In some examples, the default tag bit 410 can be stored in a configuration register of the processing circuit 400. The first comparator circuit 422 determines whether the memory tag bit 108 matches the address tag bit 420 based on the comparison. In this context, a "match" occurs if the compared bits (e.g., the tag bit 108 and the address tag bit 420) are the same (i.e., exactly the same), or have an expected relationship to each other. When the compared bits are different, a mismatch occurs, where the memory tag bit 108 and the address tag bit 420 do not match. For example, when the memory tag bit 108 is different from the address tag bit 420, a mismatch signal 426 is generated.

[0035] exist Figure 4In the example shown, assume that the default mark mode indicator 408 stores a binary "0" in the second mode when the default mark bit 410 is not used. The default mark mode indicator 408 is coupled to an inverter 428 that generates a binary "1" in the second mode, and the inverter is coupled to an OR gate circuit 434. The output of the OR gate circuit 434 is coupled to an AND gate circuit 436. The mismatch signal 426 (indicating that the memory mark bit 108 is different from the address mark bit 420) is also coupled to the AND gate circuit 436. Therefore, when the processor circuit 400 is in the second mode (e.g., when the default mark bit is not used), the exception signal 128 can be generated in response to the mismatch signal 426.

[0036] On the other hand, Figure 4 In the example shown, it is assumed that when the default mark bit 410 is adopted, the default mark mode indicator 408 stores a binary "1" in the first mode. It should be recognized that the default mark mode indicator 408 can use any two values ​​to indicate the first mode and the second mode, and the logic circuit will be adjusted accordingly. In this case, the inverter 428 provides a binary "0" to the OR gate circuit 434, so the exception signal 128 is not generated based solely on the mismatch signal 426. Instead, the comparator circuit 432 also compares the memory mark bit 108 with the default mark bit 410. If the memory mark bit 108 does not match the default mark bit 410, a "1" is provided to the OR gate circuit 434 coupled to the AND gate circuit 436, as described above. Therefore, in the first mode, if the memory mark bit 108 does not match the address mark bit 420 and does not match the default mark bit 410, an exception signal 128 can be generated.

[0037] The exception signal 128 may cause the processing circuit 400 to take action, such as re-executing the memory access instruction 404, performing an error recovery process, and / or providing the exception signal 128 to a service processor. Figure 4 The specific implementation of the logic circuits shown in is merely one non-limiting example of how to provide the functionality described herein.

[0038] Figure 5 is a block diagram illustrating an example of a processor-based system 500, which may include a processor 502, as a non-limiting example. The processor-based system 500 may be Figure 1 The system 100 in FIG. 1 and the processor 502 may be Figure 1 Processor 502 includes a level 1 (L1) cache 506 and may access an L2 cache 508 via communications on a system bus 510. Processor 502 includes Figure 1 The default flag register 512 corresponds to the default flag register 130 in .

[0039] The system bus 510 may be busy communicating with other devices coupled to the system bus 510. Figure 5 As shown, these devices may include a memory array 516. Devices coupled to the system bus 510 may also include one or more input devices 518, one or more output devices 520, one or more network interface devices 522, and one or more display controllers 525, as examples. The input devices 518 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 520 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 522 may be any device configured to allow data to be exchanged with a network 526. The network 526 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), Bluetooth, or the like. TM Networks and the Internet. Network interface device 522 may be configured to support any type of communication protocol desired.

[0040] The processor 502 may also be configured to access a display controller 525 via the system bus 510 to control information sent to one or more displays 528. The display controller 525 sends information to be displayed to the display 528 via one or more video processors 530, which processes the information to be displayed into a format suitable for the display 528. The display 528 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0041] The memory array 516 of the processor-based system 500 may include a set of computer-readable instructions 532 stored in a non-transitory computer-readable medium 535 (e.g., memory) that the processor 502 may access and execute to perform tasks that require instructions and / or data from the memory array 516. These computer-readable instructions 532 may be stored in the non-transitory computer-readable medium 535. The computer-readable instructions 532 may also be sent or received over the network 526 via the network interface device 522, such that the network 526 includes the non-transitory computer-readable medium 535. The computer-readable instructions 532 may also be sent or received from the input device 518.

[0042] Although the non-transitory computer-readable medium 535 is shown as a single medium in the exemplary embodiment, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium that can store, encode, or carry a set of instructions for execution by a processing device and cause the processing device to perform any one or more of the methods in the embodiments disclosed herein. The term "computer-readable medium" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0043] Those skilled in the art will further recognize that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. For example, the initiator and target devices described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip. A processor is a circuit that may include a microcontroller, a microprocessor, or other circuits that may execute software or firmware instructions. A controller is a circuit that may include a microcontroller, a microprocessor, and / or a dedicated hardware circuit (e.g., a field programmable gate array (FPGA)), which does not necessarily execute software or firmware instructions. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information required. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above in general terms of functionality. How such functionality is implemented depends on the specific application, design choice, and / or design constraints imposed on the entire system. A skilled technician may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as causing a deviation from the scope of the present disclosure.

[0044] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0045] The aspects disclosed herein may be embodied in hardware and in instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of non-transitory computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0046] It should also be noted that the operation steps described in any exemplary aspect herein are used to provide examples and discussions. The operations may be performed in a variety of different orders other than the order shown. In addition, the operations described in a single operation step may actually be performed in a plurality of different steps. In addition, one or more operation steps discussed in the exemplary aspects may be combined. It should be understood that the operation steps shown in the flow chart may be modified in a variety of different ways, which is obvious to those skilled in the art. Those skilled in the art will also understand that any of a variety of different techniques and methods may be used to represent information and signals. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be cited in the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0047] The previous description of the present disclosure is provided to enable those skilled in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system, characterized in that: include: Memory circuits; as well as A processing circuit is coupled to the memory circuit and is configured to: executing a memory access instruction to access a first memory address of the memory circuit; as well as In response to executing the memory access instruction: receiving, from the memory circuit, a first flag bit associated with the first memory address; Determining that the first flag bit is different from a second flag bit in the memory access instruction; as well as In response to the mode indicator indicating the first mode, the first flag bit is compared with a default flag bit.

2. The system according to claim 1, characterized in that The processing circuit is further configured to generate an exception signal in response to the mode indicator indicating the second mode.

3. The system according to claim 1, characterized in that The processing circuit is also configured to generate an alarm in response to determining that the first flag bit matches the default flag bit.

4. The system according to claim 1, characterized in that The processing circuit is further configured to complete execution of the memory access instruction in response to determining that the first flag bit matches the default flag bit.

5. The system according to claim 1, characterized in that The processing circuit is further configured to generate an exception signal in response to determining that the first flag bit is different from the default flag bit.

6. The system according to claim 1, wherein: Also includes: A memory control circuit comprising an interface configured to be coupled to an external device, Wherein, the memory control circuit is configured as follows: receiving data over the interface for storage in the memory circuit; and The data and the default flag bit are stored in the memory circuit.

7. The system according to claim 6, characterized in that The memory control circuit includes a direct memory access (DMA) control circuit.

8. The system of claim 1, wherein: The processing circuit also includes a tag checking circuit configured to: comparing the first flag bit to the second flag bit to determine whether the first flag bit matches the second flag bit; and The first flag bit is compared with the default flag bit to determine whether the first flag bit matches the default flag bit.

9. A processing circuit, characterized in that: Configured to be coupled to the memory circuit, the processing circuit is configured to: executing a memory access instruction to access a first memory address of a memory circuit; and In response to executing the memory access instruction: receiving, from the memory circuit, a first flag bit associated with the first memory address; Determining that the first flag bit is different from a second flag bit in the memory access instruction; as well as In response to the mode indicator indicating the first mode, the first flag bit is compared with a default flag bit.

10. The processing circuit according to claim 9, characterized in that The processing circuit is further configured to generate an exception signal in response to the mode indicator indicating the second mode.

11. The processing circuit according to claim 9, characterized in that: The processing circuit is also configured to generate an alarm in response to determining that the first flag bit matches the default flag bit.

12. The processing circuit according to claim 9, characterized in that The processing circuit is also configured to complete execution of the memory access instruction in response to determining that the first flag bit matches the default flag bit.

13. The processing circuit according to claim 9, characterized in that: The processing circuit is further configured to generate an exception signal in response to determining that the first flag bit is different from the default flag bit.

14. The processing circuit according to claim 9, characterized in that Also includes: a first tag check circuit configured to compare the first tag bit with the second tag bit to determine whether the first tag bit matches the second tag bit; as well as The second flag check circuit is configured to compare the first flag bit with the default flag bit in response to the mode indicator indicating the first mode.

15. The processing circuit according to claim 13, characterized in that: Also included is a tag creation circuit configured to: determining the first flag bit corresponding to the first memory address, the first flag bit having a first value in a set of flag bit values; and In response to the mode indicator indicating the first mode, the value of the default flag bit is excluded from the set of flag bit values.

16. A method in a system comprising a processing circuit coupled to a memory circuit, characterized in that, The method includes: executing a memory access instruction to access a first memory address of the memory circuit; and In response to executing the memory access instruction: Accessing a first flag bit associated with the first memory address; Determining that the first flag bit is different from a second flag bit in the memory access instruction; and In response to the mode indicator indicating the first mode, the first flag bit is compared with a default flag bit.

17. The method according to claim 16, characterized in that Also included is generating an exception signal in response to the mode indicator indicating the second mode.

18. The method according to claim 16, characterized in that Also included is generating an alarm in response to determining that the first flag bit matches the default flag bit.

19. The method according to claim 16, characterized in that The method also includes, in response to determining that the first flag bit matches the default flag bit, completing execution of the memory access instruction.

20. The method of claim 16, wherein: The method also includes generating an abnormal signal in response to determining that the first mark bit is different from the default mark bit.

21. The method of claim 16, wherein: Also includes: receiving data to be stored in the memory circuit at an interface coupled to an external device; as well as The data is stored in the memory circuit, wherein the data includes the default flag bit.

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