Data processing device and processing method
By designing a data processing device in the storage control chip, using command queues, completion queues, command processing modules and DMA engine modules, the atomicity problem of non-aligned address operations during parallel operation of multiple CPUs is solved, and memory saving and CPU time-consuming optimization is achieved.
Patent Information
- Application Number
- CN202411899107.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-04-01
AI Technical Summary
When multiple CPUs operate in parallel in the memory control chip, the atomicity of 33-bit or above non-aligned address operations cannot be guaranteed, resulting in memory waste and increased CPU operation time.
A data processing device is designed, including M command queues, M completion queues, command processing module and DMA engine module. The command arbitration module arbitrates the command queue, calculates the operation address, splits the table entry into a 32-bit primary table and an N-bit secondary table, and performs 32-bit reading and writing through the DMA engine module to ensure the atomicity of the operation.
The atomicity of multi-CPU processing non-32-bit alignment table operations in the memory control chip is realized, avoiding additional memory usage and saving CPU operation time.
Smart Images
Figure CN119739655A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer storage technology, and in particular to a data processing device and a processing method. Background Art
[0002] As the capacity of storage devices increases, the mapping table from logical addresses to physical addresses also increases. When the capacity of storage devices increases to 16T bytes, the general mapping granularity is 4K bytes, and the number of table entries reaches 16TB / 4KB>232 items. Then each table entry needs at least 33 bits to meet the addressing requirements. The increase in channel capacity will continue to increase the size requirements of table entries. We noticed that 33-bit addresses are non-aligned accesses for current CPU accesses. The CPU generally only supports 4-bit / 8-bit / 16-bit / 32-bit / 64-bit memory or cache accesses. The 33-bit address CPU needs to be split into 2 access operations, such as 2 32-bit accesses. If it is a 34-bit address, the CPU needs to be split into 2 to 3 32-bit accesses to complete the operation. At present, storage control chips are all multi-CPU structures. When there are multiple CPUs operating in parallel, the atomicity of 33-bit and above operations cannot be guaranteed. Of course, this problem can be solved by expanding the table entries to 64 bits, so that each table entry address is aligned, and the CPU only needs a 64-bit access to complete the operation. However, this will waste 48% of the memory for a 33-bit table and 47% of the memory space for a 34-bit table. The waste of a large amount of memory space will lead to a significant increase in material costs. In addition, the number of memory particles placed on the PCB board will increase, resulting in an increase in area and difficulty in layout and wiring. Summary of the invention
[0003] In order to overcome the deficiencies of the above technologies, the present invention provides a data processing device and method for preventing the CPU in a storage control chip from directly reading and writing 33-bit or above non-aligned addresses, ensuring the atomicity of operations, and releasing the CPU computing power.
[0004] The technical solution adopted by the present invention to overcome the technical problems is: A data processing device, comprising: M command queues, each command queue corresponds to a CPU, and is used to store the commands configured by the corresponding CPU of the control chip; M completion queues, each of which corresponds to a CPU and is used to store the corresponding CPU acquisition completion information of the control chip; The command processing module uses the command arbitration module to arbitrate each command queue, obtains a command from the M command queues and parses the command. The command processing module calculates the operation address according to the operation address offset of the command, splits the table entry into a 32-bit main table and an N-bit secondary table according to the operation address, writes the 32-bit main table and the N-bit secondary table into the completion queue corresponding to the command queue, and sends an interrupt signal to notify the CPU; The DMA engine module has several DMA engines, each of which works in parallel. The DMA engine module performs 32-bit reading and writing of the memory.
[0005] Furthermore, each command queue is independent of each other.
[0006] Furthermore, the fields of each command queue include: command sequence number, command type, operation address offset, operand, the command types include: read, write, add, subtract, XOR, compare and exchange, the operand is 64 bits long, and the operand is configured through the configuration module.
[0007] Furthermore, each completion queue is independent of each other.
[0008] Furthermore, the fields of each completion queue include: command sequence number, command type, result status, and result data. The command types include: read, write, add, subtract, XOR, and exchange after comparison. The result status is normal completion or abnormal completion. The result data is 64 bits long, and the result data is configured through the configuration module.
[0009] Furthermore, the command processing module calculates the operation address according to the operation address offset, and splits the table entry into a 32-bit main table and an N-bit secondary table according to the operation address as follows: The main table offset address is calculated according to the formula: main table offset address = main table base address + 32 / 8 * operation address offset; The secondary table offset address is calculated according to the formula: secondary table offset address = secondary table base address + N * operation address offset / 32; The offset bit in the secondary table offset address is calculated according to the formula: offset bit in secondary table offset address = N * operation address offset % 32. Operation address offset % 32 means the operation address offset modulo 32. If the main table offset address of the command is the same as the main table offset address of the unfinished command and the secondary table offset of the command is the same as the main table offset address of the unfinished command, it is determined to be overlapped, and the command waits for the previous unfinished command to be completed before processing; The DMA arbitration module is used to call the specified DMA engine module to modify the 32-bit data corresponding to the 32-bit main table and the N-bit data corresponding to the secondary table. Corresponding to the X-bit table entry, the DMA engine module reads the 32-bit data of the secondary table offset address, and after modifying the N-bit data of the offset position in the secondary table offset address, the DMA engine module writes the 32-bit data back to the memory secondary table offset address.
[0010] Furthermore, it also includes a configuration module for configuring the number and depth of command queues, configuring the number and depth of completion queues, configuring the number of DMA engines, configuring the main table base address, configuring the secondary table base address, configuring the number of table item bits, and configuring interrupt signals.
[0011] On the other hand, the present invention also relates to a data processing method, characterized in that it comprises the following steps: S1. Complete the configuration of the number and depth of command queues through the configuration module, complete the configuration of the number and depth of completion queues, complete the configuration of the number of DMA engines, complete the configuration of the main table base address, complete the configuration of the secondary table base address, and complete the configuration of the number of table entry bits; S2. When the CPU operates the unaligned table, the command sequence number, command type, operation address offset, and operand field in the configuration command are written into the command queue corresponding to the CPU; S3. The command processing module uses the command arbitration module to arbitrate each command queue, obtains a command from the M command queues and parses the command. The command processing module calculates the operation address according to the operation address offset of the command, splits the table entry into a 32-bit main table and an N-bit secondary table according to the operation address, writes the 32-bit main table and the N-bit secondary table into the completion queue corresponding to the command queue, and sends an interrupt signal to notify the CPU; S4. The command processing module forms a completion message command number, command type, result status, result data field according to the operation result and writes it to the completion queue corresponding to the command queue; S5.CPU reads the completion queue and obtains the completion result.
[0012] Furthermore, in step S4, an interrupt signal is triggered after writing into the completion queue, and the CPU reads the completion queue after receiving the interrupt signal.
[0013] The beneficial effects of the present invention are: solving the problem of how to ensure the atomicity of multi-CPU processing non-32-bit alignment table operations in the storage control chip, avoiding additional memory occupation, saving CPU operation time, avoiding the CPU in the storage control chip directly reading and writing 33-bit and above non-aligned addresses, ensuring the atomicity of the operation, and releasing the CPU computing power. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a structural diagram of the device of the present invention; Figure 2 is a flow chart of the non-aligned operation of the present invention; Figure 3 The present invention is a flow chart of the method. DETAILED DESCRIPTION
[0015] The following is combined with Figure 1 , Attachment Figure 2 , Attachment Figure 3 The present invention is further described.
[0016] Example 1 A data processing device, such as Figure 1 As shown, including: There are M command queues, each command queue corresponds to a CPU, and is used to store commands configured by the corresponding CPU of the control chip.
[0017] There are M completion queues, each of which corresponds to a CPU and is used to store the completion information obtained by the corresponding CPU of the control chip.
[0018] The command processing module uses the command arbitration module to arbitrate each command queue, obtains a command from M command queues and parses the command. The command processing module calculates the operation address according to the operation address offset of the command, splits the table entry into a 32-bit main table and an N-bit secondary table according to the operation address, writes the 32-bit main table and the N-bit secondary table into the completion queue corresponding to the command queue and triggers an interrupt signal to notify the CPU, N = the number of table entry bits - 32.
[0019] The DMA engine module has several DMA engines, each of which works in parallel. The DMA engine module performs 32-bit reading and writing of the memory.
[0020] In this embodiment, each command queue is independent of each other.
[0021] In this embodiment, the fields of each command queue include: command sequence number, command type, operation address offset (i.e., the number of table entries starting from the base address of the mapping table), operand, the command types include: read, write, add, subtract, XOR, compare and exchange, the operand is 64 bits long, and the operand is configured through the configuration module, such as the number to be written for write operation and the number to be added for add operation. The command sequence number is non-repetitive and is configured by the user so as to check the correspondence between the completion message and the command in the completion queue.
[0022] In this embodiment, the completion queues are independent of each other.
[0023] In this embodiment, the fields of each completion queue include: command sequence number, command type, result status, and result data. The command types include: read, write, add, subtract, XOR, and exchange after comparison. The result status is normal completion or abnormal completion. The result data is 64 bits long. The result data is configured through the configuration module, such as placing read data during a read operation.
[0024] In this embodiment, as shown in the attached Figure 2 As shown, the command processing module calculates the operation address according to the operation address offset, and splits the table entry into a 32-bit main table and an N-bit secondary table according to the operation address as follows: The main table offset address is calculated according to the formula: main table offset address = main table base address + 32 / 8 * operation address offset. The main table offset address unit is byte.
[0025] The secondary table offset address is calculated according to the formula: secondary table offset address = secondary table base address + N * operation address offset / 32. The secondary table offset address unit is byte.
[0026] The offset bit in the secondary table offset address is calculated according to the formula: offset bit in secondary table offset address = N * operation address offset % 32, where operation address offset % 32 means the operation address offset modulo 32. The unit of the offset bit in the secondary table offset address is bit.
[0027] If the main table offset address of the command is the same as the main table offset address of the unfinished command, it is determined to be overlapped, and the command waits for the previous unfinished command to be processed after completion. If the main table offset address of the command is the same as the main table offset address of the unfinished command and the secondary table offset address of the command is the same as the secondary table offset address of the unfinished command, it is determined to be overlapped.
[0028] The DMA arbitration module is used to call the specified DMA engine module to modify the 32-bit data corresponding to the 32-bit main table and the N-bit data corresponding to the secondary table. Corresponding to the X-bit table entry, the DMA engine module reads the 32-bit data of the secondary table offset address, and after modifying the N-bit data of the offset position in the secondary table offset address, the DMA engine module writes the 32-bit data back to the memory secondary table offset address.
[0029] In this embodiment, it also includes a configuration module for configuring the number and depth of command queues, configuring the number and depth of completion queues, configuring the number of DMA engines, configuring the main table base address, configuring the secondary table base address, configuring the number of table entry bits, and configuring interrupt signals.
[0030] Example 2 A data processing method, characterized in that it comprises the following steps: S1. Complete the configuration of the number and depth of command queues through the configuration module, complete the configuration of the number and depth of completion queues, complete the configuration of the number of DMA engines, complete the configuration of the main table base address, complete the configuration of the secondary table base address, and complete the configuration of the number of table entry bits; S2. When the CPU operates the unaligned table, the command sequence number, command type, operation address offset, and operand field in the configuration command are written into the command queue corresponding to the CPU; S3. The command processing module uses the command arbitration module to arbitrate each command queue, obtains a command from the M command queues and parses the command. The command processing module calculates the operation address according to the operation address offset of the command, splits the table entry into a 32-bit main table and an N-bit secondary table according to the operation address, writes the 32-bit main table and the N-bit secondary table into the completion queue corresponding to the command queue, and sends an interrupt signal to notify the CPU; S4. The command processing module forms a completion message command number, command type, result status, result data field according to the operation result and writes it to the completion queue corresponding to the command queue; S5.CPU reads the completion queue and obtains the completion result.
[0031] In this embodiment, in step S4, an interrupt signal is triggered after writing into the completion queue, and the CPU reads the completion queue after receiving the interrupt signal.
[0032] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A data processing device, characterized in that: include: M command queues, each command queue corresponds to a CPU, and is used to store the commands configured by the corresponding CPU of the control chip; M completion queues, each of which corresponds to a CPU and is used to store the corresponding CPU acquisition completion information of the control chip; The command processing module uses the command arbitration module to arbitrate each command queue, obtains a command from the M command queues and parses the command. The command processing module calculates the operation address according to the operation address offset of the command, splits the table entry into a 32-bit main table and an N-bit secondary table according to the operation address, writes the 32-bit main table and the N-bit secondary table into the completion queue corresponding to the command queue, and sends an interrupt signal to notify the CPU; The DMA engine module has several DMA engines, each of which works in parallel. The DMA engine module performs 32-bit reading and writing of the memory.
2. The data processing device according to claim 1, characterized in that: Each command queue is independent of each other.
3. The data processing device according to claim 1, characterized in that: The fields of each command queue include: command sequence number, command type, operation address offset, operand, the command type includes: read, write, add, subtract, XOR, compare and exchange, the operand is 64 bits long, and the operand is configured through the configuration module.
4. The data processing device according to claim 1, characterized in that: Each completion queue is independent of each other.
5. The data processing device according to claim 1, characterized in that: The fields of each completion queue include: command sequence number, command type, result status, result data, the command types include: read, write, add, subtract, XOR, compare and exchange, the result status is normal completion or abnormal completion, the result data is 64 bits long, and the result data is configured through the configuration module.
6. The data processing device according to claim 1, characterized in that: The command processing module calculates the operation address according to the operation address offset, and splits the table entry into a 32-bit main table and an N-bit secondary table according to the operation address as follows: The main table offset address is calculated according to the formula: main table offset address = main table base address + 32 / 8 * operation address offset; The secondary table offset address is calculated according to the formula: secondary table offset address = secondary table base address + N * operation address offset / 32; The offset bit in the secondary table offset address is calculated according to the formula: offset bit in secondary table offset address = N * operation address offset % 32. Operation address offset % 32 means the operation address offset modulo 32. If the main table offset address of the command is the same as the main table offset address of the unfinished command, it is determined to be overlapped, and the command waits for the previous unfinished command to be completed and then processed; The DMA arbitration module is used to call the specified DMA engine module to modify the 32-bit data corresponding to the 32-bit main table and the N-bit data corresponding to the secondary table. Corresponding to the X-bit table entry, the DMA engine module reads the 32-bit data of the secondary table offset address, and after modifying the N-bit data of the offset position in the secondary table offset address, the DMA engine module writes the 32-bit data back to the memory secondary table offset address.
7. The data processing device according to claim 6, characterized in that: It also includes a configuration module for configuring the number and depth of command queues, configuring the number and depth of completion queues, configuring the number of DMA engines, configuring the main table base address, configuring the secondary table base address, configuring the number of table entries, and configuring interrupt signals.
8. A data processing method using a data processing device according to any one of claims 1 to 6, characterized in that: The steps include: S1. Complete the configuration of the number and depth of command queues through the configuration module, complete the configuration of the number and depth of completion queues, complete the configuration of the number of DMA engines, complete the configuration of the main table base address, complete the configuration of the secondary table base address, and complete the configuration of the number of table entry bits; S2. When the CPU operates the unaligned table, the command sequence number, command type, operation address offset, and operand field in the configuration command are written into the command queue corresponding to the CPU; S3. The command processing module uses the command arbitration module to arbitrate each command queue, obtains a command from the M command queues and parses the command. The command processing module calculates the operation address according to the operation address offset of the command, splits the table entry into a 32-bit main table and an N-bit secondary table according to the operation address, writes the 32-bit main table and the N-bit secondary table into the completion queue corresponding to the command queue, and sends an interrupt signal to notify the CPU; S4. The command processing module forms a completion message command number, command type, result status, result data field according to the operation result and writes it to the completion queue corresponding to the command queue; S5.CPU reads the completion queue and obtains the completion result.
9. The data processing method according to claim 8, characterized in that: In step S4, an interrupt signal is triggered after writing into the completion queue, and the CPU reads the completion queue after receiving the interrupt signal.