Internal integrated circuit bus system, address conflict processing method and product

Abstract

The invention relates to the technical field of servers, and discloses an internal integrated circuit bus system, an address conflict processing method and a product. The system comprises an I2C bus, a conflict processing unit and an address configuration unit, the I2C bus is connected to the BMC, the at least one first slave device and the external plug-in card; a second slave device is integrated in the external plug-in card; the conflict processing unit comprises a control circuit between the BMC and each first slave device; the BMC is used for cutting off power supply of all the first slave devices through the control circuit or cutting off links, connected to the I2C bus, of all the first slave devices through the control circuit; the address configuration unit comprises configuration circuits of which the number is the same as that of all the first slave devices; and the BMC is also used for sending a first signal to the first slave device to modify the address of the first slave device under the condition that the address conflict between any first slave device and the second slave device is detected. According to the method and the device, the address conflict problem in the I2C bus can be detected and self-repaired.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to an internal integrated circuit bus system, an address conflict processing method and a product. Background Art

[0002] The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus that includes a serial data line SDA and a serial clock line SCL, which transmits information between I2C devices connected to the I2C bus. Each device on the I2C bus has a unique 7-bit binary address. The slave devices connected to the I2C bus communicate with the host by identifying the address code sent by the master device and responding to it.

[0003] In the server field, BMC (Baseboard Management Controller) is usually used as the master device of the I2C bus, and BMC manages the server through the I2C bus. For I2C devices deployed on the motherboard, the address of the device can be modified by setting the address configuration pin on the device. AIC (Add-in Card) is a commonly used expansion device in the server, which usually integrates some external I2C devices and is connected to the I2C bus of the server through the interface on the PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) slot of the add-in card. For the add-in card, BMC cannot modify its address. Since the device inserted in the add-in card is usually purchased or configured by the user, there is a probability of address conflict with the I2C device on the motherboard. If there are two or more devices with the same address on the I2C bus, it will cause a bus error, unable to communicate normally, causing server failure and affecting business operation. Therefore, it is necessary to find a method to avoid address conflicts in the I2C bus and improve the stability of server operation. Summary of the invention

[0004] In view of this, the present application aims to propose an internal integrated circuit bus system, an address conflict processing method and a product to avoid address conflicts in the internal integrated circuit bus and improve the stability of server operation.

[0005] To achieve the above purpose, the technical solution of this application is as follows:

[0006] A first aspect of an embodiment of the present application provides an internal integrated circuit bus system, comprising: an internal integrated circuit bus, a conflict handling unit, and an address configuration unit;

[0007] The internal integrated circuit bus is connected to: a baseboard management controller, at least one first slave device and an external plug-in card; at least one second slave device is integrated in the external plug-in card;

[0008] The conflict processing unit includes a control circuit between the baseboard management controller and each first slave device; the baseboard management controller is used to cut off the power supply of all the first slave devices through the control circuit, or cut off the link connecting all the first slave devices to the internal integrated circuit bus through the control circuit before detecting whether there is an address conflict between the first slave device and the second slave device;

[0009] The address configuration unit includes configuration circuits having the same number as all the first slave devices, and each first slave device is connected to the baseboard management controller via a first signal line; the baseboard management controller is further used to send a first signal to the first slave device via the first signal line to modify the address of the first slave device when an address conflict is detected between any first slave device and any second slave device.

[0010] Optionally, a protection chip is provided in the control circuit;

[0011] Each first slave device is connected to the protection chip respectively, and the protection chip is also connected to the mainboard power supply;

[0012] The baseboard management controller is connected to the protection chip through a second signal line; the baseboard management controller is specifically used to send a second signal through the second signal line to control the protection chip to cut off or restore its own output power supply.

[0013] Optionally, cutting off the power supply of all first slave devices by the control circuit specifically includes: setting the second signal to a low level to control the protection chip to cut off the power supply of the mainboard power supply to the first slave devices;

[0014] The baseboard management controller is also used to restore the power supply of all the first slave devices through the control circuit when it is detected that there is no address conflict between all the first slave devices and the second slave devices, specifically including: setting the second signal to a high level to control the protection chip to restore the power supply of the mainboard power supply to the first slave devices.

[0015] Optionally, the control circuit is provided with: transistors having the same number as that of all first slave devices;

[0016] The baseboard management controller is connected to the G pole of each transistor through a third signal line; the D pole of each transistor is connected to the internal integrated circuit bus, and the S pole of each transistor is connected to a first slave device;

[0017] The baseboard management controller is specifically used to send a third signal through the third signal line to control the transistor to be in an on state or an off state.

[0018] Optionally, cutting off the links connecting all the first slave devices to the internal integrated circuit bus by the control circuit specifically includes: setting the third signal to a low level so that the transistors in the links connecting the first slave devices to the internal integrated circuit bus are in a cut-off state;

[0019] The baseboard management controller is also used to restore the links connecting all the first slave devices to the internal integrated circuit bus through the control circuit when it is detected that there is no address conflict between all the first slave devices and the second slave devices, specifically including: setting the third signal to a high level so that the transistors in the links connecting each first slave device to the internal integrated circuit bus are in an on state.

[0020] Optionally, the configuration circuit is provided with: a mainboard power supply, a transistor, a pull-up resistor and a pull-down resistor; the baseboard management controller is connected to the G pole of the transistor through a first signal line; one end of the pull-up resistor is connected to the mainboard power supply, and the other end is connected to the D pole of the transistor; one end of the pull-down resistor is connected to the S pole of the transistor, and the other end is connected to an address configuration pin of a first slave device;

[0021] Sending a first signal to the first slave device through the first signal line to modify the address of the first slave device includes:

[0022] Acquire the current address of the first slave device; the address of the first slave device is determined based on the level state of the address configuration pin of the first slave device;

[0023] Based on the current address of the first slave device, determining a transistor in a configuration circuit connected to an address configuration pin of the first slave device;

[0024] Modifying the first signal output to the transistor so that the level state of the address configuration pin connected to the transistor is switched specifically includes:

[0025] The first signal is set to a high level, so that the transistor is in a conducting state, the address configuration pin is connected to the mainboard power supply through the pull-up resistor, and the level state of the address configuration pin is switched to a high level;

[0026] Or, the first signal is set to a low level so that the transistor is in a cut-off state, the address configuration pin of the first slave device is grounded through the pull-down resistor, and the level state of the address configuration pin is switched to a low level.

[0027] Optionally, the first slave device carries one or three address configuration pins; in the configuration circuit, the number of pull-down resistors is the same as the number of address configuration pins carried by the first slave device.

[0028] Optionally, a resistance ratio of the pull-up resistor to the pull-down resistor is 1:10.

[0029] According to a second aspect of an embodiment of the present application, there is provided an address conflict handling method, which is applied to the internal integrated circuit bus system provided in the first aspect of the embodiment of the present application, and the method includes:

[0030] After the server is powered on, each first slave device is controlled to initialize its own address;

[0031] Reading and storing the addresses of all first slave devices through the baseboard management controller;

[0032] Cutting off the power supply of all first slave devices by the control circuit, or cutting off the links connecting all first slave devices to the internal integrated circuit bus by the control circuit;

[0033] Reading the addresses of all the second devices, and detecting whether there is an address conflict between all the first slave devices and all the second slave devices;

[0034] In the case that there is an address conflict between any first slave device and any second slave device, a first signal is sent to the first slave device through a first signal line to modify the address of the first slave device.

[0035] According to a third aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the address conflict handling method described in the second aspect of the embodiment of the present application are implemented.

[0036] According to the fourth aspect of the embodiments of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps in the address conflict handling method described in the second aspect of the embodiments of the present application are implemented.

[0037] The internal integrated circuit bus system provided in the present application includes an I2C bus, a conflict handling unit and an address configuration unit. Among them, the I2C bus is connected to a baseboard management controller (BMC), one or more first slave devices (slave devices on the mainboard) and an external card, and one or more second slave devices (external slave devices) are integrated in the external card. The conflict handling unit includes a control circuit between the BMC and each first slave device. In this solution, the BMC will perform address conflict detection on the first slave device and the second slave device, and control all first slave devices to stop running through the control circuit before detection, thereby isolating the first slave device from the second slave device. In the case of an address conflict between the first slave device and the second slave device, the BMC also modifies the address of the first slave device with the address conflict through the configuration circuit in the address configuration unit to achieve address conflict repair.

[0038] In the present application, a conflict processing unit is used to isolate the first slave device on the mainboard before confirming that there are no duplicate addresses on the I2C bus, so as to avoid malfunctions caused by devices with address conflicts running together. After isolating the first slave device, if there is an address conflict, the address of the first slave device is modified by configuring the circuit to repair the address conflict on the bus, thereby realizing detection and self-repair of address conflict problems in the I2C bus, avoiding management failure of the server due to address conflicts in the I2C bus, and improving the stability of the server. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0040] Figure 1 This is a schematic diagram of the I2C bus architecture in the server;

[0041] Figure 2 is a framework diagram of an internal integrated circuit bus system proposed in one embodiment of the present application;

[0042] Figure 3 This is one of the schematic diagrams of the architecture of the I2C bus system proposed in one embodiment of the present application;

[0043] Figure 4 This is the second schematic diagram of the architecture of the I2C bus system proposed in one embodiment of the present application;

[0044] Figure 5 is a schematic diagram of a configuration circuit in an embodiment of the present application;

[0045] Figure 6 is a flow chart of an address conflict handling method proposed in an embodiment of the present application;

[0046] Figure 7 It is a schematic diagram of an electronic device proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] It should be understood that the references to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0049] In the various embodiments of the present application, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0050] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects as detailed in the present application.

[0051] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0052] Figure 1 This is a schematic diagram of the I2C bus architecture in the server. Figure 1As shown, an I2C bus architecture is shown, and the I2C bus is connected to the slave devices (1, 2, 3) on the mainboard side and the external slave devices (a, b, c) integrated in the plug-in card. In the related art, before the server leaves the factory, when configuring the addresses of the slave devices 1, 2, and 3 on the mainboard side including the plug-in card, in order to avoid address conflicts, an exhaustive method is used to list all possible AIC cards, and the addresses of the I2C devices that may be integrated thereon are determined, and the addresses of the slave devices 1, 2, and 3 are configured based on this, so that the addresses of the various devices are different. However, due to the wide variety of types and models of AIC cards, the addresses of the I2C devices that can be selected thereon are also varied, and the use of an exhaustive method cannot ensure that there will be no address conflicts. The model of the plug-in card that the server presets to use before leaving the factory is not necessarily the same as the model after leaving the factory. After the server leaves the factory, the user may reconfigure and replace the new AIC card, so it is difficult to avoid address conflicts on the I2C bus. Once an address conflict occurs, the communication between devices on the entire bus will not be able to proceed normally, and the BMC will not be able to manage the server. For example, when a temperature sensor is set in the I2C bus, the BMC cannot read the temperature and cannot adjust the heat dissipation, resulting in serious problems such as overheating of the server.

[0053] The internal integrated circuit bus system provided by the present application can avoid address conflicts in the I2C bus, thereby preventing the BMC from failing to manage the server due to address conflicts in the I2C bus.

[0054] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0055] Figure 2 1 is a schematic diagram of an internal integrated circuit bus system according to an embodiment of the present application. Figure 2 As shown, the internal integrated circuit bus system includes: an internal integrated circuit bus, a conflict processing unit and an address configuration unit;

[0056] The internal integrated circuit bus is connected to: a baseboard management controller, at least one first slave device and an external plug-in card; at least one second slave device is integrated in the external plug-in card;

[0057] The conflict processing unit includes a control circuit between the baseboard management controller and each first slave device; the baseboard management controller is used to cut off the power supply of all the first slave devices through the control circuit, or cut off the link connecting all the first slave devices to the internal integrated circuit bus through the control circuit before detecting whether there is an address conflict between the first slave device and the second slave device;

[0058] The address configuration unit includes configuration circuits having the same number as all the first slave devices, and each first slave device is connected to the baseboard management controller via a first signal line; the baseboard management controller is further used to send a first signal to the first slave device via the first signal line to modify the address of the first slave device when an address conflict is detected between any first slave device and any second slave device.

[0059] In this embodiment, the internal integrated circuit bus system includes an I2C bus, a conflict handling unit, and an address configuration unit. Among them, the I2C bus is connected to the BMC, one or more first slave devices, and an external card. One or more second slave devices are inserted into the slot of the external card. The first slave device is a slave device deployed on the mainboard before the server leaves the factory, and the second slave device is an external slave device. Common first slave devices include: a temperature sensor chip for temperature monitoring, a FRU (Field Replaceable Unit) chip for board information storage, a power monitoring chip for monitoring power supply, etc. Common external cards include: GPU (Graphics Processing Unit, graphics processor) card, FPGA (Field Programmable Gate Array, field programmable logic array) card, NIC (Network Interface Card, network card) and storage expansion card, etc.

[0060] The BMC controls the conflict handling unit to isolate the first slave device on the mainboard to avoid running the first slave device and the second slave device at the same time when there is an address conflict between the first slave device and the second slave device, which causes an I2C bus failure. The conflict handling unit includes a control circuit between the BMC and each first slave device. After the server is powered on, the BMC controls all first slave devices to stop running through the control circuit so as to detect the addresses of all first slave devices and second slave devices in the bus and determine whether there is an address conflict between the first slave device and the second slave device in the bus. In the case of an address conflict, the address of the conflicting first slave device is modified accordingly through the configuration circuit in the address configuration unit.

[0061] The address configuration unit includes a plurality of configuration circuits, wherein the number of the configuration circuits is the same as the number of first slave devices in the bus, and the BMC is connected to a first slave device through each configuration circuit. A first signal line is provided in each configuration circuit, and the BMC sends a first signal to the first slave device whose address needs to be modified through the first signal line to modify the address of the first slave device, thereby repairing the address conflict problem in the I2C bus.

[0062] In this embodiment, the BMC, as the master device on the I2C bus, implements isolation operation on all first slave devices through the conflict processing unit, so as to avoid running the first slave device and the second slave device at the same time without detecting whether there is a conflict in the address. When a conflict is detected between the addresses of the first slave device and the second slave device, the address of the conflicting first slave device is modified by configuring the circuit, so as to repair the address conflict, thereby realizing the detection and self-repair of the address conflict problem in the I2C bus, avoiding the management failure of the server due to the address conflict in the I2C bus, and improving the stability of the server.

[0063] As an implementation mode of the present application, a protection chip is provided in the control circuit;

[0064] Each first slave device is connected to the protection chip respectively, and the protection chip is also connected to the mainboard power supply;

[0065] The baseboard management controller is connected to the protection chip through a second signal line; the baseboard management controller is specifically used to send a second signal through the second signal line to control the protection chip to cut off or restore its own output power supply.

[0066] Figure 3 This is one of the schematic diagrams of the architecture of the I2C bus system proposed in one embodiment of the present application. Figure 3 As shown, in one embodiment, the I2C bus is connected to the BMC, three first slave devices (slave device 1, slave device 2, slave device 3) and three second slave devices (slave device a, slave device b, slave device c). A protection chip is provided in the control circuit for powering device 1, slave device 2, and slave device 3. The input of the protection chip is connected to the mainboard power supply, and the output is connected to each first slave device. The BMC accesses the protection chip through the second signal line, and controls the protection chip to output the mainboard power supply to each first slave device by sending a second signal to the protection chip, or cuts off the mainboard power supply to each first slave device.

[0067] As an implementation mode of the present application, cutting off the power supply of all first slave devices by the control circuit specifically includes: setting the second signal to a low level to control the protection chip to cut off the power supply of the mainboard power supply to the first slave device;

[0068] The baseboard management controller is also used to restore the power supply of all the first slave devices through the control circuit when it is detected that there is no address conflict between all the first slave devices and the second slave devices, specifically including: setting the second signal to a high level to control the protection chip to restore the power supply of the mainboard power supply to the first slave devices.

[0069] In one embodiment, a protection chip is provided in the control circuit, and its output is connected to all first slave devices at the same time. The baseboard management controller sends a second signal to control the protection chip to uniformly cut off or uniformly restore the power supply to all first slave devices. In this embodiment, the addresses of the first slave devices and the second slave devices in the bus are detected by the control circuit, and the specific steps are as follows:

[0070] (1) After the server is turned on, each first slave device initializes its own communication address through the pull-up and pull-down resistors connected to the motherboard power supply or ground. It is worth noting that the initialization address of each first slave device is different;

[0071] (2) The BMC scans all first slave devices in the link, reads the address of each first slave device, and writes it into the memory;

[0072] (3) On the second signal line connected from the BMC to the protection chip, a pull-down resistor connected to ground is set, and the second signal is configured to be low level by default. At this time, the protection chip has no output, and slave devices 1, 2, and 3 are not powered. That is, all first slave devices in the bus are isolated, and each first slave device stops running;

[0073] (4) After the server is powered on, the BMC scans the addresses of all second slave devices (slave device a, slave device b, slave device c) integrated on the AIC plug-in card and compares them with the addresses of all first slave devices stored previously. If the same address appears, it is determined that there is an address conflict between the first slave device and the second slave device; if the same address does not exist, it means that there is no address conflict between the first slave device and the second slave device in the bus.

[0074] (5) When there is no address conflict between the first slave device and the second slave device, the BMC sends a second signal to the protection chip through the second signal line, sets the second signal to a high level, and the protection chip starts to output power, restores power to slave device 1, slave device 2, and slave device 3, and all the first slave devices start to operate.

[0075] In this embodiment, by setting a protection chip in the control circuit, the BMC can realize unified control of the power supply status (power on or off) of all first slave devices. The BMC only needs to send the second signal once to uniformly isolate or release the isolation of all first slave devices, which is convenient for operation, does not require the layout of complex circuits, and saves equipment costs.

[0076] In one embodiment, the same number of protection chips as the first slave devices are provided in the control circuit to improve the flexibility of the control circuit. Specifically, the BMC is connected to each protection chip through the second signal line, and the output of each protection chip is connected to a corresponding first slave device. In this embodiment, the baseboard management controller can send a second signal to one or more protection chips through the second signal line to control the protection chip to cut off or restore the power supply to one or more first slave devices.

[0077] Based on the control circuit structure in this embodiment, when the BMC needs to modify the address of the first slave device with an address conflict, a second signal can be sent to the protection chip connected to other first slave devices that do not need to modify the address, so as to control the protection chip to restore the power supply of other first slave devices in the bus that do not have address conflicts and resume operation. That is, after the server is powered on, most devices without address conflicts can run quickly, reducing delays, without waiting for individual first slave devices to modify addresses, and improving the overall response efficiency of the server.

[0078] As an implementation mode of the present application, the control circuit is provided with: transistors having the same number as all the first slave devices;

[0079] The baseboard management controller is connected to the G pole of each transistor through a third signal line; the D pole of each transistor is connected to the internal integrated circuit bus, and the S pole of each transistor is connected to a first slave device;

[0080] The baseboard management controller is specifically used to send a third signal through the third signal line to control the transistor to be in an on state or an off state.

[0081] Figure 4 This is the second schematic diagram of the architecture of the I2C bus system proposed in one embodiment of the present application. Figure 4As shown, in one embodiment, the I2C bus is connected to the BMC, three first slave devices (slave device 1, slave device 2, slave device 3) and three second slave devices (slave device a, slave device b, slave device c). A plurality of NMOS (N-Metal Oxide Semiconductor) tubes are provided in the control circuit, and each NMOS tube is respectively provided on a circuit where a first slave device is connected to the I2C bus. Among them, the D pole of each NMOS tube is connected to a serial data line SDA and a serial clock line SCL of the I2C bus, the S pole of the NMOS tube is connected to a first slave device, and the G pole of each NMOS tube is connected to the BMC through a third signal line. The BMC sends a third signal through the third signal line to control each NMOS tube to be in an on state or an off state, thereby controlling the on and off state of the two links (SDA / SCL) of each first slave device connected to the I2C bus.

[0082] As an implementation mode of the present application, the links connecting all first slave devices to the internal integrated circuit bus are cut off by the control circuit, specifically including: setting the third signal to a low level so that the crystals in the links connecting each first slave device to the internal integrated circuit bus are in a cut-off state;

[0083] The baseboard management controller is also used to restore the links connecting all the first slave devices to the internal integrated circuit bus through the control circuit when it is detected that there is no address conflict between all the first slave devices and the second slave devices, specifically including: setting the third signal to a high level so that the transistors in the links connecting each first slave device to the internal integrated circuit bus are in an on state.

[0084] In one embodiment, a third signal line is provided in the control circuit, and the third signal line is connected to each NMOS tube at the same time. The BMC sends a third signal based on the third signal line to control each NMOS tube to be in an on or off state at the same time. In this embodiment, the address of the first slave device and the second slave device in the bus is detected by the control circuit, and the specific steps are as follows:

[0085] (1) After the server is turned on, each first slave device initializes its own communication address through the pull-up and pull-down resistors connected to the motherboard power supply or ground. It is worth noting that the initialization address of each first slave device is different;

[0086] (2) The BMC scans all first slave devices in the link, reads the address of each first slave device, and writes it into the memory;

[0087] (3) A pull-down resistor connected to the ground is set on the third signal line, and the third signal is configured to a low level by default through the BMC. At this time, all NMOS tubes are in the cut-off state, slave device 1, slave device 2, and slave device 3 are not connected to the I2C bus, and each first slave device stops running;

[0088] (4) After the server is powered on, the BMC scans the addresses of all second slave devices (slave device a, slave device b, slave device c) integrated on the AIC plug-in card and compares them with the addresses of all first slave devices stored previously. If the same address appears, it is determined that there is an address conflict between the first slave device and the second slave device; if the same address does not exist, it means that there is no address conflict between the first slave device and the second slave device in the bus;

[0089] (5) When there is no address conflict between the first slave device and the second slave device, the BMC sends a third signal through the third signal line, sets the third signal to a high level to turn on all NMOS transistors, connects slave device 1, slave device 2, and slave device 3 to the I2C bus, and all first slave devices start to operate.

[0090] In this embodiment, by setting a third signal line in the control circuit and connecting all NMOS tubes to the third signal line, the BMC can realize unified control of the link on / off status of all first slave devices connected to the I2C bus. The BMC only needs to send the third signal once to uniformly isolate or release the isolation of all first slave devices, which is convenient for operation, does not require the layout of complex circuits and multiple protection chips, and saves equipment costs.

[0091] In one embodiment, a plurality of third signal lines are provided in the configuration circuit to improve the flexibility of the control circuit. Specifically, the BMC accesses the G pole of the NMOS tube connected to each first slave device through the plurality of third signal lines. The BMC sends a third signal through each third signal line to realize the cut-off and conduction control of each NMOS tube respectively. In this embodiment, the BMC can realize the on-off state of the link of one or more first slave devices connected to the I2C bus by sending a third signal to one or more NMOS tubes.

[0092] Based on the control circuit structure in this embodiment, when the BMC needs to modify the address of the first slave device with an address conflict, a third signal can be sent to the NMOS tube connected to the first slave device that does not need to modify the address to control the corresponding NMOS tube to be turned on, so that the first slave device without address conflict can be connected to the I2C bus. That is, most of the devices without address conflict can be quickly operated after the server is powered on, reducing delays, without waiting for individual first slave devices to modify addresses, and improving the overall response efficiency of the server.

[0093] As an implementation mode of the present application, the configuration circuit is provided with: a mainboard power supply, a transistor, a pull-up resistor and a pull-down resistor; the baseboard management controller is connected to the G pole of the transistor through a first signal line; one end of the pull-up resistor is connected to the mainboard power supply, and the other end is connected to the D pole of the transistor; one end of the pull-down resistor is connected to the S pole of the transistor, and the other end is connected to an address configuration pin of a first slave device;

[0094] Sending a first signal to the first slave device through the first signal line to modify the address of the first slave device includes:

[0095] Acquire the current address of the first slave device; the address of the first slave device is determined based on the level state of the address configuration pin of the first slave device;

[0096] Based on the current address of the first slave device, determining a transistor in a configuration circuit connected to an address configuration pin of the first slave device;

[0097] Modifying the first signal output to the transistor so that the level state of the address configuration pin connected to the transistor is switched specifically includes:

[0098] The first signal is set to a high level, so that the transistor is in a conducting state, the address configuration pin is connected to the mainboard power supply through the pull-up resistor, and the level state of the address configuration pin is switched to a high level;

[0099] Or, the first signal is set to a low level so that the transistor is in a cut-off state, the address configuration pin of the first slave device is grounded through the pull-down resistor, and the level state of the address configuration pin is switched to a low level.

[0100] Figure 5 Schematic diagram of a configuration circuit in an embodiment of the present application. Figure 5 As shown, in this embodiment, the configuration circuit includes a mainboard power supply, an NMOS tube, a pull-up resistor and a pull-down resistor; the baseboard management controller is connected to the G pole of the NMOS tube through a first signal line; one end of the pull-up resistor is connected to the mainboard power supply, and the other end is connected to the D pole of the NMOS tube; one end of the pull-down resistor is connected to the S pole of the NMOS tube, and the other end is connected to an address configuration pin of a first slave device.

[0101] In the above embodiment, when the BMC detects that there is an address conflict between the first slave device and the second slave device, the BMC modifies the address of the first slave device by configuring the circuit. Specifically, the address of the first slave device is modified in the following steps:

[0102] (1) Obtaining the current address of the first slave device whose address needs to be modified;

[0103] (2) determining an NMOS transistor of a configuration circuit connected to an address configuration pin of the first slave device based on the current address of the first slave device;

[0104] (3) Modify the first signal output to the G pole of the NMOS tube in the configuration circuit to change the level state of each address configuration pin of the first slave device. Specifically, the first signal is set to a high level to turn on the NMOS tube; the first signal is set to a low level to turn off the NMOS tube.

[0105] The address configuration pin carried by the first slave device indicates the upper limit of the number of addresses that the device can configure, and the number of address configuration pins connected to the NMOS tube in the configuration circuit is the number of different addresses that can be modified at present. Figure 5 Taking the configuration circuit shown in FIG. 1 as an example, the first slave device in the figure has 3 address configuration pins, that is, it can realize the switching of 2^3 addresses, but Figure 5 In the circuit, only the A0 pin is connected to the NMOS tube, and the A1 and A2 pins are fixed to the ground. Therefore, the only pin with a variable level state is A0. Figure 5 The first slave device can only switch between two different addresses. If you want to change the level of the A1 and A2 pins to achieve the switching of eight different addresses, you need to add two NMOS tubes in the configuration circuit and connect them to the A1 and A2 pins respectively.

[0106] Specifically, when the NMOS is in the cut-off state, the three address configuration pins A0, A1, and A2 are grounded by the pull-down resistors R2, R3, and R4, respectively, that is, the pins A0, A1, and A2 are all low level, and the address (last three digits) of the first slave device is configured as 1010_000. When the BMC sets the first signal output to the G pole of the NMOS tube to a high level, the NMOS tube is in the on state, so that the A0 pin of the first slave device is connected to the motherboard power supply through R1, and the input level of the A0 pin is set to a high level, so that the address (last three digits) of the first slave device is configured as 1010_001.

[0107] As an implementation manner of the present application, the first slave device carries one or three address configuration pins; in the configuration circuit, the number of pull-down resistors is the same as the number of address configuration pins carried by the first slave device.

[0108] In the above embodiment, the address configuration of the first slave device is realized by setting the high and low levels of the address configuration pins on the chip. Specifically, the addresses that can be configured by the first slave device are pre-set, corresponding to the level states of the address configuration pins one by one, and the first slave device is controlled to switch its own address by changing the level states of the address configuration pins. For example, Figure 5 For the first slave device in the system, the levels of pins A0, A1, and A2 are "high, low, low", and the corresponding address is "1010_001".

[0109] Among them, the number of optional addresses is related to the number of address configuration pins carried by the first slave device. One address configuration pin can distinguish two different addresses according to the high level and the low level. For the first slave device carrying 3 address configuration pins, 2^3=8 different address switching can be achieved. In this embodiment, the address configuration pins of the first slave device are 1 or 3, and the number of pull-down resistors is the same as the number of address configuration pins.

[0110] As an implementation manner of the present application, the resistance ratio of the pull-up resistor to the pull-down resistor is 1:10.

[0111] In the above embodiment, the level of the address configuration pin is actually determined by the ratio of the pull-up resistor and the pull-down resistor. When the voltage of the mainboard power supply is 3.3V, the pull-up resistor and the pull-down resistor are each allocated a part of the voltage component by parallel connection. To set the address configuration pin to a high level, it is only necessary that the voltage component allocated to the pull-down resistor exceeds the critical value for determining a high level. Usually, a voltage value exceeding 2V is determined as a high level. Therefore, 2V is used as the critical value, and the ratio of the pull-up resistor to the pull-down resistor is calculated, which needs to be less than about 0.65.

[0112] In order to facilitate the selection of resistor elements with corresponding resistance values ​​when laying out the configuration circuit, to facilitate calculation, and to increase the redundancy of the device in judging the level state, and to prevent the level state recognition error caused by voltage instability, in one embodiment, the resistance ratio of the pull-up resistor to the pull-down resistor is set to 1:10. That is, Figure 5 The input level of the A0 pin is 3V, which is recognized as a high level by the first slave device.

[0113] Based on the same inventive concept, an embodiment of the present application provides an address conflict handling method. Figure 6 , Figure 6 1 is a flow chart of an address conflict handling method proposed in one embodiment of the present application. Figure 6 As shown, the method includes:

[0114] S1: After the server is powered on, each first slave device is controlled to initialize its own address;

[0115] S2: Read and store the addresses of all first slave devices through the baseboard management controller;

[0116] S3: Cutting off the power supply of all first slave devices through the control circuit, or cutting off the links connecting all first slave devices to the internal integrated circuit bus through the control circuit;

[0117] S4: reading the addresses of all the second devices, and detecting whether there is an address conflict between all the first slave devices and all the second slave devices;

[0118] S5: When there is an address conflict between any first slave device and any second slave device, send a first signal to the first slave device through a first signal line to modify the address of the first slave device.

[0119] As an implementation manner of the present application, cutting off the power supply of all first slave devices by the control circuit includes:

[0120] The second signal is set to a low level to control the protection chip to cut off the power supply of the mainboard power supply to the first slave device.

[0121] As an implementation manner of the present application, cutting off the links connecting all first slave devices to the internal integrated circuit bus by the control circuit includes:

[0122] The third signal is set to a low level to turn off transistors in the link connecting each first slave device to the inter-IC bus.

[0123] As an implementation manner of the present application, when an address conflict is detected between any first slave device and any second slave device, sending a first signal to the first slave device through the first signal line to modify the address of the first slave device includes:

[0124] Acquire the current address of the first slave device; the address of the first slave device is determined based on the level state of the address configuration pin of the first slave device;

[0125] Based on the current address of the first slave device, determining a transistor in a configuration circuit connected to an address configuration pin of the first slave device;

[0126] Modifying the first signal output to the transistor so that the level state of the address configuration pin connected to the transistor is switched specifically includes:

[0127] The first signal is set to a high level, so that the transistor is in a conducting state, the address configuration pin is connected to the mainboard power supply through the pull-up resistor, and the level state of the address configuration pin is switched to a high level;

[0128] Or, the first signal is set to a low level so that the transistor is in a cut-off state, the address configuration pin of the first slave device is grounded through the pull-down resistor, and the level state of the address configuration pin is switched to a low level.

[0129] As an implementation manner of the present application, the address conflict handling method further includes:

[0130] After modifying the address of the first slave device, re-detecting whether there is an address conflict between all the first slave devices and all the second slave devices;

[0131] When it is detected that there is no address conflict between all the first slave devices and the second slave device, the control circuit restores power to all the first slave devices, or restores the links connecting all the first slave devices to the internal integrated circuit bus.

[0132] As an implementation manner of the present application, restoring power supply to all first slave devices through the control circuit includes:

[0133] The second signal is set to a high level to control the protection chip to restore the mainboard power supply to the first slave device.

[0134] As an implementation manner of the present application, restoring the links of all first slave devices connected to the internal integrated circuit bus through the control circuit includes:

[0135] The third signal is set to a high level to turn on transistors in the link connecting each first slave device to the inter-IC bus.

[0136] Based on the same inventive concept, an embodiment of the present application provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps in the address conflict handling method described in any of the above embodiments of the present application are implemented.

[0137] Based on the same inventive concept, an embodiment of the present application provides a readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the address conflict handling method described in any of the above embodiments of the present application are implemented.

[0138] Based on the same inventive concept, an embodiment of the present application provides an electronic device. Figure 7 Schematic diagram of an electronic device according to an embodiment of the present application. Figure 7 As shown, the electronic device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps in the address conflict handling method described in any of the above embodiments of the present application are implemented.

[0139] Regarding the method in the above embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment of the internal integrated circuit bus system, and will not be elaborated here.

[0140] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

[0141] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and components involved are not necessarily required by the present application.

[0142] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0143] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0144] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0145] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0146] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the present application is interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0147] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0148] The internal integrated circuit bus system, address conflict handling method and product provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An internal integrated circuit bus system, characterized in that: include: Inter-IC bus, conflict handling unit and address configuration unit; The internal integrated circuit bus is connected to: a baseboard management controller, at least one first slave device and an external plug-in card; at least one second slave device is integrated in the external plug-in card; The conflict processing unit includes a control circuit between the baseboard management controller and each first slave device; The baseboard management controller is used to cut off the power supply of all the first slave devices through the control circuit, or cut off the link connecting all the first slave devices to the internal integrated circuit bus through the control circuit before detecting whether there is an address conflict between the first slave device and the second slave device; The address configuration unit includes configuration circuits having the same number as all the first slave devices, and each first slave device is connected to the baseboard management controller via a first signal line; the baseboard management controller is further used to send a first signal to the first slave device via the first signal line to modify the address of the first slave device when an address conflict is detected between any first slave device and any second slave device.

2. The intra-IC bus system according to claim 1, wherein: A protection chip is provided in the control circuit; Each first slave device is connected to the protection chip respectively, and the protection chip is also connected to the mainboard power supply; The baseboard management controller is connected to the protection chip through a second signal line; The baseboard management controller is specifically used to send a second signal through the second signal line to control the protection chip to cut off or restore its own output power supply.

3. The intra-IC bus system according to claim 2, wherein: Cutting off the power supply of all first slave devices by the control circuit specifically includes: setting the second signal to a low level to control the protection chip to cut off the power supply of the mainboard power supply to the first slave devices; The baseboard management controller is also used to restore the power supply of all the first slave devices through the control circuit when it is detected that there is no address conflict between all the first slave devices and the second slave devices, specifically including: setting the second signal to a high level to control the protection chip to restore the power supply of the mainboard power supply to the first slave devices.

4. The intra-IC bus system according to claim 1, wherein: The control circuit is provided with: transistors having the same number as all the first slave devices; The baseboard management controller is connected to the G pole of each transistor through a third signal line; the D pole of each transistor is connected to the internal integrated circuit bus, and the S pole of each transistor is connected to a first slave device; The baseboard management controller is specifically used to send a third signal through the third signal line to control the transistor to be in an on state or an off state.

5. The intra-IC bus system according to claim 4, wherein: Cutting off the links connecting all first slave devices to the internal integrated circuit bus by the control circuit specifically includes: setting the third signal to a low level so that the transistors in the links connecting each first slave device to the internal integrated circuit bus are in a cut-off state; The baseboard management controller is also used to restore the links connecting all the first slave devices to the internal integrated circuit bus through the control circuit when it is detected that there is no address conflict between all the first slave devices and the second slave devices, specifically including: setting the third signal to a high level so that the transistors in the links connecting each first slave device to the internal integrated circuit bus are in an on state.

6. The intra-IC bus system according to claim 1, wherein: The configuration circuit is provided with: a mainboard power supply, a transistor, a pull-up resistor and a pull-down resistor; the baseboard management controller is connected to the G pole of the transistor through a first signal line; one end of the pull-up resistor is connected to the mainboard power supply, and the other end is connected to the D pole of the transistor; one end of the pull-down resistor is connected to the S pole of the transistor, and the other end is connected to an address configuration pin of a first slave device; Sending a first signal to the first slave device through the first signal line to modify the address of the first slave device includes: Acquire the current address of the first slave device; the address of the first slave device is determined based on the level state of the address configuration pin of the first slave device; Based on the current address of the first slave device, determining a transistor in a configuration circuit connected to an address configuration pin of the first slave device; Modifying the first signal output to the transistor so that the level state of the address configuration pin connected to the transistor is switched specifically includes: The first signal is set to a high level, so that the transistor is in a conducting state, the address configuration pin is connected to the mainboard power supply through the pull-up resistor, and the level state of the address configuration pin is switched to a high level; Or, the first signal is set to a low level so that the transistor is in a cut-off state, the address configuration pin of the first slave device is grounded through the pull-down resistor, and the level state of the address configuration pin is switched to a low level.

7. The intra-IC bus system according to claim 6, wherein: The first slave device carries one or three address configuration pins; in the configuration circuit, the number of pull-down resistors is the same as the number of address configuration pins carried by the first slave device.

8. The intra-IC bus system according to claim 6, wherein: The resistance ratio of the pull-up resistor to the pull-down resistor is 1:

10.

9. A method for handling address conflicts, characterized in that: The internal integrated circuit bus system according to any one of claims 1 to 8 comprises: After the server is powered on, each first slave device is controlled to initialize its own address; Reading and storing the addresses of all first slave devices through the baseboard management controller; Cutting off the power supply of all first slave devices by the control circuit, or cutting off the links connecting all first slave devices to the internal integrated circuit bus by the control circuit; Reading the addresses of all the second devices, and detecting whether there is an address conflict between all the first slave devices and all the second slave devices; In the case that there is an address conflict between any first slave device and any second slave device, a first signal is sent to the first slave device through a first signal line to modify the address of the first slave device.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the method of claim 9 are implemented.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps in the method according to claim 9 are implemented.

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