Template calculation optimization method, device and equipment on multi-core DSP (Digital Signal Processor)

Abstract

The invention relates to a template calculation optimization method, device and equipment on a multi-core DSP (Digital Signal Processor). The method comprises the following steps: dividing an input data grid into a plurality of data blocks, and distributing a DSP core for each data block; in the current time step, all the DSP cores complete first-level calculation on the distributed data blocks, the data blocks are further divided into a plurality of sub-blocks, and each sub-block comprises a plurality of adjacent grid points. And at the next time step, loading the sub-blocks to a vector on-chip memory of the DSP, and carrying out secondary calculation on the sub-blocks by utilizing a vector calculation unit of the DSP to obtain a new value of each grid point. And packaging new values obtained by calculation into new sub-blocks, storing the new sub-blocks back to the vector on-chip memory, and transmitting the new sub-blocks from the vector on-chip memory to the off-chip memory for loading and storage through a data moving unit of the DSP by adopting a three-buffering mechanism. By adopting the method, the calculation performance of the multi-core DSP can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of multi-core DSP (digital signal processor) calculation optimization, and in particular to a template calculation optimization method, device and equipment on a multi-core DSP. Background Art

[0002] Stencil calculations are a common computing pattern in high performance computing (HPC) applications, and are used in areas such as image processing, convolutional neural networks, and partial differential equation solving. These calculations are often the performance bottleneck in many scientific applications because they are memory-bound and require efficient data reuse and access patterns.

[0003] When an application needs to perform Stencil calculations during operation, it can send a Stencil calculation execution request to the processor. The processor that receives the Stencil calculation execution request can traverse each or a specified number of data points of the data to be Stencil calculated, and perform calculation operations on each data point and the neighboring data points corresponding to each data point. The same calculation operation is performed on the data point and its neighboring data points each time during the traversal process. The calculation domain can be a data matrix, such as a two-dimensional grid, a three-dimensional grid, etc.

[0004] Traditional optimization methods mainly focus on CPU and GPU architectures, which enhance performance by improving data locality and parallelism, reducing communication overhead, etc. However, there is no consensus on the best optimization method for stencil computing on emerging HPC processors, especially multi-core digital signal processors (DSPs). The unique architecture of DSPs, with very long instruction words (VLIW) and vector units, provides opportunities to exploit instruction-level and data-level parallelism, but also brings challenges to the performance optimization of stencil computing applications due to differences in their hardware architecture.

[0005] In summary, multi-core DSPs are ideal for performing template calculation tasks due to their VLIW and vector units. Designing efficient template calculation programs for multi-core DSPs includes two parts: microkernel design and on-chip and off-chip data transfer. Among them, efficient microkernel design is to fully utilize the VLIW and vector units of DSP when the data is on-chip. However, there is currently a lack of microkernels specifically designed for template calculation applications to fully utilize these hardware features, resulting in the program's performance not being optimal. Summary of the invention

[0006] Based on this, it is necessary to provide a template calculation optimization method, device and equipment on a multi-core DSP that can improve the energy efficiency of mature development of multi-core DSP processors and template calculation applications in response to the above technical problems.

[0007] A template calculation optimization method on a multi-core DSP, the method comprising: The input data grid is divided into several data blocks, and a DSP core is assigned to each data block. The data block contains several grid points.

[0008] At the current time step, all DSP cores complete the first-level calculation of the allocated data block, and further divide the data block into multiple sub-blocks, each of which contains multiple adjacent grid points.

[0009] At the next time step, the sub-block is loaded into the vector on-chip memory of the DSP, and the vector computing unit of the DSP is used to perform secondary calculations on the sub-block to obtain the new value of each grid point.

[0010] The calculated new values ​​are packaged into new sub-blocks and stored back in the vector on-chip memory. The new sub-blocks are transferred from the vector on-chip memory to the off-chip memory through the DSP's data movement unit using a triple buffer mechanism for loading and storage.

[0011] A template calculation optimization device on a multi-core DSP, the device comprising: The data block allocation module is used to divide the input data grid into several data blocks and allocate a DSP core to each data block. The data block contains several grid points.

[0012] The data block segmentation module is used to complete the first-level calculation of the allocated data block by all DSP cores at the current time step, and further divide the data block into multiple sub-blocks, each of which contains multiple adjacent grid points.

[0013] The template calculation module is used to load the sub-block into the vector on-chip memory of the DSP at the next time step, and use the vector calculation unit of the DSP to perform secondary calculation on the sub-block to obtain the new value of each grid point.

[0014] The data handling module is used to package the calculated new values ​​into new sub-blocks and store them back to the vector on-chip memory. The new sub-blocks use a triple buffer mechanism to transfer from the vector on-chip memory to the off-chip memory through the DSP's data movement unit for loading and storage.

[0015] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented: The input data grid is divided into several data blocks, and a DSP core is assigned to each data block. The data block contains several grid points.

[0016] At the current time step, all DSP cores complete the first-level calculation of the allocated data block, and further divide the data block into multiple sub-blocks, each of which contains multiple adjacent grid points.

[0017] At the next time step, the sub-block is loaded into the vector on-chip memory of the DSP, and the vector computing unit of the DSP is used to perform secondary calculations on the sub-block to obtain the new value of each grid point.

[0018] The calculated new values ​​are packaged into new sub-blocks and stored back in the vector on-chip memory. The new sub-blocks are transferred from the vector on-chip memory to the off-chip memory through the DSP's data movement unit using a triple buffer mechanism for loading and storage.

[0019] The above-mentioned template calculation optimization method, device and equipment on a multi-core DSP first divides the input data grid into multiple data blocks, allocates a DSP core to each data block, and fully utilizes the multi-core parallelism to start the first step of parallel computing, which enables the first-level calculation to be carried out synchronously on multiple lines, laying the foundation for overall efficiency. At the current time step, all DSP cores are turned on synchronously to complete the first-level calculation of the assigned data blocks, and the subdivision of data blocks in the first-level calculation is closely linked to the subsequent steps. The fine sub-block division provides an adaptive data granularity for vector on-chip memory loading and second-level calculation, allowing the vector calculation unit of the DSP to be fully utilized, accurately mining data-level parallelism, making the calculation granularity finer, and laying the foundation for subsequent in-depth processing. Without reasonable data division in the early stage, the vector calculation unit cannot operate efficiently, which will cause hardware resources to be idle or underutilized. Then, in the next time step, the sub-blocks of the data block are further divided and loaded into the vector on-chip memory of the DSP. With the help of the unique vector computing unit of the DSP, the secondary calculation is carried out to fully exploit the data-level parallelism and accurately calculate the new value of each grid point. The subsequent steps are closely connected. The fine sub-block division provides an adaptive data granularity for the vector on-chip memory loading and secondary calculation, allowing the vector computing unit of the DSP to be fully utilized and accurately exploit the data-level parallelism. Not only that, after the calculated new values ​​are packaged into new sub-blocks and stored back in the vector on-chip memory, a three-buffer mechanism is adopted to use the DSP's data movement unit to efficiently transmit between the vector on-chip memory and the off-chip memory. The packaging after calculating the new value is also closely linked with the three-buffer mechanism. The data is packaged and regularized so that it can be smoothly transmitted between the storage levels through the data movement unit using the three-buffer mechanism. The three-buffer mechanism cleverly balances the data loading and storage requirements, avoiding the high latency caused by frequent reading and writing of the off-chip memory, and ensuring that the data can be updated and stored in time, reducing communication overhead. This all-round design, from data partitioning and computing division to storage and transmission, adapts to the unique hardware architecture of DSP very long instruction word (VLIW) and vector unit, overcomes the performance optimization obstacles to template computing applications caused by architectural differences, and ultimately achieves the goal of high-performance template computing on multi-core DSP platforms, opening up a new path for template computing optimization on emerging HPC processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a flow chart of a template calculation optimization method on a multi-core DSP in one embodiment; Figure 2 A schematic diagram of a microkernel calculation process in an embodiment; Figure 3 A diagram of a parallel computing strategy of a microkernel on a multi-core DSP processor in one embodiment; Figure 4A schematic diagram of a microkernel triple buffer mechanism in one embodiment; Figure 5 A microkernel structure block diagram in one embodiment, wherein: Figure 5 (a) is the 2D5P template shape information, Figure 5 (b) is a schematic diagram of local calculation. Figure 5 (c) is a schematic diagram of data reuse. Figure 5 (d) register allocation; Figure 6 A schematic diagram of a microkernel computing execution flow in one embodiment; Figure 7 It is a structural block diagram of a template calculation optimization device on a multi-core DSP in one embodiment; Figure 8 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] In one embodiment, Figure 1 As shown, a template calculation optimization method on a multi-core DSP is provided, comprising the following steps: Step 102: divide the input data grid into a number of data blocks, and allocate a DSP core to each data block.

[0023] A data block contains a number of grid points.

[0024] Step 104: At the current time step, all DSP cores complete the first-level calculation of the allocated data block, and further divide the data block into a plurality of sub-blocks, each of which contains a plurality of adjacent grid points.

[0025] Step 106, at the next time step, the sub-block is loaded into the vector on-chip memory of the DSP, and the vector computing unit of the DSP is used to perform secondary calculations on the sub-block to obtain a new value for each grid point.

[0026] Step 108, pack the calculated new values ​​into new sub-blocks and store them back into the vector on-chip memory. The new sub-blocks are transferred from the vector on-chip memory to the off-chip memory through the DSP's data movement unit using a triple buffer mechanism for loading and storage.

[0027] In the above-mentioned template calculation optimization method on a multi-core DSP, first, the input data grid is divided into multiple data blocks, and a DSP core is assigned to each data block, making full use of multi-core parallelism, starting the first step of parallel computing, which enables the first-level calculation to be carried out synchronously on multiple lines, laying the foundation for overall efficiency. At the current time step, all DSP cores are turned on synchronously to complete the first-level calculation of the assigned data blocks, and the subdivision of data blocks in the first-level calculation is closely linked to the subsequent steps. The fine sub-block division provides an adaptive data granularity for vector on-chip memory loading and second-level calculation, allowing the vector calculation unit of the DSP to be fully utilized, accurately mining data-level parallelism, making the calculation granularity finer, and laying the foundation for subsequent in-depth processing. Without reasonable data division in the early stage, the vector calculation unit cannot operate efficiently, which will cause hardware resources to be idle or underutilized. Then, in the next time step, the sub-blocks of the data block are further divided and loaded into the vector on-chip memory of the DSP. With the help of the unique vector computing unit of the DSP, the secondary calculation is carried out to fully exploit the data-level parallelism and accurately calculate the new value of each grid point. The subsequent steps are closely connected. The fine sub-block division provides an adaptive data granularity for the vector on-chip memory loading and secondary calculation, allowing the vector computing unit of the DSP to be fully utilized and accurately exploit the data-level parallelism. In addition, after the calculated new values ​​are packaged into new sub-blocks and stored back in the vector on-chip memory, a three-buffer mechanism is adopted to efficiently transmit between the vector on-chip memory and the off-chip memory using the data movement unit of the DSP. The packaging after calculating the new value is also closely linked with the three-buffer mechanism. The data is packaged and regularized so that it can be smoothly transmitted between the storage levels through the data movement unit using the three-buffer mechanism. The three-buffer mechanism cleverly balances the data loading and storage requirements, avoiding the high latency caused by frequent reading and writing of the off-chip memory, and ensuring that the data can be updated and stored in time, reducing communication overhead. This all-round design, from data partitioning and computing division to storage and transmission, adapts to the unique hardware architecture of DSP very long instruction word (VLIW) and vector unit, overcomes the performance optimization obstacles to template computing applications caused by architectural differences, and ultimately achieves the goal of high-performance template computing on multi-core DSP platforms, opening up a new path for template computing optimization on emerging HPC processors.

[0028] In one embodiment, parameter information of a multi-core DSP is obtained, wherein the parameter information includes: information of a data grid, template mode information, and DSP parameter information. The data grid information includes: grid size and grid dimension. The template mode information includes: data dependency range, data dependency point number, and data dependency shape. DSP parameter information: size of global shared memory, number of floating-point multiplication and addition units, number of vector registers, memory bandwidth, and number of DSP cores.

[0029] In one embodiment, the microkernel shape is determined according to the parameter information, the input data grid is divided into a number of data blocks with the same number of data columns and data rows according to the microkernel shape, and a DSP core is allocated to each data block.

[0030] In one embodiment, at the current time step, the DSP core of the allocated data block selects the instruction corresponding to the primary computing mode according to the DSP parameter information, the template mode information and the microkernel shape, and packages the instructions corresponding to the primary computing mode into a primary instruction package to ensure that multiple multiplication and accumulation instructions can be executed in each clock cycle. The allocated data block is vectorized according to the multiplication and accumulation instructions to perform primary calculation, further divide the data block into multiple sub-blocks, and in the sub-blocks, multiple adjacent grid points are combined into vectors, which are processed in parallel by the vector calculation unit.

[0031] In one of the embodiments, at the next time step, a three-buffer mechanism is used to load the sub-block into the vector on-chip memory of the DSP, and the memory access path information is determined based on the grid parameter information, template mode information and DSP parameter information corresponding to the multi-core DSP chip. According to the path information, each sub-block is loaded, calculated and stored in three stages through the first-level three-buffer, so that the sub-block is completely processed by the vector processing unit. The second-level three-buffer is used to load, calculate and store the sub-blocks that have been processed at the first level step by step between the main memory and the vector on-chip memory through the vector calculation unit of the DSP, and the new value of each grid point is obtained. The three-buffer mechanism includes: a first-level three-buffer and a second-level three-buffer. The first-level three-buffer occurs between the vector on-chip memory and the vector register of the DSP, and is used to realize the parallel execution of data loading and calculation within the sub-block. The second-level three-buffer occurs between the vector on-chip memory and the off-chip memory of the DSP, and is used to realize the parallel execution of data loading, calculation and storage between sub-blocks.

[0032] In one embodiment, each sub-block is loaded, calculated and stored in three stages through a first-level three-buffer according to path information. In the loading stage, the sub-block is loaded from the vector on-chip memory of the DSP to the vector register of the vector processing unit. In the calculation stage, the multiplication and addition operation unit of the vector register of the vector processing unit is used to perform floating-point multiplication and addition operations. In the storage stage, the sub-block is stored back from the vector register to the vector on-chip memory. Through the instruction set pipeline, the calculation of the current sub-block, the loading of the next sub-block and the storage of the previous sub-block are performed in the same time segment, so that all sub-blocks are completely processed by the vector processing unit at the first level.

[0033] In one embodiment, a secondary calculation of three stages, namely, loading, calculating and storing, is performed step by step between the main memory and the vector on-chip memory by using a secondary three-buffer through the vector calculation unit of the DSP. In the loading stage, the sub-block is moved from the main memory to the vector on-chip memory of the DSP. In the calculation stage, all operations of the primary three-buffer are performed. In the storage stage, the sub-block is stored from the vector on-chip memory back to the main memory. Through a loop operation, when the sub-block in the first buffer is used for calculation, the next sub-block is loaded into the second buffer of the vector on-chip memory until the calculation is completed, and the new value of each grid point is obtained.

[0034] In one of the embodiments, the data transmission of the sub-block to the chip or to the off-chip is optimized by interleaving single-word and double-word instructions. The size of the sub-block is selected according to the on-chip storage capacity of the DSP, the characteristics of the vector computing unit and the data reuse strategy. The loading and storage operations of the sub-block use a DMA engine for asynchronous data transmission. The calculation of the sub-block is performed using a microkernel to utilize the vector computing unit and the optimized instruction pipeline technology of the DSP. The shape of the microkernel is designed according to the number of vector registers of the DSP, the instruction packet filling constraints of the vector computing unit and the instruction delay constraints. The calculated new values ​​are packaged into new sub-blocks and stored back to the vector on-chip memory. All new sub-blocks are stored in the third buffer using a three-buffer mechanism, and are written back from the vector on-chip memory to the main memory through the data movement unit of the DSP to complete the loading and storage of the input data.

[0035] In one embodiment, if Figure 2 As shown, a microkernel computing process is provided, which specifically includes the following contents: S1. Parameter information acquisition: First, collect the necessary multi-core DSP chip parameters, including the size and dimension of the input grid, the data dependency range, number of points and shape of the template pattern, as well as the DSP's global shared memory size, vector on-chip cache size, number of floating-point multiplication and addition units, number of vector registers, main memory bandwidth, global shared memory bandwidth and number of multi-core DSP cores. These parameters are the basis for microkernel design and optimization.

[0036] S2. Determine the shape of the microkernel: Determine the shape of the microkernel, including the configuration of data columns and rows, based on the collected parameter information. The shape of the microkernel directly affects its execution efficiency on the DSP, so it needs to be optimized based on the hardware characteristics of the DSP and the template calculation requirements.

[0037] S3. Microkernel computing strategy formulation: Formulate the computing strategy of the microkernel, including instruction pipeline optimization and data reuse strategy configuration. Design the instruction pipeline of the microkernel to ensure that multiple FMAC instructions can be executed in each cycle, and configure the data reuse strategy to reduce the number of accesses to the external memory and improve computing efficiency.

[0038] S4, microkernel execution and result output: Execute microkernel calculations, use the DSP's vector processing unit to process data in parallel, and store the results back to the on-chip memory after the calculation is completed, and then output the calculation results. This step includes data loading, calculation execution, result storage and exception handling to ensure the correctness and synchronization of the calculation.

[0039] In an optional embodiment, the DSP core includes an instruction scheduling unit, a scalar processing unit, a vector processing unit and a DMA engine, wherein the vector processing unit includes a vector on-chip cache and a plurality of vector processing elements, each of which includes a plurality of 64-bit vector registers and a plurality of floating-point multiplication and addition units. This hardware configuration provides a physical basis for the efficient execution of the microkernel.

[0040] It is worth noting that by implementing the template calculation optimization method on the multi-core DSP described in the present invention, the processing efficiency and resource utilization of the multi-core DSP chip can be significantly improved, especially when executing calculation-intensive template calculation tasks.

[0041] In one embodiment, if Figure 3 As shown, a microkernel parallel computing strategy on a multi-core DSP processor is provided, which specifically includes the following contents: Microkernel initialization: The process starts with the initialization of the microkernel, including configuring the DSP parameters required by the microkernel, such as the size of the global shared memory, the size of the vector on-chip cache, the number of floating-point multiplication and addition units, etc.

[0042] Data block allocation and microkernel execution: The input grid is divided into multiple data blocks, each of which is assigned to a DSP core. Each DSP core loads its corresponding data block into the vector register and executes the microkernel calculation. This step reflects thread-level parallelism, where each DSP core acts as an execution thread and processes its assigned data block in parallel.

[0043] Vector-level parallelism: In data-level parallelism, the SIMD instructions of the DSP core are used to group continuous grid points into vectors and perform parallel calculations in the microkernel. This step optimizes the vector processing of data and improves computing efficiency.

[0044] Result aggregation and output: After the microkernel has completed the calculation, the results of each DSP core need to be aggregated and output. This step includes storing the calculation results from the vector registers back to the on-chip memory and integrating the results of each core to form the final output grid.

[0045] In one embodiment, if Figure 4 As shown, a microkernel three-buffer mechanism is provided, which determines the memory access path information based on the multi-core DSP chip grid parameter information, the template mode information and the DSP parameter information, and the two-level three-buffer mechanism overlaps the calculation and communication tasks.

[0046] In an optional embodiment, the first level triple buffer (LV1) breaks down the tile data into smaller sub-tiles, each of which can be fully processed by the VPU. The sub-tiles are divided into three stages: loading, computing, and storing to achieve data overlap. In the loading stage, a size of The sub-tiles of size are loaded from the AM to the vector registers of the VPU (vector processing unit). In the compute phase, floating-point multiplication and addition operations are performed using the FMAC unit of the VPU. In the storage phase, the size of The sub-tile of the current sub-tile is stored from the vector register back to the tile of the AM. Through the instruction set pipeline, the calculation of the current sub-tile, the loading of the next sub-tile, and the storage of the previous sub-tile are performed in the same time slice. There is a delay between the prefetch and the last storage operation, but the overall design enhances parallelism and overlap by minimizing the overhead of loading and storing, thereby improving overall performance.

[0047] In an optional embodiment, the second level triple buffer (LV2) divides the tile into three stages: loading, computing, and storing to achieve data overlap. In the loading stage, the size of The tiles of size are moved from DDR to AM. In the calculation phase, all operations of LV1 are performed. In the storage phase, the size of The tiles are stored from AM (vector on-chip cache) back to DDR (main memory). Through loop operation, when the tile in the first buffer is used for calculation, the next tile is loaded into the second buffer of AM; after the calculation is completed, the data is stored in the third buffer and written back to DDR from AM. This level also realizes the effective overlap of loading, calculation and storage, thereby improving the efficiency of data processing.

[0048] It is worth noting that this step effectively utilizes the memory bandwidth of the FT-M7032 platform through a two-level triple buffering mechanism, decouples data loading, calculation, and storage operations, and achieves overlap between them, thereby improving the efficiency of template calculation.

[0049] In one embodiment, if Figure 5 As shown, a microkernel structure block diagram is provided, including vector registers, VFMAC units and instruction pipelines, and microkernel shape information is determined based on multi-core DSP chip grid parameter information, template mode information and the DSP parameter information.

[0050] It should be noted that the shape of the microkernel refers to the size of the data processed by each call to the microkernel. The microkernel shape information includes data column information and data row information, which is constructed by the following inequality model: (1) Vector register constraint: ensure that common points in the same sub-tile only need to be loaded into the vector register once. For a 2D k-point template, the new value of each point depends on k points, among which there are 2d common points. Therefore, in each sub-tile, there are a total of points, among which M REG -1 adjacent point shared To ensure that these common points only need to be loaded once, M REG and N REG The value of needs to satisfy the following inequality: ; (2) Instruction packet filling constraint: Ensure that 3 FMAC instructions can be issued per cycle. For a two-dimensional k-point template, each point needs to perform k floating-point multiplication and addition operations. Therefore, each sub-tile needs to perform To ensure that 3 FMAC instructions can be issued per cycle, It needs to be a multiple of 3 and needs to satisfy the following formula: ; (3) Instruction delay constraint-1: Avoid pipeline stalls due to data dependencies and ensure that the delay between instructions is minimized. Since FMAC instructions have data dependencies, it is necessary to ensure that the delay between instructions is minimized. For example, the second FMAC instruction can only start the read operation after the first FMAC instruction completes the write operation. Therefore, M REG and N REG The value of needs to satisfy the following inequality: ; (4) Instruction latency constraint-2: Optimize data transfer instructions and ensure that prefetch and store operations are completed within two iterations. The VLDW / VLDDW instructions load vectors into the AM, and each instruction has a latency of 9 cycles; the VFMULAD instruction performs vector multiplication, and each instruction has a latency of 6 cycles; the VSTDW instruction stores the calculated data back to the AM, and this instruction has a latency of 4 cycles. Therefore, it is necessary to ensure that the prefetch and store operations are completed within two iterations, satisfying the following inequality: ; In an optional embodiment, the shape of the microkernel is determined according to the above constraints. For example, for a 2D5P template, the shape of the microkernel can be determined to be 4x4, as shown in Figure 5 (a) Two-dimensional five-point template shape information (2D5Pstencil), Figure 5 (b) Local calculation, Figure 5 (c) Data reuse, Figure 5 (d) Register allocation is shown.

[0051] It is worth noting that this step effectively utilizes the vector computing unit of DSP by carefully designing and implementing the microkernel, thus improving the efficiency of template calculation. The design of the microkernel takes into account the vector register constraints, instruction packet filling constraints and instruction delay constraints, and minimizes the delay through the instruction pipeline design, thereby achieving high-performance template calculation.

[0052] In one embodiment, if Figure 6 As shown, a microkernel computing execution process is provided, which specifically includes microkernel initialization, data loading, computing execution, result storage and exception handling: 1. Get parameter information The present invention first needs to obtain the following parameter information in order to perform subsequent optimization design and calculation: Grid parameter information: Get grid parameter information from the input grid, including the size (MxN) and dimensions (2D or 3D) of the grid. For example, for a 2D grid, you need to get the number of rows M and columns N of the grid; for a 3D grid, you need to get the three dimensions of the grid MxNxL.

[0053] Template pattern information: Get template parameter information from the template pattern, including the range of data dependency, the number of data dependency points (k), and the shape of data dependency (box or star). For example, for a 2D5P template, the range of data dependency is a 3x3 window, the number of data dependency points is 5 points, and the shape of data dependency is a box.

[0054] DSP parameter information: Get DSP parameter information from the DSP chip, including the size of the global shared memory (GSM), the size of the vector on-chip cache (AM), the number of floating-point multiply-add units (VFMAC), the number of vector registers, the bandwidth of the main memory (DDR), the bandwidth of the GSM, and the number of multi-core DSP cores. For example, the parameter information of the FT-M7032 DSP chip includes: GSM=8MB, AM=768KB, VFMAC=3, vector registers=64, DDR bandwidth=340.8GBits / s, GSM bandwidth=85.2GBits / s, number of cores=8.

[0055] 2. Determine the microkernel shape The microkernel is the core module of the template calculation, and the determination of its shape is crucial to the calculation performance. The present invention adopts the following steps to determine the shape of the microkernel: Microkernel structure: The microkernel is tailored for stencil computations and is capable of processing fixed-size data blocks (e.g., 16x16). The microkernel is designed with data dependencies and computation patterns in mind to ensure that each computation step fully utilizes the DSP’s vector processing units.

[0056] Template parameter analysis: Based on the template parameter information, determine the range and number of data dependencies. The design parameters of the microkernel include the number of data points, the number of vectors, and the data dependency distance. These parameters can be adjusted according to different template calculation requirements to achieve the best performance. This information determines the amount of data that the microkernel needs to load. For example, for a 2D5P template, the microkernel needs to load data for 5 points (i.e., a 3x3 window).

[0057] Analysis of the number of vector registers and VFMACs: The microkernel is designed with full consideration of the use of vector registers to achieve data reuse in registers and reduce the number of memory accesses. First, the number of vector registers and the number of VFMACs are determined based on the DSP parameter information. This information determines the number of data columns and data rows that the microkernel can process. For example, the FT-M7032 DSP chip has 64 vector registers and 3 VFMACs, so the number of data columns and data rows of the microkernel should be 64 and 16, respectively.

[0058] Data reuse analysis: Next, analyze data dependencies and determine data reuse strategies. Data reuse is a key factor in improving computational efficiency. For example, multiple sub-blocks can be combined into larger data blocks to reduce the number of data loading times. For example, four 2x2 sub-blocks can be combined into a 4x4 data block, which can reduce the number of data loading times and improve data locality.

[0059] Cache capacity analysis: Then, analyze the capacity of the AM and determine the shape information of the microkernel so that it can store the data of the entire sub-block. For example, the AM capacity of the FT-M7032 DSP chip is 768KB, so the shape of the microkernel should be able to store 64x16 data blocks, that is, 1024KB.

[0060] Comprehensive analysis: Finally, the above analysis results are combined to determine the shape information of the microkernel, such as the number of data columns and data rows. For example, for the FT-M7032 DSP chip and the 2D5P template, the shape of the microkernel can be 64x16.

[0061] 3. Instruction pipeline optimization Instruction selection and packing: Select the instructions that best suit the microkernel computing mode and pack them into instruction packets to ensure that multiple FMAC (multiply-accumulate) instructions can be executed in each clock cycle.

[0062] Latency hiding: hiding the latency caused by data dependencies through carefully designed instruction pipelines, for example, by pre-computing and storing intermediate results to avoid repeated data accesses in subsequent computations.

[0063] 4. Data reuse strategy Vector register reuse: Implement multiple reuse of data in vector registers in the microkernel to reduce access to external memory.

[0064] Cache optimization: Utilize the cache mechanism of the DSP processor, such as L1 and L2 cache, to further reduce access to external memory.

[0065] 5. Microkernel computing Microkernel initialization: Before the microkernel starts computing, it first needs to initialize the necessary parameters and registers, including loading template parameters, configuring vector registers, and setting the working mode of the VFMAC unit.

[0066] Data loading: The microkernel loads the required sub-block data from the on-chip memory (AM) into the vector registers. This step uses the DMA engine to implement asynchronous data transfer to reduce computational latency.

[0067] Calculation execution: Once the data is loaded into the vector register, the microkernel begins to perform calculations. During the calculation process, the microkernel uses multiple floating-point multiplication and addition units (VFMACs) in the DSP's vector processing unit (VPU) to process data in parallel. The calculation process of the microkernel follows a specific algorithm logic and performs predetermined mathematical operations on each grid point and its neighboring points according to the requirements of the template calculation.

[0068] Intermediate result processing: The intermediate results generated during the calculation process can be temporarily stored in vector registers for subsequent calculations. This can reduce the number of accesses to external storage and improve calculation efficiency.

[0069] Result storage: After completing the calculation, the microkernel stores the result data back to the on-chip memory (AM). This step also uses the DMA engine to implement asynchronous data transfer so that the microkernel can perform other computing tasks at the same time.

[0070] Exception handling and synchronization: During the microkernel calculation process, it is necessary to handle possible exceptions and ensure the synchronization of the calculation. This includes ensuring that all dependent data has been loaded and the calculation results are stored correctly.

[0071] 6. Performance model construction Performance Prediction: Build a performance model to predict the performance under different microkernel sizes, instruction pipeline configurations, and triple buffering mechanism settings.

[0072] Parameter adjustment: According to the performance test results, adjust the parameters of the microkernel to optimize the performance.

[0073] It is worth noting that the sub-blocks adopt an overlapping block strategy, and each sub-block contains a boundary data area to ensure that the grid point data inside the sub-block is independent of the data of other sub-blocks during the calculation process and to ensure the correctness of the calculation. The size of the sub-block is selected according to the on-chip storage capacity of the digital signal processor, the characteristics of the vector calculation unit, and the data reuse strategy to maximize data locality, reduce the number of data transmissions, and make full use of the vector calculation unit of the DSP. The calculation of the sub-block adopts a vectorized approach, which combines multiple adjacent grid points into vectors and is processed in parallel by the vector calculation unit to make full use of the instruction-level parallelism and data-level parallelism of DSPs and improve the calculation efficiency. The loading and storage operations of the sub-blocks adopt a three-buffer mechanism to decouple the loading, calculation, and storage operations, allowing them to overlap with the calculation tasks, so as to effectively use the DMA engine of the DSP for asynchronous data transmission and improve the degree of calculation-communication overlap. The loading and storage operations of the sub-blocks use the DMA engine for asynchronous data transmission to improve data transmission efficiency and reduce data transmission delay. The loading and storing operations of the sub-blocks use a two-level triple buffering mechanism to decouple the loading and storing operations, allowing them to overlap with the computing tasks to increase the degree of computing-communication overlap and further accelerate the template calculation. The calculation of the sub-blocks is performed using a specially designed microkernel to fully utilize the vector computing unit of the digital signal processor, and by optimizing the instruction pipeline, reduce the instruction execution delay and improve the computing efficiency. The data reuse strategy includes combining multiple sub-blocks into larger data blocks to reduce the number of data loading times, improve data locality, reduce the number of data transmission times, and improve computing efficiency. The loading and storing operations of the sub-blocks use data pre-fetch and post-fetch techniques to reduce data transmission delay and improve data transmission efficiency.

[0074] It should be understood that although Figure 1-Figure 2 , Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1-Figure 2 , Figure 6 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0075] In one embodiment, Figure 7As shown, a template calculation optimization device on a multi-core DSP is provided, including: a data block allocation module 702, a data block segmentation module 704, a template calculation module 706 and a data handling module 708, wherein: The data block allocation module 702 is used to divide the input data grid into a number of data blocks and allocate a DSP core to each data block. A data block contains a number of grid points.

[0076] The data block segmentation module 704 is used to complete the first-level calculation of the allocated data block by all DSP cores at the current time step, and further divide the data block into multiple sub-blocks, each of which contains multiple adjacent grid points.

[0077] The template calculation module 706 is used to load the sub-block into the vector on-chip memory of the DSP at the next time step, and use the vector calculation unit of the DSP to perform secondary calculation on the sub-block to obtain a new value for each grid point.

[0078] The data handling module 708 is used to pack the calculated new values ​​into new sub-blocks and store them back to the vector on-chip memory. The new sub-blocks are transferred from the vector on-chip memory to the off-chip memory through the DSP's data movement unit using a triple buffer mechanism for loading and storage.

[0079] For the specific definition of a template calculation optimization device on a multi-core DSP, please refer to the definition of a template calculation optimization method on a multi-core DSP mentioned above, which will not be repeated here. Each module in the above-mentioned template calculation optimization device on a multi-core DSP can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0080] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 8As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a template calculation optimization method on a multi-core DSP is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse, etc.

[0081] Those skilled in the art will understand that Figure 7-Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0082] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented: The input data grid is divided into several data blocks, and a DSP core is assigned to each data block. The data block contains several grid points.

[0083] At the current time step, all DSP cores complete the first-level calculation of the allocated data block, and further divide the data block into multiple sub-blocks, each of which contains multiple adjacent grid points.

[0084] At the next time step, the sub-block is loaded into the vector on-chip memory of the DSP, and the vector computing unit of the DSP is used to perform secondary calculations on the sub-block to obtain the new value of each grid point.

[0085] The calculated new values ​​are packaged into new sub-blocks and stored back in the vector on-chip memory. The new sub-blocks are transferred from the vector on-chip memory to the off-chip memory through the DSP's data movement unit using a triple buffer mechanism for loading and storage.

[0086] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0087] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A template calculation optimization method on a multi-core DSP, characterized in that: The method comprises: Divide the input data grid into a plurality of data blocks, and allocate a DSP core to each of the data blocks; the data block includes a plurality of grid points; At the current time step, all the DSP cores complete the first-level calculation of the allocated data block, and further divide the data block into a plurality of sub-blocks, each of which contains a plurality of adjacent grid points; At the next time step, the sub-block is loaded into the vector on-chip memory of the DSP, and the vector computing unit of the DSP is used to perform secondary calculation on the sub-block to obtain a new value of each grid point; The calculated new values ​​are packaged into new sub-blocks and stored back in the vector on-chip memory. The new sub-blocks are transferred from the vector on-chip memory to the off-chip memory through the data movement unit of the DSP using a triple buffer mechanism for loading and storage.

2. The method according to claim 1, characterized in that Before the step of dividing the input data grid into a plurality of data blocks and allocating a DSP core to each of the data blocks, the method further includes: Acquire parameter information of the multi-core DSP, wherein the parameter information includes: information of the data grid, template mode information and DSP parameter information; The information of the data grid includes: grid size and grid dimension; The template pattern information includes: data dependency range, data dependency point number and data dependency shape; The DSP parameter information includes: the size of global shared memory, the number of floating-point multiplication and addition units, the number of vector registers, the memory bandwidth, and the number of DSP cores.

3. The method according to claim 2, characterized in that Divide the input data grid into several data blocks and assign a DSP core to each of the data blocks, including: The microkernel shape is determined according to the parameter information, and the input data grid is divided into a plurality of data blocks consisting of the same number of data columns and data rows according to the microkernel shape, and a DSP core is allocated to each of the data blocks.

4. The method according to any one of claims 1 to 3, characterized in that: At the current time step, all of the DSP cores complete the first-level calculation of the allocated data block, and further divide the data block into a plurality of sub-blocks, each of which contains a plurality of adjacent grid points, including: At the current time step, the DSP core to which the data block has been allocated selects instructions corresponding to the primary computing mode according to the DSP parameter information, the template mode information and the microkernel shape, and packages the instructions corresponding to the primary computing mode into a primary instruction package to ensure that a plurality of multiplication and accumulation instructions can be executed in each clock cycle; According to the multiply-accumulate instruction, the allocated data block is subjected to primary calculation in a vectorized manner, and the data block is further divided into a plurality of sub-blocks. In the sub-blocks, a plurality of adjacent grid points are formed into vectors, which are processed in parallel by a vector calculation unit.

5. The method according to claim 4, characterized in that At the next time step, the sub-block is loaded into the vector on-chip memory of the DSP, and the vector computing unit of the DSP is used to perform secondary calculations on the sub-block to obtain a new value for each of the grid points, including: In the next time step, the sub-block is loaded into the vector on-chip memory of the DSP by using a three-buffer mechanism, and the memory access path information is determined based on the grid parameter information corresponding to the multi-core DSP chip, the template mode information and the DSP parameter information; Performing three stages of loading, calculating and storing each of the sub-blocks through a first-level three-buffer according to the path information, so that the sub-blocks are completely processed by a vector processing unit at the first level; Using the secondary triple buffer, the vector computing unit of the DSP performs three stages of secondary computing of loading, computing and storing the sub-blocks that have been processed at the primary level between the main memory and the vector on-chip memory, so as to obtain a new value of each grid point; The three-buffer mechanism includes: a primary three-buffer and a secondary three-buffer; The first level three buffering occurs between the vector on-chip memory and the vector register of the DSP, and is used to realize the parallel execution of data loading and calculation within the sub-block; The secondary triple buffer occurs between the vector on-chip memory and the off-chip memory of the DSP, and is used to implement parallel execution of data loading, calculation and storage between sub-blocks.

6. The method according to claim 5, characterized in that The method further comprises: performing three stages of loading, calculating and storing each sub-block through a first-level three-buffer according to the path information, so that the sub-block is completely processed by a vector processing unit at the first level, including: According to the path information, each of the sub-blocks is loaded, calculated and stored in three stages through the first-level three buffers. In the loading stage, the sub-block is loaded from the vector on-chip memory of the DSP to the vector register of the vector processing unit; in the calculation stage, the multiplication and addition operation unit of the vector register of the vector processing unit is used to perform floating-point multiplication and addition operations; in the storage stage, the sub-block is stored from the vector register back to the vector on-chip memory; Through the instruction set pipeline, the calculation of the current sub-block, the loading of the next sub-block and the storage of the previous sub-block are performed in the same time segment, so that all the sub-blocks are completely processed by the vector processing unit at the first level.

7. The method according to claim 5, characterized in that The sub-blocks that have been processed at the first level are loaded, calculated, and stored in three stages between the main memory and the vector on-chip memory by using the second-level triple buffer through the vector calculation unit of the DSP, and a new value of each grid point is obtained, including: The sub-blocks that have been processed at the first level are loaded, calculated and stored in three stages between the main memory and the vector on-chip memory by using the second-level triple buffer through the vector calculation unit of the DSP. In the loading stage, the sub-blocks are transferred from the main memory to the vector on-chip memory of the DSP; in the calculation stage, all operations of the first-level triple buffer are performed; in the storage stage, the sub-blocks are stored from the vector on-chip memory back to the main memory; Through a loop operation, when the sub-block in the first buffer is used for calculation, the next sub-block is loaded into the second buffer of the vector on-chip memory until the calculation is completed and a new value of each grid point is obtained.

8. The method according to any one of claims 5 to 7, characterized in that: The data transmission of the sub-blocks onto the chip or off the chip is optimized by using interleaved single-word and double-word instructions; The size of the sub-block is selected according to the on-chip storage capacity of the DSP, the characteristics of the vector computing unit and the data reuse strategy; The loading and storing operations of the sub-blocks adopt a DMA engine to perform asynchronous data transfer; The calculation of the sub-block is performed by using a micro-kernel to utilize the vector computing unit and optimized instruction pipeline technology of the DSP; The shape of the microkernel is designed according to the number of vector registers of the DSP, the instruction packet filling constraint and the instruction delay constraint of the vector computing unit; The calculated new value is packaged into a new sub-block and stored back in the vector on-chip memory. The new sub-block is transferred from the vector on-chip memory to the off-chip memory through the data movement unit of the DSP using a triple buffer mechanism for loading and storage, including: The calculated new values ​​are packaged into new sub-blocks and stored back in the vector on-chip memory. All the new sub-blocks are stored in the third buffer using a three-buffer mechanism and written back from the vector on-chip memory to the main memory through the data movement unit of the DSP to complete the loading and storage of input data.

9. A template calculation optimization device on a multi-core DSP, characterized in that: The device comprises: A data block allocation module, used to divide the input data grid into a plurality of data blocks, and allocate a DSP core to each of the data blocks; the data block includes a plurality of grid points; A data block segmentation module, used for, at the current time step, all the DSP cores complete the first-level calculation of the allocated data block, and further divide the data block into a plurality of sub-blocks, wherein the sub-blocks include a plurality of adjacent grid points; A template calculation module, used for loading the sub-block into the vector on-chip memory of the DSP at the next time step, and performing secondary calculation on the sub-block using the vector calculation unit of the DSP to obtain a new value of each grid point; The data handling module is used to pack the calculated new values ​​into new sub-blocks and store them back into the vector on-chip memory. The new sub-blocks are transferred from the vector on-chip memory to the off-chip memory through the data movement unit of the DSP using a triple buffer mechanism for loading and storage.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

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