Bank address decoder and memory

Abstract

The embodiment of the invention provides a memory bank address decoder and a semiconductor memory, and the memory bank address decoder comprises a command address processing circuit which is used for determining a first operation address signal according to a first command signal, a second command signal, a first undecoded address signal and a second undecoded address signal; wherein the first undecoded address signal is an address signal corresponding to the first command signal, and the second undecoded address signal is an address signal corresponding to the second command signal; the address decoding circuit is connected with the command address processing circuit and receives the first operation address signal, and the address decoding circuit is used for decoding the first operation address signal to obtain a second operation address signal; and the command address activation circuit is connected with the address decoding circuit and receives the second operation address signal, and the command address activation circuit is used for generating a memory bank activation address signal according to the information of the first command signal, the second command signal and the second operation address signal.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of memory, and in particular to a storage body address decoder and a memory. Background Art

[0002] Under the current technical framework, various commands are required to operate the memory, and the address decoding logic of each command is processed independently. Subsequently, each command is used as a clock signal to sample and latch the decoded memory address, and then generate an enable signal that determines the on or off state of the memory. However, this practice of configuring the address decoding circuit separately for each type of command inevitably leads to a significant consumption of chip area, which is contrary to the trend of pursuing high integration and compact layout in modern integrated circuit design, thus constituting a potential obstacle to improving the overall performance and efficiency of the system.

[0003] Therefore, exploring a new circuit that can not only meet the needs of command address decoding but also significantly reduce area consumption is of great significance for improving the integration and overall performance of the storage system. Summary of the invention

[0004] The embodiments of the present application provide a storage body address decoder and a memory, which at least help to solve the problem of excessive area occupied by the address decoding circuit.

[0005] According to some embodiments of the present application, the embodiments of the present application provide a memory address decoder, characterized in that it includes a command address processing circuit, an address decoding circuit and a command address activation circuit, wherein:

[0006] The command address processing circuit is used to determine a first operation address signal according to a first command signal, a second command signal, a first undecoded address signal and a second undecoded address signal; wherein the first undecoded address signal is an address signal corresponding to the first command signal, and the second undecoded address signal is an address signal corresponding to the second command signal;

[0007] The address decoding circuit is connected to the command address processing circuit and receives the first operation address signal, and the address decoding circuit is used to decode the first operation address signal to obtain a second operation address signal;

[0008] The command address activation circuit is connected to the address decoding circuit and receives the second operation address signal. The command address activation circuit is used to generate a storage body activation address signal according to information of the first command signal, the second command signal and the second operation address signal.

[0009] In some embodiments, the command address processing circuit includes a command processing circuit and a command address latch circuit, wherein the command processing circuit is used to narrow the effective level width of the first command signal according to the first command signal and the second command signal to generate a first narrowed command signal; wherein the effective level width of the first narrowed command signal is narrower than the first command signal; the command address latch circuit is connected to the command processing circuit and receives the first narrowed command signal, and is used to generate a first operation address signal according to the first narrowed command signal, the second command signal, the first undecoded address signal and the second undecoded address signal.

[0010] In some embodiments, the command processing circuit includes a first inverter and a first NOR gate, the input end of the first inverter receives the first command signal, the first input end of the first NOR gate is connected to the output end of the first inverter, the second input end of the first NOR gate receives the second command signal, and the output end of the first NOR gate outputs the first narrowing command signal.

[0011] In some embodiments, the command address latch circuit includes a first gated inverter and a second gated inverter; wherein, the control end of the first gated inverter receives the first narrowed command signal, and the input end of the first gated inverter receives the first undecoded address signal; the control end of the second gated inverter receives the second command signal, and the input end of the second gated inverter receives the second undecoded address signal; the output end of the first gated inverter and the output end of the second gated inverter are connected to the input end of the second inverter, and the output end of the second inverter outputs the first operation address signal.

[0012] In some embodiments, the command address latch circuit also includes a third inverter and a third gated inverter; wherein, the input end of the third inverter is connected to the output end of the second inverter, the output end of the third inverter is connected to the input end of the third gated inverter, the control end of the third gated inverter receives the first narrowing command signal and the second command signal, and the output end of the third gated inverter is connected to the input end of the third inverter.

[0013] In some embodiments, the command address activation circuit is connected to the command address processing circuit and the address decoding circuit and receives the first narrowed command signal and the second operation address signal. The command address activation circuit is used to perform sampling processing and logical operation processing on the first narrowed command signal and the second command signal according to the second operation address signal to generate a storage body activation address signal.

[0014] In some embodiments, the command address activation circuit includes a first trigger, a second trigger and a first latch, wherein the data input terminal of the first trigger receives the first narrowed command signal, the clock input terminal of the first trigger receives the second operation address signal, and the data output terminal of the first trigger is connected to the first input terminal of the first latch; the data input terminal of the second trigger receives the second command signal, the clock input terminal of the second trigger receives the second operation address signal, and the data output terminal of the second trigger is connected to the second input terminal of the first latch; and the output terminal of the first latch outputs the storage body activation address signal.

[0015] In some embodiments, the data output terminals of the first trigger and the second trigger both include a data positive output terminal and a data negative output terminal, the data negative output terminal of the first trigger is connected to the first input terminal of the first latch; the data negative output terminal of the second trigger is connected to the second input terminal of the first latch; the first latch includes two NAND gates.

[0016] In some embodiments, the data output terminals of the first trigger and the second trigger both include a data positive output terminal and a data negative output terminal, and the data negative output terminal of the first trigger is connected to the first input terminal of the first latch; the data positive output terminal of the second trigger is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate receives a full storage body control signal, and the output terminal of the second NOR gate is connected to the second input terminal of the first latch; the first latch includes two NAND gates.

[0017] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a memory, which includes a storage body address decoder and a storage body as described in any of the aforementioned embodiments, and the storage body is connected to the storage body address decoder for activating the corresponding storage body according to the storage body activation address signal.

[0018] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0019] The present application provides a memory address decoder, which determines a first operation address signal according to a first command signal and a second command signal by setting a command address processing circuit, so that an address decoding circuit can be used to sequentially decode the addresses corresponding to the first command signal and the second command signal to obtain a second operation address signal; and through a command address activation circuit, the second operation address is processed using the information of the first command signal and the second command signal to generate a corresponding memory activation address signal to determine whether the corresponding memory address is turned on, so that the memory address decoder in different types of commands in the memory can be reused through control logic, which can effectively reduce the layout area. In addition, due to the addition of a latch structure, the corresponding memory address information is latched and output according to the command information, which can avoid invalid signal flipping and reduce dynamic power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0021] Figure 1 A schematic diagram of the structure of a storage address decoder provided in an embodiment of the present disclosure.

[0022] Figure 2 A waveform diagram of an overlapped first command signal and a second command signal provided in an embodiment of the present disclosure.

[0023] Figure 3 A schematic diagram of the circuit structure of a command address processing circuit provided in an embodiment of the present disclosure.

[0024] Figure 4 A waveform diagram of a first narrowing command signal and a second command signal provided in an embodiment of the present disclosure.

[0025] Figure 5 A circuit structure diagram of another command address processing circuit provided in an embodiment of the present disclosure.

[0026] Figure 6 A schematic diagram of the circuit structure of a third gated inverter provided in an embodiment of the present disclosure.

[0027] Figure 7 A circuit structure diagram of another command address processing circuit provided in an embodiment of the present disclosure.

[0028] Figure 8 A schematic diagram of the circuit structure of a command address activation circuit provided in an embodiment of the present disclosure.

[0029] Fig. 9A detailed circuit structure diagram of a command address activation circuit provided in an embodiment of the present disclosure.

[0030] Fig.10 A detailed circuit structure diagram of another command address activation circuit provided in an embodiment of the present disclosure.

[0031] Fig.11 A schematic diagram of a memory provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Below, the exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present invention. As will be appreciated by those skilled in the art, the described embodiments can be modified in various ways, all of which do not deviate from the spirit or scope of the present invention. For example, the exemplary embodiments provided herein are considered to be able to be combined with each other in whole or in part to achieve. Specifically, an element described in a specific exemplary embodiment, even if not described in another exemplary embodiment, can also be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

[0033] Throughout this specification, when any part is referred to as being "connected" to another part, it includes the case where any part and another part are "indirectly connected" to each other due to other parts being interposed therebetween, as well as the case where any part and another part are "directly connected" to each other. For example, it should be understood that when an element is referred to as being "connected" or "coupled" to or "on another element", it may be directly connected or coupled to or on the other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, or is referred to as "contacting" or "contacting" another element, there are no intermediate elements at the contact point.

[0034] In addition, "electrical connection" conceptually includes physical connection and physical disconnection. It is understood that when a component is referred to by terms such as "first" and "second", the component is not limited thereto. They may be used only for the purpose of distinguishing the component from other components and may not limit the order or importance of the components. In some cases, the first component may be referred to as the second component without departing from the scope of the claims set forth herein. Similarly, the second component may also be referred to as the first component.

[0035] Each operation of the memory (such as activation, refresh, precharge, read, write, etc.) needs to receive the corresponding command and address information before it can be performed. In the prior art, the address decoding corresponding to the commands of various operations of the memory is performed separately. Subsequently, each type of command is used as a clock signal to sample and latch the decoded storage body address, and then generate an enable signal that determines the on or off state of the storage body. For example, for the activation command (Activate) and the precharge command (Pre-charge), the activation command has a set of address decoding circuits, and the precharge command has a set of address decoding circuits. When the activation command or the precharge command is received, the address decoding circuit performs address decoding respectively. This consumes a large amount of area.

[0036] Therefore, exploring a new circuit that can not only meet the needs of command address decoding but also significantly reduce area consumption is of great significance for improving the integration and overall performance of the storage system.

[0037] The present application provides a memory address decoder, including a command address processing circuit, an address decoding circuit and a command address activation circuit, wherein the command address processing circuit is used to determine a first operation address signal according to a first command signal, a second command signal, a first undecoded address signal and a second undecoded address signal; wherein the first undecoded address signal is an address signal corresponding to the first command signal, and the second undecoded address signal is an address signal corresponding to the second command signal; the address decoding circuit is connected to the command address processing circuit and receives the first operation address signal, and the address decoding circuit is used to decode the first operation address signal to obtain a second operation address signal; the command address activation circuit is connected to the address decoding circuit and receives the second operation address signal, and the command address activation circuit is used to generate a memory activation address signal according to the information of the first command signal, the second command signal and the second operation address signal. Through the command address processing circuit, the first command signal and the second command signal can reuse the same address decoding circuit, effectively reducing the chip area. In addition, due to the addition of a latch structure, the corresponding memory address information is latched and output according to the command information, which can avoid invalid signal flipping and reduce dynamic power consumption.

[0038] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0039] Figure 1A schematic diagram of the structure of a memory address decoder provided by an embodiment of the present disclosure. Figure 1 , the memory address decoder 10 includes a command address processing circuit 110, an address decoding circuit 120 and a command address activation circuit 130, wherein,

[0040] The command address processing circuit 110 is used to determine the first operation address signal OP1<4:0> according to the first command signal CMD_ACT, the second command signal CMD_PRE, the first undecoded address signal ACT_BA<4:0> and the second undecoded address signal PRE_BA<4:0>; wherein the first undecoded address signal ACT_BA<4:0> is the address signal of the operation corresponding to the first command signal CMD_ACT, and the second undecoded address signal PRE_BA<4:0> is the address signal of the operation corresponding to the second command signal CMD_PRE;

[0041] The address decoding circuit 120 is connected to the command address processing circuit 110 and receives the first operation address signal OP1<4:0>. The address decoding circuit 120 is used to decode the first operation address signal OP1<4:0> to obtain a second operation address signal OP2<31:0>;

[0042] The command address activation circuit 130 is connected to the address decoding circuit 120 and receives the second operation address signal OP2<31:0>. The command address activation circuit 130 is used to generate a storage body activation address signal OP3<31:0> based on the information of the first command signal CMD_ACT, the second command signal CMD_PRE and the second operation address signal OP2<31:0>.

[0043] Among them, the first command signal and the second command signal are commands for performing different types of operations on the memory, for example, the first command signal can be an activation command (Activate, ACT), and the second command signal can be a pre-charge command (Pre-charge, PRE), a read command (Read), a write command (Write), a read command with automatic pre-charge (Read with AutoPre-charge, RAP), a read command with automatic pre-charge (Write with Auto Pre-charge, WAP), etc. For the convenience of presentation, the context takes the activation command as the first command signal (CMD_ACT) and the pre-charge command as the second command signal (CMD_PRE) as an example. The first command signal and the second command signal are decoded command signals. For example, the first command signal CMD_ACT is a pulse signal with an effective level width of 2 system clock cycle widths (2T), and the second command signal CMD_PRE is a pulse signal with an effective level pulse width of 1 system clock cycle width (1T). Among them, the system clock cycle refers to the cycle of the system clock ck. The effective level can be a high level or a low level, and this article takes the effective level as an example of a high level.

[0044] The command address processing circuit 110 controls the output sequence of the first undecoded address signal ACT_BA<4:0> and the second undecoded address signal PRE_BA<4:0> of the corresponding operation by adopting the decoded first command signal CMD_ACT and the second command signal CMD_PRE as control signals, and sequentially outputs the address of the corresponding operation according to the timing of receiving the first command signal CMD_ACT and the second command signal CMD_PRE, thereby realizing the selection of the storage body address under different commands, so that the address decoding circuit 120 only receives and decodes the address corresponding to the command under different command timings, thereby realizing the multiplexing of the address decoding circuit of the storage body.

[0045] That is, if the command address processing circuit 110 first receives the first command signal CMD_ACT and then receives the second command signal CMD_PRE, the command address processing circuit 110 processes the first undecoded address signal ACT_BA<4:0> and the second undecoded address signal PRE_BA<4:0> in sequence, and outputs the first undecoded address signal ACT_BA<4:0> and the second undecoded address signal PRE_BA<4:0> in sequence as the first operation address signal OP1<4:0>.

[0046] That is, the first operation address signal OP1<4:0> is the address signal corresponding to the command signal at the valid level between the first command signal CMD_ACT and the second command signal CMD_PRE. When the first command signal CMD_ACT is at the valid level, the first operation address signal OP1<4:0> is the address signal corresponding to the first command signal CMD_ACT; when the second command signal CMD_PRE is at the valid level, the first operation address signal OP1<4:0> is the address signal corresponding to the second command signal CMD_PRE.

[0047] In some embodiments, a conventional decoder is used to form the address decoding circuit 120. For example, in the case of receiving a six-bit first operation address signal OP1<4:0>, the address decoding circuit 120 can use a 5-32 binary decoder to decode the input 5-bit data into 32-bit data with only one bit in a valid level state, thereby obtaining a second operation address signal OP2<31:0>.

[0048] The command address activation circuit 130 is connected to the address decoding circuit 120 and receives the second operation address signal OP2<4:0>. The command address activation circuit 130 is used to generate a storage body activation address signal OP3<31:0> based on the information of the first command signal CMD_ACT, the second command signal CMD_PRE and the second operation address signal OP2<31:0>.

[0049] The second operation address signal OP2<31:0> includes a decoded address signal corresponding to the timing of the first command signal CMD_ACT and the second command signal CMD_PRE. The command address activation circuit 130 receives the second operation address signal OP2<4:0>, and processes these signals according to the information of the first command signal CMD_ACT, the second command signal CMD_PRE and the second operation address signal OP2<31:0>. At the moment of the timing operation of the first command signal CMD_ACT and the second command signal CMD_PRE, the corresponding address signal is processed to generate a corresponding storage body activation address signal, thereby turning on or off the storage body.

[0050] Thus, through the circuit shown in this embodiment, the bank address decoding circuits of different commands can be reused. Moreover, for the addresses corresponding to different commands, the corresponding bank activation address signals are generated according to the timing and address information of the commands, thereby avoiding invalid signal flipping and reducing dynamic power consumption.

[0051] Since the first command signal CMD_ACT is a pulse signal with a 2T effective level width, and the second command signal CMD_PRE is a pulse signal with a 1T effective level pulse width, in some operating scenarios, an activation command may be followed by a pre-charge command, resulting in overlap of the first command signal and the second command signal. Figure 2 FIG. 4 shows a waveform diagram of a first command signal CMD_ACT and a second command signal CMD_PRE overlapping each other. Figure 2 As shown, in the first cycle (first 1T) of the first command signal CMD_ACT, the address decoding and address selection corresponding to the activation command can be performed. However, for the second cycle (second 1T) of the first command signal CMD_ACT, since the first command signal CMD_ACT has not yet ended, and the second command signal CMD_PRE has been received at this time, a signal conflict will occur at this time, resulting in the inability to correctly decode and select the corresponding address.

[0052] In this regard, Figure 3 A circuit structure diagram of a command address processing circuit provided in an embodiment of the present disclosure. The command address processing circuit 110 includes a command processing circuit 111 and a command address latch circuit 112. The command processing circuit 111 is used to narrow the effective level width of the first command signal CMD_ACT according to the first command signal CMD_ACT and the second command signal CMD_PRE to generate a first narrowed command signal CMD_ACTD; wherein the effective level width of the first narrowed command signal CMD_ACTD is narrower than that of the first command signal CMD_ACT;

[0053] The command address latch circuit 112 is connected to the command processing circuit 111 and receives the first narrowed command signal CMD_ACTD, and is used to generate a first operation address signal OP1<4:0> according to the first narrowed command signal CMD_ACTD, the second command signal CMD_PRE, the first undecoded address signal ACT_BA<4:0> and the second undecoded address signal PRE_BA<4:0>.

[0054] That is, the command address processing circuit 110 processes the first command signal, the second command signal, the first undecoded address signal, and the second undecoded address signal, and outputs the first operation address signal as the address signal corresponding to the command signal at the valid level between the first command signal and the second command signal; and the priority of the second command signal is higher than the first command signal. When the first command signal is at the valid level, the first operation address signal is the address signal corresponding to the first command signal; when the second command signal is at the valid level, the first operation address signal is the address signal corresponding to the second command signal; when the first command signal and the second command signal are at the valid level at the same time, the first operation address signal is the address signal corresponding to the second command signal.

[0055] The command processing circuit narrows the effective level width of the first command signal based on the second command signal, so that the effective level width of the first command signal is narrowed, thereby avoiding the conflict between the first command signal and the second command signal.

[0056] After narrowing, when the second command signal is at a valid level, the first command signal is at an invalid level. Figure 4 A waveform diagram of a first narrowed command signal CMD_ACTD and a second command signal CMD_PRE is shown. The first narrowed command signal CMD_ACTD is at an effective level in the first cycle, and the second command signal CMD_PRE is at an effective level in the second cycle. Thus, the command address latch circuit 112 can output the first undecoded address signal ACT_BA<4:0> in the first cycle, and output the second undecoded address signal PRE_BA<4:0> in the second cycle, and the address decoding circuit can decode the storage body address corresponding to the first command signal in the first cycle, and decode the storage body address corresponding to the second command signal in the second cycle.

[0057] Therefore, the command address processing circuit 110 can accurately respond to the first command signal and the second command signal in various situations, and output a correct first operation address signal, so that the memory address decoder can correctly decode it.

[0058] In some embodiments, Figure 3 As shown, the command processing circuit 111 includes a first inverter INV1 and a first NOR gate NOR1, the input end of the first inverter INV1 receives the first command signal CMD_ACT, the first input end of the first NOR gate NOR1 is connected to the output end of the first inverter INV1, the second input end of the first NOR gate NOR1 receives the second command signal CMD_PRE, and the output end of the first NOR gate NOR1 outputs the first narrowed command signal CMD_ACTD.

[0059] Therefore, by narrowing the first command signal CMD_ACT through the second command signal CMD_PRE, the first command signal CMD_ACT and the second command signal CMD_PRE can be accurately connected.

[0060] In some embodiments, Figure 3 As shown, the command address latch circuit 112 includes a first gated inverter GINV1 and a second gated inverter GINV2; wherein, the control end of the first gated inverter GINV1 receives the first narrowed command signal CMD_ACTD, and the input end of the first gated inverter GINV1 receives the first undecoded address signal ACT_BA<4:0>; the control end of the second gated inverter GINV2 receives the second command signal CMD_PRE, and the input end of the second gated inverter GINV2 receives the second undecoded address signal PRE_BA<4:0>; the output end of the first gated inverter GINV1 and the output end of the second gated inverter GINV2 are connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 outputs the first operation address signal OP1<4:0>.

[0061] In this embodiment, the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE are used as control signals of the gated inverter to control the transmission timing of the corresponding address signal. When the command signal is in an effective level state, the corresponding address information is transmitted to the subsequent stage, so that the corresponding command signal sequentially outputs its corresponding address information. Specifically, when the first narrowing command signal CMD_ACTD is in an effective level state ( Figure 3 , the first gate inverter GINV1 is turned on, and the first undecoded address signal ACT_BA<4:0> is output as the first operation address signal OP1<4:0>; when the second command signal CMD_PRE is in the valid level state ( Figure 3 The second gate inverter GINV2 is turned on, and the second undecoded address signal PRE_BA<4:0> is output as the first operation address signal OP1<4:0>.

[0062] Figure 5 A circuit structure diagram of another command address processing circuit provided by an embodiment of the present disclosure. Figure 3The same parts of the embodiments are not repeated here. In addition, the command address latch circuit 110 also includes a third inverter INV3 and a third gated inverter GINV3; wherein, the input end of the third inverter GINV3 is connected to the output end of the second inverter INV2, the output end of the third inverter INV3 is connected to the input end of the third gated inverter GINV3, the control end of the third gated inverter GINV3 receives the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE, and the output end of the third gated inverter GINV3 is connected to the input end of the third inverter.

[0063] Since the first narrowed command signal CMD_ACTD and the second command signal CMD_PRE perform address latching in time-sharing, when performing address latching, only one third gated inverter GINV3 can be used to perform address latching of two commands. In addition, the address information can be latched according to the command information by mounting the third inverter INV3 and the third gated inverter GINV3 at the output end of the command address latch circuit 110. When the current command signal ends and the next command signal has not yet arrived, the circuit can latch the current address information, so that the command address latch circuit 110 can latch and output the corresponding storage body address information according to the command information. And only under the corresponding command will the address information of the activated storage body be transmitted to the decoding unit for decoding, and the level flipping and decoding process will not occur when there is no corresponding command. Therefore, the waste of dynamic power consumption can be avoided.

[0064] In some embodiments, the circuit structure of the third gate inverter GINV3 can be as follows: Figure 6 shown. Figure 6 In the embodiment, the third gated inverter GINV3 includes an inverter formed by an NMOS and a PMOS, and an NMOS for receiving a control signal is formed between the source of the NMOS and the ground level. The control end of the NMOS forms the control end of the third gated inverter GINV3, and the control end of the third gated inverter GINV3 receives control signals through a first OR gate: the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE. When any of the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE is at a valid level, the third gated inverter GINV3 is turned on, and the signals received at the input ends of the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE are latched; when both the first narrowing command signal CMD_ACTD and the second command signal CMD_PRE are at an invalid level, the third gated inverter GINV3 is turned off, and the input signal is no longer latched, thereby reducing power consumption.

[0065] In some embodiments, the first command signal may be an activation command Activate, and the second command signal may be one or more of multiple types of command signals different from the first command signal type, the multiple types of command signals including a pre-charge command (Pre-charge, PRE), a read command (Read), a write command (Write), a read command with automatic pre-charge (Read with Auto Pre-charge, RAP), and a read command with automatic pre-charge (Write with Auto Pre-charge, WAP). Figure 7 Take the example that the second command signal includes a plurality of command signals of different types.

[0066] Figure 7 A circuit structure diagram of another command address processing circuit provided by an embodiment of the present disclosure. Figure 3 The same parts as in the embodiments will not be described in detail. Figure 3 The difference between the embodiments is that the second command signal includes multiple decoded command signals, specifically: precharge command CMD_PRE, read command CMD_READ, write command CMD_WRITE, read command with automatic precharge CMD_RAP, write command with automatic precharge CMD_WAP. In some other embodiments, the second command signal can also be part of the above signals.

[0067] refer to Figure 7 Corresponding to the fact that the second command signal includes a plurality of decoded command signals, the command processing circuit 111 further includes a second OR gate OR2. The second OR gate OR2 includes a plurality of input terminals, and all command signals of the second command signal are used as input terminals of the second OR gate OR2, so that when any signal in the second command signal is at a valid level, the valid level of the first command signal can be cut off, thereby correctly decoding the address.

[0068] Corresponding to the second command signal including a plurality of decoded command signals, the command address latch circuit 112 includes a plurality of gated inverters. The control terminal of each gated inverter receives the first command signal CMD_ACTD or a second command signal, such as Figure 7 The control end of the gated inverter GINVn shown in FIG. 1 receives the second command signal CMD_WAP; the input end of each gated inverter receives the address information corresponding to the command signal received by the control end, such as Figure 7 The control end of the gated inverter GINVn shown in FIG. 1 receives the second command signal WAP_BA<4:0>. Therefore, each gated inverter can transmit the address information of the operation corresponding to the command signal to the next stage under the control of the first command signal or the corresponding second command signal.

[0069] Corresponding to the second command signal including a plurality of decoded command signals, the control terminal of the third gate-controlled inverter GINV3 receives the first command signal and all the second command signals.

[0070] Through the above design, the storage address decoders of multiple commands can be reused, further saving area.

[0071] In some embodiments, the command address activation circuit 130 is connected to the command address processing circuit 110 and the address decoding circuit 120 and receives the first narrowed command signal CMD_ACTD and the second operation address signal OP2<31:0>. The command address activation circuit 130 is used to perform sampling processing and logical operation processing on the first narrowed command signal and the second command signal according to the second operation address signal OP2<31:0> to generate a storage body activation address signal OP3<31:0>.

[0072] That is, the command address activation circuit 130 directly receives the first narrowed command signal CMD_ACTD after narrowing, and uses the command signal to participate in the processing, thereby avoiding decoding conflicts. In addition, the first narrowed command signal CMD_ACTD and the second command signal CMD_PRE are sampled and processed by the second operation address signal OP2<31:0>, and the storage body activation address signal OP3<31:0> is generated. At the time of the timing operation of the first command signal CMD_ACT and the second command signal CMD_PRE, the corresponding address signal can be activated to generate the corresponding storage body activation address signal, thereby avoiding invalid signal flipping and reducing dynamic power consumption.

[0073] In another embodiment, the command address activation circuit 130 may not be connected to the command address processing circuit 110, and may not receive the first narrowed command signal CMD_ACTD, but may directly receive the first command signal CMD_ACT. In this case, the command address activation circuit 130 is also provided with a circuit similar to the command processing circuit 111, so that the first command signal is narrowed in the command address activation circuit 130 to obtain the narrowed first narrowed command signal that does not conflict with the second command signal.

[0074] In another embodiment, the command address activation circuit 130 may not be connected to the command address processing circuit 110, and does not receive the first narrowed command signal CMD_ACTD but directly receives the first command signal CMD_ACT. In this case, the command address activation circuit 130 uses its own processing logic design (such as a sequential circuit design similar to a latch) to make the priority of the second command signal CMD_PRE higher than the first command signal CMD_ACT. When the second command signal CMD_PRE is at a valid level, the second command signal CMD_PRE and the corresponding operation address are output, so that the first command signal CMD_ACT is directly used for sampling processing and logic operation processing to generate the storage body activation address signal OP3<31:0>.

[0075] Figure 8 The following is a schematic diagram of the circuit structure of a command address activation circuit provided by an embodiment of the present disclosure. Figure 8 As shown, the command address activation circuit 130 includes a first flip-flop DFF1, a second flip-flop DFF2 and a first latch LAT1, wherein:

[0076] The data input terminal D of the first flip-flop DFF1 receives the first shrink command signal CMD_ACTD, the clock input terminal Clk of the first flip-flop DFF1 receives the second operation address signal OP2<31:0>, and the data output terminal of the first flip-flop DFF1 is connected to the first input terminal of the first latch LAT1;

[0077] The data input terminal D of the second flip-flop DFF2 receives the second command signal CMD_PRE, the clock input terminal Clk of the second flip-flop DFF2 receives the second operation address signal OP2<31:0>, and the data output terminal of the second flip-flop DFF2 is connected to the second input terminal of the first latch LAT1;

[0078] The output end of the first latch LAT1 outputs the bank activation address signal OP3<31:0>.

[0079] Thus, through the timing logic of the trigger and latch, the address information of the activated storage body will be transmitted to the subsequent stage only under the corresponding command, and the level flipping and decoding process will not occur when there is no corresponding command and activation address. Therefore, the waste of dynamic power consumption can be avoided.

[0080] The first flip-flop DFF1 and the second flip-flop DFF2 may adopt a conventional D-type flip-flop structure. The first latch LAT1 may adopt a conventional NAND gate or NOR gate latch.

[0081] Fig. 9 A method provided in the embodiment of the present disclosure Figure 8The detailed circuit structure diagram of the command address activation circuit is shown in Figure 1. Fig. 9 As shown, the data output terminals of the first trigger DFF1 and the second trigger DFF2 both include a data positive output terminal Q and a data negative output terminal QN. The data negative output terminal QN of the first trigger DFF1 is connected to the first input terminal of the first latch LAT1; the data negative output terminal QN of the second trigger DFF2 is connected to the second input terminal of the first latch LAT1; the first latch LAT1 includes two NAND gates.

[0082] refer to Fig. 9 The data input terminal D of the first flip-flop DFF1 receives the first narrowing command signal CMD_ACTD, the clock input terminal Clk of the first flip-flop DFF1 receives the second operation address signal OP2<31:0>, and the data output terminal of the first flip-flop DFF1 is connected to the first input terminal of the first latch LAT1; the data input terminal D of the second flip-flop DFF2 receives the second command signal CMD_PRE, the clock input terminal Clk of the second flip-flop DFF2 receives the second operation address signal OP2<31:0>, and the data output terminal of the second flip-flop DFF2 is connected to the second input terminal of the first latch LAT1. The first latch LAT1 includes two NAND gates connected in a latch structure, and the first input terminal of the first latch LAT1 is the set terminal of the latch structure, and the first input terminal of the first latch LAT1 is the reset terminal of the latch structure.

[0083] The memory is provided with a plurality of banks, each of which receives one bit of the bank activation address signal. This paper takes the memory including 32 banks as an example, the bank activation address signal has 32 bits, OP3<31:0>, and each bank receives one bit of the bank activation address signal OP3<31:0>.

[0084] Correspondingly, the command activation address circuit 130 is also provided with a plurality of command activation address units, and the number of command activation address units is the same as the number of memory banks. Each command activation address unit receives one bit of the second operation address signal OP2<31:0> and performs operation processing with the corresponding command signal.

[0085] The second operation address signal OP2<31:0> serves as a clock signal for each command activation address unit. For the command activation address unit of the activated memory address, the corresponding second operation address signal is at a valid level. At this time, when the first narrowing command signal CMD_ACTD is at a valid level, the first input terminal of the first latch LAT1 receives an invalid level, and the output terminal of the first latch LAT1 outputs a valid level to start the memory that should be activated. When the second command signal CMD_PRE is at a valid level, the second input terminal of the first latch LAT1 receives an invalid level, and the output terminal of the first latch LAT1 outputs an invalid level to turn off the activated memory.

[0086] Thus, the memory bank corresponding to the memory bank address is activated by the first command signal CMD_ACT, and the memory bank corresponding to the memory bank address is deactivated by the second command signal CMD_PRE, thereby controlling the memory bank.

[0087] It should be noted that in the field of electronic technology, under the premise of ensuring logical correctness, the signal is input or output after being inverted, or the input or output signal is inverted, which is an easy change made by those skilled in the art in practical applications in terms of form and details, and does not deviate from the spirit and scope of the present application. In other words, the processing of the signal or the processing of the inverted signal belongs to the easily deformable embodiment of the present application.

[0088] Fig.10 Another embodiment of the present disclosure provides Figure 8 Detailed circuit diagram of the command address activation circuit. Fig.10 Zhongyu Figure 8 and Fig. 9 The similarities will not be repeated here. Fig.10 In the embodiment, the data output terminals of the first trigger DFF1 and the second trigger DFF2 both include a data positive phase output terminal Q and a data negative phase output terminal QN, the data negative phase output terminal QN of the first trigger DFF1 is connected to the first input terminal of the first latch LAT1; the data positive phase output terminal of the second trigger DFF2 is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate receives the full storage body control signal, and the output terminal of the second NOR gate is connected to the second input terminal of the first latch LAT1; the first latch LAT1 includes two NAND gates.

[0089] refer to Fig.10The data input terminal D of the first flip-flop DFF1 receives the first narrowing command signal CMD_ACTD, the clock input terminal Clk of the first flip-flop DFF1 receives the second operation address signal OP2<31:0>, and the data inverting output terminal QN of the first flip-flop DFF1 is connected to the first input terminal of the first latch LAT1; the data input terminal D of the second flip-flop DFF2 receives the second command signal CMD_PRE, the clock input terminal Clk of the second flip-flop DFF2 receives the second operation address signal OP2<31:0>, and the data positive output terminal Q of the second flip-flop DFF2 is connected to the first input terminal of the second NOR gate NOR2, the second input terminal of the second NOR gate NOR2 receives the full storage bank control signal CMD_PRE All, and the output terminal of the second NOR gate NOR2 is connected to the second input terminal of the first latch LAT1. The first latch LAT1 includes two NAND gates connected in a latch structure, and the first input terminal of the first latch LAT1 is the set terminal of the latch structure, and the first input terminal of the first latch LAT1 is the reset terminal of the latch structure.

[0090] Thus, the full-storage-bank control signal CMD_PRE All is introduced through the second NOR gate NOR2, so that the activation of the storage bank is also controlled by the full-storage-bank control signal CMD_PRE All. The full-storage-bank control signal can be a signal for precharging the full-storage-bank. Specifically, the second operation address signal OP2<31:0> serves as a clock signal for each command activation address unit. For the command activation address unit of the activated storage bank address, its corresponding second operation address signal is a valid level. At this time, when the first narrowed command signal CMD_ACTD is a valid level, the first input end of the first latch LAT1 receives an invalid level, and the output end of the first latch LAT1 outputs a valid level to start the storage bank that should be activated. When the second command signal CMD_PRE or the full-storage-bank control signal CMD_PRE All is a valid level, the second input end of the first latch LAT1 receives an invalid level, and the output end of the first latch LAT1 outputs an invalid level to turn off the activated storage bank.

[0091] Therefore, the whole memory bank control signal is introduced through the second NOR gate to increase the control over the whole memory bank, increase the pre-charge function of the whole memory bank, and increase the flexibility of design.

[0092] Fig.11 A schematic diagram of a memory provided by an embodiment of the present disclosure. Fig.10As shown, the memory 1 includes the bank address decoder 10 and a plurality of banks 20 as described in any of the foregoing embodiments, and the plurality of banks 20 are connected to the bank address decoder 10 and are used to activate the corresponding banks according to the bank activation address signal. Specifically, the banks 20 include banks 0 (Bank0) to 31 (Bank31), each of which receives one bit of the bank activation address signal OP3<31:0> and is turned on or off by the corresponding signal.

[0093] The memory bank is composed of multiple memory cells in an array. The memory may be a dynamic random access memory (DRAM), a static random access memory (SRAM), a NAND FLASH, a NOR FLASH, a ferroelectric memory (FeRAM), etc., and this application does not make specific limitations.

[0094] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application, so the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A memory address decoder, characterized in that: It includes a command address processing circuit, an address decoding circuit and a command address activation circuit, wherein: The command address processing circuit is used to determine a first operation address signal according to a first command signal, a second command signal, a first undecoded address signal and a second undecoded address signal; wherein the first undecoded address signal is an address signal corresponding to the first command signal, and the second undecoded address signal is an address signal corresponding to the second command signal; The address decoding circuit is connected to the command address processing circuit and receives the first operation address signal, and the address decoding circuit is used to decode the first operation address signal to obtain a second operation address signal; The command address activation circuit is connected to the address decoding circuit and receives the second operation address signal. The command address activation circuit is used to generate a storage body activation address signal based on the information of the first command signal, the second command signal and the second operation address signal.

2. The memory address decoder according to claim 1, wherein: The command address processing circuit includes a command processing circuit and a command address latch circuit, wherein: The command processing circuit is used for narrowing the effective level width of the first command signal according to the first command signal and the second command signal to generate a first narrowed command signal; wherein the effective level width of the first narrowed command signal is narrower than that of the first command signal; The command address latch circuit is connected to the command processing circuit and receives the first narrowed command signal, and is used to generate a first operation address signal according to the first narrowed command signal, the second command signal, the first undecoded address signal and the second undecoded address signal.

3. The memory address decoder according to claim 2, wherein: The command processing circuit includes a first inverter and a first NOR gate, the input end of the first inverter receives the first command signal, the first input end of the first NOR gate is connected to the output end of the first inverter, the second input end of the first NOR gate receives the second command signal, and the output end of the first NOR gate outputs the first narrowing command signal.

4. The memory bank address decoder according to claim 3, characterized in that: The command address latch circuit includes a first gated inverter and a second gated inverter; wherein, the control end of the first gated inverter receives the first narrowed command signal, and the input end of the first gated inverter receives the first undecoded address signal; the control end of the second gated inverter receives the second command signal, and the input end of the second gated inverter receives the second undecoded address signal; the output end of the first gated inverter and the output end of the second gated inverter are connected to the input end of the second inverter, and the output end of the second inverter outputs the first operation address signal.

5. The memory address decoder according to claim 4, characterized in that: The command address latch circuit also includes a third inverter and a third gated inverter; wherein, the input end of the third inverter is connected to the output end of the second inverter, the output end of the third inverter is connected to the input end of the third gated inverter, the control end of the third gated inverter receives the first narrowing command signal and the second command signal, and the output end of the third gated inverter is connected to the input end of the third inverter.

6. The memory bank address decoder according to claim 2, wherein: The command address activation circuit is connected to the command address processing circuit and the address decoding circuit and receives the first narrowed command signal and the second operation address signal. The command address activation circuit is used to perform sampling processing and logical operation processing on the first narrowed command signal and the second command signal according to the second operation address signal to generate a storage body activation address signal.

7. The memory bank address decoder according to claim 6, wherein: The command address activation circuit includes a first trigger, a second trigger and a first latch, wherein: A data input terminal of the first trigger receives the first narrowing command signal, a clock input terminal of the first trigger receives the second operation address signal, and a data output terminal of the first trigger is connected to a first input terminal of the first latch; The data input terminal of the second flip-flop receives the second command signal, the clock input terminal of the second flip-flop receives the second operation address signal, and the data output terminal of the second flip-flop is connected to the second input terminal of the first latch; The output end of the first latch outputs the memory bank activation address signal.

8. The memory bank address decoder according to claim 7, wherein: The data output ends of the first trigger and the second trigger both include a data positive output end and a data negative output end, the data negative output end of the first trigger is connected to the first input end of the first latch; the data negative output end of the second trigger is connected to the second input end of the first latch; the first latch includes two NAND gates.

9. The memory bank address decoder according to claim 7, wherein: The data output ends of the first trigger and the second trigger both include a data positive output end and a data negative output end, and the data negative output end of the first trigger is connected to the first input end of the first latch; the data positive output end of the second trigger is connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives a full storage body control signal, and the output end of the second NOR gate is connected to the second input end of the first latch; the first latch includes two NAND gates.

10. A memory, characterized in that: The memory comprises a storage body address decoder as described in any one of claims 1 to 9 and a plurality of storage bodies, wherein the plurality of storage bodies are connected to the storage body address decoder, and the memory is used to activate corresponding storage bodies according to the storage body activation address signal.

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