Method for depositing stress dielectric layer in groove between grids and semiconductor device

Abstract

The invention discloses a method for depositing a stress dielectric layer in a groove between grids and a semiconductor device. The method comprises the following steps: providing a semiconductor structure at least provided with a first grid and a second grid; forming a first stress dielectric layer on the surface of the semiconductor structure; etching the first stress dielectric layer; forming a second stress dielectric layer on the surface of the semiconductor structure; the first stress dielectric layer is a pressure stress dielectric layer formed according to the following steps: first deposition treatment: depositing a first dielectric layer with a first deposition thickness on the surface of the semiconductor structure; performing first plasma processing on the whole film layer of the first dielectric layer, wherein the first deposition thickness does not exceed the processing depth of the first plasma processing; and performing first deposition processing and first plasma processing for multiple times based on the set first cycle number, and forming a pressure stress dielectric layer on the surface of the semiconductor structure. The appearance of the gate structure after the pseudo gate is removed can be improved, and then metal filling is improved.

Description

Technical Field

[0001] The present invention relates generally to the field of semiconductor manufacturing and more particularly to a method for depositing a stressed dielectric layer in a trench between gate electrodes and a semiconductor device. Background Art

[0002] In the semiconductor integrated circuit manufacturing process, structures with technology nodes of 28nm and sub-28nm usually use metal gates. The above metal gates are usually formed using a gate-last process. In the gate-last process, an amorphous silicon dummy gate (Dummy Poly Silicon) is required to define the formation area of ​​the gate structure using the amorphous silicon dummy gate, then form a sidewall, and then form an interlayer dielectric layer to fill the trenches between the amorphous silicon dummy gates. After that, the amorphous silicon dummy gates are removed and metal is filled in the area where the amorphous silicon dummy gates are removed to form a metal gate.

[0003] However, in the above methods, the interlayer dielectric layer is usually formed by HARP (High Aspect Ratio Process). However, the film deposited by HARP is relatively loose and easy to absorb water. As time goes by, the stress of the film will be significantly reduced, causing the structure after the pseudo gate is removed to be deformed by the stress of the interlayer dielectric deposited in the side trench, affecting the subsequent filling of the metal gate. In addition, the filling capacity of HARP is limited and cannot be applied to sub-28nm structures.

[0004] In view of this, there is an urgent need to provide a method for depositing a stressed dielectric layer in the trenches between gates to improve the morphology of the gate structure after the dummy gate is removed (before the metal gate is filled), thereby improving the metal filling to be suitable for structures with technology nodes of 28nm and sub-28nm. Summary of the invention

[0005] In order to at least solve one or more of the technical problems mentioned above, the present application proposes a method for depositing a stress dielectric layer in a trench between gates and a semiconductor device in multiple aspects.

[0006] In a first aspect, the present application provides a method for depositing a stress dielectric layer in a trench between gates, comprising: providing a semiconductor structure, the semiconductor structure having at least a first gate and a second gate, a trench between the first gate and the second gate; forming a first stress dielectric layer on the surface of the semiconductor structure to partially fill the trench; etching the first stress dielectric layer to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate; forming a second stress dielectric layer on the surface of the semiconductor structure to fill the trench; wherein the first stress dielectric layer is a compressive stress dielectric layer formed by the following steps: a first deposition process, based on a set first deposition thickness, depositing a first dielectric layer on the surface of the semiconductor structure by a HARP process; a first plasma treatment, based on a set first plasma treatment power and a first plasma treatment time, performing a first plasma treatment on the entire film layer of the first dielectric layer by a plasma containing an inert gas, wherein the first deposition thickness of the first dielectric layer does not exceed the treatment depth of the first plasma treatment at the first plasma treatment power and the first plasma treatment time; and performing the first deposition process and the first plasma treatment for multiple cycles based on a set first number of cycles to form a compressive stress dielectric layer on the surface of the semiconductor structure.

[0007] In some embodiments, the compressive stress of the compressive stress dielectric layer is -100 MPa to -50 MPa.

[0008] In some embodiments, the step of forming the first stress dielectric layer satisfies at least one of the following conditions: the first deposition thickness is 40Å~70Å; the first plasma treatment power is 400W~600W; the first plasma treatment time is 15s~20s; the inert gas is Ar or He; the first cycle number is 10 times~20 times; the chamber pressure of the first deposition treatment is 500 torr~600 torr; and the chamber pressure of the first plasma treatment is 20torr~50 torr.

[0009] In some embodiments, the second stress dielectric layer is a tensile stress dielectric layer formed by the following steps: a second deposition process, based on a set second deposition thickness, using a HARP process to deposit a second dielectric layer in a groove filled with the first stress dielectric layer; a second plasma treatment, based on a set second plasma treatment power and a second plasma treatment time, using a plasma containing an inert gas to perform a second plasma treatment on the film surface of the second dielectric layer, wherein the second deposition thickness of the second dielectric layer exceeds the treatment depth of the second plasma treatment at the second plasma treatment power and the second plasma treatment time; based on a set second number of cycles, performing the second deposition process and the second plasma treatment for multiple cycles until the groove is filled to form a tensile stress dielectric layer in the groove.

[0010] In some embodiments, the step of forming the second stress dielectric layer satisfies at least one of the following conditions: the second deposition thickness is 150Å~200Å; the second plasma treatment power is 200W~300W; the second plasma treatment time is 10s~15s; the inert gas is Ar or He; the second cycle number is 15 times~25 times; the chamber pressure of the second deposition treatment is 500 torr~600 torr; and the chamber pressure of the second plasma treatment is 20 torr~50 torr.

[0011] In some embodiments, etching the first stress dielectric layer to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate includes: determining an etching time based on a deposition thickness and an etching speed of the first stress dielectric layer; and etching the first stress dielectric layer based on the etching time to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate.

[0012] In some embodiments, after etching the first stress dielectric layer to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate, and before forming a second stress dielectric layer on the surface of the semiconductor structure to fill the trench, the method further includes: treating the etched semiconductor structure based on a plasma containing an inert gas.

[0013] In some embodiments, after forming the second stress dielectric layer, the method further includes: processing the second stress dielectric layer based on a planarization process until the dummy gate in the first gate and the dummy gate in the second gate are exposed; removing the dummy gate in the first gate and the dummy gate in the second gate, and filling the first gate after removing the dummy gate and the second gate after removing the dummy gate with metal, respectively.

[0014] In some embodiments, the height of the dummy gate before the planarization process is greater than the height of the dummy gate after the planarization process.

[0015] In some embodiments, a width of the gate structure at the second stress dielectric layer is greater than a width of the gate structure at the first stress dielectric layer.

[0016] In a second aspect, the present application provides a semiconductor device, wherein a stress dielectric layer in a trench between gates of the semiconductor device is prepared by the method described in the first aspect or any embodiment of the first aspect.

[0017] Compared with the prior art, the unexpected technical effect of the present application is that it can improve the gate structure after the dummy gate is removed (before metal filling), thereby improving the gate metal filling.

[0018] The embodiment of the present application introduces a plasma treatment process into HARP, and deposits a dielectric layer in the groove between the gates in a deposition-surface treatment cyclic deposition mode. During the deposition process, the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment can be set in each cycle to obtain a dielectric layer with different stress performances, so as to improve the gate structure after the pseudo gate is removed (before metal filling) through stress, thereby improving the gate metal filling, which can be applied to structures with technology nodes of 28nm and sub-28nm. In particular, when forming a compressive stress dielectric layer, by cyclic deposition-surface treatment in multiple times, the thickness of the film layer deposited each time does not exceed the treatment depth of the plasma treatment, and the entire film layer of the formed dielectric layer can be treated each time, rather than being limited to the surface of the dielectric layer. Therefore, this cyclic treatment mode can change the stress of the dielectric layer and obtain a compressive stress dielectric layer. In addition, since the dielectric layer after plasma surface treatment will reduce the occurrence of overhangs, this improves the filling ability of HARP, ensures that there are no holes in the grooves between the gates, ensures the stability of the product, and improves the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become easy to understand. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein: Figure 1 An exemplary flowchart of a method for depositing a stress dielectric layer in a trench between gates according to some embodiments of the present application is shown; Figure 2 An exemplary flowchart of a method for forming a stress dielectric layer by deposition-surface treatment according to some embodiments of the present application is shown; Figure 3 An exemplary schematic diagram of the present application for obtaining different stress performances through deposition-surface treatment is shown; Figure 4A A schematic cross-sectional structure diagram of forming a trench in a semiconductor structure according to some embodiments of the present application is shown; Figure 4B A schematic cross-sectional structure diagram of forming a first stress medium layer in some embodiments of the present application is shown; Figure 4C A schematic cross-sectional structure diagram of etching the first dielectric layer in some embodiments of the present application is shown; Figure 4D A schematic cross-sectional structure diagram of plasma treatment of a semiconductor structure after etching according to some embodiments of the present application is shown.

[0020] Figure 4E A schematic cross-sectional structure diagram of forming a second stress medium layer in some embodiments of the present application is shown; Figure 5A A schematic cross-sectional structure diagram of a semiconductor structure that has been planarized in some embodiments of the present application is shown; Figure 5B A schematic cross-sectional structure diagram of a semiconductor structure after the dummy gate is removed according to some embodiments of the present application is shown; Figure 5C A schematic cross-sectional structure diagram of a semiconductor structure after metal filling in some embodiments of the present application is shown; Figure 6 A schematic diagram showing the effect of plasma treatment power and cycle number on the stress performance of the dielectric layer.

[0021] Description of reference numerals: First substrate 111; oxide dielectric layer 112; tensile stress 140; compressive stress 150; A second substrate 410; a first gate 420; a second gate 430; a first dummy gate 440; a second dummy gate 450 ; a contact etch stop layer (CESL) 460 ; a first stress dielectric layer 470 ; and a second stress dielectric layer 480 . DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0023] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present application indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0024] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in this application specification and claims, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms. It should also be further understood that the term "and / or" used in this application specification and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0025] It should also be understood that, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "on," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. When an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0026] The specific implementation of the present application is described in detail below with reference to the accompanying drawings.

[0027] The embodiment of the present application provides a solution for depositing a stressed dielectric layer in the grooves between the gates, by introducing a plasma treatment process in HARP, and depositing the dielectric layer in the grooves between the gates in a deposition-surface treatment cyclic deposition mode. During the deposition process, the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment can be set in each cycle to obtain a dielectric layer with different stress performances, so that dielectric layers with different stress performances are deposited at different positions in the grooves between the gates, so as to improve the gate structure after the pseudo gate is removed (before metal filling) through stress, thereby improving the gate metal filling.

[0028] Figure 1 An exemplary flow chart of a method 100 for depositing a stressed dielectric layer in a trench between gates according to some embodiments of the present application is shown.

[0029] like Figure 1As shown, in step S110, a semiconductor structure is provided, and the semiconductor structure has at least a first gate 420 and a second gate 430, and a trench is provided between the first gate 420 and the second gate 430; then, in step S120, a first stress dielectric layer 470 is formed on the surface of the semiconductor structure to partially fill the trench. Then, in step S130, the first stress dielectric layer 470 is etched to remove the first stress dielectric layer 470 on the top of the first gate 420 and the first stress dielectric layer 470 on the top of the second gate 430. Then, in step S140, a second stress dielectric layer 480 is formed on the surface of the semiconductor structure to fill the trench. The first stress dielectric layer 470 and the second stress dielectric layer 480 can both be formed by deposition-surface treatment.

[0030] Figure 2 An exemplary flow chart of a method for forming a stress medium layer by deposition-surface treatment in some embodiments of the present application is shown. The method can be used to form the first stress medium layer 470 and the second stress medium layer 480 described above.

[0031] like Figure 2 As shown, in step S210, based on the set deposition thickness, a dielectric layer is deposited on the surface of the semiconductor structure using the HARP process; then, in step S220, based on the set plasma processing power and plasma processing time, the dielectric layer is treated with plasma containing an inert gas. Then, in step S230, based on the set number of cycles, the steps of depositing the dielectric layer and the plasma processing step are repeated multiple times to form a stress dielectric layer on the surface of the semiconductor structure; wherein the stress performance of the stress dielectric layer is controlled by adjusting the deposition thickness, plasma processing power, plasma processing time and number of cycles.

[0032] Figure 3 An exemplary schematic diagram of the present application for obtaining different stress performances through deposition-surface treatment is shown.

[0033] like Figure 3 As shown in S310, first, an oxide dielectric layer 112, such as silicon oxide SiO2, is deposited on a first substrate 111 (such as a silicon substrate) at a high temperature using a HARP process. Then, as shown in S320, a plasma containing an inert gas such as Ar is used to treat the oxide dielectric layer 112. As shown by the arrows, the above-mentioned deposition-plasma treatment process is repeated multiple times.

[0034] The HARP oxide deposition process itself is a purely thermal process. The HARP oxide surface itself contains a large number of groups: -CH3, -OH, etc., which makes the surface of the deposited dielectric layer relatively loose. When the thickness of the dielectric layer deposited in a single cycle is thicker, for example, exceeding the processing depth of the subsequent plasma treatment, the plasma treatment will only affect the surface structure of the film layer of the dielectric layer, and the bottom layer of the film layer is still relatively loose. In this way, when the device comes out of the high temperature environment, the HARP oxide will shrink more than the substrate, thereby showing tensile stress (as shown in 140 in the figure).

[0035] If the thickness of the dielectric layer deposited in a single cycle is very thin, for example, not exceeding the processing depth of the subsequent plasma treatment, then when the dielectric layer is subjected to high-power, long-term plasma treatment, the entire film layer of the dielectric layer can be treated, that is, the entire film layer becomes dense, not just limited to the surface of the film layer. By cyclically performing this thin film layer deposition, high-power, multi-frequency plasma treatment, the groups in the oxide dielectric layer 112 are taken away each time, so that the entire dielectric layer becomes denser after multiple cycles. In this way, when the device returns to room temperature from a high-temperature environment, the dielectric layer shrinks less than the substrate, that is, the thermal expansion coefficient is smaller, thereby exhibiting compressive stress (as shown in 150 in the figure).

[0036] Based on the above principles, in the embodiment of the present application, a plasma treatment process is introduced into HARP, and a dielectric layer is deposited on the surface of the semiconductor device in a cyclic deposition mode of deposition-surface treatment. During the deposition process, the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment can be adjusted in each cycle to obtain a dielectric layer with different stress performances, thereby improving the device performance. Furthermore, by performing deposition-surface treatment in multiple cycles, it is convenient to control the treatment depth layer by layer when forming a compressive stress dielectric layer, so that the entire formed dielectric layer can be treated, rather than being limited to the surface of the dielectric layer. Therefore, this cyclic treatment mode can effectively change the stress of the dielectric layer.

[0037] In addition, since the plasma treatment takes away the radicals in the oxide dielectric layer 112 , the dielectric layer becomes denser, which is helpful to reduce the holes in the dielectric layer.

[0038] Furthermore, as a thermal reaction process of conformal growth, the valence bond concentration on the substrate surface will affect its growth rate, and a low deposition rate can obtain better filling capacity. Therefore, in the next cycle of deposition, since the previous plasma treatment reduces the valence bonds on the surface of the oxide dielectric layer 112, the deposition rate of HARP can be reduced, thereby obtaining better filling performance.

[0039] It can be understood that since the plasma treatment process is performed from top to bottom, the treatment effect on the top of the semiconductor device surface is stronger, and the valence bonds on the top oxide surface are reduced more, while the treatment effect on the bottom of the semiconductor device surface is weaker, and the valence bonds on the bottom oxide surface are reduced less. Therefore, in the next cycle of deposition, the deposition rate of HARP oxide on the top of the semiconductor device surface is more affected, and the deposition rate on the bottom of the semiconductor device surface is less affected. The deposition rate of HARP oxide on the top of the semiconductor device surface is lower than that on the bottom of the semiconductor device surface, so the occurrence of hanging on the top of the semiconductor device surface can be reduced, which is also beneficial to reduce the holes in the deposited dielectric layer and improve the filling effect.

[0040] Furthermore, based on the above principle, it can be seen that the deposition of dielectric layers with different stresses and plasma surface treatment can be completed in the same machine. This is conducive to reducing material transfer and machine replacement time, thereby significantly improving production efficiency, and reducing equipment investment and space occupation, thereby reducing production costs. In addition, completing step S210, step S220, and step S230 in succession in the same machine can better control the production process and reduce errors.

[0041] based on Figure 1 The preparation process of the method for depositing a stress dielectric layer in the trench between the gates is as follows. Figure 4A-4E The schematic diagram of the semiconductor cross-sectional structure is shown, and an exemplary process flow of a method for depositing a stress dielectric layer in a trench between gates using some embodiments of the present application is described in detail.

[0042] Figure 4A A schematic cross-sectional structure diagram of forming a trench in a semiconductor structure according to an embodiment of the present application is shown.

[0043] like Figure 4A As shown, a semiconductor structure is provided. The semiconductor structure has at least a first gate 420 and a second gate 430 , and a trench is formed between the first gate 420 and the second gate 430 .

[0044] Specifically, in the embodiment of the present application, the semiconductor structure may include a second substrate 410 and a first gate 420 and a second gate 430 stacked on the second substrate 410. A first dummy gate 440 is disposed in the first gate 420, and a second dummy gate 450 is disposed in the second gate 430. In the embodiment of the present application, the first dummy gate 440 and the second dummy gate 450 are both amorphous silicon dummy gates, and here, the first dummy gate 440 and the second dummy gate 450 are used to determine the metal-filled area.

[0045] Specifically, the material of the second substrate 410 is a material containing Si element, and specifically can be at least one of the following materials: Si, SiGe, SiC, SiGeC or other compound semiconductors containing Si element. The second substrate 410 can be a semiconductor single-layer structure or a multi-layer structure composed of these materials. The second substrate 410 can also be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), etc.

[0046] In the embodiment of the present application, a trench is formed between the first gate 420 and the second gate 430, and the trench has an upward opening, a bottom surface, and side walls. The two side walls of the trench are respectively a side wall of the first gate 420 and a side wall of the second gate 430; the bottom surface of the trench is the surface of the second substrate 410 between the first gate 420 and the second gate 430.

[0047] In the embodiment of the present application, a contact hole etch stop layer (CESL) 460 is deposited on the surface of the second substrate 410 (including the bottom surface of the groove and the surface other than the bottom surface of the groove, the surface of the second substrate 410 occupied by the first gate 420 and the surface of the second substrate 410 occupied by the second gate 430), the surface of the first gate 420 and the surface of the second gate 430. In the embodiment of the present application, the contact hole etch stop layer (CESL) 460 can be a silicon nitrogen compound, for example, silicon nitride. Of course, the contact hole etch stop layer (CESL) 460 can also be other feasible materials, and the embodiment of the present application is not specifically limited to this.

[0048] It should be noted that the semiconductor structure also includes other structures not shown in the figure, such as an oxide layer, a nitride layer, etc., which are not related to the invention of the present application and will not be described in detail in the embodiments of the present application.

[0049] Figure 4B A schematic cross-sectional structure diagram of forming a first stress dielectric layer 470 according to an embodiment of the present application is shown.

[0050] like Figure 4B As shown, a first stress dielectric layer 470 is formed on the surface of the semiconductor structure to partially fill the trench. The first stress dielectric layer 470 is formed by the method of steps S210 to S230 described above. Specifically, first, based on the set deposition thickness, a dielectric layer is deposited on the surface of the semiconductor structure using the HARP process.

[0051] Specifically, the material used for the dielectric layer can be any suitable dielectric material known in the art, for example, it can be a combination of one or more of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), fluorosilicate glass, undoped silicate glass (USG) or tetraethyl orthosilicate, and the embodiments of the present application are not limited thereto.

[0052] Specifically, in the HARP process, chemical vapor deposition is performed through a thermal process, and the process temperature of the HARP process is generally 500° C. to 600° C.

[0053] In the HARP process, the control of deposition thickness can usually be achieved through the following factors. The HARP process uses a thermochemical reaction of ozone (O3) and tetraethoxysilane (TEOS) to form an oxide film. The thickness of the deposited film can be affected by precisely controlling the flow and ratio of these chemical raw materials. The temperature during the deposition process has a significant effect on the rate of the chemical reaction and the quality and purity of the film. Higher temperatures can increase the rate of the chemical reaction, thereby affecting the deposition rate and film thickness. The pressure during the deposition process also affects the growth of the film. Lower pressures generally result in slower deposition rates but can improve the vertical quality of the film. The reaction time during the deposition process is a direct way to control the thickness of the film. By controlling the reaction time, the thickness of the deposited film can be precisely controlled. Therefore, the desired deposition thickness can be obtained by adjusting one or more of the above process parameters of HARP. Next, the dielectric layer is treated with plasma containing an inert gas based on the set plasma treatment power and plasma treatment time.

[0054] In the embodiments of the present application, the above-mentioned inert gas uses Ar or He or other feasible gases, which is not specifically limited in the embodiments of the present application. The embodiments of the present application are only described with the inert gas being Ar or He.

[0055] Specifically, the dielectric layer is treated with a plasma containing Ar or He, which removes the -CH3, -H, -OH and other valence bonds on the surface of the dielectric layer. In the process of removing the valence bonds on the surface of the dielectric layer, the valence bonds on the surface of the dielectric layer are simply blown away by the plasma, and a physical reaction occurs. Compared to removing the valence bonds by chemical reactions, the embodiments of the present application do not affect other properties of the dielectric layer in the process of blowing away the valence bonds on the surface of the dielectric layer.

[0056] By adjusting the plasma processing power and plasma processing time, the processing depth of the dielectric layer can be controlled, and the amount of valence bonds on the surface of the dielectric layer can be removed, thereby adjusting the compactness of the dielectric layer and changing the thermal expansion coefficient of the dielectric layer to provide different stress performances.

[0057] Finally, based on the set number of cycles, the dielectric layer deposition step and the plasma treatment step are repeated multiple times to form a first stress dielectric layer 470 on the surface of the semiconductor structure to partially fill the trench.

[0058] Specifically, the stress performance of the first stress dielectric layer 470 can be determined by the number of cycles, the thickness of each deposited dielectric layer during the cycle, the plasma processing power during the cycle, and the plasma processing time. Specifically, the first stress dielectric layer 470 is a compressive stress dielectric layer.

[0059] Specifically, in the process of repeatedly cycling the above-mentioned steps of depositing the dielectric layer and the plasma treatment, the dielectric layer is deposited, the above-mentioned dielectric layer is treated with a plasma containing Ar or He, and then the dielectric layer is deposited again. Since the dielectric layer is treated with a plasma containing Ar or He, the valence bonds on the surface of the dielectric layer are taken away, so that the valence bonds on the surface of the dielectric layer located at the top of the semiconductor structure are reduced, thereby reducing the deposition rate when the dielectric layer is deposited on the top of the semiconductor structure again. Since the treatment effect is weaker at the bottom of the semiconductor structure, the deposition rate is less affected, so the occurrence of top hanging of the semiconductor structure can be reduced, and the premature sealing of the groove can be avoided, thereby reducing the holes formed in the process of depositing the dielectric layer using the HARP process.

[0060] The method for forming a compressive stress dielectric layer includes: a first deposition process, based on a set first deposition thickness, using a HARP process to deposit a first dielectric layer in a groove; a first plasma treatment, based on a set first plasma treatment power and a set first plasma treatment time, using a plasma containing an inert gas to perform a first plasma treatment on the entire film layer of the first dielectric layer, wherein the first deposition thickness of the first dielectric layer does not exceed the treatment depth of the first plasma treatment at the first plasma treatment power and the first plasma treatment time; and based on a set first number of cycles, performing the first deposition process and the first plasma treatment for multiple cycles to form a compressive stress dielectric layer in the groove.

[0061] Specifically, in the process of forming the first stress dielectric layer 470, a first dielectric layer having a first deposition thickness is deposited on the surface of the semiconductor device using the HARP process. Considering that the maximum processing depth of plasma processing under conditions of high power and long time is about 100Å, the above-mentioned first deposition thickness is set to not more than 100Å, preferably can be set to 40Å~70Å, illustratively can be 40Å, 50Å, 60Å, 70Å, etc., of course, it can also be other values ​​within the above range, which is not limited here. In some embodiments, during the first deposition process, the pressure of the chamber can be set at 500 torr~600torr.

[0062] Next, the dielectric layer is treated with a plasma containing an inert gas, wherein the inert gas is Ar or He, the first plasma treatment power is 400W~600W, exemplarily 400W, 450W, 500W, 550W, 600W, etc., and of course other values ​​within the above range are also possible, which are not limited here; the first plasma treatment time is 15s~20s, exemplarily 15s, 16s, 17s, 18s, 19s, 20s, etc., and of course other values ​​within the above range are also possible, which are not limited here; the chamber pressure of the first plasma treatment is 20 torr~50 torr, exemplarily 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 50 torr, etc., and of course other values ​​within the above range are also possible, which are not limited here. During the plasma treatment process, the smaller the chamber pressure, the more stable the plasma and the more uniform the treatment effect. However, when the first deposition process and the first plasma process are performed in the same chamber, since the two processes are performed cyclically, it is necessary to frequently switch back and forth between the pressures required for each process. This pressure switching may bring some negative effects. For example, the pressure switching may cause the deposits on the inner wall or components of the chamber to peel off, resulting in particle contamination; since the pressure switching is usually achieved by exhausting gas, when the switching is achieved by exhausting gas with a large flow rate in order to save time, the gas flow may blow the particles on the semiconductor device, causing contamination, etc. Therefore, in some embodiments of the present application, the chamber pressure of the plasma treatment can be increased to minimize the pressure difference between the deposition process and the plasma treatment process, thereby reducing the adverse effects of the pressure switching.

[0063] Then, the first deposition process and the first plasma process are cycled for 10 to 20 times, illustratively, 10, 11, 12, 14, 15, 16, 18, 20, etc., which are not limited here. A compressive stress dielectric layer with a compressive stress of -100 MPa to -50 MPa is formed in the aforementioned groove. It can be understood that the number of cycles may depend on the depth required to be filled in the groove and the thickness of the dielectric layer obtained after a single cycle of treatment.

[0064] In the embodiment of forming the first stress dielectric layer 470, the dielectric layer is treated with a high power plasma containing Ar or He for a long time, and then the steps of depositing the dielectric layer and plasma treatment are repeated for multiple times, so that the obtained stress dielectric layer shrinks less than the semiconductor structure containing Si element, thereby obtaining a compressive stress dielectric layer. Moreover, by treating the dielectric layer with plasma, the holes formed in the process of depositing the dielectric layer using the HARP process can be reduced, and a denser compressive stress dielectric layer can be obtained.

[0065] Figure 4CA schematic cross-sectional structure diagram of etching the first dielectric layer according to an embodiment of the present application is shown.

[0066] like Figure 4C As shown, after the first stress dielectric layer 470 is deposited on the surface of the semiconductor structure, the first stress dielectric layer 470 is etched to remove the first stress dielectric layer 470 on the top of the first gate 420 and the first stress dielectric layer 470 on the top of the second gate 430, so as to facilitate the subsequent deposition of the second stress dielectric layer 480 on the top of the first gate 420 and the top of the second gate 430, so as to achieve the effect of depositing dielectric layers with different stresses at different positions in the groove of the gate structure.

[0067] In the embodiment of the present application, the etching time is determined based on the deposition thickness and etching speed of the first stress dielectric layer 470; the first stress dielectric layer 470 is etched based on the determined etching time to remove the first stress dielectric layer 470 on the top of the first gate 420 and the first stress dielectric layer 470 on the top of the second gate 430. In the embodiment of the present application, the first stress dielectric layer 470 is etched by a high bias etching method.

[0068] In the embodiment of the present application, since the dielectric layer is deposited from top to bottom, the thickness of the first stress dielectric layer 470 deposited at various positions on the surface of the semiconductor structure is different. When determining the etching time based on the deposition thickness and etching speed of the first stress dielectric layer, the etching time can be determined based on the average value of the thickness of the first stress dielectric layer 470 deposited at various positions on the surface of the semiconductor structure and the etching speed, or it can be determined based on the thickness and etching speed deposited on the surfaces of the first gate and the second gate. The embodiment of the present application does not specifically limit this.

[0069] In the actual etching process, the determined etching time may be appropriately increased or decreased based on the actual etching situation to ensure better removal of the first stress dielectric layer 470 on the top of the first gate 420 and the first stress dielectric layer 470 on the top of the second gate 430 .

[0070] After the first stress dielectric layer 470 is etched, some residues of the first stress dielectric layer 470 may remain on the top of the first gate 420 and the top of the second gate 430. Therefore, for better subsequent metal filling, after etching the surface of the semiconductor structure and before depositing the second stress dielectric layer, the surface of the etched semiconductor structure may be subjected to a plasma treatment. Specifically, the etched semiconductor structure may be treated with a plasma containing an inert gas.

[0071] Figure 4D A schematic cross-sectional structure diagram of plasma treatment of an etched semiconductor structure according to an embodiment of the present application is shown.

[0072] like Figure 4D As shown, in order to improve the subsequent metal filling effect, the semiconductor structure after etching is subjected to another plasma treatment. Specifically, the inert gas used in the plasma treatment is Ar or He; the plasma treatment power can be the same as the plasma treatment power set when the first stress dielectric layer 470 is formed, or it can be different; the plasma treatment time can also be the same as the plasma treatment time set when the first stress dielectric layer 470 is formed, or it can be different; the embodiment of the present application does not specifically limit the above-mentioned plasma treatment power and plasma treatment time, which can be determined according to the actual situation of the process treatment.

[0073] Figure 4E A schematic cross-sectional structure diagram of forming the second stress medium layer 480 according to an embodiment of the present application is shown.

[0074] like Figure 4E As shown, a second stress dielectric layer 480 is formed on the surface of the semiconductor structure to fill the groove. The second stress dielectric layer 480 is also formed by the method of steps S210 to S230. Specifically, first, based on the set deposition thickness, a dielectric layer is deposited on the surface of the semiconductor structure using the HARP process. Secondly, based on the set plasma treatment power and plasma treatment time, the aforementioned dielectric layer is treated with a plasma containing an inert gas. Finally, based on the set number of cycles, the steps of depositing the dielectric layer and the plasma treatment step are repeated multiple times to form a second stress dielectric layer 480 on the surface of the semiconductor structure to completely fill the aforementioned groove.

[0075] Specifically, the stress performance of the second stress dielectric layer 480 can be determined by the number of cycles, the thickness of each deposited dielectric layer during the cycle, the plasma processing power during the cycle, and the plasma processing time. Specifically, the second stress dielectric layer 480 is a tensile stress dielectric layer.

[0076] The method for forming a tensile stress dielectric layer includes: a second deposition process, based on a set second deposition thickness, using a HARP process to deposit a second dielectric layer in a groove filled with a first stress dielectric layer; a second plasma treatment, based on a set second plasma treatment power and a second plasma treatment time, using a plasma containing an inert gas to perform a second plasma treatment on a film surface of the second dielectric layer, wherein a second deposition thickness of the second dielectric layer exceeds a treatment depth of the second plasma treatment at the second plasma treatment power and the second plasma treatment time; and based on a set second number of cycles, performing the second deposition process and the second plasma treatment for multiple cycles until the groove is filled to form a tensile stress dielectric layer in the groove.

[0077] Specifically, in the process of forming the second stress dielectric layer 480, a second dielectric layer with a second deposition thickness is deposited on the surface of the semiconductor device by using the HARP process. Considering that the maximum processing depth of plasma processing under conditions of high power and long time is about 100Å, the above-mentioned second deposition thickness is set to be more than 100Å, preferably can be set to 150Å~200Å, exemplarily can be 150Å, 160Å, 170Å, 180Å, 190Å, 200Å, etc., of course, it can also be other values ​​within the above range, which is not limited here. In some embodiments, during the second deposition process, the pressure of the chamber can be set at 500 torr~600 torr.

[0078] Next, the dielectric layer is treated with a plasma containing an inert gas, wherein the inert gas is Ar or He, the second plasma treatment power is 200W~300W, exemplarily 200W, 250W, 300W, etc., and of course other values ​​within the above range are also possible, which are not limited here; the second plasma treatment time is 10s~15s, exemplarily 10s, 11s, 12s, 13s, 14s, 15s, etc., and of course other values ​​within the above range are also possible, which are not limited here; the chamber pressure of the second plasma treatment is 20 torr~50 torr, exemplarily 20 torr, 25 torr, 30torr, 35 torr, 40 torr, 50 torr, etc., and of course other values ​​within the above range are also possible, which are not limited here. The reasons for setting the chamber pressure are the same as above and will not be repeated here.

[0079] Then, the second deposition process and the second plasma process are cycled for 15 to 25 times, illustratively, 15, 16, 17, 18, 19, 20, etc., which are not limited here. A tensile stress dielectric layer with a tensile stress of 100 MPa to 150 MPa is formed in the aforementioned groove. It can be understood that the number of cycles may depend on the depth to be filled in the groove and the thickness of the dielectric layer obtained after a single cycle of treatment.

[0080] Other implementations and technical effects may refer to the above description of the formation of the first stress medium layer 470 , which will not be described in detail here.

[0081] In the above-mentioned embodiment of forming the second stress dielectric layer 480, the thickness of the dielectric layer deposited in a single cycle is relatively thick, for example, exceeding the processing depth of the subsequent plasma treatment. When the dielectric layer is treated with a plasma containing Ar or He at a lower power, the treatment time is relatively short, so the plasma treatment will only affect the surface structure of the film layer of the dielectric layer, and the bottom layer of the film layer is still relatively loose. When the steps of depositing the dielectric layer and the steps of plasma treatment are performed through multiple cycles, a tensile stress dielectric layer can still be obtained. Moreover, by plasma treating the dielectric layer, the holes formed in the process of depositing the dielectric layer using the HARP process can be reduced, and a more dense tensile stress dielectric layer can be obtained.

[0082] As an optional implementation of the embodiment of the present application, the method of depositing a stress dielectric layer in the groove between the gates also includes: processing the second stress dielectric layer 480 based on a planarization process until the dummy gate in the first gate 420 and the dummy gate in the second gate 430 are exposed; removing the dummy gate in the first gate 420 and the dummy gate in the second gate 430, and filling the first gate 420 after the dummy gate is removed and the second gate 430 after the dummy gate is removed with metal.

[0083] Figure 5A A schematic cross-sectional structure diagram of a semiconductor structure that has undergone planarization according to an embodiment of the present application is shown.

[0084] like Figure 5A As shown, the second stress dielectric layer 480 is processed based on a planarization process until the dummy gate in the first gate 420 and the dummy gate in the second gate 430 are exposed. Specifically, a chemical mechanical polishing (CMP) process may be used during the planarization process.

[0085] Specifically, in order to ensure that the first dummy gate 440 in the first gate 420 and the second dummy gate 450 in the second gate 430 can be better taken out, the height of the dummy gate after the planarization process is less than the height of the dummy gate before the planarization process. As for the specific value of the height of the dummy gate after the planarization process being less than the height of the dummy gate before the planarization process, it can be set to any value, for example, 20Å, 30Å, etc., under the premise of ensuring the performance of the metal gate, and the embodiment of the present application is not specifically limited.

[0086] Figure 5B A schematic cross-sectional structure diagram of a semiconductor structure after the dummy gate is removed according to an embodiment of the present application is shown.

[0087] like Figure 5BAs shown, after the first dummy gate 440 in the first gate 420 and the second dummy gate 450 in the second gate 430 are removed, the width W2 inside the gate structure at the second stress dielectric layer 480 is greater than the width W1 inside the gate structure at the first stress dielectric layer 470, ensuring that the structure after the dummy gate is removed (before metal filling) is an inverted trapezoid, thereby allowing for better metal filling. Specifically, during actual deposition, the compressive stress exhibited by the deposited first stress dielectric layer is controlled to be smaller than the tensile stress exhibited by the second stress dielectric layer by controlling the number of cycles, the thickness of each deposited dielectric layer during the cycle, the plasma processing power during the cycle, and the plasma processing time, so as to ensure that after the dummy gate is removed, the width inside the gate structure at the second stress dielectric layer 480 is greater than the width inside the gate structure at the first stress dielectric layer 470.

[0088] Figure 5C A schematic cross-sectional structure diagram of a semiconductor structure after metal filling according to an embodiment of the present application is shown.

[0089] like Figure 5C As shown, in the embodiment of the present application, the filled metal may be: titanium nitride (TiN), tantalum nitride (TaN), tungsten (W) and cobalt (Co), etc. The embodiment of the present application does not specifically limit this and can be determined according to actual usage.

[0090] from Figure 5C It can be seen that there are no voids in the filled gate structure and the metal filling performance is good.

[0091] Figure 6 The figure shows the effect of plasma treatment power and cycle number on the stress performance of the dielectric layer. In this figure, the thickness of the final dielectric layer obtained in various cases is the same, for example, 1500 Å. Figure 6 As shown, the dielectric layer stress performance in four cases is shown, namely: At point A, the plasma treatment power is 150W, the cycle is 15 times, and the dielectric layer stress is 137MPa; At point B, the plasma treatment power is 200 W, the cycle is 15 times, and the dielectric layer stress is 110 MPa; At point C, the plasma treatment power is 300W, the cycle is 30 times, and the dielectric layer stress is -48MPa; At point D, the plasma treatment power is 500 W, the cycle is 30 times, and the dielectric layer stress is -90 MPa.

[0092] It can be seen that since the thickness of the final dielectric layer is the same, the fewer the number of cycles, the thicker the film layer deposited in a single cycle. When the plasma treatment power is low, only the surface of the film layer is treated, and the dielectric layer is relatively loose. Therefore, when it returns to room temperature from a high temperature environment, the dielectric layer will shrink more than the substrate, showing tensile stress. Conversely, when the thickness of the final dielectric layer is the same, the more the number of cycles, the thinner the film layer deposited in a single cycle. When the plasma treatment power increases, more groups in the dielectric layer will be taken away, and the entire film layer will be treated, making the dielectric layer denser and having a smaller thermal expansion coefficient. Therefore, when it returns to room temperature from a high temperature environment, the dielectric layer will shrink less than the silicon-containing substrate, showing compressive stress.

[0093] Therefore, the embodiment of the present application can deposit a dielectric layer in the groove between the gates in a deposition-surface treatment cyclic deposition mode by introducing a plasma treatment process in HARP. During the deposition process, the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment can be adjusted in each cycle to obtain a dielectric layer with different stress performances, thereby depositing dielectric layers with different stress performances at different positions in the groove between the gates, so as to improve the gate structure after the pseudo gate is removed (before metal filling) through stress, thereby improving the gate metal filling.

[0094] In summary, compared with the prior art, the unexpected technical effect of the present application is that it can improve the gate structure after the dummy gate is removed (before metal filling), thereby improving the gate metal filling.

[0095] The embodiment of the present application further provides a semiconductor device, in which a stress dielectric layer in a trench between gates of the semiconductor device is prepared by using the method 100 for depositing a stress dielectric layer in a trench between gates.

[0096] Although multiple embodiments of the present application have been shown and described herein, it is obvious to those skilled in the art that such embodiments are provided only by way of example. Those skilled in the art can think of many changes, modifications and alternatives without departing from the thought and spirit of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be adopted. The attached claims are intended to limit the scope of protection of the present application, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for depositing a stressed dielectric layer in a trench between gate electrodes, characterized in that: include: Providing a semiconductor structure, wherein the semiconductor structure has at least a first gate and a second gate, and a trench is provided between the first gate and the second gate; forming a first stress dielectric layer on the surface of the semiconductor structure to partially fill the trench; Etching the first stress dielectric layer to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate; forming a second stress dielectric layer on the surface of the semiconductor structure to fill the trench; Wherein, the first stress medium layer is a compressive stress medium layer formed by the following steps: A first deposition process, based on a set first deposition thickness, using a HARP process to deposit a first dielectric layer on the surface of the semiconductor structure; A first plasma treatment, based on a set first plasma treatment power and a set first plasma treatment time, using a plasma containing an inert gas to perform a first plasma treatment on the entire film layer of the first dielectric layer, wherein the first deposition thickness of the first dielectric layer does not exceed a treatment depth of the first plasma treatment at the first plasma treatment power and the first plasma treatment time; Based on the set first cycle number, the first deposition process and the first plasma process are performed multiple times in a cycle to form a compressive stress dielectric layer on the surface of the semiconductor structure.

2. The method according to claim 1, characterized in that The compressive stress of the compressive stress medium layer is -100MPa~-50MPa.

3. The method according to claim 2, characterized in that The step of forming the first stress dielectric layer satisfies at least one of the following conditions: The first deposition thickness is 40Å~70Å; The first plasma treatment power is 400W~600W; The first plasma treatment time is 15s to 20s; The inert gas is Ar or He; The number of cycles is 10 to 20 times; The chamber pressure of the first deposition process is 500 torr to 600 torr; and The chamber pressure of the first plasma treatment is 20 torr~50 torr.

4. The method according to claim 1, characterized in that: The second stress dielectric layer is a tensile stress dielectric layer formed by the following steps: a second deposition process, based on a set second deposition thickness, using a HARP process to deposit a second dielectric layer in the groove filled with the first stress dielectric layer; second plasma treatment, based on the set second plasma treatment power and second plasma treatment time, using plasma containing an inert gas to perform a second plasma treatment on the film surface of the second dielectric layer, wherein the second deposition thickness of the second dielectric layer exceeds the treatment depth of the second plasma treatment at the second plasma treatment power and the second plasma treatment time; Based on the set second cycle number, the second deposition process and the second plasma process are performed for multiple cycles until the trench is filled to form a tensile stress dielectric layer in the trench.

5. The method according to claim 4, characterized in that The step of forming the second stress dielectric layer satisfies at least one of the following conditions: The second deposition thickness is 150Å~200Å; The second plasma treatment power is 200W~300W; The second plasma treatment time is 10s to 15s; The inert gas is Ar or He; The number of cycles is 15 to 25 times; The chamber pressure of the second deposition process is 500 torr to 600 torr; and The chamber pressure of the second plasma treatment is 20 torr~50 torr.

6. The method according to claim 1, characterized in that The etching of the first stress dielectric layer to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate includes: determining an etching time based on a deposition thickness and an etching speed of the first stress dielectric layer; The first stress dielectric layer is etched based on the etching time to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate.

7. The method according to claim 1, characterized in that After etching the first stress dielectric layer to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate, and before forming a second stress dielectric layer on the surface of the semiconductor structure to fill the trench, the method further includes: The etched semiconductor structure is processed based on a plasma containing an inert gas.

8. The method according to claim 1, characterized in that After forming the second stress medium layer, the method further includes: Processing the second stress dielectric layer based on a planarization process until the dummy gate in the first gate and the dummy gate in the second gate are exposed; The dummy gate in the first gate and the dummy gate in the second gate are removed, and the first gate after the dummy gate is removed and the second gate after the dummy gate is removed are filled with metal respectively.

9. The method according to claim 8, characterized in that The height of the dummy gate before the planarization process is greater than the height of the dummy gate after the planarization process.

10. The method according to claim 8, characterized in that The width of the gate structure at the second stress dielectric layer is greater than the width of the gate structure at the first stress dielectric layer.

11. A semiconductor device, characterized in that: The stress dielectric layer in the trench between the gates of the semiconductor device is prepared by the method according to any one of claims 1 to 10.

Images