Method for Depositing Stress Medium Layer in Trench between Gates and Semiconductor Device

Abstract

The present application discloses a method for depositing a stress medium layer in a trench between gates and a semiconductor device. The method includes: providing a semiconductor structure having at least a first gate and a second gate; forming a first stress medium layer on the surface of the semiconductor structure; etching the first stress medium layer; forming a second stress medium layer on the surface of the semiconductor structure; the first stress medium layer is a compressive stress medium layer formed as follows: a first deposition process, depositing a first medium layer with a first deposition thickness on the surface of the semiconductor structure; performing a first plasma process on the entire film layer of the first medium layer, wherein the first deposition thickness does not exceed the processing depth of the first plasma process; based on the set first number of cycles, repeatedly performing the first deposition process and the first plasma process multiple times to form a compressive stress medium layer on the surface of the semiconductor structure. The present application can improve the morphology of the gate structure after dummy gate removal, and further improve metal filling.

Description

Technical Field

[0001] The present application generally relates to the field of semiconductor manufacturing. More specifically, the present application relates to a method for depositing a stress medium layer in a trench between gates and a semiconductor device. Background Art

[0002] In the semiconductor integrated circuit manufacturing process, metal gates are typically used for structures with a technology node of 28 nm and below 28 nm. The above metal gates are usually formed by a gate-last process. In the gate-last process, a non-silicon dummy poly gate is required. The formation region of the gate structure is defined by the non-silicon dummy poly gate. Then, sidewalls are formed, and an interlayer dielectric layer is formed to fill the trench between the non-silicon dummy poly gates. After that, the non-silicon dummy poly gate is removed, and metal filling is performed in the region where the non-silicon dummy poly gate is removed to form a metal gate.

[0003] However, in the above method, the interlayer dielectric layer is usually formed by HARP (High Aspect Ratio Process). However, the film deposited by HARP is relatively loose and easy to absorb water. Over time, the stress of the film will be significantly reduced, resulting in deformation of the structure after the removal of the dummy gate due to the stress of the interlayer dielectric deposited in the side trench, affecting the subsequent filling of the metal gate. Moreover, the filling ability of HARP is limited and cannot be applied to structures below 28 nm.

[0004] In view of this, there is an urgent need to provide a method for depositing a stress medium layer in a trench between gates to improve the topography of the gate structure after the removal of the dummy gate (before metal gate filling), thereby improving metal filling to be applicable to structures with a technology node of 28 nm and below 28 nm. Summary of the Invention

[0005] In order to solve at least one or more of the above-mentioned technical problems, the present application proposes a method for depositing a stress medium layer in a trench between gates and a semiconductor device in multiple aspects.

[0006] In a first aspect, the present application provides a method for depositing a stress medium layer in a trench between gates, including: providing a semiconductor structure having at least a first gate and a second gate on the semiconductor structure, and having a trench between the first gate and the second gate; forming a first stress medium layer on the surface of the semiconductor structure to partially fill the trench; etching the first stress medium layer to remove the first stress medium layer on top of the first gate and the first stress medium layer on top of the second gate; forming a second stress medium layer on the surface of the semiconductor structure to fill the trench; wherein, the first stress medium layer is a compressive stress medium layer formed by the following steps: a first deposition process, based on a set first deposition thickness, depositing a first medium layer on the surface of the semiconductor structure using the HARP process; a first plasma process, based on a set first plasma process power and a first plasma process time, using a plasma containing an inert gas to perform a first plasma process on the entire film layer of the first medium layer, wherein the first deposition thickness of the first medium layer does not exceed the processing depth of the first plasma process at the first plasma process power and the first plasma process time; based on a set first number of cycles, repeatedly performing the first deposition process and the first plasma process multiple times to form a compressive stress medium layer on the surface of the semiconductor structure.

[0007] In some embodiments, the compressive stress of the compressive stress medium layer is -100 MPa to -50 MPa.

[0008] In some embodiments, the step of forming the first stress medium layer satisfies at least one of the following conditions: the first deposition thickness is 40 Å to 70 Å; the first plasma process power is 400 W to 600 W; the first plasma process time is 15 s to 20 s; the inert gas is Ar or He; the first number of cycles is 10 to 20 times; the chamber pressure of the first deposition process is 500 torr to 600 torr; and the chamber pressure of the first plasma process is 20 torr to 50 torr.

[0009] In some embodiments, the second stress medium layer is a tensile stress medium layer formed by the following steps: a second deposition process, based on a set second deposition thickness, depositing a second medium layer in the trench filled with the first stress medium layer using the HARP process; a second plasma process, based on a set second plasma process power and second plasma process time, performing a second plasma process on the film surface of the second medium layer using a plasma containing an inert gas, wherein the second deposition thickness of the second medium layer exceeds the processing depth of the second plasma process at the second plasma process power and second plasma process time; based on a set second number of cycles, repeatedly performing the second deposition process and the second plasma process until the trench is filled to form a tensile stress medium layer in the trench.

[0010] In some embodiments, the steps of forming the second stress medium layer satisfy at least one of the following conditions: the second deposition thickness is 150 Å to 200 Å; the second plasma process power is 200 W to 300 W; the second plasma process time is 10 s to 15 s; the inert gas is Ar or He; the second number of cycles is 15 to 25; the chamber pressure of the second deposition process is 500 torr to 600 torr; and the chamber pressure of the second plasma process is 20 torr to 50 torr.

[0011] In some embodiments, the etching of the first stress medium layer to remove the first stress medium layer on top of the first gate and the first stress medium layer on top of the second gate includes: determining an etching time based on the deposition thickness and etching rate of the first stress medium layer; etching the first stress medium layer based on the etching time to remove the first stress medium layer on top of the first gate and the first stress medium layer on top of the second gate.

[0012] In some embodiments, after the etching of the first stress medium layer to remove the first stress medium layer on top of the first gate and the first stress medium layer on top of the second gate, and before forming a second stress medium layer on the surface of the semiconductor structure to fill the trench, the method further includes: performing a plasma process on the etched semiconductor structure using a plasma containing an inert gas.

[0013] In some embodiments, after forming the second stress medium layer, the method further includes: processing the second stress medium layer based on a planarization process until the dummy gates in the first gate and the dummy gates in the second gate are exposed; removing the dummy gates in the first gate and the dummy gates in the second gate, and filling the first gate and the second gate after removing the dummy gates with metal respectively.

[0014] In some embodiments, the height of the dummy gate before planarization is greater than the height of the dummy gate after planarization.

[0015] In some embodiments, the width inside the gate structure at the second stress medium layer is greater than the width inside the gate structure at the first stress medium layer.

[0016] In a second aspect, the present application provides a semiconductor device, and the stress medium layer in the trench between the gates of the semiconductor device is prepared by the method described in the first aspect or any embodiment of the first aspect.

[0017] Compared with the prior art, the unexpected technical effect of the present application is that it can improve the gate structure after the removal of the dummy gate (before metal filling), thereby improving the gate metal filling.

[0018] In the embodiments of the present application, a plasma treatment process is introduced in HARP, and a dielectric layer is deposited in the trench between the gates in a deposition-surface treatment cycle deposition mode. During the deposition process, different stress performance dielectric layers can be obtained by setting the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment in each cycle process. Through the stress effect, the gate structure after the removal of the dummy gate (before metal filling) can be improved, thereby improving the gate metal filling, and it can be applied to structures with a technology node of 28 nm and sub-28 nm. In particular, when forming a compressive stress dielectric layer, by depositing-surface treating in multiple cycles, and the thickness of each deposited film layer does not exceed the treatment depth of the plasma treatment, the entire film layer of the formed dielectric layer can be treated each time, rather than being limited to the surface of the dielectric layer. Therefore, this cycle treatment mode can change the stress of the dielectric layer to obtain a compressive stress dielectric layer. In addition, since the dielectric layer after plasma surface treatment will reduce the occurrence of overhangs, this improves the filling ability of HARP, ensures that there are no holes in the trench between the gates, guarantees the stability of the product, and improves the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present application will become readily understood. In the drawings, several embodiments of the present application are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0020] Figure 1 An exemplary flowchart of a method for depositing a stress dielectric layer in a trench between gates in some embodiments of the present application is shown;

[0021] Figure 2An exemplary flowchart of a method for forming a stress medium layer by deposition - surface treatment according to some embodiments of the present application is shown;

[0022] Figure 3 An exemplary schematic diagram of the present application for obtaining different stress performances through deposition - surface treatment is shown;

[0023] Figure 4A A schematic cross - sectional structure diagram of forming a trench in a semiconductor structure according to some embodiments of the present application is shown;

[0024] Figure 4B A schematic cross - sectional structure diagram of forming a first stress medium layer according to some embodiments of the present application is shown;

[0025] Figure 4C A schematic cross - sectional structure diagram of etching a first dielectric layer according to some embodiments of the present application is shown;

[0026] Figure 4D A schematic cross - sectional structure diagram of plasma - treating a semiconductor structure after etching according to some embodiments of the present application is shown.

[0027] Figure 4E A schematic cross - sectional structure diagram of forming a second stress medium layer according to some embodiments of the present application is shown;

[0028] Figure 5A A schematic cross - sectional structure diagram of a semiconductor structure after planarization treatment according to some embodiments of the present application is shown;

[0029] Figure 5B A schematic cross - sectional structure diagram of a semiconductor structure after removing a dummy gate according to some embodiments of the present application is shown;

[0030] Figure 5C A schematic cross - sectional structure diagram of a semiconductor structure after metal filling according to some embodiments of the present application is shown;

[0031] Figure 6 A schematic diagram showing the influence of plasma treatment power and cycle number on the stress performance of the dielectric layer is shown.

[0032] Description of reference numerals:

[0033] First substrate 111; Oxide dielectric layer 112; Tensile stress 140; Compressive stress 150;

[0034] Second substrate 410; First gate 420; Second gate 430; First dummy gate 440;

[0035] Second dummy gate 450; Contact hole etch stop layer (CESL) 460; First stress medium layer 470; Second stress medium layer 480. Detailed implementation manners

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0037] It should be understood that the terms "including" and "comprising" used in the specification and claims of the present application indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0038] It should also be understood that the terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and claims of the present application, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should be further understood that the term "and / or" used in the specification and claims of the present application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0039] It should also be understood that, for the sake of convenience of description, spatial relative terms such as "below", "beneath", "under", "above", "on", etc. may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figures. When an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0040] The specific implementation manners of the present application will be described in detail below with reference to the accompanying drawings.

[0041] The embodiments of the present application provide a solution for depositing a stress medium layer in the trench between the gates. By introducing a plasma treatment process in HARP, a deposition-surface treatment cycle deposition mode is used to deposit a medium layer in the trench between the gates. During the deposition process, different stress performance medium layers can be obtained by setting the thickness of the deposited medium layer, the power of the plasma treatment, and the time of the plasma treatment in each cycle, so as to deposit medium layers with different stress performances at different positions in the trench between the gates, and improve the gate structure after the pseudo-gate is removed (before metal filling) through the stress effect, thereby improving the gate metal filling.

[0042] Figure 1 FIG. 4 shows an exemplary flowchart of a method 100 for depositing a stress medium layer in the trench between the gates according to some embodiments of the present application.

[0043] As Figure 1 shown, in step S110, a semiconductor structure is provided, and at least a first gate 420 and a second gate 430 are provided on the semiconductor structure, and there is a trench between the first gate 420 and the second gate 430; then, in step S120, a first stress medium layer 470 is formed on the surface of the semiconductor structure to partially fill the trench. Then, in step S130, the first stress medium layer 470 is etched to remove the first stress medium layer 470 on top of the first gate 420 and the first stress medium layer 470 on top of the second gate 430. Then, in step S140, a second stress medium layer 480 is formed on the surface of the semiconductor structure to fill the trench. Among them, both the first stress medium layer 470 and the second stress medium layer 480 can be formed by deposition-surface treatment.

[0044] Figure 2 FIG. 5 shows an exemplary flowchart of a method for forming a stress medium layer by deposition-surface treatment according to some embodiments of the present application. This method can be used to form the above-mentioned first stress medium layer 470 and second stress medium layer 480.

[0045] As Figure 2 shown, in step S210, based on the set deposition thickness, a medium layer is deposited on the surface of the semiconductor structure by using the HARP process; then, in step S220, the medium layer is treated with a plasma containing an inert gas based on the set plasma treatment power and plasma treatment time. Then, in step S230, based on the set number of cycles, the steps of depositing the medium layer and the plasma treatment step are cycled multiple times to form a stress medium layer on the surface of the semiconductor structure; the stress performance of the stress medium layer is controlled by adjusting the deposition thickness, the plasma treatment power, the plasma treatment time, and the number of cycles.

[0046] Figure 3An exemplary schematic diagram of the present application for obtaining different stress performances through deposition-surface treatment is shown.

[0047] like Figure 3 As shown in S310, first, a HARP process is used to deposit an oxide dielectric layer 112, such as silicon oxide SiO, on a first substrate 111 (such as a silicon substrate) at a high temperature. 2 Then, as shown in S320, a plasma containing an inert gas such as Ar is used to treat the oxide dielectric layer 112. As shown by the arrows, the above deposition-plasma treatment process is repeated multiple times.

[0048] The HARP oxide deposition process itself is a purely thermal process. The HARP oxide surface itself contains a large number of groups: -CH3, -OH, etc., which makes the surface of the deposited dielectric layer relatively loose. When the thickness of the dielectric layer deposited in a single cycle is thicker, for example, exceeding the processing depth of the subsequent plasma treatment, the plasma treatment will only affect the surface structure of the film layer of the dielectric layer, and the bottom layer of the film layer is still relatively loose. In this way, when the device comes out of the high temperature environment, the HARP oxide will shrink more than the substrate, thereby showing tensile stress (as shown in 140 in the figure).

[0049] If the thickness of the dielectric layer deposited in a single cycle is very thin, for example, not exceeding the processing depth of the subsequent plasma treatment, then when the dielectric layer is subjected to high-power, long-term plasma treatment, the entire film layer of the dielectric layer can be treated, that is, the entire film layer becomes dense, not just limited to the surface of the film layer. By cyclically performing this thin film layer deposition, high-power, multi-frequency plasma treatment, the groups in the oxide dielectric layer 112 are taken away each time, so that the entire dielectric layer becomes denser after multiple cycles. In this way, when the device returns to room temperature from a high-temperature environment, the dielectric layer shrinks less than the substrate, that is, the thermal expansion coefficient is smaller, thereby exhibiting compressive stress (as shown in 150 in the figure).

[0050] Based on the above principles, in the embodiment of the present application, a plasma treatment process is introduced into HARP, and a dielectric layer is deposited on the surface of the semiconductor device in a cyclic deposition mode of deposition-surface treatment. During the deposition process, the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment can be adjusted in each cycle to obtain a dielectric layer with different stress performances, thereby improving the device performance. Furthermore, by performing deposition-surface treatment in multiple cycles, it is convenient to control the treatment depth layer by layer when forming a compressive stress dielectric layer, so that the entire formed dielectric layer can be treated, rather than being limited to the surface of the dielectric layer. Therefore, this cyclic treatment mode can effectively change the stress of the dielectric layer.

[0051] In addition, since the plasma treatment removes the groups in the oxide dielectric layer 112, making the dielectric layer denser, which is beneficial to reducing the holes in the dielectric layer.

[0052] Furthermore, as HARP is a thermal reaction process for conformal growth, the valence bond concentration on the substrate surface affects its growth rate, and a low deposition rate can achieve better filling ability. Therefore, in the deposition process of the next cycle, since the previous plasma treatment reduces the valence bonds on the surface of the oxide dielectric layer 112, this can reduce the deposition rate of HARP, thereby obtaining better filling performance.

[0053] It can be understood that since the plasma treatment is carried out by spraying from top to bottom during the plasma treatment process, the treatment effect on the top surface of the semiconductor device is stronger, and the valence bonds on the top oxide surface are reduced more, while the treatment effect on the bottom surface of the semiconductor device is weaker, and the valence bonds on the bottom oxide surface are reduced less. Thus, in the deposition process of the next cycle, the deposition rate of HARP oxide on the top surface of the semiconductor device is more affected, and the deposition rate on the bottom surface of the semiconductor device is less affected. The deposition rate of HARP oxide on the top surface of the semiconductor device is less than that on the bottom surface of the semiconductor device. Therefore, the occurrence of hanging on the top surface of the semiconductor device can be reduced, which is also beneficial to reducing the holes in the deposited dielectric layer and improving the filling effect.

[0054] Furthermore, based on the above principle, it can be seen that the deposition of dielectric layers with different stresses and the plasma surface treatment can both be completed in the same machine. This is beneficial to reducing material transfer and machine replacement time, thereby significantly improving production efficiency, and can reduce equipment investment and space occupation, thereby reducing production costs. In addition, continuously completing step S210, step S220, and step S230 in the same machine can better control the production process and reduce errors.

[0055] Based on Figure 1 the preparation process of the method for depositing a stress dielectric layer in the trench between the gates, the following combines Figures 4A - 4E the schematic cross-sectional structure diagram of the semiconductor shown to detail the exemplary process flow of the method for depositing a stress dielectric layer in the trench between the gates using some embodiments of the present application.

[0056] Figure 4A The schematic cross-sectional structure diagram showing the formation of a trench in the semiconductor structure according to an embodiment of the present application is shown.

[0057] As Figure 4A shown, a semiconductor structure is provided, which at least has a first gate 420 and a second gate 430, and there is a trench between the first gate 420 and the second gate 430.

[0058] Specifically, in the embodiments of the present application, the semiconductor structure may include a second substrate 410, and a first gate 420 and a second gate 430 stacked on the second substrate 410. Among them, a first dummy gate 440 is provided in the first gate 420, and a second dummy gate 450 is provided in the second gate 430. In the embodiments of the present application, both the first dummy gate 440 and the second dummy gate 450 are amorphous silicon dummy gates. Here, the first dummy gate 440 and the second dummy gate 450 are used to determine the metal filling area.

[0059] Specifically, the material of the second substrate 410 is a material containing Si element, and specifically may be at least one of the following materials: Si, SiGe, SiC, SiGeC or other compound semiconductors containing Si element. The second substrate 410 may be a semiconductor single-layer structure or a multi-layer structure composed of these materials. The second substrate 410 may also be silicon on insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon-germanium-on-insulator stacked silicon (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), etc.

[0060] In the embodiments of the present application, a trench is formed between the first gate 420 and the second gate 430. The trench has an upward opening, a bottom surface and side walls. Among them, the two side walls of the trench are respectively a side wall of the first gate 420 and a side wall of the second gate 430; the bottom surface of the trench is the surface of the second substrate 410 between the first gate 420 and the second gate 430.

[0061] In the embodiments of the present application, a contact hole etch stop layer (CESL) 460 is deposited on the surface of the second substrate 410 (including the bottom surface of the trench and the surface except the bottom surface of the trench, the surface of the second substrate 410 occupied by the first gate 420, and the surface of the second substrate 410 occupied by the second gate 430), the surface of the first gate 420, and the surface of the second gate 430. In the embodiments of the present application, the contact hole etch stop layer (CESL) 460 may be a silicon nitride compound, for example, silicon nitride. Of course, the contact hole etch stop layer (CESL) 460 may also be other feasible materials, and the embodiments of the present application do not specifically limit this.

[0062] It should be noted that the semiconductor structure also includes other structures not shown in the figure, such as an oxide layer, a nitride layer, etc., which are not related to the inventive point of the present application, and the embodiments of the present application will not elaborate on them for the time being.

[0063] Figure 4B The cross-sectional structure diagram of forming the first stress medium layer 470 in the embodiments of the present application is shown.

[0064] As Figure 4BAs shown, a first stress medium layer 470 is formed on the surface of the semiconductor structure to partially fill the trench. The first stress medium layer 470 is formed by the method of steps S210 to S230 above. Specifically, first, based on the set deposition thickness, a dielectric layer is deposited on the surface of the semiconductor structure by the HARP process.

[0065] Specifically, the material used for the dielectric layer can be any suitable dielectric material well known in the art. For example, it can be one or a combination of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), fluorosilicate glass, undoped silicate glass (USG), or tetraethyl orthosilicate, and the embodiments of the present application are not limited thereto.

[0066] Specifically, in the HARP process, chemical vapor deposition is carried out through a thermal process, and the process temperature of the HARP process is generally 500°C to 600°C.

[0067] In the HARP process, the control of the deposition thickness can usually be achieved through the following factors. The HARP process uses the thermal chemical reaction of ozone (O 3 ), and tetraethyl orthosilicate (TEOS) to form an oxide film. By precisely controlling the flow rate and ratio of these chemical raw materials, the thickness of the deposited film can be affected. The temperature during the deposition process has a significant impact on the reaction rate of the chemical reaction and the quality and purity of the thin film. A higher temperature can increase the reaction rate of the chemical reaction, thereby affecting the deposition rate and the thickness of the thin film. The pressure during the deposition process also affects the growth of the thin film. A lower pressure usually results in a slower deposition rate, but can improve the quality of the thin film in the vertical direction. The reaction time during the deposition process is a direct method for controlling the thickness of the thin film. By controlling the reaction time, the thickness of the deposited thin film can be precisely controlled. Therefore, the desired deposition thickness can be obtained by adjusting one or more of the above process parameters of the HARP.

[0068] Next, based on the set plasma treatment power and plasma treatment time, the aforementioned dielectric layer is treated with a plasma containing an inert gas.

[0069] In the embodiments of the present application, the aforementioned inert gas is Ar or He or other feasible gases, and the embodiments of the present application do not specifically limit it. The embodiments of the present application are only described with the inert gas being Ar or He.

[0070] Specifically, by treating the aforementioned dielectric layer with a plasma containing Ar or He, this will remove -CH on the surface of the dielectric layer 3, -H, -OH equivalent bonds. In the process of removing the valence bonds on the surface of the dielectric layer, only the valence bonds on the surface of the dielectric layer are blown away by the plasma, and a physical reaction occurs. Compared with removing the valence bonds by means of a chemical reaction, in the process of blowing away the valence bonds on the surface of the dielectric layer in the embodiments of the present application, other properties of the dielectric layer are not affected.

[0071] By adjusting the plasma treatment power and the plasma treatment time, the treatment depth of the dielectric layer can be controlled, and the amount of valence bonds removed from the surface of the dielectric layer can be adjusted, so as to adjust the compactness of the dielectric layer and change the thermal expansion coefficient of the dielectric layer, so as to provide different stress performances.

[0072] Finally, based on the set number of cycles, the steps of depositing the dielectric layer and the plasma treatment step are cycled multiple times to form a first stress dielectric layer 470 on the surface of the semiconductor structure to partially fill the above-mentioned trench.

[0073] Specifically, the stress performance of the first stress dielectric layer 470 can be determined by the number of cycles, the thickness of the dielectric layer deposited each time during the cycle process, the plasma treatment power and the plasma treatment time during the cycle process. Specifically, the first stress dielectric layer 470 is a compressive stress dielectric layer.

[0074] Specifically, during the process of cycling the above-mentioned steps of depositing the dielectric layer and the plasma treatment step multiple times, by depositing the dielectric layer, the dielectric layer is subjected to the first plasma treatment with a plasma containing Ar or He, and then the dielectric layer is deposited again. Since the dielectric layer is treated with a plasma containing Ar or He, this will remove the valence bonds on the surface of the dielectric layer, reducing the valence bonds on the surface of the dielectric layer at the top of the semiconductor structure, thereby weakening the deposition rate when depositing the dielectric layer on the top of the semiconductor structure again. And the bottom of the semiconductor structure is less affected by the treatment effect, and the deposition rate is less affected. Therefore, the occurrence of hanging at the top of the semiconductor structure can be reduced, the trench can be prevented from being sealed in advance, and thus the holes formed during the deposition of the dielectric layer by the HARP process can be reduced.

[0075] The method for forming a compressive stress dielectric layer includes: a first deposition treatment, depositing a first dielectric layer in the trench by using the HARP process based on the set first deposition thickness; a first plasma treatment, performing a first plasma treatment on the entire film layer of the first dielectric layer with a plasma containing an inert gas based on the set first plasma treatment power and the first plasma treatment time, wherein the first deposition thickness of the first dielectric layer does not exceed the treatment depth of the first plasma treatment at the first plasma treatment power and the first plasma treatment time; and based on the set first number of cycles, repeatedly performing the first deposition treatment and the first plasma treatment to form a compressive stress dielectric layer in the trench.

[0076] Specifically, in the process of forming the first stress medium layer 470, a first medium layer with a first deposition thickness is deposited on the surface of the semiconductor device by using the HARP process. Considering that the maximum processing depth of plasma processing under conditions such as high power and long time is about 100 Å, therefore, the above first deposition thickness is set to not exceed 100 Å, preferably it can be set to 40 Å - 70 Å, and exemplarily it can be 40 Å, 50 Å, 60 Å, 70 Å, etc. Of course, it can also be other values within the above range, which are not limited herein. In some embodiments, during the first deposition process, the pressure in the chamber can be set at 500 torr - 600 torr.

[0077] Then, the medium layer is processed by using a plasma containing an inert gas, wherein the inert gas is Ar or He, the first plasma processing power is 400 W - 600 W, and exemplarily it can be 400 W, 450 W, 500 W, 550 W, 600 W, etc. Of course, it can also be other values within the above range, which are not limited herein; the first plasma processing time is 15 s - 20 s, and exemplarily it can be 15 s, 16 s, 17 s, 18 s, 19 s, 20 s, etc. Of course, it can also be other values within the above range, which are not limited herein; the chamber pressure of the first plasma processing is 20 torr - 50 torr, and exemplarily it can be 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 50 torr, etc. Of course, it can also be other values within the above range, which are not limited herein. During the plasma processing, the smaller the chamber pressure, the more stable the plasma and the more uniform the processing effect. However, when the first deposition process and the first plasma processing are performed in the same chamber, since the two processes are executed cyclically, it is necessary to frequently switch back and forth between the pressures required for each process. This pressure switching will bring some negative impacts. For example, the pressure switching may cause the deposits on the inner wall or components of the chamber to peel off, resulting in particle contamination; since the pressure switching is usually achieved by pumping and venting gas, when the switching is achieved by large-flow pumping and venting gas to save time, the airflow may blow the particles on the semiconductor device, causing contamination, and so on. Therefore, in some embodiments of the present application, the chamber pressure of the plasma processing can be increased to minimize the pressure difference between the deposition process and the plasma processing process, and reduce the adverse effects brought by the pressure switching.

[0078] Then, the first deposition process and the first plasma process are cycled 10 to 20 times. Exemplarily, it can be 10 times, 11 times, 12 times, 14 times, 15 times, 16 times, 18 times, 20 times, etc., which is not limited herein. A compressive stress dielectric layer with a compressive stress of -100 MPa to -50 MPa is formed in the aforementioned trench. It can be understood that the number of the above cycles can depend on the depth to be filled in the trench and the thickness of the dielectric layer obtained after a single cycle process.

[0079] In the embodiment of forming the first stress dielectric layer 470, when the dielectric layer is processed by plasma with a higher power and containing Ar or He for a longer time, and then the steps of depositing the dielectric layer and the plasma process are cycled multiple times, the resulting stress dielectric layer shrinks less compared to the semiconductor structure containing Si element, so that a compressive stress dielectric layer can be obtained. Moreover, by processing the dielectric layer with plasma, the holes formed during the deposition of the dielectric layer by the HARP process can be reduced, and a relatively dense compressive stress dielectric layer can be obtained.

[0080] Figure 4C The cross-sectional structure schematic diagram of etching the first dielectric layer according to the embodiment of the present application is shown.

[0081] As Figure 4C shown, after the first stress dielectric layer 470 is deposited on the surface of the semiconductor structure, the first stress dielectric layer 470 is etched to remove the first stress dielectric layer 470 on top of the first gate 420 and the first stress dielectric layer 470 on top of the second gate 430, so as to facilitate the subsequent deposition of the second stress dielectric layer 480 on top of the first gate 420 and the second gate 430, so as to achieve the effect of depositing dielectric layers with different stresses at different positions in the trench of the gate structure.

[0082] In the embodiment of the present application, the etching time is determined based on the deposition thickness and etching rate of the first stress dielectric layer 470; the first stress dielectric layer 470 is etched based on the determined etching time to remove the first stress dielectric layer 470 on top of the first gate 420 and the first stress dielectric layer 470 on top of the second gate 430. In the embodiment of the present application, the first stress dielectric layer 470 is etched by the method of high bias etch.

[0083] In the embodiments of the present application, since the deposition of the dielectric layer is carried out from top to bottom, the thickness of the first stress dielectric layer 470 deposited at various positions on the surface of the semiconductor structure is different. When determining the etching time based on the deposition thickness and etching rate of the first stress dielectric layer, the etching time can be determined based on the average value of the thickness of the first stress dielectric layer 470 deposited at various positions on the surface of the semiconductor structure and the etching rate, or can be determined based on the thickness deposited on the surfaces of the first gate and the second gate and the etching rate. The embodiments of the present application do not specifically limit this.

[0084] In the actual etching process, the determined etching time can also be appropriately increased or decreased based on the actual etching situation to ensure better removal of the first stress dielectric layer 470 on the top of the first gate 420 and the first stress dielectric layer 470 on the top of the second gate 430.

[0085] After the etching of the first stress dielectric layer 470 is completed, there may still be some residues of the first stress dielectric layer 470 on the tops of the first gate 420 and the second gate 430. Therefore, in order to achieve better metal filling in the subsequent process, after etching the surface of the semiconductor structure and before depositing the second stress dielectric layer, the surface of the etched semiconductor structure can be subjected to a plasma treatment again. Specifically, the etched semiconductor structure is treated with a plasma containing an inert gas.

[0086] Figure 4D The cross-sectional structure diagram of the plasma treatment of the etched semiconductor structure according to the embodiments of the present application is shown.

[0087] As Figure 4D shown, in order to improve the subsequent metal filling effect, the etched semiconductor structure is subjected to a plasma treatment again. Specifically, the inert gas used in the plasma treatment is Ar or He; the plasma treatment power can be the same as or different from the plasma treatment power set when forming the first stress dielectric layer 470; the plasma treatment time can also be the same as or different from the plasma treatment time set when forming the first stress dielectric layer 470; the embodiments of the present application do not specifically limit the above plasma treatment power and plasma treatment time, and can be determined according to the actual situation of the process treatment.

[0088] Figure 4E The cross-sectional structure diagram of forming the second stress dielectric layer 480 according to the embodiments of the present application is shown.

[0089] As Figure 4EAs shown, a second stress medium layer 480 is formed on the surface of the semiconductor structure to fill the trench. The second stress medium layer 480 is also formed by the method of steps S210 to S230 above. Specifically, first, based on the set deposition thickness, a dielectric layer is deposited on the surface of the semiconductor structure using the HARP process. Secondly, based on the set plasma treatment power and plasma treatment time, the aforementioned dielectric layer is treated with a plasma containing an inert gas. Finally, based on the set number of cycles, the steps of depositing the dielectric layer and the plasma treatment step are cycled multiple times to form a second stress medium layer 480 on the surface of the semiconductor structure to completely fill the aforementioned trench.

[0090] Specifically, the stress performance of the second stress medium layer 480 can be determined by the number of cycles, the thickness of each dielectric layer deposited during the cycle, the plasma treatment power, and the plasma treatment time during the cycle. Specifically, the second stress medium layer 480 is a tensile stress medium layer.

[0091] The method for forming a tensile stress medium layer includes: a second deposition process, based on the set second deposition thickness, depositing a second dielectric layer in the trench filled with the first stress medium layer using the HARP process; a second plasma treatment, based on the set second plasma treatment power and second plasma treatment time, treating the film surface of the second dielectric layer with a plasma containing an inert gas, where the second deposition thickness of the second dielectric layer exceeds the treatment depth of the second plasma treatment at the second plasma treatment power and second plasma treatment time; and based on the set second number of cycles, repeatedly performing the second deposition process and the second plasma treatment until the trench is filled to form a tensile stress medium layer in the trench.

[0092] Specifically, during the formation of the second stress medium layer 480, a second dielectric layer with a second deposition thickness is deposited on the surface of the semiconductor device using the HARP process. Considering that the maximum treatment depth of plasma treatment under conditions such as high power and long time is about 100 Å, therefore, the above second deposition thickness is set to exceed 100 Å, preferably it can be set to 150 Å - 200 Å, and exemplarily it can be 150 Å, 160 Å, 170 Å, 180 Å, 190 Å, 200 Å, etc. Of course, it can also be other values within the above range, which are not limited here. In some embodiments, during the second deposition process, the pressure in the chamber can be set between 500 torr and 600 torr.

[0093] Next, the dielectric layer is processed with a plasma containing an inert gas, where the inert gas is Ar or He, the second plasma processing power is 200 W to 300 W, and exemplary values can be 200 W, 250 W, 300 W, etc. Of course, other values within the above range are also possible and are not limited herein; the second plasma processing time is 10 s to 15 s, and exemplary values can be 10 s, 11 s, 12 s, 13 s, 14 s, 15 s, etc. Of course, other values within the above range are also possible and are not limited herein; the chamber pressure of the second plasma processing is 20 torr to 50 torr, and exemplary values can be 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 50 torr, etc. Of course, other values within the above range are also possible and are not limited herein. The reason for setting the chamber pressure is the same as above and will not be repeated here.

[0094] Then, the second deposition process and the second plasma process are cycled 15 to 25 times, and exemplary values can be 15 times, 16 times, 17 times, 18 times, 19 times, 20 times, etc., which are not limited herein. A tensile stress dielectric layer with a tensile stress of 100 MPa to 150 MPa is formed in the foregoing trench. It can be understood that the above number of cycles can depend on the depth to be filled in the trench and the thickness of the dielectric layer obtained after a single cycle of processing.

[0095] For other embodiments and technical effects, reference can be made to the description of the formation of the first stress dielectric layer 470 above, which will not be elaborated here.

[0096] In the above embodiment of forming the second stress dielectric layer 480, the thickness of the dielectric layer deposited in a single cycle is relatively thick, for example, exceeding the processing depth of the subsequent plasma processing. When processing the dielectric layer with a plasma having a lower power and containing Ar or He, the processing time is short. Therefore, the plasma processing only affects the surface structure of the dielectric layer film, and the bottom layer of the film is still relatively loose. When the steps of depositing the dielectric layer and the plasma processing step are performed through multiple cycles, a tensile stress dielectric layer can still be obtained. Moreover, by processing the dielectric layer with plasma, the holes formed during the deposition of the dielectric layer by the HARP process can be reduced, and a relatively dense tensile stress dielectric layer can be obtained.

[0097] As an optional embodiment of the embodiment of the present application, the method of depositing a stress dielectric layer in the trench between the gates further includes: processing the second stress dielectric layer 480 based on a planarization process until the dummy gates in the first gate 420 and the dummy gates in the second gate 430 are exposed; removing the dummy gates in the first gate 420 and the dummy gates in the second gate 430, and filling the first gate 420 and the second gate 430 after removing the dummy gates with metal respectively.

[0098] Figure 5A The cross-sectional structure diagram of the semiconductor structure after planarization processing according to an embodiment of the present application is shown.

[0099] As Figure 5A shown, the second stress medium layer 480 is processed based on the planarization processing technology until the dummy gates in the first gate 420 and the dummy gates in the second gate 430 are exposed. Specifically, during the planarization processing, a chemical mechanical polishing (CMP) process can be adopted.

[0100] Specifically, in order to ensure that the first dummy gate 440 in the first gate 420 and the second dummy gate 450 in the second gate 430 can be better removed, the height of the dummy gate after planarization processing is less than the height of the dummy gate before planarization processing. As for the specific value of the height of the dummy gate after planarization processing being less than the height of the dummy gate before planarization processing, it can be set to any value on the premise of ensuring the performance of the metal gate, for example, 20 Å, 30 Å, etc. The embodiments of the present application do not make specific limitations.

[0101] Figure 5B The cross-sectional structure diagram of the semiconductor structure after removing the dummy gate according to an embodiment of the present application is shown.

[0102] As Figure 5B shown, after removing the first dummy gate 440 in the first gate 420 and the second dummy gate 450 in the second gate 430, the width W2 inside the gate structure at the second stress medium layer 480 is greater than the width W1 inside the gate structure at the first stress medium layer 470, ensuring that the structure after removing the dummy gate (before metal filling) is an inverted trapezoid, and thus metal filling can be better performed. Specifically, during actual deposition, by controlling the number of cycles, the thickness of each deposited dielectric layer during the cycle, the plasma processing power and the plasma processing time during the cycle, the magnitude of the compressive stress exhibited by the deposited first stress medium layer is controlled to be less than the magnitude of the tensile stress exhibited by the second stress medium layer, ensuring that after removing the dummy gate, the width inside the gate structure at the second stress medium layer 480 is greater than the width inside the gate structure at the first stress medium layer 470.

[0103] Figure 5C The cross-sectional structure diagram of the semiconductor structure after metal filling according to an embodiment of the present application is shown.

[0104] As Figure 5C shown, in the embodiments of the present application, the filled metal can be: titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), etc. The embodiments of the present application do not make specific limitations on this and can be determined according to actual usage.

[0105] From Figure 5C it can be seen that there are no voids in the filled gate structure and the metal filling performance is good.

[0106] Figure 6 The figure shows a schematic diagram of the influence of plasma treatment power and number of cycles on the stress performance of the dielectric layer. In this figure, the final thickness of the dielectric layer obtained in various cases is the same, for example, 1500 Å. As Figure 6 shown, the stress performance of the dielectric layer in four cases is shown, which are respectively:

[0107] At point A, the plasma treatment power is 150 W, the number of cycles is 15, and the stress of the dielectric layer is 137 MPa;

[0108] At point B, the plasma treatment power is 200 W, the number of cycles is 15, and the stress of the dielectric layer is 110 MPa;

[0109] At point C, the plasma treatment power is 300 W, the number of cycles is 30, and the stress of the dielectric layer is -48 MPa;

[0110] At point D, the plasma treatment power is 500 W, the number of cycles is 30, and the stress of the dielectric layer is -90 MPa.

[0111] It can be seen that since the final thickness of the dielectric layer is the same, the fewer the number of cycles, the greater the thickness of the film layer deposited in a single cycle. When the plasma treatment power is small, only the surface of the film layer is treated, and the dielectric layer is relatively loose. Therefore, when returning from a high-temperature environment to room temperature, the dielectric layer will shrink more compared to the substrate and exhibit tensile stress. On the contrary, when the final thickness of the dielectric layer is the same, the more the number of cycles, the smaller the thickness of the film layer deposited in a single cycle. When the plasma treatment power increases, more groups in the dielectric layer will be removed, and the entire film layer will be treated, making the dielectric layer denser and having a smaller coefficient of thermal expansion. Therefore, when returning from a high-temperature environment to room temperature, the dielectric layer will shrink less compared to the silicon-containing substrate and exhibit compressive stress.

[0112] Therefore, in the embodiments of the present application, a plasma treatment process can be introduced into HARP to deposit the dielectric layer in the trenches between the gates in a deposition-surface treatment cycle deposition mode. During the deposition process, different stress performance dielectric layers can be obtained by adjusting the thickness of the deposited dielectric layer, the power of the plasma treatment, and the time of the plasma treatment in each cycle, so as to deposit dielectric layers with different stress performance at different positions in the trenches between the gates, and improve the gate structure after the pseudo-gate is removed (before metal filling) through the stress effect, thereby improving the gate metal filling.

[0113] In summary, compared with the prior art, the unexpected technical effect of the present application is that it can improve the gate structure after the pseudo-gate is removed (before metal filling), thereby improving the gate metal filling.

[0114] An embodiment of the present application further provides a semiconductor device, and a stress medium layer in a trench between the gates of the semiconductor device is prepared by using the method 100 for depositing a stress medium layer in a trench between the gates as described above.

[0115] Although multiple embodiments of the present application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many changes, variations, and alternative ways may occur to those skilled in the art without departing from the spirit and scope of the present application. It should be understood that various alternatives to the embodiments of the present application described herein may be employed in practicing the present application. The appended claims are intended to define the scope of protection of the present application and thus cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for depositing a stressed dielectric layer in a trench between gate electrodes, characterized in that: include: Providing a semiconductor structure, wherein the semiconductor structure has at least a first gate and a second gate, and a trench is provided between the first gate and the second gate; forming a first stress dielectric layer on the surface of the semiconductor structure to partially fill the trench; Etching the first stress dielectric layer to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate; forming a second stress dielectric layer on the surface of the semiconductor structure to fill the trench; Wherein, the first stress medium layer is a compressive stress medium layer formed by the following steps: A first deposition process, based on a set first deposition thickness, using a HARP process to deposit a first dielectric layer on the surface of the semiconductor structure; A first plasma treatment, based on a set first plasma treatment power and a set first plasma treatment time, using a plasma containing an inert gas to perform a first plasma treatment on the entire film layer of the first dielectric layer, wherein the first deposition thickness of the first dielectric layer does not exceed a treatment depth of the first plasma treatment at the first plasma treatment power and the first plasma treatment time; Based on the set first cycle number, performing the first deposition process and the first plasma process for multiple cycles to form a compressive stress dielectric layer on the surface of the semiconductor structure; The step of forming the first stress dielectric layer satisfies the following conditions: The first deposition thickness is 40Å~70Å; The first plasma treatment power is 400W~600W; The first plasma treatment time is 15s to 20s; The inert gas is Ar or He; The number of cycles is 10 to 20 times; The chamber pressure of the first deposition process is 500 torr to 600 torr; and The chamber pressure of the first plasma treatment is 20 torr~50 torr.

2. The method according to claim 1, characterized in that The compressive stress of the compressive stress medium layer is -100MPa~-50MPa.

3. The method according to claim 1, characterized in that The second stress dielectric layer is a tensile stress dielectric layer formed by the following steps: a second deposition process, based on a set second deposition thickness, using a HARP process to deposit a second dielectric layer in the groove filled with the first stress dielectric layer; second plasma treatment, based on the set second plasma treatment power and second plasma treatment time, using plasma containing an inert gas to perform a second plasma treatment on the film surface of the second dielectric layer, wherein the second deposition thickness of the second dielectric layer exceeds the treatment depth of the second plasma treatment at the second plasma treatment power and the second plasma treatment time; Based on the set second cycle number, the second deposition process and the second plasma process are performed for multiple cycles until the trench is filled to form a tensile stress dielectric layer in the trench.

4. The method according to claim 3, characterized in that The step of forming the second stress dielectric layer satisfies at least one of the following conditions: The second deposition thickness is 150Å~200Å; The second plasma treatment power is 200W~300W; The second plasma treatment time is 10s to 15s; The inert gas is Ar or He; The number of cycles is 15 to 25 times; The chamber pressure of the second deposition process is 500 torr to 600 torr; and The chamber pressure of the second plasma treatment is 20 torr~50 torr.

5. The method according to claim 1, characterized in that The etching of the first stress dielectric layer to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate includes: determining an etching time based on a deposition thickness and an etching speed of the first stress dielectric layer; The first stress dielectric layer is etched based on the etching time to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate.

6. The method according to claim 1, characterized in that After etching the first stress dielectric layer to remove the first stress dielectric layer on the top of the first gate and the first stress dielectric layer on the top of the second gate, and before forming a second stress dielectric layer on the surface of the semiconductor structure to fill the trench, the method further includes: The etched semiconductor structure is processed based on a plasma containing an inert gas.

7. The method according to claim 1, characterized in that After forming the second stress dielectric layer, the method further includes: Processing the second stress dielectric layer based on a planarization process until the dummy gate in the first gate and the dummy gate in the second gate are exposed; The dummy gate in the first gate and the dummy gate in the second gate are removed, and the first gate after the dummy gate is removed and the second gate after the dummy gate is removed are filled with metal respectively.

8. The method according to claim 7, characterized in that The height of the dummy gate before the planarization process is greater than the height of the dummy gate after the planarization process.

9. The method according to claim 7, characterized in that: The width of the gate structure at the second stress dielectric layer is greater than the width of the gate structure at the first stress dielectric layer.

10. A semiconductor device, characterized in that: The stress dielectric layer in the trench between the gates of the semiconductor device is prepared by the method according to any one of claims 1 to 9.

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