A method for reducing SiC MOSFET gate oxide failure

Abstract

The present invention relates to the technical field of SiC MOSFET, and discloses a method for reducing gate oxide failure of SiC Mosfet, comprising the following steps: preparing a 4H-SiC or 6H-SiC single crystal substrate with a clean surface, and depositing a layer of high-k dielectric material with a thickness of 5nm to 20nm on the SiC substrate as a gate insulating layer by atomic layer deposition technology. The method for reducing gate oxide failure of SiC Mosfet can reduce gate leakage current while maintaining a high breakdown voltage by selecting high-k dielectric materials such as hafnium silicate or aluminum zinc oxide, thereby improving the performance and reliability of the device, depositing a silicon nitride buffer layer between the SiC substrate and the high-k dielectric material, thereby significantly reducing the interface state density, further improving the quality and stability of the gate insulating layer, and effectively optimizing the interface quality between the gate and the gate insulating layer by performing low-temperature annealing in an inert gas atmosphere, and integrating a temperature sensor in the SiC MOSFET.

Description

Technical Field

[0001] The invention relates to the technical field of SiC MOSFET, and in particular to a method for reducing SiC MOSFET gate oxide failure. Background Art

[0002] The gate oxide in SiC MOSFET (silicon carbide metal-oxide-semiconductor field-effect transistor) refers to the insulating layer between the gate and the SiC substrate, which is usually composed of silicon dioxide (SiO2) or other high-k dielectric materials. The gate oxide layer plays a vital role in SiC MOSFET. However, the silicon dioxide gate insulating layer commonly used in the prior art is prone to failure under high temperature and high electric field conditions, and some processes in the prior art use toxic or volatile precursors, which pollute the environment. At the same time, the existing SiC MOSFET lacks real-time monitoring and feedback mechanisms, and cannot promptly detect and prevent gate oxide failure caused by overheating, which not only shortens the life of the device, but also causes unpredictable failures of the device in actual applications, seriously affecting the stability and reliability of the system. Summary of the invention

[0003] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] A method for reducing SiC MOSFET gate oxide failure comprises the following steps:

[0006] S1. preparing a 4H-SiC or 6H-SiC single crystal substrate with a clean surface;

[0007] S2. Depositing a layer of high-k dielectric material with a thickness of 5 nm to 20 nm as a gate insulating layer on the SiC substrate by atomic layer deposition technology, wherein the high-k dielectric material is selected from one or more of hafnium-based oxides, aluminum-based oxides or zirconium-based oxides;

[0008] S3, depositing a layer of polysilicon gate on the high-k dielectric material by low-pressure chemical vapor deposition technology, with a thickness of 50nm to 200nm;

[0009] S4, placing the structure with the gate deposited thereon in an inert gas atmosphere for low-temperature annealing treatment, wherein the annealing temperature is 300° C. to 600° C. and the time is 10 minutes to 60 minutes, so as to optimize the interface quality between the gate and the gate insulating layer;

[0010] S5. Coat a layer of passivation material with a thickness of 100 nm to 500 nm on the top and sidewalls of the polysilicon gate, wherein the passivation material is selected from one or more of silicon dioxide, silicon nitride or polyimide to protect the gate and reduce the impact of the external environment.

[0011] As a further solution of the present invention: the specific composition of the high-k dielectric material in step S2 is hafnium silicate or aluminum zinc oxide, wherein the hafnium content of the hafnium silicate is 20% to 50%, and the aluminum content of the aluminum zinc oxide is 50% to 80%.

[0012] As a further solution of the present invention: before depositing the high-k dielectric material, the SiC substrate described in step S1 is first cleaned with a hydrofluoric acid solution to remove the natural oxide layer on the surface, and then rinsed with deionized water and dried.

[0013] As a further solution of the present invention: the method further comprises:

[0014] Before step S2, a silicon nitride buffer layer with a thickness of 2 nm to 10 nm is deposited between the SiC substrate and the high-k dielectric material to further reduce the interface state density. The silicon nitride buffer layer is deposited by plasma enhanced chemical vapor deposition technology.

[0015] As a further solution of the present invention: the deposition temperature of the silicon nitride buffer layer is 300° C. to 500° C., and the deposition rate is 1 nm / min to 3 nm / min.

[0016] As a further solution of the present invention: the doping type of the polysilicon gate described in step S3 is n-type or p-type, and the doping concentration is 1×10^19cm^-3 to 1×10^21cm^-3.

[0017] As a further solution of the present invention: the low-temperature annealing treatment in step S4 is performed in a nitrogen or argon atmosphere, and the annealing pressure is 1 atm to 10 atm.

[0018] As a further solution of the present invention: the passivation material described in step S5 is coated by spin coating or spray coating technology, and after coating, it is pre-cured at 100°C to 200°C for 5 minutes to 30 minutes, and then finally cured at 300°C to 400°C for 30 minutes to 2 hours.

[0019] As a further solution of the present invention: the method further comprises:

[0020] After step S5, a temperature sensor is integrated in the SiC MOSFET. The temperature sensor is integrated inside the SiC MOSFET through micro-electromechanical system technology, adjacent to the gate insulation layer but electrically isolated, and is used to monitor the operating temperature and adjust the operating state through a feedback mechanism to prevent gate oxide failure caused by overheating.

[0021] As a further solution of the present invention: the temperature sensor includes a temperature sensitive element based on resistance change, the material of the element is platinum or copper, and the linearity of the resistance change with temperature is better than 0.1%.

[0022] As a further solution of the present invention: the materials and processes used in the entire preparation process all meet environmental protection standards to ensure the sustainability of the production process, specifically including the use of non-toxic, low-volatile precursors and solvents, and the recovery and reuse of waste gas and waste liquid.

[0023] As a further solution of the present invention: after the preparation of the SiC MOSFET, its performance is verified by aging test and reliability test, and the test conditions include high temperature storage, temperature cycle, humidity bias and high voltage accelerated life test to ensure the stability and reliability of the device under extreme conditions.

[0024] As a further solution of the present invention: the method also includes, before step S2, performing surface modification treatment on the SiC substrate to improve the adhesion and interface quality of the high-k dielectric material, and the surface modification treatment includes one or more of ultraviolet light irradiation, ozone treatment or plasma treatment.

[0025] As a further solution of the present invention: the conditions of the surface modification treatment are: ultraviolet light irradiation time is 10 minutes to 60 minutes, ozone treatment concentration is 10ppm to 100ppm, plasma treatment power is 100W to 500W, and treatment time is 1 minute to 10 minutes.

[0026] As a further solution of the present invention: the method also includes, after step S3, performing ion implantation doping on the polysilicon gate to further optimize the conductive performance of the gate, the ion implantation dose is 1×10^14cm^-2 to 1×10^16cm^-2, and the energy is 10keV to 50keV.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] By selecting high-k dielectric materials such as hafnium silicate or aluminum zinc oxide, the gate leakage current can be reduced while maintaining a high breakdown voltage, thereby improving the performance and reliability of the device. A silicon nitride buffer layer is deposited between the SiC substrate and the high-k dielectric material, which can significantly reduce the interface state density and further improve the quality and stability of the gate insulating layer. By performing low-temperature annealing in an inert gas atmosphere, the interface quality between the gate and the gate insulating layer can be effectively optimized, interface defects can be reduced, and the long-term reliability of the device can be improved. The temperature sensor integrated in the SiC MOSFET can monitor the operating temperature and adjust the operating state through feedback, thereby preventing gate oxide failure caused by overheating and improving the stability and life of the device. By coating a layer of passivation material on the top and sidewalls of the polysilicon gate, the gate can be effectively protected, the impact of the external environment can be reduced, and the durability and reliability of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The present invention is a schematic flow chart of a method for reducing gate oxide failure of SiC Mosfet. DETAILED DESCRIPTION

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, the specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings.

[0031] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0032] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0033] Example 1

[0034] See also Figure 1 , which is the first embodiment of the present invention, and provides a method for reducing gate oxide failure of SiC Mosfet, in order to verify that by depositing high-k dielectric material, polysilicon gate, silicon nitride buffer layer and passivation material on SiC substrate and performing low temperature annealing treatment, the gate oxide reliability of SiC MOSFET can be significantly improved, comprising:

[0035] Experimental materials: 4H-SiC single crystal substrate (size: 10mm×10mm), hafnium silicate (HfSiOx), polysilicon, silicon nitride, silicon dioxide, argon, hydrofluoric acid solution (49% HF), spin coating equipment, low-temperature annealing furnace, plasma enhanced chemical vapor deposition (PECVD) equipment, atomic layer deposition (ALD) equipment, low-pressure chemical vapor deposition (LPCVD) equipment, and temperature sensor (based on platinum);

[0036] Experimental equipment: plasma enhanced chemical vapor deposition (PECVD) equipment, atomic layer deposition (ALD) equipment, low pressure chemical vapor deposition (LPCVD) equipment, low temperature annealing furnace, spin coating equipment, scanning electron microscope (SEM), four-probe tester, capacitance-voltage (CV) meter, leakage current tester, temperature cycle tester, humidity bias tester and high voltage accelerated life tester;

[0037] The specific steps are as follows:

[0038] Step 1: Prepare SiC substrate:

[0039] The 4H-SiC single crystal substrate was cleaned with a hydrofluoric acid solution (49% HF) to remove the natural oxide layer on the surface, and then rinsed with deionized water and dried;

[0040] Surface modification: The SiC substrate was plasma treated at 300 W for 5 minutes to improve the adhesion and interface quality of the high-k dielectric material.

[0041] Step 2: Deposit a silicon nitride buffer layer: Use plasma enhanced chemical vapor deposition (PECVD) technology to deposit a 5 nm thick silicon nitride buffer layer on the SiC substrate at a deposition temperature of 400°C and a deposition rate of 2 nm / min, using SiH4 and NH3 as precursors;

[0042] Step 3, depositing high-k dielectric material: using atomic layer deposition (ALD) technology to deposit a 10 nm thick layer of hafnium silicate (HfSiOx) on the silicon nitride buffer layer, the hafnium content is 30%, and the deposition conditions are: the precursor is hafnium tetrachloride (HfCl4) and water vapor, the deposition temperature is 300 ° C, the deposition rate is 0.1nm / cycle, and each cycle includes a HfCl4 pulse of 1s, a water vapor pulse of 1s, and a purge time of 10s each;

[0043] Step 4: Deposit polysilicon gate: Use low pressure chemical vapor deposition (LPCVD) technology to deposit a 100nm thick n-type polysilicon gate on the high-k dielectric material, with a doping concentration of 5×10^20cm^-3. The deposition conditions are: the precursor is silane (SiH4), the doping gas is phosphine (PH3), the deposition temperature is 600℃, the deposition pressure is 100mTorr, and the flow ratio is 1:100.

[0044] Step 5, low temperature annealing treatment: placing the structure with the gate deposited thereon in a low temperature annealing furnace under an argon atmosphere for low temperature annealing treatment, the annealing temperature is 450° C., the time is 30 minutes, and the annealing pressure is 5 atm;

[0045] Step 6: Apply passivation material: Spin coating technology is used to apply a layer of silicon dioxide passivation material with a thickness of 200 nm on the top and sidewalls of the polysilicon gate. After coating, pre-curing treatment is performed at 150°C for 15 minutes, and then final curing treatment is performed at 350°C for 1 hour. Tetraethyl orthosilicate (TEOS) is used as a precursor.

[0046] Step 7: Integrated temperature sensor: A platinum-based temperature sensor is integrated into the SiC MOSFET. It is integrated inside the SiC MOSFET through micro-electromechanical system (MEMS) technology, adjacent to the gate insulation layer but electrically isolated. The size of the temperature sensor is 1mm×1mm, and the linearity of resistance change with temperature is better than 0.1%.

[0047] The experimental data table is as follows:

[0048]

[0049]

[0050] In summary: By depositing a silicon nitride buffer layer, a hafnium silicate high-k dielectric material, and an n-type polysilicon gate on a 4H-SiC single crystal substrate, performing low-temperature annealing and coating a silicon dioxide passivation material, and finally integrating a platinum-based temperature sensor, the gate oxide reliability of SiC MOSFET can be significantly improved. Experimental results show that the treated SiC MOSFET has significant improvements in breakdown voltage, leakage current, threshold voltage, and flat band voltage, and exhibits excellent reliability in high-temperature storage, temperature cycling, humidity bias, and high-voltage accelerated life tests.

[0051] Example 2

[0052] See also Figure 1, which is the second embodiment of the present invention, verifies that by depositing a high-k dielectric material, a polysilicon gate, a silicon nitride buffer layer and a passivation material on a SiC substrate, and performing a low-temperature annealing treatment and ion implantation doping, the gate oxide reliability and conductive performance of a SiC MOSFET can be further improved, including:

[0053] Experimental materials: 6H-SiC single crystal substrate (size: 10mm×10mm), aluminum zinc oxide (AlZnOx), polycrystalline silicon, silicon nitride, silicon nitride, argon gas, hydrofluoric acid solution (49% HF), spin coating equipment, low-temperature annealing furnace, plasma enhanced chemical vapor deposition (PECVD) equipment, atomic layer deposition (ALD) equipment, low-pressure chemical vapor deposition (LPCVD) equipment, ion implantation equipment, temperature sensor (based on copper);

[0054] Experimental equipment: plasma enhanced chemical vapor deposition (PECVD) equipment, atomic layer deposition (ALD) equipment, low pressure chemical vapor deposition (LPCVD) equipment, low temperature annealing furnace, spin coating equipment, ion implantation equipment, scanning electron microscope (SEM), four-probe tester, capacitance-voltage (CV) meter, leakage current tester, temperature cycle tester, humidity bias tester and high voltage accelerated life tester;

[0055] The specific steps are as follows:

[0056] Step 1: Prepare the SiC substrate: Use a hydrofluoric acid solution (49% HF) to clean the 6H-SiC single crystal substrate to remove the natural oxide layer on the surface, then rinse with deionized water and dry;

[0057] Surface modification: The SiC substrate was irradiated with UV light for 30 minutes to improve the adhesion and interface quality of the high-k dielectric material.

[0058] Step 2: Deposit a silicon nitride buffer layer: Use plasma enhanced chemical vapor deposition (PECVD) technology to deposit a silicon nitride buffer layer with a thickness of 8 nm on the SiC substrate, the deposition temperature is 450°C, the deposition rate is 2.5 nm / min, and SiH4 and NH3 are used as precursors;

[0059] Step 3, depositing high-k dielectric material: using atomic layer deposition (ALD) technology to deposit a layer of aluminum zinc oxide (AlZnOx) with a thickness of 15 nm on the silicon nitride buffer layer, the aluminum content is 60%, and the deposition conditions are: the precursors are trimethylaluminum (TMA) and dimethylzinc (DMZ), the deposition temperature is 350 ° C, the deposition rate is 0.1nm / cycle, and each cycle includes a TMA pulse of 1s, a DMZ pulse of 1s, and a purge time of 10s each;

[0060] Step 4: Deposit polysilicon gate: Use low pressure chemical vapor deposition (LPCVD) technology to deposit a 150nm thick p-type polysilicon gate on the high-k dielectric material, with a doping concentration of 2×10^20cm^-3. The deposition conditions are: the precursor is silane (SiH4), the doping gas is borane (B2H6), the deposition temperature is 600℃, the deposition pressure is 100mTorr, and the flow ratio is 1:100.

[0061] Step 5, ion implantation doping: ion implantation doping is performed on the polysilicon gate, with a dose of 5×10^15cm^-2, an energy of 30keV, and boron ions (B+) are used as doping ions. After implantation, a rapid thermal annealing treatment is performed at 450°C for 10 minutes;

[0062] Step 6, low temperature annealing treatment: placing the structure with the gate deposited thereon in a low temperature annealing furnace under a nitrogen atmosphere for low temperature annealing treatment, the annealing temperature is 500° C., the time is 45 minutes, and the annealing pressure is 8 atm;

[0063] Step 7: Apply passivation material: Use spraying technology to apply a layer of silicon nitride passivation material with a thickness of 300nm on the top and sidewalls of the polysilicon gate. After coating, perform pre-curing treatment at 180°C for 20 minutes, and then perform final curing treatment at 380°C for 1.5 hours, using SiH4 and NH3 as precursors;

[0064] Step 8. Integrated temperature sensor: A copper-based temperature sensor is integrated into the SiC MOSFET. It is integrated inside the SiC MOSFET through micro-electromechanical system (MEMS) technology, adjacent to the gate insulation layer but electrically isolated. The size of the temperature sensor is 1mm×1mm, and the linearity of resistance change with temperature is better than 0.1%.

[0065] The experimental data table is as follows:

[0066]

[0067] In summary, through the detailed experimental data and results of the above two embodiments, it can be clearly seen that the method for reducing SiC MOSFET gate oxide failure provided by the present invention has significant effects in improving the breakdown voltage of the device, reducing leakage current, optimizing conductivity and improving reliability. The improvement not only improves the performance of SiC MOSFET, but also ensures the environmental protection and sustainability of the production process, and has high creativity and application value.

[0068] Importantly, it should be noted that the construction and arrangement of the present application shown in a plurality of different exemplary embodiments are only exemplary. Although only a few embodiments are described in detail in this disclosure, it should be readily understood by those who refer to this disclosure that many modifications are possible (e.g., the size, scale, structure, shape and proportion of various elements, and parameter values ​​(e.g., temperature, pressure, etc.), installation arrangement, use of materials, color, directional changes, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in the application. For example, the element shown as integrally formed can be composed of multiple parts or elements, the position of the element can be inverted or otherwise changed, and the nature or number or position of the discrete element can be changed or changed. Therefore, all such modifications are intended to be included in the scope of the present invention. The order or sequence of any process or method steps can be changed or reordered according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure of performing the function described herein, and is not only structurally equivalent but also equivalent structure. Without departing from the scope of the present invention, other replacements, modifications, changes and omissions can be made in the design, operating conditions and arrangement of the exemplary embodiments. Therefore, the invention is not limited to a specific embodiment, but extends to numerous modifications still falling within the scope of the appended claims.

[0069] Additionally, in order to provide a concise description of exemplary embodiments, all features of an actual embodiment (ie, those features that are not relevant to the best mode presently contemplated for carrying out the invention or those that are not relevant to implementing the invention) may not be described.

[0070] It will be appreciated that in the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort may be complex and time-consuming, but will be a routine task of design, fabrication, and production for those of ordinary skill having the benefit of this disclosure without undue experimentation.

[0071] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A method for reducing SiC Mosfet gate oxide failure, characterized in that: The steps include: S1. preparing a 4H-SiC or 6H-SiC single crystal substrate with a clean surface; S2. Depositing a layer of high-k dielectric material with a thickness of 5 nm to 20 nm as a gate insulating layer on the SiC substrate by atomic layer deposition technology, wherein the high-k dielectric material is selected from one or more of hafnium-based oxides, aluminum-based oxides or zirconium-based oxides; S3, depositing a layer of polysilicon gate on the high-k dielectric material by low-pressure chemical vapor deposition technology, with a thickness of 50nm to 200nm; S4, placing the structure with the gate deposited thereon in an inert gas atmosphere for low-temperature annealing treatment, wherein the annealing temperature is 300° C. to 600° C. and the time is 10 minutes to 60 minutes, so as to optimize the interface quality between the gate and the gate insulating layer; S5. Coat a layer of passivation material with a thickness of 100 nm to 500 nm on the top and sidewalls of the polysilicon gate, wherein the passivation material is selected from one or more of silicon dioxide, silicon nitride or polyimide to protect the gate and reduce the impact of the external environment.

2. A method for reducing SiC MOSFET gate oxide failure according to claim 1, characterized in that: The specific composition of the high-k dielectric material in step S2 is hafnium silicate or aluminum zinc oxide, wherein the hafnium content of the hafnium silicate is 20% to 50%, and the aluminum content of the aluminum zinc oxide is 50% to 80%.

3. The method for reducing SiC MOSFET gate oxide failure according to claim 1, characterized in that: Before depositing the high-k dielectric material, the SiC substrate in step S1 is first cleaned with a hydrofluoric acid solution to remove the natural oxide layer on the surface, and then rinsed with deionized water and dried.

4. A method for reducing SiC Mosfet gate oxide failure according to any one of claims 1 to 3, characterized in that: The method further comprises: Before step S2, a silicon nitride buffer layer with a thickness of 2 nm to 10 nm is deposited between the SiC substrate and the high-k dielectric material to further reduce the interface state density. The silicon nitride buffer layer is deposited by plasma enhanced chemical vapor deposition technology.

5. A method for reducing SiC MOSFET gate oxide failure according to claim 4, characterized in that: The deposition temperature of the silicon nitride buffer layer is 300° C. to 500° C., and the deposition rate is 1 nm / min to 3 nm / min.

6. The method for reducing SiC MOSFET gate oxide failure according to claim 1, characterized in that: The doping type of the polysilicon gate described in step S3 is n-type or p-type, and the doping concentration is 1×10^19cm^-3 to 1×10^21cm^-3.

7. The method for reducing SiC MOSFET gate oxide failure according to claim 1, characterized in that: The low temperature annealing treatment in step S4 is performed in a nitrogen or argon atmosphere, and the annealing pressure is 1 atm to 10 atm.

8. A method for reducing SiC MOSFET gate oxide failure according to any one of claims 1 to 7, characterized in that: The passivation material described in step S5 is coated by spin coating or spray coating technology, and after coating, it is pre-cured at 100°C to 200°C for 5 minutes to 30 minutes, and then finally cured at 300°C to 400°C for 30 minutes to 2 hours.

9. The method for reducing SiC MOSFET gate oxide failure according to claim 1, characterized in that: The method further comprises: After step S5, a temperature sensor is integrated in the SiC MOSFET. The temperature sensor is integrated inside the SiC MOSFET through micro-electromechanical system technology, adjacent to the gate insulation layer but electrically isolated, and is used to monitor the operating temperature and adjust the operating state through a feedback mechanism to prevent gate oxide failure caused by overheating.

10. The method for reducing SiC MOSFET gate oxide failure according to claim 1, characterized in that: The temperature sensor includes a temperature sensitive element based on resistance change. The material of the element is platinum or copper, and the linearity of the resistance change with temperature is better than 0.1%.

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