A method for preparing TSV silicon wafer
During the preparation process of TSV silicon wafers, the scallop pattern on the side walls of the through-silicon holes is etched in three stages, which solves the problem of side wall scallop pattern affecting performance in the prior art, and achieves more efficient through-silicon hole preparation and performance improvement.
Patent Information
- Application Number
- CN202411840592.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-01
AI Technical Summary
Bosch etching technology often forms scallop patterns on the side walls of through-silicon holes, resulting in unsmooth interfaces of subsequent fill materials, seriously affecting the performance of TSV and the reliability of the three-dimensional integrated system.
By providing a thinner first lithography layer and a larger second opening, the Bosch process etching is used to remove the side wall scallop patterns of the through-silicon holes in three stages, and the smoothing of the side wall is gradually achieved.
The scallop pattern on the side walls of the through-silicon holes is effectively removed, which improves the smoothness of the side walls and improves the performance and reliability of the TSV.
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Figure CN119742275A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor processing, and in particular to a method for preparing a TSV silicon wafer. Background Art
[0002] TSV (Through Silicon Via) is a technology called through silicon via in Chinese. It is a technology that creates vertical conduction between chips and wafers. TSV technology achieves vertical electrical interconnection of through silicon vias by filling conductive materials such as copper, tungsten, and polysilicon. TSV technology has the advantages of high density, high integration, and high-speed interconnection. It is a key technology for realizing 3D advanced packaging. Industry insiders call TSV the fourth generation of packaging technology after wire bonding, tape automated bonding (TAB), and flip chip (FC).
[0003] Through silicon via technology provides technical support for the smallest chip interconnection and the smallest disk spacing interconnection. Through silicon vias can not only shorten the conduction path between chips, improve signal speed, reduce power consumption and noise, but also realize heterogeneous architecture integration to meet the future consumer electronics requirements for thin and energy-saving devices.
[0004] Bosch etching technology is the current mainstream through-silicon via etching method. Because etching and passivation are performed alternately, scallop patterns will inevitably form on the sidewalls of the through-silicon vias, and their scale generally ranges from tens of nanometers to hundreds of nanometers. Scallop patterns will cause subsequent filling layers and interfaces between them to be uneven, which will seriously affect the performance of TSV and the reliability of three-dimensional integrated systems. Therefore, it is very important to reduce the scallop patterns on the inner wall of the TSV. Summary of the invention
[0005] The present invention discloses a method for preparing a TSV silicon wafer, which is used to solve related technical problems in the background technology.
[0006] The technical solution provided by the present invention is as follows: A method for preparing a TSV silicon wafer comprises the following steps:
[0007] S1, depositing an etching stop protection layer, and depositing a metal layer on the non-etching surface of the silicon wafer;
[0008] S2, first photolithography layer, coating the first layer of negative photoresist on the etched surface of the silicon wafer and exposing it;
[0009] S3, second photoresist layer, coating a second layer of negative photoresist on the first layer of photoresist and exposing;
[0010] S4, developing the first opening and the second opening whose inner diameter is larger than the first opening, and developing the first opening and the second opening according to the exposure pattern;
[0011] S5, first stage etching, according to the inner diameter of the first opening, etching by Bosch process to form a through silicon via of the first morphology, and entering the second stage etching when the first opening is consumed to be consistent with the inner diameter of the second opening;
[0012] S6, second stage etching, according to the second opening inner diameter, etching by Bosch process, forming a deeper etching, while removing the scalloped protrusions on the sidewall of the silicon through hole of the first morphology in sequence, when etching to the etching stop protection layer, the second stage etching ends, and the silicon through hole of the second morphology with a smooth upper sidewall and a scalloped protrusion on the lower sidewall is obtained;
[0013] S7, the third stage of etching, according to the second opening inner diameter, by etching through the Bosch process, the scalloped protrusions on the sidewall of the through silicon via of the second morphology are eliminated to obtain a through silicon via of the third morphology with a smooth sidewall;
[0014] S8, removing the first photoresist layer, the second photoresist layer and the deposited etch stop protection layer on the silicon wafer respectively.
[0015] In one embodiment, the inner diameter of the second opening is a diameter for preparing a through silicon via.
[0016] In one implementation, the first photoresist layer is relatively thin, which satisfies the consumption of etching depth in the first stage.
[0017] In one embodiment, the thickness of the second photoresist layer satisfies the consumption of the target etching depth.
[0018] In one implementation, the first stage etching in step S5 specifically includes:
[0019] S501, a gas is introduced into the first opening for etching to form a layer of first etching holes;
[0020] S502, introducing gas to form a passivation layer in the first etching hole;
[0021] S503, removing the passivation layer at the bottom of the first etched hole through physical bombardment and chemical reaction according to the first opening;
[0022] S504, repeating steps S501-S503, when the protruding portion of the first opening is consumed and the inner diameter of the second opening is consistent, the first stage of etching ends, and a through silicon via of the first morphology is obtained.
[0023] In one embodiment, after the first stage etching of step S5 is completed, the upper scalloped protrusion of the sidewall of the through silicon via of the first morphology is exposed in the second opening; the second stage etching of step S6 specifically includes:
[0024] S601, breaking the passivation layer at the bottom of the upper scalloped protrusion and the through silicon via of the first morphology through physical bombardment and chemical reaction according to the second opening;
[0025] S602, introducing gas to perform etching to eliminate the protrusions on the upper sidewall, forming a first smooth portion, and etching to form a second etching hole in the next layer;
[0026] S603, introducing gas to deposit a passivation layer at the first smooth portion and the second etched hole;
[0027] S604, repeating steps S601-603, when etching reaches the etching stop protection layer, the second stage of etching ends, and a through silicon via with a second morphology of smooth upper sidewalls and scalloped lower sidewalls is obtained.
[0028] In one embodiment, the third stage etching in step S7 specifically includes:
[0029] S701, bombarding the passivation layer of the scalloped protrusion portion of the upper sidewall of the through silicon via of the second morphology according to the second opening inner diameter;
[0030] S702, introducing gas for etching to eliminate scalloped protrusions and form a second smooth portion;
[0031] S703, depositing a passivation layer on the second smooth portion;
[0032] S704, repeating the above steps S701-S703 until all the remaining scalloped protrusions are etched to obtain a through silicon via of the third morphology with smooth sidewalls.
[0033] Compared with the prior art, the present invention has the following beneficial effects:
[0034] The method for preparing a TSV silicon wafer of the present invention can ensure that during the first stage of etching, the first opening of the first photolithography layer is consumed to be consistent with the second opening by setting a thinner first photolithography layer and a slightly larger second opening; thereby achieving the purpose of eliminating the side wall burrs through the first opening and the second opening during the second stage of etching, while continuing to etch the silicon via downward, and completely eliminating the scallop pattern on the inner wall during the third stage of etching; thereby achieving the beneficial effects of efficiently opening the silicon via, reducing the scallop pattern on the side wall of the silicon via, improving the side wall roughness, and improving the performance and reliability of the silicon via wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 is a schematic diagram of step S1 in the method for preparing a TSV silicon wafer of the present invention;
[0036] Figure 2 is a schematic diagram of step S2 in the method for preparing a TSV silicon wafer of the present invention;
[0037] Figure 3 is a schematic diagram of step S3 in the method for preparing a TSV silicon wafer of the present invention;
[0038] Figure 4 is a schematic diagram of step S4 in the method for preparing a TSV silicon wafer of the present invention;
[0039] Figure 5-6 is a schematic diagram of step S5 in the method for preparing a TSV silicon wafer of the present invention;
[0040] Figure 7-13 is a schematic diagram of step S6 in the method for preparing a TSV silicon wafer of the present invention;
[0041] Fig.14 is a schematic diagram of step S7 in the method for preparing a TSV silicon wafer of the present invention;
[0042] Fig.15 It is a schematic diagram of step S8 in the method for preparing a TSV silicon wafer of the present invention.
[0043] The figure numbers are as follows: 1. silicon wafer; 2. etching stop protection layer; 3. first photolithography layer; 4. second photolithography layer; 5. first opening; 6. second opening; 7. silicon via of first morphology; 8. scalloped protrusion; 9. silicon via of second morphology; 10. silicon via of third morphology; 11. first etching hole; 12. passivation layer; 13. first smooth portion; 14. second etching hole; 15. second smooth portion. DETAILED DESCRIPTION
[0044] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.
[0045] like Figure 1-15 As shown, the present invention is a method for preparing a TSV silicon wafer 1, comprising the steps of:
[0046] S1, depositing an etching stop protection layer 2, such as Figure 1 As shown, a metal layer with a thickness of 500A-5000A is deposited on the non-etched surface of the silicon wafer 1. When the metal layer is etched, the through silicon via etching is completed.
[0047] S2, first photolithography layer 3, such as Figure 2As shown, a first layer of negative photoresist is applied on the etching surface of the silicon wafer 1 and exposed; as shown in the figure, a layer of negative photoresist is applied on the surface of the silicon wafer 1, the upper surface of the silicon wafer 1 is blocked, and then the non-perforated area is exposed; the thickness of the first layer of photoresist is about 100-1000A, which is relatively thin and meets the consumption of the etching depth in the first stage.
[0048] S3, second photolithography layer 4, such as Figure 3 As shown, a second layer of negative photoresist is coated on the first layer of photoresist and exposed; as shown in the figure, a layer of negative photoresist is coated on the upper surface of the first layer of photoresist, the upper surface of the first layer of photoresist is blocked, and then the non-perforated area is exposed; the diameter of the perforated opening of the second photoresist layer 4 is larger than the diameter of the perforated opening of the first photoresist layer 3; the thickness of the second layer of photoresist needs to meet the consumption of the target etching depth.
[0049] S4, developing the first opening 5 and the second opening 6 with an inner diameter larger than the first opening 5, such as Figure 4 As shown, the first opening 5 and the second opening 6 are developed according to the exposure pattern; because the diameter of the punched opening of the second photoresist layer 4 is larger than the diameter of the punched opening of the first photoresist layer 3, the second opening 6 can be developed before the first opening 5 is developed, which does not affect the development of the first opening 5 on the first photoresist layer 3, thereby improving the development efficiency of the method.
[0050] S5, first stage etching, such as Figure 5-6 As shown, according to the inner diameter of the first opening 5, the first morphology of the through silicon via 7 is formed by etching through the Bosch process; during the etching process, the thinner first photolithography layer 3 is easily removed due to physical bombardment and reaction with the etching gas, but because it is blocked by the second photolithography layer 4, the expansion of the first opening 5 can only reach the same size as the second opening 6. When the inner diameters of the two tend to be consistent, the first stage of etching ends; the thinner design allows the first opening 5 to quickly coincide with the second opening 6, and also meets the subsequent second stage of etching, while etching and removing the scallop pattern protrusion 8, which improves the preparation efficiency of the through silicon via. As shown in the figure, it specifically includes:
[0051] S501, SF6 gas is introduced into the first opening 5 for etching to form a layer of first etching holes 11;
[0052] S502, introducing C4F8 gas to form a passivation layer 12 in the first etching hole 11;
[0053] S503, removing the passivation layer 12 at the bottom of the etching hole through physical bombardment and chemical reaction according to the first opening 5;
[0054] S504, repeating steps S501-S503, when the protruding portion of the first opening is consumed and the inner diameter is consistent with the second opening, the first stage of etching ends, and a through silicon via 7 of the first morphology is obtained.
[0055] In this embodiment, the first stage etching time is short, and the first etching hole 11 with a depth of one to several tens of layers is formed. The fewer the number of layers of the first etching hole 11, the shorter the third stage etching time is, and the higher the efficiency of the overall preparation method is.
[0056] S6, the second stage etching, such as Figure 7-13 As shown, when the first stage etching of step S5 is completed, the upper scalloped protrusions 8 on the sidewalls of the through silicon via 7 of the first morphology are exposed in the second opening 6; according to the inner diameter of the second opening 6, the scalloped protrusions 8 on the sidewalls of the through silicon via 7 of the first morphology are removed in sequence by etching through the Bosch process to form a deeper etching, and when etching reaches the etching stop protection layer 2, the second stage etching is completed to obtain a through silicon via 9 of the second morphology with a smooth upper sidewall and a scalloped lower sidewall; as shown in the figure, specifically:
[0057] S601, such as Figure 7 As shown, according to the second opening 6, the uppermost scalloped protrusion 8 and the passivation layer 12 at the bottom of the etched hole of the first morphology are broken through physical bombardment and chemical reaction; the uppermost scalloped protrusion 8 portion has been exposed to the ion bombardment area, and at this time, the portion of the bottom of the silicon via 7 of the first morphology that is not blocked by the scalloped protrusion 8 portion is also exposed to the ion bombardment area, so during the ion bombardment, the passivation layer 12 of the uppermost scalloped protrusion 8 and the passivation layer 12 at the bottom of the silicon via 7 of the first morphology that is not blocked by the scalloped protrusion 8 portion are broken at the same time; therefore, the passivation layer 12 at the bottom of the silicon via 7 of the first morphology that is broken is consistent with the area where the bottom passivation layer is broken during the first stage etching process, thereby ensuring the consistency of the size of the silicon via during subsequent downward etching.
[0058] S602, such as Figure 8 As shown, SF6 gas is introduced for etching to eliminate the upper sidewall protrusions, forming a first smooth portion 13, and at the same time, etching to form the next layer of second etching holes 14; while etching downward one layer, the scallop pattern protrusions 8 of one layer are partially eliminated, and the through silicon hole etching and scallop pattern elimination are carried out simultaneously, thereby improving the preparation efficiency of through silicon holes with smooth sidewalls.
[0059] S603, such as Fig. 9 As shown, C4F8 gas is introduced to deposit a passivation layer 12 at the first smooth portion 13 and the second etched hole 14;
[0060] S604, such as Figure 10-13 As shown, steps S601-603 are repeated, and when the etching stops at the etching stop protection layer 2, the second stage of etching is finished, and a through silicon via 9 of a second morphology with a smooth upper sidewall and a scalloped protrusion 8 on the lower sidewall is obtained.
[0061] The second stage etching of this embodiment optimizes the process steps and achieves the purpose of simultaneously eliminating scallop patterns and continuing downward etching, thereby achieving the beneficial effects of efficiently opening through silicon vias, reducing scallop patterns on the side walls of the through silicon vias, improving the side wall roughness, and enhancing the performance and reliability of the through silicon via wafer.
[0062] S7, such as Fig.14 As shown, in the third stage of etching, according to the inner diameter of the second opening 6, the scalloped protrusions 8 on the side wall of the through silicon via 9 of the second morphology are partially eliminated by etching through the Bosch process, so as to obtain a through silicon via 10 of the third morphology with smooth side walls; the design of the second opening 6 meets the requirements of the through silicon via size and provides a basis for the etching hole size; as shown in the figure, it specifically includes:
[0063] S701, bombarding the passivation layer 12 of the scalloped protrusion 8 on the upper sidewall of the through silicon via 9 of the second morphology according to the inner diameter of the second opening 6;
[0064] S702, introducing SF6 gas for etching to eliminate the scalloped protrusions 8 and form a second smooth portion 15;
[0065] S703, introducing C4F8 gas to deposit a passivation layer 12 on the second smooth portion 15;
[0066] S704 , repeat the above steps S701 - S703 until all the remaining scalloped protrusions 8 are etched to obtain a through silicon via 10 of the third morphology with smooth sidewalls.
[0067] The third stage etching of this embodiment can quickly eliminate the scallop pattern protrusions 8 remaining after the second stage etching, further improving the efficiency of the entire method.
[0068] S8, such as Fig.15 As shown, the photoresist and the bottom etching stop protection layer on the silicon wafer are removed, and the first photoresist layer 3, the second photoresist layer 4 and the etching stop protection layer 2 on the silicon wafer 1 are removed respectively by a wet process.
[0069] Example 1
[0070] S1, depositing an etching stop protection layer 2, such as Figure 1 As shown, a metal layer with a thickness of 2000 Å is deposited on the non-etched surface of the silicon wafer 1. When the metal layer is etched, the through silicon via etching is completed.
[0071] S2, first photolithography layer 3, coating a first layer of negative photoresist with a thickness of 300A on the etched surface of the silicon wafer 1, and exposing it;
[0072] S3, second photoresist layer 4, coating a second layer of negative photoresist with a thickness of 12 μm on the first layer of photoresist, and exposing;
[0073] S4, developing the first opening 5 and the second opening 6 having an inner diameter greater than the first opening 5, and developing the first opening 5 and the second opening 6 according to the exposure pattern, wherein the inner diameter of the first opening 5 is 49.9 μm, and the inner diameter of the second opening 6 is 50 μm;
[0074] S5, first stage etching, according to the inner diameter of the first opening 5, etching is performed by Bosch process to form a through silicon via 7 of the first morphology, and when the first opening 5 is consumed to be consistent with the inner diameter of the second opening 6, the second stage etching is entered;
[0075] S501, SF6 gas is introduced into the first opening 5 for etching to form a first etching hole 11; wherein the process parameters are: time 1.5S, pressure 35mtorr, RF power 2300W, lower electrode power 30W, etching gas flow 400sccm;
[0076] S502, introducing C4F8 gas to form a passivation layer 12 in the first etched hole 11; process parameters: time 1.3S, pressure 35mtorr, RF power 2300W, passivation gas flow rate 324sccm;
[0077] S503, removing the passivation layer 12 at the bottom of the etching hole by physical bombardment and chemical reaction according to the first opening 5; wherein the process parameters are: time 1.2S, pressure 35mtorr, RF power 2300w, lower electrode power 160W, etching gas flow 200sccm;
[0078] S504, repeating steps S501-S503, when the protruding portion of the first opening is consumed and the inner diameter is consistent with the second opening, the first stage of etching ends, and a through silicon via 7 of the first morphology is obtained.
[0079] S6, second stage etching, according to the inner diameter of the second opening 6, etching by Bosch process, forming a deeper etching, while removing the scalloped protrusions 8 on the sidewalls of the silicon through hole 7 of the first morphology in sequence, when etching to the etching stop protection layer 2, the second stage etching is completed, and the silicon through hole 9 of the second morphology with a smooth upper sidewall and a scalloped protrusion 8 on the lower sidewall is obtained;
[0080] S601, breaking the upper scalloped protrusion 8 and the passivation layer 12 at the bottom of the first morphology of the through silicon via 7 through physical bombardment and chemical reaction according to the second opening 6; wherein the process parameters are: time 1.2S, pressure 35mtorr, RF power 2300W, lower electrode power 160W, etching gas flow rate 200sccm;
[0081] S602, introducing SF6 gas for etching to eliminate the upper sidewall protrusions, forming the first smooth portion 13, and etching to form the next layer of second etching holes 14; wherein the process parameters are: time 1.5S, pressure 35mtorr, RF power 2300W, lower electrode power 30W, etching gas flow 400sccm;
[0082] S603, introducing C4F8 gas to deposit a passivation layer 12 at the first smooth portion 13 and the second etched hole 14; process parameters: time 1.3S, pressure 35mtorr, RF power 2300W, passivation gas flow rate 324sccm;
[0083] S604, such as Figure 10-13 As shown, steps S601-603 are repeated, and when the etching stops at the etching stop protection layer 2, the second stage of etching is finished, and a through silicon via 9 of a second morphology with a smooth upper sidewall and a scalloped protrusion 8 on the lower sidewall is obtained.
[0084] S7, the third stage of etching, according to the inner diameter of the second opening 6, the scalloped protrusions 8 on the side wall of the through silicon via 9 of the second morphology are partially eliminated by etching through the Bosch process, and the through silicon via 10 of the third morphology with smooth side walls is obtained;
[0085] S701, bombarding the passivation layer 12 of the scalloped protrusion 8 of the upper sidewall of the through silicon via 9 of the second morphology according to the inner diameter of the second opening 6; wherein the process parameters are: time 1.2S, pressure 25mtorr, RF power 2300W, lower electrode power 160W, etching gas flow rate 200sccm;
[0086] S702, introducing SF6 gas for etching to eliminate the scalloped protrusions 8 and form a second smooth portion 15; wherein the process parameters are: time 1.5S, pressure 35mtorr, RF power 2300W, lower electrode power 30W, etching gas flow rate 200sccm;
[0087] S703, introducing C4F8 gas to deposit the passivation layer 12 on the second smooth portion 15; process parameters: time 1.3S, pressure 35mtorr, RF power 2300W, passivation gas flow rate 324sccm;
[0088] S704 , repeat the above steps S701 - S703 until all the remaining scalloped protrusions 8 are etched to obtain a through silicon via 10 of the third morphology with smooth sidewalls.
[0089] S8 , respectively removing the first photoresist layer 3 , the second photoresist layer 4 and the deposited etch stop protection layer 2 on the silicon wafer 1 .
[0090] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.
[0091] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a TSV silicon wafer (1), characterized in that: The steps include: S1, depositing an etching stop protection layer (2), and depositing a metal layer on the non-etching surface of the silicon wafer (1); S2, first photolithography layer (3), coating a first layer of negative photoresist on the etched surface of the silicon wafer (1) and exposing it; S3, second photoresist layer (4), coating a second layer of negative photoresist on the first layer of photoresist and exposing it to light; S4, developing the first opening (5) and the second opening (6) having an inner diameter greater than the first opening (5), and developing the first opening (5) and the second opening (6) according to the exposure pattern; S5, first stage etching, etching by Bosch process according to the inner diameter of the first opening (5) to form a silicon through hole (7) of the first morphology, and entering the second stage etching when the first opening (5) is consumed to the same inner diameter as the second opening (6); S6, second stage etching, according to the inner diameter of the second opening (6), etching by Bosch process, forming a deeper etching, while sequentially removing the scalloped protrusions (8) on the side walls of the silicon through hole (7) of the first morphology, when etching reaches the etching stop protection layer (2), the second stage etching is completed, and the silicon through hole (9) of the second morphology with a smooth upper side wall and a scalloped protrusion (8) on the lower side wall is obtained; S7, a third stage of etching, according to the inner diameter of the second opening (6), etching by Bosch process, partially eliminating the scalloped protrusions (8) on the side wall of the through silicon via (9) of the second morphology, and obtaining a through silicon via (10) of the third morphology with smooth side walls; S8, respectively removing the first photolithography layer (3), the second photolithography layer (4) and the etching stop protection layer (2) on the silicon wafer (1).
2. A method for preparing a TSV silicon wafer (1) according to claim 1, characterized in that: The inner diameter of the second opening (5) is the diameter for preparing a through silicon via.
3. The method for preparing a TSV silicon wafer (1) according to claim 1, characterized in that: The thickness of the first photolithography layer (3) is relatively thin, which satisfies the consumption of the etching depth in the first stage.
4. A method for preparing a TSV silicon wafer (1) according to claim 1, characterized in that: The thickness of the second photolithography layer (4) satisfies the consumption of the target etching depth.
5. The method for preparing a TSV silicon wafer (1) according to claim 1, characterized in that: The first stage etching in step S5 specifically includes: S501, a gas is introduced into the first opening (5) for etching to form a layer of first etching holes (11); S502, introducing gas to form a passivation layer (12) in the first etching hole (11); S503, removing the passivation layer (12) at the bottom of the first etched hole (11) through physical bombardment and chemical reaction according to the first opening (5); S504, repeating steps S501-S503, when the protruding portion of the first opening (5) is consumed and the inner diameter is consistent with the second opening (6), the first stage of etching is completed, and a through silicon via (7) of the first morphology is obtained.
6. A method for preparing a TSV silicon wafer (1) according to claim 1, characterized in that: After the first stage etching in step S5 is completed, the upper scalloped protrusion (8) on the side wall of the through silicon via (7) of the first morphology is exposed in the second opening (6); the second stage etching in step S6 specifically includes: S601, breaking the upper scalloped protrusion (8) and the passivation layer (12) at the bottom of the through silicon via (7) of the first morphology through physical bombardment and chemical reaction according to the second opening (6); S602, introducing gas to perform etching to eliminate the protrusions on the upper sidewall, forming a first smooth portion (13), and at the same time, etching to form a second etching hole (14) in the next layer; S603, introducing gas to deposit a passivation layer (12) on the first smooth portion (13) and the second etched hole (14); S604, repeating steps S601-603, when etching reaches the etching stop protection layer (2), the second stage of etching ends, and a silicon through hole (9) with a second morphology of a smooth upper sidewall and a scalloped lower sidewall is obtained.
7. A method for preparing a TSV silicon wafer (1) according to claim 1, characterized in that: Step S7, the third stage etching specifically includes: S701, bombarding the passivation layer (12) of the scalloped protrusion (8) on the upper sidewall of the through silicon via (9) of the second morphology according to the inner diameter of the second opening (6); S702, introducing gas for etching to eliminate the scalloped protrusions (8) and form a second smooth portion (15); S703, depositing a passivation layer (12) on the second smooth portion (15); S704, repeating the above steps S701-S703 until all the remaining scalloped protrusions (8) are etched to obtain a through silicon via (10) of a third morphology with smooth sidewalls.
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