Power, signaling and thermal path co-optimization

Abstract

The invention relates to power, signaling and thermal path co-optimization. Chip structures and electronic modules are described that include power transfer network (PDN) routing structures and signal routing structures to balance power, signaling, and thermal requirements. In one embodiment, a chip includes a device layer, a PDN routing structure on top of the device layer, and a signal routing structure under the device layer.

Description

[0001] Related patent applications

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 586,645, filed on September 29, 2023, which is incorporated herein by reference. Technical Field

[0003] Embodiments described herein relate to semiconductor chip manufacturing, and more particularly to power delivery and signal network routing. Background Art

[0004] A typical high-performance logic chip, such as a processor, is designed to have both signal routing and power routing in a back-end-of-line (BEOL) stack formed above a semiconductor substrate and front-end-of-line (FEOL) device layers. In a conventional front-side power delivery arrangement, chip contact pads (e.g., solder bump landing pads for flip-chip connections) are formed on top of the BEOL stack in an arrangement referred to as front-side connection to chip contact pads. Thus, front-side connection implies that the chip contact pads are formed on top of the semiconductor substrate and FEOL device layers. In this case, the BEOL stack is also located on the front side, and the BEOL stack is considered to face the board when the chip is flip-chip mounted on a board or other wiring substrate. Such a BEOL stack may include 10 to 20 metal layers, for example, where the metal layers of the lower and middle levels are designated for signal routing and the top metal layer, which is the thickest and widest metal layer with the widest pitch, is designated for power routing and delay-sensitive or long routing. In such a typical configuration, both the power delivery wiring and the signal wiring are located on the same side of the chip, and both paths to the device layer are made through the same metal layer in the BEOL stack. However, as semiconductor process nodes, as measured by transistor size, continue to shrink, this also correlates with finer wiring requirements, which also correlates with increased resistance in the wiring through the metal layers. This increased resistance can further contribute to voltage drops in power delivery. Furthermore, since the metal stack is the same for both the power delivery interconnects and the signal interconnects, it needs to be adequately adapted for both at the same time, which may not be optimal for either.

[0005] More recently, it has been proposed to redistribute the power delivery wiring to the back side of the chip. In such a backside power delivery arrangement, the conventional BEOL stack formed on top of the FEOL device layer can be used primarily for signal wiring, while separate power wiring and chip contact pads are formed on the back side of the FEOL device layer (below it). Now, since the power network and contact pads are located on the back side of the device layer, this arrangement is called backside connection. Since the power network and signal wiring can be decoupled, each can be better optimized for its function. In such an arrangement, the backside power delivery wiring can be considered to face the board, such as when the chip is mounted to a board or other wiring substrate in a flip-chip manner. Summary of the invention

[0006] Chip structures and electronic modules are described that include power delivery network (PDN) routing structures and signal routing structures to balance power, signaling, and thermal requirements. In one embodiment, the chip includes a device layer, a PDN routing structure located on top of the device layer, and a signal routing structure located below the device layer. A variety of material selections and physical arrangements can be selected to achieve the necessary device performance, including thermal conductivity, dielectric constant and thickness of interlayer dielectric (ILD) layers, thickness and width of metal routing layers, and vertical connectivity arrangements including stacked vias, device layer vias, and power delivery vias. In addition, such arrangements can also align thermal pathways for thermal management of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a schematic cross-sectional side view illustration of an electronic module and main thermal path through a chip with backside connections and backside PDN routing structure.

[0008] Figure 1B is a schematic cross-sectional side view illustration of an electronic module and a primary thermal path through a chip with backside connections and a topside PDN routing structure according to an embodiment.

[0009] Figure 2A is a high level illustration of thermal resistance and capacitance per interlayer dielectric thickness according to an embodiment.

[0010] Figure 2B is a high level illustration of thermal conductivity and relative permittivity for engineering materials, according to an embodiment.

[0011] Figure 3 is a schematic cross-sectional side view illustration of a chip with backside connections and topside PDN wiring structures according to one embodiment.

[0012] Figure 4A is a schematic side view illustration of a signal routing structure metal routing layer spacing according to one embodiment.

[0013] Figure 4B is a schematic side view illustration of a signal routing structure metal routing layer layout according to one embodiment.

[0014] Figure 4C is a schematic top layout diagram illustration of a signal wiring structure metal wiring layer layout according to one embodiment.

[0015] Figure 5A is a schematic side view illustration of a PDN wiring structure metal wiring layer spacing according to one embodiment.

[0016] Figure 5B is a schematic side view illustration of a metal wiring layer layout of a PDN wiring structure according to one embodiment.

[0017] Figure 5C is a schematic top layout diagram illustration of a metal wiring layer layout of a PDN wiring structure according to one embodiment.

[0018] Figure 6 is a schematic cross-sectional side view illustration of an electronic module and power delivery pathways through a chip with backside connections and topside PDN wiring structure.

[0019] Figure 7 is a schematic cross-sectional side view illustration of a chip having backside connections and a combination of device layer vias and power delivery vias through the device layer to the top surface PDN routing structure according to one embodiment.

[0020] Figure 8 is a schematic cross-sectional side view illustration of a chip including an electroless bonding thermal solution layer according to one embodiment.

[0021] 9A to 9C is a schematic cross-sectional side view illustration of a series of electroless bonding thermal solution layers according to one embodiment.

[0022] Fig. 10A is a schematic cross-sectional side view illustration of a thermal solution layer including an active layer according to one embodiment.

[0023] Fig. 10B is a schematic cross-sectional side view illustration of a thermal solution layer including passive devices according to one embodiment.

[0024] Fig. 10C is a schematic cross-sectional side view illustration of a thermal solution layer including microchannels according to one embodiment.

[0025] Fig. 10Dis a schematic cross-sectional side view illustration of a thermal solution layer including an active layer and optical vias according to one embodiment. DETAILED DESCRIPTION

[0026] Embodiments describe chip structures and electronic modules that include a power delivery network (PDN) wiring structure and a signal wiring structure to balance power, signaling, and thermal requirements. In one embodiment, the chip structure includes a device layer, a PDN wiring structure located on top of the device layer, and a signal wiring structure located below the device layer. According to the embodiment, the metal wiring layer of the PDN wiring structure can be thicker and wider than the metal wiring layer of the signal wiring structure.

[0027] In one aspect, embodiments describe chip structures and electronic modules in which routing structures and PDNs for signal routing are decoupled from each other in a particular arrangement to balance signaling and power requirements while also balancing thermal requirements so as not to offset the expected gains associated with decoupling the signal routing and PDN routing. For example, it has been observed that for previous proposals for back-side power delivery arrangements with back-side PDN routing and top-side signal routing, the thermal path of the device may be suboptimal because the thermal path is hindered by the thermal resistance of the stack on either side of the device layer. According to embodiments, both signal transmission and power transmission can be optimized together while also aligning with the main thermal path of the chip. This can be achieved by decoupling the signal routing structure and the PDN routing structure and positioning the PDN routing structure on the top surface of the device layer and closer to the thermal solution layer (also known as the thermal packaging solution layer). The signal routing structure can be designed to have a line width, spacing, and height that supports the device layer density, energy requirements, and RC. The PDN routing structure can then be designed to have an interlayer dielectric (ILD) layer having a higher thermal conductivity (k 热 ) to promote heat flow along the intended thermal path (i.e., to the thermal solution layer). In addition, the metal wiring layers in the PDN wiring structure can be thicker, wider to obtain low resistance and finely spaced to increase packaging density, which can help thermal conductivity along the thermal path and also allow the integration of devices with electromagnetic properties. For example, the PDN wiring structure can include an integrated capacitor. An ILD layer with higher thermal conductivity can also have a higher dielectric constant, which can also support higher capacitance.

[0028] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and structures. In the following description, many specific details such as specific configurations, sizes and processes are shown to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. "One embodiment" mentioned throughout the specification refers to the specific features, structures, constructions or characteristics described in conjunction with the embodiments being included in at least one embodiment. Therefore, the phrase "in one embodiment" that appears in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, constructions or characteristics may be combined in one or more embodiments in any appropriate manner.

[0029] As used herein, the terms "over", "under", "to", "between", and "on" may refer to the relative position of one layer relative to other layers. A layer that is "over", "under", or "on" or bonded "to" or "in contact with" another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" multiple layers may be directly in contact with the multiple layers or may have one or more intervening layers.

[0030] According to an embodiment, the PDN routing structure can be decoupled from the signal routing structure to promote electrical performance gains. According to an embodiment, the thermal path for thermal management can also be controlled. Now refer to Figure 1A to Figure 1B , Figure 1A is a schematic cross-sectional side view illustration of an electronic module and a primary thermal path through a chip having backside connections and a backside PDN wiring structure; Figure 1B is a schematic cross-sectional side view illustration of an electronic module and a primary thermal path through a chip with backside connections and a topside PDN wiring structure according to an embodiment. Figure 1A to Figure 1BAs shown in each of the electronic modules 100, each includes a wiring substrate 102 (such as an interposer or a printed circuit board (PCB)) and a chip 104, which is mounted on the wiring substrate 102. For example, the chip 104 can be mounted to the wiring substrate 102 in a flip-chip manner using a plurality of solder bumps 106. The chips 104 can each include a device layer 108, a PDN wiring structure 110, and a signal wiring structure 112. A thermal solution layer 114 (such as a thermal cover, a heat sink, a heat sink, etc.) can be additionally included as part of the chip 104 or as a separate component. The thermal solution layer 114 can be a single layer or material, or can be a combination of multiple layers, materials and structures. For example, the thermal solution layer 114 can be formed of a variety of thermally conductive materials, including metals, aluminum nitride, silicon, diamond, silicon carbide, etc. The thermal solution layer 114 can also provide mechanical support and thus serve as a thermal mechanical solution. In one embodiment, the thermal solution layer is formed of a silicon substrate having sufficient thermal conductivity to act as a heat sink and having a coefficient of thermal expansion (CTE) that is compatible with the chip material. The thermal solution layer can be bonded to the underlying wiring structure using a bonding layer 116, which can be a thin oxide, metal, solder, etc. In one embodiment, the thermal solution layer is bonded to the underlying structure using oxide-oxide bonding of the bonding layer 116. In another embodiment, the thermal solution layer is bonded to the underlying structure using metal bonding, such as using metal diffusion bonding (e.g., aluminum-aluminum metal layers) or transient liquid phase (TLP) bonding, in which one or more intermetallic compounds are formed by interdiffusion of the bonding layer 116. Other bonding techniques may be used, such as hybrid bonding (including metal-metal bonding and oxide-oxide bonding), bonding to anisotropic conductive films (ACFs) (such as films including compressed cores (e.g., metal or polymer particles / balls) with solder skin / shell), silicon bonding techniques (e.g., cyclopentasilane or inks including silicon nanocrystals, such as silicon hybrids including silicon nanocrystals dispersed in a silicon matrix), as well as electroless bump formation, electroless (liquid) atomic layer deposition (ALD), and vapor phase ALD bonding.

[0031] exist Figure 1A In the particular configuration illustrated in FIG. 1 , the signal routing structure 112 is located on top of the device layer 108, while the PDN routing structure is located below the device layer 108. Figure 1B In the particular embodiment illustrated in FIG, the PDN routing structure is located on top of the device layer 108, while the signal routing structure 112 is located below the device layer 108. As shown by the arrows, heat is generated in the device layer. Figure 1A In a particular configuration, since both the signal wiring structure 112 and the wiring substrate 102 are characterized by low thermal conductivity, the primary thermal paths are misaligned. Therefore, the generated heat may not be adequately dissipated. Figure 1BIn the embodiment illustrated in FIG, the main thermal path is aligned with the PDN wiring structure characterized by relatively high thermal conductivity, which promotes heat transfer to the thermal solution layer 114 and chip efficiency. The difference in thermal path can be attributed to a combination of process conditions, including the use of higher thermal conductivity materials to form the ILD layer in the PDN wiring structure 110, and the increased metal density and size of the metal wiring layer (using less dielectric material). For example, the thermal resistance of the PDN wiring structure can be less than the thermal resistance of the signal wiring structure 112. Even 0.1C*mm 2 Differences in W / W can also have a measurable effect on heat transfer.

[0032] Reference now FIG. 2A to FIG. 2B , Figure 2A is a high level illustration of thermal resistance and capacitance per inter-layer dielectric (ILD) thickness according to an embodiment; Figure 2B The thermal conductivity and relative dielectric constant (e.g., dielectric constant ε) of integrated circuit (IC) engineering materials according to the embodiments are r ). Figure 3 As further described in detail, the signal wiring structure 112 and the PDN wiring structure 110 may include multiple metal wiring layers separated by ILD layers. The signal wiring structure 112 may require low capacitance between wiring layers, which can be achieved using low dielectric constant (low-k) ILD materials and thicker ILD layers. However, as Figure 1A As shown in , including low-k ILD materials and thicker ILD layers in the signal routing structure 112 may hinder the thermal path to the thermal solution layer 114 due to the corresponding lower thermal conductivity and higher thermal resistance of the ILD layer and the overall stacking of the signal routing structure 112. However, in Figure 1B In the embodiment illustrated in FIG. 1 , the PDN wiring structure 110 may alternatively be located above the device layer 108, wherein the PDN wiring structure 110 stack may include an ILD layer having a small thickness and formed of a material having a high dielectric constant (high-k) between metal wiring layers. Figure 1B As shown in , thermal access to the thermal solution layer 114 is facilitated by selecting a higher dielectric constant and higher thermal conductivity ILD material and a smaller thickness in the PDN wiring structure 110 .

[0033] Figure 31 is a schematic cross-sectional side view illustration of a chip 104 with a backside connection and a topside PDN wiring structure according to one embodiment. The device layer 108 according to the embodiment may be formed in a semiconductor layer 118, which includes a semiconductor wafer such as a silicon wafer or a III-V wafer, etc. Additionally, the device layer 108 may be formed in a top epitaxial layer of a silicon-on-insulator (SOI) substrate or a bulk silicon substrate, etc. A plurality of devices 120 are then formed in the semiconductor layer 118. For example, a doped well region and a source / drain region may be formed in the semiconductor layer 118 using a suitable diffusion technique. A gate is then formed over a channel region between the source / drain regions using a suitable technique such as polysilicon deposition. A silicide contact may then be formed on the gate and source / drain regions, as is known. The gate may then be insulated in a dielectric layer 122, followed by a plug contact 124 to the gate and source / drain regions. For example, the plug contact may be formed by etching and depositing a suitable conductive material such as tungsten, but the embodiment is not limited thereto. A certain amount of metal wiring may also be included. These conductive plug contacts and optional wiring together form a layer that may be referred to as a metal zero (M0) layer, which may be understood to represent the end of the FEOL process. It will be understood that, although a plurality of planar transistors are illustrated, this is exemplary and the embodiments are not limited thereto. For example, the transistor may be a non-planar transistor, including various dual-gate transistors, tri-gate transistors, gate-all-around transistors, and the like. In addition, in some designs in which the device layer 108 mainly includes only transistors and dielectrics, the thickness of the semiconductor layer 118 may not exist.

[0034] In the specific embodiment illustrated, a plurality of device layer vias 126 (e.g., nano-TSVs, micro-TSVs) may be formed through the semiconductor layer 118 and directly connected to the device 120, connected to the metal zero (M0) layer wiring, or additionally extended through the dielectric layer 122 to connect to the wiring layer to be formed subsequently. The device layer vias 126 may, for example, be nano-vias having a width of less than 200 nm (such as approximately 100 nm) and may have a pitch of tens to hundreds of nm to contact the device. The semiconductor layer 118 and therefore the device layer vias 126 may have a thickness and height of approximately hundreds of nm (such as 200 nm to 500 nm). Micro vias may have a larger width and height. It will be understood that the bulk semiconductor substrate on which the device layer 108 is formed may still exist during the formation of the device layer 108, and the device layer vias 126 do not need to extend further than the thickness of the device layer 108.

[0035] Now briefly refer to FIG. 4A to FIG. 4C and FIG. 5A to FIG. 5C , provides an illustration of the interval ( Figure 4A ) of the signal wiring structure metal wiring layer 132, and a schematic side view of the layout of the signal wiring structure metal wiring layer 132 ( Figure 4B ) and top layout diagram ( Figure 4C ) is illustrated so as to be spaced apart from the metal wiring layer 136 of the PDN wiring structure according to the embodiment ( Figure 5A ) and a schematic side view of the layout of the metal wiring layer 136 of the PDN wiring structure ( Figure 5B ) and top layout diagram ( Figure 5C ) are compared. For example, Figure 4A and Figure 5A As shown in , the wiring within the signal wiring structure 112 may include sparse wiring and vias separated by a relatively non-thermally conductive low dielectric constant (low-k) ILD layer, while the PDN wiring structure 110 may include wide metal wiring planes separated by a high dielectric constant (high-k) ILD layer and may have a higher via density. In such a configuration, the PDN wiring structure 110 may have a higher thermal conductivity than the signal wiring structure 112. Figure 4B and Figure 5B The more sparse / longer signal routing structure 112 network wiring is illustrated compared to the PDN routing structure 110 routing network which may be more dense (more closely spaced metal routing layers and via density and thickness of metal layers). Figure 4C Illustrated with Figure 5C The metal planes of the PDN wiring structure shown in Figure 1 are more sparsely laid out than the signal lines. Each pair in this comparison can be Figure 3 Reference is made to the following discussion.

[0036] Still reference Figure 3 , then, the PDN wiring structure 110 can be formed over the device layer 108. The PDN wiring structure 110 can be formed over the device layer 108 using conventional BEOL build-up structure technology, including dual damascene processing for complementary metal oxide transistor (CMOS) chip manufacturing. The PDN wiring structure 110 can also be a non-CMOS technology, such as an ultra-fine ceramic technology formed at high temperatures that are not feasible with CMOS technology and then bonded using a wafer-on-wafer (WoW) or chip-on-wafer (CoW) assembly, which can include hybrid bonding, non-electrical bump formation, etc. The PDN wiring structure 110 can include a combination of generation and bonding technologies.

[0037] The PDN wiring structure 110 may include a main power network structure 111 and optionally one or more second lower metal wiring layers (M) having fine wiring. 低2) in order to provide the necessary device wiring requirements. It may not be feasible for the rough wiring of the main power network structure 111 to make direct contact with the transistors, and therefore a second lower metal wiring layer may be included in the PDN wiring structure 110. Including a second lower metal wiring layer within the PDN wiring structure 110 can also improve signal wiring compared to previous proposals of back power delivery arrangements with back PDN wiring and top signal wiring, where it has been observed that random logic components are limited by the number of metal layers in the back PDN wiring. According to an embodiment, the back signal wiring structure 112 and the second lower metal layer (M) within the top PDN wiring structure 110 are 低2 ) can provide increased wiring capabilities for logic components.

[0038] As described above, the PDN wiring structure 110 may be formed using a combination of deposition and bonding techniques. 低2 ) can be formed using conventional BEOL and CMOS processing techniques, and the main power network structure 111 can be similarly formed, or can be formed using different techniques and bonded to the second lower metal wiring layer (M) by, for example, hybrid bonding or non-electrical bump formation. 低2 ).

[0039] Then, the thermal solution layer 114 can be formed on the PDN wiring structure 110. Alternatively, the thermal solution layer 114 can be formed with the PDN wiring structure 110 before bonding the PDN wiring structure to the device layer 108. For example, a bonding layer 116 such as a thin oxide layer or other combinations of dielectric layers can be used for oxide-oxide or dielectric-dielectric bonding. Metal layers can also be used for metal-metal bonding to increase thermal conductivity. Other bonding techniques can be used, such as hybrid bonding (including metal-metal bonding and oxide-oxide bonding), bonding with anisotropic conductive films (ACFs) (such as films including compressed cores (e.g., metal or polymer particles / balls) with solder skin / shell), silicon bonding techniques (e.g., cyclopentasilane or inks including silicon nanocrystals), and non-electric bump formation. The thermal solution layer 114 can also be used as a handle wafer during subsequent processing. At this point, the bulk substrate supporting the device layer 108 can be thinned or removed using any suitable technique such as grinding or stripping techniques and polishing. Signal routing structures 112 may then be formed on the backside of device layer 108. This may be followed by the formation of a passivation layer 141, such as silicon nitride, and chip contact terminal 142 formation, such as metal post contacts for landing pads for solder bump drops.

[0040] For example, the thermal solution layer 114 may be formed of multiple layers and materials. In the illustrated exemplary embodiment, the thermal solution layer may include a lower portion 114A that is compatible with the supporting thin device layer 108, while the upper portion 114B may be suitable for a conventional system thermal solution layer, such as a thermal cover, heat sink, heat sink, etc. The lower portion 114A and the upper portion 114B may be the same continuous material, such as silicon, diamond, etc. In other configurations, the lower portion 114A may be silicon, diamond, etc., followed by a second material for the upper portion 114B, such as a metal.

[0041] The signal wiring structure 112 may be formed using more conventional BEOL stacked structure CMOS processing techniques, materials, and technology nodes. The signal wiring structure 112 may include a plurality of metal wiring layers 132 separated by an ILD layer 128 and connected to vias 134 extending through the ILD layer 128. The wiring layer thickness may vary depending on the wiring level. For example, the lower metal layer (M 低 ) can have the finest wiring size, the upper metal layer (M 高 ) has a coarser wiring size and a larger thickness and line width, the middle level metal layer (M 中 ) is located somewhere in the middle. Optionally, some upper metal layers (M 高 ) may be used for the power delivery network. The total number of metal wiring layers 132 may vary depending on the technology node and chip type, and may often vary between a total of 10 and 20 metal wiring layers 132. The respective metal wiring layers 132 are separated into 低 、M 中 、M 高 The ILD layer 128 in the inner portion may also be a different dielectric material with different dielectric constants, where the ILD layer 128 surrounds and separates the lower metal layer (M) having the lowest dielectric constant. 低 ). Surrounding and separating the second lower metal layer (M 低2 The ILD layer 130 may be formed by surrounding and separating the lower metal layer (M 低 ) are formed of similar materials having similar dielectric constants to those of the ILD layers 128. Therefore, the ILD layer 130 surrounding and separating the metal layers within the main power network structure 111 can be formed of a different material and have a dielectric constant than that surrounding and separating the signal wiring structure 112. 中 、M 高 At least those IDL layers within metal wiring layers 132 have a high dielectric constant.

[0042] According to the embodiment, the signal wiring structure 112 and the PDN wiring structure 110 can be decoupled to address competing interests. For example, the signal wiring structure 112 may require a larger ILD layer 128 thickness between the metal wiring layers 132 in order to maintain low capacitance. Similarly, for similar reasons, the line spacing within the metal wiring layer can be further separated. Additionally, low-k dielectric materials can be used for the ILD layer 128. Suitable low-k dielectric materials include fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped oxide (CDO), polymers, methyl silsesquioxane (MSQ), dry gels, etc. Many low-k dielectric materials can also be porous. Although not directly related, low dielectric constant materials are generally associated with low thermal conductivity, which can be beneficial to signal integrity. However, the ILD layer 130 of the PDN wiring structure 110 can be formed of a material with higher thermal conductivity. Although not directly related to the relationship with the dielectric constant, high dielectric constant (high-k) materials can be selected to have a dielectric constant greater than 4 (such as 5 to 10 or higher) and manufacturing process friendly. Exemplary high-k materials include oxides, nitrides, oxynitrides, silicon, silicon nitride (Si3N4), and more specialized technical ceramics such as aluminum oxide (Al2O3), boron carbide (B4C), tungsten carbide (WC), aluminum nitride (AlN), silicon carbide (SiC), etc. The metal wiring layers 136 of the PDN wiring structure 110 (and in particular the metal wiring layers within the main power network structure 111) are comparable to the metal wiring layers of the signal wiring structure 112 (and in particular the metal wiring layers higher than M 低 Similarly, via 138 can be wider than via 134, and there can be a higher via density within PDN routing structure 110 compared to signal routing structure 112. For example, PDN routing structure 110 can include a via density of greater than 10% by volume within the via / dielectric layer (and the entire PDN routing structure 110), while signal routing structure 112 can include a via density of less than 5% by volume within the via / dielectric layer (and the entire signal routing structure 112).

[0043] Still reference Figure 3 , the ILD layer 128 of the signal wiring structure 112 may have a thickness of 1 μm to meet the resistance, capacitance and density requirements. However, the ILD layer 130 of the PDN wiring structure 110 (and in particular the ILD layer of the main power network structure 111) may be much thinner, such as at least half the thickness of the ILD layer 128 (excluding any common M 低 For example, the ILD layer 130 may be between 0.05 μm and 0.5 μm thick. For illustrative purposes, the upper metal layer M in the signal wiring structure 112 may be between 0.05 μm and 0.5 μm thick. 高The PDN wiring structure 110 may be separated by a silicon oxide ILD layer 128 having a thickness of 0.5 μm to 1 μm and a dielectric constant of 3.9, while the metallization layer of the PDN wiring structure 110 may be separated by a high-k ILD layer 130 having a thickness of 0.1 μm and a dielectric constant of 9. Such a change in parameters may result in a 22.5 times greater capacitance per unit area (9×1) / (4×0.1)=22.5 C / mm 2 Such an increase may further facilitate the inclusion of integrated capacitors 135 in the PDN wiring structure 110. For example, such capacitors may be metal-insulator-metal (MIM) capacitors formed between planes in a metallization layer, possibly with a high dielectric constant (high-k) dielectric ILD material (e.g., with a dielectric contact greater than 4).

[0044] Figure 6 1 is a schematic cross-sectional side view illustration of an electronic module and power delivery pathways through a chip having backside connections and a topside PDN wiring structure. As shown, the power delivery network may receive high power (Vdd) and low power (Vss) signals from wiring substrate 102, for example, through solder bumps 106. These signals may optionally be routed to one or more upper metal layers (M) of signal wiring structure 112. 高 ) and then vertically emitted through the signal routing structure 112, through the device layer 108 and into the PDN routing structure 110, where the signal can be further globally routed and distributed to the devices in the device layer 108. It has been observed that potential electrical weaknesses may be sharing metal routing layers and dielectric layers that have been designed for signal routing and transmission within the signal routing structure 112. For example, finer line thickness and via width may result in higher resistance.

[0045] Figure 7 is a schematic cross-sectional side view illustration of a chip according to one embodiment having a combination of backside connections and device layer vias 126 and power delivery vias through the device layer to the top surface PDN wiring structure. In particular, Figure 7The embodiments illustrated in the drawings show several structural arrangements that can be used individually or in any combination to reduce resistance. For example, stacked vias can be used to shorten the power transmission path. As shown, the vias 134 in the stacked signal wiring structure 112 can be stacked so that closely adjacent vias overlap each other at least partially. The stacked vias 134 can pass through most or all of the signal wiring structure 112. Similar arrangements of stacked vias 138 can also be used in the PDN wiring structure 110. In the specific embodiment illustrated, the stacked vias 134 are connected to the device layer vias 126 extending through the device layer 108. Alternatively, a power transmission via 140 can be included. The customized power transmission via 140 can be wider than the device layer via 126, such as about microns or tens of microns. The power transmission via can also extend through the thicker device layer 108, and can optionally extend further into the signal wiring structure 112 and / or the PDN wiring structure 110. Thus, while the illustrated power delivery via 140 extends through both the signal wiring structure 112 and / or the PDN wiring structure 110, this is intended to illustrate an extreme example, and the power delivery via 140 may extend through any thickness, ranging from the device layer to any thickness, or a portion of the thickness of the surrounding wiring layers. In alternative variations also shown, the power delivery via may extend through or partially through one of the wiring layers. For example, a power delivery via 140A is also shown that extends partially through the signal wiring structure 112 and then branches out using the metal wiring layer 132 to connect to the device layer via 126. In this configuration, many of the metal wiring layers of the signal wiring structure 112 may be bypassed using the power delivery via 140A for power delivery. Additionally, the power delivery vias 140, 140A may have a customized height or delivery path with fewer interfaces. For example, common diffusion barriers and metal-metal layers between various vias and metal wiring layers can be avoided, and instead continuous metal (e.g., copper) power transmission vias are formed through multiple metal and dielectric layers without having to pass through multiple interfaces, which may still exist in (e.g.,) a stacked via arrangement.

[0046] Figure 8 is a schematic cross-sectional side view illustration of a chip including an electroless bonding thermal solution layer 114 according to one embodiment. 9A to 9C 1 is a schematic cross-sectional side view illustration of a series of electroless bonding thermal solution layers according to one embodiment. As shown, the thermal solution layer 114 may include a plurality of bonding pads 152 that are aligned with the bonding pads 154 of the PDN wiring structure 110. For example, each of the bonding pads 152 may be a copper pad or a protruding post. FIG. 9A to FIG. 9BAs shown in , the thermal solution layer 114 and the PDN wiring structure 110 can be aligned and secured above each other using a pressure plate and / or an optional spacer 156, which can be used to adhere the structures to each other and / or control the spacing between the aligned bond pads 152, 154. For example, the optional spacer can be formed of an adhesive material (e.g., a polymer) to help align the thermal solution layer 114 and the PDN wiring structure 110 and hold these structures in place during electroless deposition. Then, as Fig. 9C As shown in , the processed and aligned structure can be placed in an electroless plating bath for producing a metal joint 158 ​​between the aligned bonding pads 52, 154. For example, the metal joint 158 ​​can be formed of copper, nickel, copper alloys, nickel alloys, etc. In this way, a metal joint 158 ​​with a high melting temperature (e.g., the melting temperature of copper and nickel) can be formed without subjecting the bonding structure to high temperatures. The metal joint 158 ​​can also be loaded with materials such as diamond or SiC to improve thermal performance. For example, the metal joint 158 ​​may include nickel loaded with additional materials (such as diamond or SiC). This can increase the thermal conductivity closer to copper and make the thermal expansion coefficient closer to silicon, thereby allowing a higher area fraction utilization.

[0047] The thermal solution layer 114 according to the embodiment can provide multiple functions. For example, the thermal solution layer can be formed of various enhanced thermal materials such as SiC, diamond, AlN, composite materials, etc., so as to improve the thermal characteristics of the chip while maintaining warpage and manufacturability defects. In addition, such a cover can add some functions such as capacitors, optical elements, micro-channels, etc.

[0048] Fig. 10A 1 is a schematic cross-sectional side view illustration of a thermal solution layer including an active layer 162 according to one embodiment. In such embodiments, the active layer 162 may be formed within a bulk layer 164 such as a semiconductor material (e.g., silicon) and may offload certain logic components from the underlying device layers of the chip. The active layer 162 may include a plurality of logic devices, such as transistors, etc. To enable electrical connections to the active layer 162, various electrical and thermal interconnects 153 (e.g., vias and any other wiring) may be included, which may optionally extend through one or more dielectric layers 166.

[0049] Fig. 10B is a schematic cross-sectional side view illustration of thermal solution layer 114 including passive device 170 according to one embodiment. For example, passive device 170 can be a deep trench capacitor formed in body layer 164 and electrically connected to the PDN wiring structure through interconnect 153.

[0050] Fig. 10Cis a schematic cross-sectional side view illustration of a thermal solution layer 114 including microchannels 172 according to one embodiment. For example, the microchannels 172 may be filled with a flowing liquid (or phase change fluid) to further aid in cooling.

[0051] Fig. 10D 1 is a schematic cross-sectional side view illustration of a thermal solution layer 114 including an optional active layer 162 and an optional optical pathway 174 according to one embodiment. The active layer 162 (when present) may support optical or other functions. The optical pathway 174 may, for example, include a waveguide or optical fiber. The optical pathway may be further connected to various optical components 176, including modulators, couplers, optical detectors (e.g., diodes), optical transmitters (e.g., light emitting diodes, lasers), etc. There may also be interconnects 153 for electricity and / or heat. In some embodiments, the optical components are optical-to-electrical (O / E) and electrical-to-optical (E / O) converters. For example, the thermal solution layer 114 may receive optical connectivity from / transmit optical connectivity to the PDN wiring structure 110. In this way, the thermal solution layer 114 and the PDN wiring structure 110 (or the structure below) may have complementary receivers / transceivers. Alternatively, the optical pathway may be completely contained within the thermal solution 114 layer.

[0052] In one embodiment, the electronic module includes a wiring substrate 102 and a chip 104 mounted on the wiring substrate 102. According to an embodiment, the chip includes a device layer 108, a PDN wiring structure 110 located on top of the device layer 108, and a signal wiring structure 112 located below the device layer 108. The PDN wiring structure 110 can be characterized by a higher thermal conductivity than the signal wiring structure 112. The signal wiring structure 112 can include a first plurality of metal wiring layers 132, and the PDN wiring structure 110 includes a second plurality of metal wiring layers 136. For example, the average thickness of the second plurality of metal wiring layers 136 can be greater than the average thickness of the first plurality of metal wiring layers 132. If the lower metal layer M is not considered 低 and M 低2 , which may be particularly true. The signal wiring structure 112 may additionally include a plurality of chip contact terminals 142 for bonding to the wiring substrate 102 , for example using a plurality of solder bumps 106 .

[0053] According to an embodiment, a thermal solution layer 114 (e.g., a thermal cover, heat sink, heat spreader, etc.) is bonded to the top surface of the PDN wiring structure 110 to draw heat away from the wiring structure and the device layers. The signal wiring structure 112 may include a first plurality of ILD layers 128, while the PDN wiring structure 110 includes a second plurality of ILD layers 130 characterized by a higher dielectric constant than the first plurality of ILD layers 128. For example, the second plurality of ILD layers may have a dielectric constant greater than 4, such as 5 to 9 or more.

[0054] In one embodiment, the plurality of power delivery vias 140 , 140A extend through more than one of the first plurality of metal wiring layers 132 and the first plurality of ILD layers 128 in the signal wiring structure 112 .

[0055] The PDN wiring structure 110 according to the embodiment may include fewer metal wiring layers than the signal wiring structure 112. The PDN wiring structure 110 may have a higher metal content than the signal wiring structure 112, and the PDN wiring structure 110 may also be thicker than the signal wiring structure 112. According to the embodiment, the PDN wiring structure 110 may include a greater via density than the signal wiring structure. For example, the PDN wiring structure 110 may include a via density greater than 10% by volume, while the via density of the signal wiring structure 112 is less than 5% by volume. The vias 138 within the PDN wiring structure may also be shorter than the vias 134 within the signal wiring structure 112. This is for the mid-level vias (M vias) in the signal wiring structure 112. 中 ) and upper level vias (M 高 As another indication, the average ratio of the height of the vias 138 to the thickness of the metal wiring layer 136 within the PDN wiring structure 110 can be less than the average ratio of the height of the vias 134 to the thickness of the metal wiring layer 132 within the signal wiring structure 112. A thinner ILD layer 130 can facilitate the integration of the capacitor 135 within the PDN wiring structure 110, especially when located between power planes formed in the metal wiring layer 136.

[0056] Vertical connection from the wiring substrate 102 to the PDN wiring structure 110 may be facilitated by a combination of features including stacked vias 134 within the signal wiring structure 112 and / or stacked vias 138 within the PDN wiring structure 110, device layer vias 126 extending through the device layer 108, and / or power delivery vias 140 extending through the device layer 108 and optionally through a portion or all of either the signal wiring structure 112 and the PDN wiring structure 110. Depending on the type of active device in the device layer 108 (e.g., planar transistors, fin field effect transistors (FinFETs), gate-all-around transistors, etc.), the silicon thickness may vary, so the device layer vias 126 may be TSVs that pass through some silicon or vias that largely pass through a thin silicon layer transition.

[0057] The thermal solution layer 114 according to the embodiment can be bonded to the top surface of the PDN wiring structure in a variety of ways, and the thermal solution can perform a variety of functions. In one embodiment, the thermal solution layer is bonded to the top surface of the PDN wiring structure using a uniform metal layer (e.g., using metal-metal diffusion bonding, TLP bonding, etc.). In one embodiment, the thermal solution layer includes a first plurality of bonding pads, the PDN wiring structure includes a second plurality of bonding pads, and the first plurality of bonding pads are bonded to the second plurality of bonding pads using a plurality of metal joints. For example, this can be achieved using electroless bonding. In one embodiment, the melting temperature of the plurality of metal joints is greater than the melting temperature of the first plurality of bonding pads and the second plurality of bonding pads.

[0058] The thermal solution layer may include logic devices and / or passive devices, such as deep trench capacitors electrically connected to the PDN wiring structure. In some embodiments, the thermal solution layer may include optical pathways, including various components, including any of the following: waveguides, optical wires, converters, modulators, etc. When utilizing various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible to form a chip with back-side connections and top-side PDN wiring structures. Although the embodiments are described in language specific to structural features and / or methodological behaviors, it should be understood that the appended claims are not necessarily limited to the specific features or behaviors described. The specific features and behaviors disclosed should instead be understood as embodiments of the claims for exemplification.

Claims

1. A chip structure, comprising: Device layer; a power delivery network (PDN) wiring structure located on top of the device layer; and A signal wiring structure, the signal wiring structure is located below the device layer; Wherein the signal wiring structure includes a first plurality of metal wiring layers and the PDN wiring structure includes a second plurality of metal wiring layers, and the PDN wiring structure is characterized by a higher thermal conductivity than the signal wiring structure. 2 . The chip structure according to claim 1 , wherein the signal wiring structure further comprises a plurality of chip contact terminals. 3 . The chip structure of claim 2 , wherein the signal wiring structure comprises a first plurality of interlayer dielectric (ILD) layers, and the PDN wiring structure comprises a second plurality of ILD layers, the second plurality of ILD layers being characterized by a higher dielectric constant than the first plurality of ILD layers. 4 . The chip structure of claim 3 , further comprising a plurality of power delivery vias extending through more than one of the first plurality of metal wiring layers and through more than one of the first plurality of ILD layers in the signal wiring structure. The chip structure according to claim 3 , wherein the second plurality of ILD layers have a dielectric constant greater than 4. 6 . The chip structure according to claim 2 , wherein the PDN wiring structure includes fewer metal wiring layers than the signal wiring structure. 7 . The chip structure of claim 2 , wherein the PDN wiring structure comprises a higher metal content than the signal wiring structure. 8 . The chip structure according to claim 2 , wherein the PDN wiring structure comprises a greater via density than the signal wiring structure. 9 . The chip structure according to claim 8 , wherein the via density of the PDN wiring structure is greater than 10% by volume, and the via density of the signal wiring structure is less than 5% by volume.

10. The chip structure of claim 2, wherein the PDN wiring structure comprises a smaller average ratio of via height to metal wiring layer thickness than the signal wiring structure. The chip structure according to claim 10 , wherein the PDN routing structure comprises a power plane. 12 . The chip structure according to claim 2 , further comprising a plurality of device layer vias extending through the device layer.

13. The chip structure of claim 2, wherein the PDN wiring structure comprises an integrated metal-insulator-metal (MIM) capacitor. 14 . The chip structure according to claim 2 , wherein an average thickness of the second plurality of metal wiring layers is greater than an average thickness of the first plurality of metal layers. 15 . The chip structure of claim 2 , further comprising a thermal solution layer bonded to a top surface of the PDN wiring structure. 16 . The chip structure of claim 15 , wherein the thermal solution layer is bonded to the top surface of the PDN wiring structure using a uniform metal layer. 17 . The chip structure of claim 15 , wherein the thermal solution layer comprises a first plurality of bonding pads, the PDN wiring structure comprises a second plurality of bonding pads, and the first plurality of bonding pads are bonded to the second plurality of bonding pads using a plurality of metal joints. 18 . The chip structure according to claim 17 , wherein a melting temperature of the plurality of metal bonding portions is greater than a melting temperature of the first plurality of bonding pads and the second plurality of bonding pads. The chip structure according to claim 15 , wherein the thermal solution layer comprises a logic device. 20 . The chip structure of claim 15 , wherein the thermal solution layer comprises a plurality of deep trench capacitors electrically connected to the PDN wiring structure.

21. The chip structure of claim 15, wherein the thermal solution layer comprises an optical via.

22. An electronic module, comprising: Wiring substrate; and A chip, the chip being mounted on the wiring substrate, the chip comprising: Device layer; a power delivery network (PDN) wiring structure located on top of the device layer; and A signal wiring structure, the signal wiring structure is located below the device layer; Wherein the signal wiring structure comprises a first plurality of metal wiring layers and the PDN wiring structure comprises a second plurality of metal wiring layers, and the PDN wiring structure is characterized by a higher thermal conductivity than the PDN wiring structure.

23. The electronic module according to claim 22, wherein the signal wiring structure further comprises a plurality of chip contact terminals, wherein the chip contact terminals are bonded to the wiring substrate using a plurality of solder bumps.

24. The electronic module of claim 22, wherein an average thickness of the second plurality of metal wiring layers is greater than an average thickness of the first plurality of metal layers.

25. The electronic module of claim 22, further comprising a plurality of power delivery vias extending through more than one of the first plurality of metal wiring layers and through more than one of the first plurality of inter-layer dielectric (ILD) layers in the signal wiring structure.

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