Battery pack charging current limiting circuit and method based on high-side MOS common drain

Abstract

The present invention discloses a battery pack charging current limiting circuit and method based on a high-side MOS common drain, wherein the drains of a charging MOS group and a discharging MOS group in the charging circuit are connected in common, which reduces the number of driving circuits used, reduces the cost, and is more compatible with an AFE chip compared to a MOS common source solution. The current limiting circuit is connected to both ends of the charging MOS group, and a dual charging channel is provided in the current limiting circuit. The MCU gives a pair of complementary signals to the dual channels through a driver chip, and controls the charging current limiting by adjusting the signal duty cycle. The current limiting value can be actively controlled by software or passively controlled by a preset current limiting value.

Description

Technical Field

[0001] The present invention relates to the technical field of battery management systems, and in particular to a battery pack charging current limiting circuit and method based on a high-side MOS common drain. Background Art

[0002] For lithium-ion battery packs, during the charging process, the host computer is sometimes required to calibrate the charging current value of the BMS module, or when the charging current is greater than a certain value, the charging current limiting module starts to work actively, so that the battery pack can intelligently adjust the charging current. The general charging current limiting function circuit design based on high-side MOS is a MOS common source solution. Such a charging current limiting module is usually connected in parallel in the middle of the charging and discharging MOS and on the charging and discharging positive electrode, but the design idea of ​​the high-side MOS common source solution requires an additional drive circuit, and most AFE chips do not support the high-side MOS common source design. The design of the high-side MOS common source solution is not widely applicable and the cost is relatively high. With the development of lithium-ion battery pack technology, the high-side MOS common drain solution is gradually adopted at this stage. This solution can better adapt to the AFE chip and has a lower cost. At the same time, a corresponding charging current limiting circuit is required.

[0003] A charging current limiting circuit is designed based on the high-side MOS common drain solution to realize the active and passive current limiting functions of the battery pack. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a battery pack charging current limiting circuit and method based on a high-side MOS common drain. In the circuit, the drains of the charging MOS group and the discharging MOS group are commonly connected, and the current limiting circuit is connected to both ends of the charging MOS group. A dual charging channel is provided in the current limiting circuit. The MCU gives a pair of complementary signals to the dual channels through a driving chip, and the charging current limiting is controlled by adjusting the signal duty cycle.

[0005] The technical solution adopted by the present invention is specifically: a battery pack charging current limiting circuit based on a high-side MOS common drain according to an embodiment of the present invention includes a charging MOS group, a discharging MOS group, a current limiting circuit, a high-side driving circuit, an MCU and a driving chip, wherein the drains of the charging MOS group and the discharging MOS group are connected in common, and the gates are connected to an AFE chip, the source of the charging MOS group is connected to the positive electrode of the battery pack, and the source of the discharging MOS group is connected to the charging and discharging positive electrode. The current limiting circuit is connected to both ends of the charging MOS group, and the high-side driving circuit is connected to the current limiting circuit. The MCU is connected to the driving chip and then connected to the current limiting circuit.

[0006] As an optional scheme of the technical solution of the present invention, the charging MOS group includes a first capacitor, a second capacitor and first to fourth MOS tubes in parallel, the first capacitor and the second capacitor are connected in series and connected in parallel with the first to fourth MOS tubes, the first to fourth MOS tubes have a common source, drain and gate, wherein the source is connected to the positive electrode of the battery pack, the gate is connected to the AFE chip after the protection resistor is connected in series, and also includes a first diode, the positive electrode of the first diode is connected to the source of the first to fourth MOS tubes, and the negative electrode is connected to the gate of the fourth MOS tube.

[0007] As an optional solution of the technical solution of the present invention, the discharge MOS group includes a third capacitor, a fourth capacitor and fifth to eighth MOS tubes in parallel, the third capacitor and the fourth capacitor are connected in series and connected in parallel with the fifth to eighth MOS tubes, the fifth to eighth MOS tubes have a common source, drain and gate, wherein the source is connected to the positive electrode of charging and discharging, the gate is connected to the AFE chip after the protection resistor is connected in series, and also includes a second diode and a ninth resistor in parallel, the positive electrode of the second diode is connected to the source of the fifth to eighth MOS tubes, and the negative electrode is connected to the gate of the eighth MOS tube.

[0008] As an optional solution of the technical solution of the present invention, the current limiting circuit includes ninth to eleventh MOS tubes, the drain of the ninth MOS tube is connected to the drains of the first to eighth MOS tubes, the gate is connected to the tenth resistor and then to the driving chip, the source is connected to the driving chip and the third diode and then to the gate; the drain of the tenth MOS tube is connected to the source of the ninth MOS tube, the gate is connected to the eleventh resistor and then to the driving chip, the source is connected to the charging and discharging negative electrode and the fourth diode and then to the gate; the source of the eleventh MOS tube is connected to the first inductor and then to the source of the ninth MOS tube, the gate is connected to the twelfth resistor and then to the high-side driving circuit, the source is connected to the high-side driving circuit and the fifth diode and then to the gate; it also includes the fifth and sixth capacitors connected in parallel, the positive electrode is connected to the drain of the ninth MOS tube, and the negative electrode is connected to the charging and discharging negative electrode; it also includes the seventh to tenth capacitors connected in parallel, the positive electrode is connected to the source of the eleventh MOS tube, and the negative electrode is connected to the charging and discharging negative electrode.

[0009] As an optional solution of the technical solution of the present invention, the high-side drive circuit includes a micro-power isolated power supply chip, an enabling transformer, a bridge rectifier circuit, a filtering circuit and a fast shutdown circuit. The enabling terminal of the micro-power isolated power supply chip is connected to the MCU, the voltage input terminal is connected to the onboard voltage, the voltage output terminal is connected to the enabling transformer input terminal, the enabling transformer output terminal is connected to the bridge rectifier circuit and then to the filtering circuit, and finally connected to the fast shutdown circuit and then to the source and gate of the eleventh MOS tube.

[0010] As an optional solution of the technical solution of the present invention, a battery pack charging current limiting method based on a high-side MOS common drain is provided, using the above-mentioned battery pack charging current limiting circuit based on a high-side MOS common drain, and the method comprises the following steps: S1: When the battery pack is charged, the charging MOS group is turned on and the discharging MOS group is turned off. The upper limit of the charging current is determined by the number of MOS tubes in parallel in the charging MOS group. When the battery pack is discharged, the charging MOS group is turned off and the discharging MOS group is turned on. The upper limit of the discharge current is determined by the number of MOS tubes in parallel in the discharging MOS group. When the upper computer issues a charging current limiting command and gives a current limiting value, the charging MOS group and the discharging MOS group are disconnected, the high-side drive circuit turns on the eleventh MOS tube, and the charging current limiting circuit starts to work; S2: MCU sends a pair of complementary signals to the gates of the ninth MOS tube and the tenth MOS tube through the driver chip. When the ninth MOS tube is turned on and the tenth MOS tube is turned off, the current passes through the ninth MOS tube, the first inductor, the seventh capacitor and the eighth capacitor to charge the battery pack. When the ninth MOS tube is turned off and the tenth MOS tube is turned on, the current passes through the tenth MOS tube, the first inductor, the seventh capacitor and the eighth capacitor to charge the battery pack. S3: MCU adjusts the duty cycle of the ninth MOS tube signal in the complementary signal, and the current limit value is proportional to the duty cycle.

[0011] Beneficial effects achieved by the present invention: The battery pack charging current limiting circuit and method based on high-side MOS common drain provided by the present invention, wherein the drains of the charging MOS group and the discharging MOS group in the charging circuit are connected in common, the current limiting circuit is connected to both ends of the charging MOS group, dual charging channels are provided in the current limiting circuit, and the MCU gives a pair of complementary signals to the dual channels through the driving chip, and the charging current limiting is controlled by adjusting the signal duty cycle. Compared with the MOS common source solution, the cost is reduced and the AFE chip can be better compatible. At the same time, the current limiting value can be actively controlled by software or the current limiting value can be passively controlled by preset value.

[0012] The effects of the present invention are not limited to the above effects, and those skilled in the art can derive effects not described above from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram of a charging current limiting circuit system according to an embodiment of the present invention.

[0014] Figure 2 4 is an overall circuit diagram of a charging current limiting circuit according to an embodiment of the present invention.

[0015] Figure 3 4 is a high-side driving circuit diagram of a charging current limiting circuit according to an embodiment of the present invention.

[0016] Figure 4 4 is a circuit diagram of a charging current limiting circuit driving chip according to an embodiment of the present invention.

[0017] Figure 5 Schematic diagram of dual charging channels of a charging current limiting circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the following specific embodiments are only used to explain the present invention, but not to limit the present invention. Based on the following embodiments, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the protection scope of the present invention.

[0019] It should be noted that in the description of the present invention, the terms "include" and "comprise" indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections, and are only for the convenience of describing the simplified description of the present invention, and therefore cannot be understood as limiting the present invention. In the description of the embodiments, unless otherwise clearly specified and limited, the terms "set", "connect" and the like should be understood in a broad sense. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0020] like Figure 1 The figure shows a block diagram of a battery pack charging current limiting circuit system based on a high-side MOS common drain according to an embodiment of the present invention. The drains of the charging MOS group and the discharging MOS group are connected in common, the gates are connected to the AFE chip, the source of the charging MOS group is connected to the positive electrode BAT+_ON of the battery pack, and the source of the discharging MOS group is connected to the positive electrode PACK+ for charging and discharging. When the battery pack is charging, the charging MOS group is turned on and the discharging MOS group is turned off, and the current charges the battery pack through the discharging MOS body diode and the charging MOS group; when the battery pack is discharging, the charging MOS group is turned off and the discharging MOS group is turned on, and the current is discharged to the outside through the charging MOS body diode and the discharging MOS group. The current limiting circuit is connected to both ends of the charging MOS group, and the current limiting circuit is controlled to open and close by the high-side driving circuit. The current limiting circuit is connected to the MCU through the driving chip, and the MCU inputs a driving signal to the current limiting circuit through the driving chip to control the size of the current limiting value.

[0021] like Figure 2The figure shows the overall circuit diagram of the battery pack charging current limiting circuit based on the high-side MOS common drain of the embodiment of the present invention. The charging MOS group is composed of the first to fourth MOS tubes connected in parallel, and the first to fourth MOS tubes have a common source, drain and gate. The discharging MOS group is composed of the fifth to eighth MOS tubes connected in parallel, and the fifth to eighth MOS tubes have a common source, drain and gate. The drains of the charging MOS group and the discharging MOS group are interconnected. The source of the charging MOS group is connected to the positive electrode BAT+_ON of the battery pack, and the source of the discharging MOS group is connected to the charging and discharging positive electrode PACK+. The gate of the first MOS tube Q1 is connected in series with the first resistor R1, the gate of the second MOS tube Q2 is connected in series with the second resistor R2, the gate of the third MOS tube Q3 is connected in series with the third resistor R3, the gate of the fourth MOS tube Q4 is connected in series with the fourth resistor R4, and then connected together to the AFE chip; the gate of the fifth MOS tube Q5 is connected in series with the fifth resistor R5, the gate of the sixth MOS tube Q6 is connected in series with the sixth resistor R6, the gate of the seventh MOS tube Q7 is connected in series with the seventh resistor R7, and the gate of the eighth MOS tube Q8 is connected in series with the eighth resistor R8, and then connected together to the AFE chip. The charging MOS group also includes a first capacitor C1 and a second capacitor C2 connected in series, which are connected in series with the first to fourth MOS tubes in parallel; the discharging MOS group also includes a third capacitor C3 and a fourth capacitor C4 connected in series, which are connected in series with the fifth to eighth MOS tubes in parallel. The charging MOS group also includes a first diode D1, the positive electrode of the first diode D1 is connected to the source of the fourth MOS tube Q4, and the negative electrode is connected to the gate of the fourth MOS tube Q4; the discharging MOS group also includes a second diode D2 and a ninth resistor R9 connected in parallel, the positive electrode of the second diode D2 is connected to the source of the eighth MOS tube Q8, and the negative electrode is connected to the gate of the eighth MOS tube Q8. When the battery pack is charging, the AFE chip gives a high level to the gate of the charging MOS group and a low level to the gate of the discharging MOS group; when the battery pack is discharging, the AFE chip gives a low level to the gate of the charging MOS group and a high level to the gate of the discharging MOS group.

[0022] like Figure 2The figure shows the overall circuit diagram of the battery pack charging current limiting circuit based on the high-side MOS common drain of the embodiment of the present invention. The current limiting circuit includes the ninth to eleventh MOS tubes, the drain of the ninth MOS tube Q9 is connected to the drain of the first to eighth MOS tubes Q8, and is also connected to the positive electrodes of the fifth capacitor C5 and the sixth capacitor C6 in parallel, the negative electrodes of the fifth capacitor C5 and the sixth capacitor C6 are connected to the charging and discharging negative electrode P-, the gate of the ninth MOS tube Q9 is connected to the tenth resistor R10 and then to the driving chip, the source is connected to the driving chip and the positive electrode of the third diode D3 is connected to the gate. When the driving chip gives the gate of the ninth MOS tube Q9 a low level, the ninth MOS tube Q9 is disconnected; when the driving chip gives the gate of the ninth MOS tube Q9 a high level, the ninth MOS tube Q9 is turned on. The drain of the tenth MOS tube Q10 is connected to the source of the ninth MOS tube Q9, the gate is connected to the eleventh resistor R11 and then to the driving chip, the source is connected to the charging and discharging negative electrode P- and is also connected to the positive electrode of the fourth diode D4 and then to the gate. When the driver chip gives the tenth MOS tube Q10 a low level at the gate, the tenth MOS tube Q10 is disconnected; when the driver chip gives the tenth MOS tube Q10 a high level at the gate, the tenth MOS tube Q10 is turned on. The source of the eleventh MOS tube Q11 is connected to the first inductor L1 and then to the source of the ninth MOS tube Q9, and is also connected to the positive electrodes of the seventh capacitor C7 and the eighth capacitor C8 in parallel, and the negative electrodes of the seventh capacitor C7 and the eighth capacitor C8 are connected to the charging and discharging negative electrode P-, and are also connected to the ninth capacitor C9 and the tenth capacitor C10 in parallel and then to the charging and discharging negative electrode P-, the gate of the eleventh MOS tube Q11 is connected to the twelfth resistor R12 and then to the high-side drive circuit, the source is connected to the high-side drive circuit and is also connected to the positive electrode of the fifth diode D5 and then to the gate. When the high-side drive circuit gives the eleventh MOS tube Q11 a low level at the gate, the eleventh MOS tube Q11 is disconnected, and the current limiting circuit stops running; when the high-side drive circuit gives the eleventh MOS tube Q11 a high level at the gate, the eleventh MOS tube Q11 is turned on, and the current limiting circuit starts running.

[0023] It should be noted that the above charging MOS group and discharging MOS group are both composed of four MOS tubes in parallel, which is only used to explain the schematic diagram and is not used to limit the present invention, wherein the number of MOS tubes is determined according to the actual maximum current value of charging and discharging, and the MOS tubes are NMOS tubes. In addition, the fifth to eighth capacitors are polar capacitors, which are used as voltage-stabilizing output capacitors, and the ninth and tenth capacitors are used to filter high frequencies.

[0024] like Figure 3The high-side driving circuit diagram of the battery pack charging current limiting circuit based on the high-side MOS common drain of the embodiment of the present invention is shown. From left to right, they are: micro-power isolation power supply chip U1, enabling transformer U2, bridge rectifier circuit, filter circuit and fast shutdown circuit. Among them, the enabling terminal EN of the micro-power isolation power supply chip U1 is connected to the MCU after being connected in series with the thirteenth resistor R13, and is connected to the eleventh capacitor C11 and then grounded; the GND terminal and CLK terminal of the micro-power isolation power supply chip U1 are grounded; the voltage input terminal VIN is connected to the fourteenth resistor R14 and then to the voltage output terminal of the PCB board, and is connected to the twelfth capacitor C12 and then grounded; the voltage output terminals VD1 and VD2 are connected to the input terminal of the enabling transformer U2. The output terminal of the enabling transformer U2 is connected to the input terminal of the bridge rectifier circuit. The bridge rectifier circuit is composed of four Schottky diodes, including a sixth diode D6, a seventh diode D7, an eighth diode D8 and a ninth diode D9. The sixth diode D6 and the eighth diode D8 are connected to a common cathode and then connected to a filter circuit. The seventh diode D7 and the ninth diode D9 are connected to a common anode and then connected to a filter circuit. The anode of the sixth diode D6 and the cathode of the seventh diode D7 are connected to one end of the input end of the enable rectifier circuit. The cathode of the eighth diode D8 and the ninth diode D9 are connected to the other end of the input end of the enable rectifier circuit. The filter circuit is composed of a thirteenth capacitor C13 and a fifteenth resistor R15 connected in parallel. The two ends of the output end of the rectifier circuit are connected to the two ends of the thirteenth capacitor C13. The fast shutdown circuit includes a PNP transistor Q12, the base of which is connected to the sixteenth resistor R16 and then to one end of the filter circuit, the base of which is connected to the seventeenth resistor R17 and then to the other end of the filter circuit, the base of which is connected to the tenth diode D10 and then to the emitter, the collector of which is connected to the other end of the filter circuit, and the collector of which is connected to the source of the eleventh MOS tube Q11 and the emitter of which is connected to the gate of the eleventh MOS tube Q11. When the MCU receives the charging current limiting command, it inputs a high level to the enable terminal EN of the micro-power isolation power chip U1, and the micro-power isolation power chip U1 starts to output the onboard DC power of the voltage input terminal VIN from the voltage output terminals VD1 and VD2 at a fixed frequency, and then boosts the voltage through the enable transformer U2, and then inputs a high level to the gate of the eleventh MOS tube Q11 after passing through the bridge rectifier circuit and the filter circuit, so that the eleventh MOS tube Q11 is turned on, and the current limiting circuit starts to work. When the MCU receives the command to stop charging and current limiting, it inputs a low level to the enable terminal EN of the micro-power isolation power chip U1, and the micro-power isolation power chip U1 does not work, thereby inputting a low level to the gate of the eleventh MOS tube Q11, so that the eleventh MOS tube Q11 is disconnected and the current limiting circuit stops working. Since the base of the PNP transistor Q12 is at a low level, the PNP transistor Q12 is turned on, and the gate and source of the eleventh MOS tube Q11 are short-circuited, so that the parasitic capacitance of the eleventh MOS tube Q11 can be quickly discharged, and the current limiting circuit can be quickly turned off.

[0025] like Figure 4The circuit diagram of the driving chip of the battery pack charging current limiting circuit based on the high-side MOS common drain of the embodiment of the present invention is shown. The driving chip U3, the VDD terminal is connected to the 12V DC power supply, the GND terminal is grounded, the HIN terminal is connected in series with the eighteenth resistor R18 and then connected to the MCU, the LIN terminal is connected in series with the eighteenth resistor R19 and then connected to the MCU, the VB terminal is connected to the fourteenth capacitor C14 and then connected to the VS terminal, and the eleventh diode D11 and the fifteenth capacitor C15 are connected in series and then grounded. The driving chip HO terminal is connected to the gate of the ninth MOS tube Q9, the VS terminal is connected to the source of the ninth MOS tube Q9, and the LO terminal is connected to the gate of the tenth MOS tube Q10. When the MCU receives the charging current limiting command, it gives a pair of complementary signals to the HIN terminal and the LIN terminal. When the HIN terminal is high level, the LIN terminal is low level, the HO terminal outputs a high level, the LO terminal outputs a low level, the ninth MOS tube Q9 is turned on, and the tenth MOS tube Q10 is turned off; when the HIN terminal is low level, the LIN terminal is high level, the HO terminal outputs a low level, the LO terminal outputs a high level, the ninth MOS tube Q9 is turned off, and the tenth MOS tube Q10 is turned on.

[0026] The battery pack charging current limiting circuit based on the high-side MOS common drain described in this embodiment is used to implement the battery pack charging current limiting method based on the high-side MOS common drain. The above method is further described below.

[0027] When the above-mentioned charging current limiting circuit stops working, the charging of the battery pack requires the charging MOS group to be turned on and the discharging MOS group to be turned off. The charging current charges the battery pack through the body diode of the discharging MOS group and the charging MOS group. At this time, the upper limit of the charging current is determined by the number of MOS tubes in parallel in the charging MOS group. The discharging of the battery pack requires the charging MOS group to be turned off and the discharging MOS group to be turned on. The discharging current is discharged to the outside through the body diode of the charging MOS group and the discharging MOS group. At this time, the upper limit of the discharge current is determined by the number of MOS tubes in parallel in the discharging MOS group. When the upper computer issues a charging current limiting command and gives a current limiting value, the AFE chip gives a low level to the gate of the charging MOS group and the gate of the discharging MOS group, and the charging MOS group and the discharging MOS group are both disconnected. At the same time, the MCU inputs a high level to the enable terminal EN of the micro-power isolation power supply chip U1, and the high-side drive circuit turns on the eleventh MOS tube Q11. The charging current limiting circuit starts to work, and the charging current charges the battery pack through the body diode of the discharging MOS group and the charging current limiting circuit.

[0028] After the charging current limiting circuit starts working, the MCU inputs a pair of complementary signals from the HIN and LIN terminals of the driver chip, such as Figure 4As shown in the signal EPWM1A and EPWM1B, the output terminal corresponding to the HIN terminal is the HO terminal, the output terminal corresponding to the LIN terminal is the LO terminal, and the VS terminal outputs a low-level signal. When the HIN terminal is at a high level, the LIN terminal is at a low level, the HO terminal outputs a high level, the LO terminal outputs a low level, the ninth MOS tube Q9 is turned on, the tenth MOS tube Q10 is turned off, and the charging current charges the battery pack through the ninth MOS tube Q9, the first inductor L1, the seventh capacitor C7 and the eighth capacitor C8. Figure 5 Channel ① shown in the figure, at this time, the current is provided by the external power supply; when the HIN terminal is at a low level, the LIN terminal is at a high level, the HO terminal outputs a low level, the LO terminal outputs a high level, the ninth MOS tube Q9 is disconnected, the tenth MOS tube Q10 is turned on, and the charging current charges the battery pack through the tenth MOS tube Q10, the first inductor L1, the seventh capacitor C7 and the eighth capacitor C8, as shown in FIG. Figure 5 In the channel ② shown in the figure, the current is provided by the first inductor L1.

[0029] The MCU adjusts the duty cycle of EPWM1A in the complementary signal to control the on-time of the ninth MOS tube Q9, that is, the on-time of channel ①, thereby realizing the control of the current limiting value.

[0030] In summary, the battery pack charging current limiting circuit and method based on high-side MOS common drain provided by the present invention, wherein the drains of the charging MOS group and the discharging MOS group in the charging circuit are connected in common, reduces the number of driving circuits used, reduces costs and is more compatible with AFE chips compared to the MOS common source solution. The current limiting circuit is connected to both ends of the charging MOS group, and dual charging channels are provided in the current limiting circuit. The MCU gives a pair of complementary signals to the dual channels through the driver chip, and controls the charging current limiting by adjusting the signal duty cycle. The current limiting value can be actively controlled by software or passively controlled by preset current limiting value.

[0031] The effects of the present invention are not limited to the effects listed above, and those skilled in the art can derive effects not described above from the description.

[0032] The above-described embodiments of the battery pack charging current limiting circuit and method based on the high-side MOS common drain are merely illustrative preferred embodiments and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention. In addition, various technical solutions can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them; when the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

Claims

1. A battery pack charging current limiting circuit based on high-side MOS common drain, characterized in that: include: A charging MOS group and a discharging MOS group, wherein the drains of the charging MOS group and the discharging MOS group are connected in common, the gates are connected to the AFE chip, the source of the charging MOS group is connected to the positive electrode of the battery pack, and the source of the discharging MOS group is connected to the charging and discharging positive electrode; A current limiting circuit and a high-side driving circuit, wherein the current limiting circuit is connected to both ends of the charging MOS group, and the high-side driving circuit is connected to the current limiting circuit; MCU and a driving chip, wherein the MCU is connected to the driving chip and then connected to the current limiting circuit.

2. The battery pack charging current limiting circuit based on high-side MOS common drain as claimed in claim 1, characterized in that: The charging MOS group includes a first capacitor, a second capacitor and first to fourth MOS tubes connected in parallel, the first capacitor and the second capacitor are connected in series and then connected in parallel with the first to fourth MOS tubes, the first to fourth MOS tubes share a source, a drain and a gate, wherein the source is connected to the positive electrode of the battery pack, the gate is connected to the AFE chip after the protection resistor is connected in series, and also includes a first diode, the positive electrode of the first diode is connected to the source of the first to fourth MOS tubes, and the negative electrode is connected to the gate of the fourth MOS tube.

3. The battery pack charging current limiting circuit based on high-side MOS common drain as claimed in claim 1, characterized in that: The discharge MOS group includes a third capacitor, a fourth capacitor and fifth to eighth MOS tubes connected in parallel. The third capacitor and the fourth capacitor are connected in series and then connected in parallel with the fifth to eighth MOS tubes. The fifth to eighth MOS tubes share a source, a drain and a gate, wherein the source is connected to the positive electrode of charging and discharging, the gate is connected to the AFE chip after the protection resistor is connected in series, and also includes a second diode and a ninth resistor connected in parallel, the positive electrode of the second diode is connected to the source of the fifth to eighth MOS tubes, and the negative electrode is connected to the gate of the eighth MOS tube.

4. The battery pack charging current limiting circuit based on high-side MOS common drain as claimed in claim 1, characterized in that: The current limiting circuit includes ninth to eleventh MOS tubes, wherein the drain of the ninth MOS tube is connected to the drains of the first to eighth MOS tubes, the gate is connected to the tenth resistor and then to the driving chip, the source is connected to the driving chip and simultaneously to the third diode and then to the gate; the drain of the tenth MOS tube is connected to the source of the ninth MOS tube, the gate is connected to the eleventh resistor and then to the driving chip, the source is connected to the charging and discharging negative electrode and simultaneously to the fourth diode and then to the gate; the source of the eleventh MOS tube is connected to the first inductor and then to the source of the ninth MOS tube, the gate is connected to the twelfth resistor and then to the high-side driving circuit, the source is connected to the high-side driving circuit and simultaneously to the fifth diode and then to the gate; the fifth and sixth capacitors are also connected in parallel, the positive electrode is connected to the drain of the ninth MOS tube, and the negative electrode is connected to the charging and discharging negative electrode; the seventh to tenth capacitors are also connected in parallel, the positive electrode is connected to the source of the eleventh MOS tube, and the negative electrode is connected to the charging and discharging negative electrode.

5. The battery pack charging current limiting circuit based on high-side MOS common drain as claimed in claim 1, characterized in that: The high-side drive circuit includes a micro-power isolated power supply chip, an enabling transformer, a bridge rectifier circuit, a filter circuit and a fast shutdown circuit. The enabling terminal of the micro-power isolated power supply chip is connected to the MCU, the voltage input terminal is connected to the onboard voltage, the voltage output terminal is connected to the enabling transformer input terminal, the enabling transformer output terminal is connected to the bridge rectifier circuit and then to the filter circuit, and finally connected to the fast shutdown circuit and then to the source and gate of the eleventh MOS tube.

6. A battery pack charging current limiting method based on high-side MOS common drain, characterized in that: Using the battery pack charging current limiting circuit based on high-side MOS common drain as described in any one of claims 1 to 5, the method comprises the following steps: S1: When the battery pack is charged, the charging MOS group is turned on and the discharging MOS group is turned off. The upper limit of the charging current is determined by the number of MOS tubes in parallel in the charging MOS group. When the battery pack is discharged, the charging MOS group is turned off and the discharging MOS group is turned on. The upper limit of the discharge current is determined by the number of MOS tubes in parallel in the discharging MOS group. When the upper computer issues a charging current limiting command and gives a current limiting value, the charging MOS group and the discharging MOS group are disconnected, the high-side drive circuit turns on the eleventh MOS tube, and the charging current limiting circuit starts to work; S2: MCU sends a pair of complementary signals to the gates of the ninth MOS tube and the tenth MOS tube through the driver chip. When the ninth MOS tube is turned on and the tenth MOS tube is turned off, the current passes through the ninth MOS tube, the first inductor, the seventh capacitor and the eighth capacitor to charge the battery pack. When the ninth MOS tube is turned off and the tenth MOS tube is turned on, the current passes through the tenth MOS tube, the first inductor, the seventh capacitor and the eighth capacitor to charge the battery pack. S3: MCU adjusts the duty cycle of the ninth MOS tube signal in the complementary signal, and the current limit value is proportional to the duty cycle.

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