Synchronous control method, synchronous control circuit and electronic equipment

Abstract

The present application discloses a synchronous control method, a synchronous control circuit, and an electronic device, the synchronous control method comprising: the synchronous control circuit obtains the first carrier signal and the first power supply output signal of any one of at least two energy storage conversion circuits; within each power frequency cycle of the first power supply output signal, when the first power frequency voltage phase of the first power supply output signal passes through zero in a negative direction, the second power supply output signal of each other energy storage conversion circuit is subjected to power frequency synchronous adjustment; when the first power frequency voltage phase of the first power supply output signal passes through zero in a negative direction, the second power supply output signal of each other energy storage conversion circuit is subjected to power frequency synchronous adjustment. Through the above-mentioned manner, the synchronous control method of the present application adopts interconnected signal carrier synchronization, which effectively reduces the requirements for voltage sampling accuracy and improves the accuracy of carrier synchronization; and the same synchronous control circuit is used to achieve both carrier synchronization and power frequency synchronization, which effectively reduces hardware costs and software overhead.

Description

Technical Field

[0001] The present application relates to the field of circuit control technology, and in particular to a synchronous control method, a synchronous control circuit, and an electronic device. Background Art

[0002] Power conversion systems (PCSs) are now widely used in industrial and commercial energy storage, household energy storage, and other fields due to their ability to efficiently convert AC to DC. Converting DC to AC for grid feedback or directly powering AC loads typically involves connecting the AC sides of multiple energy storage converters in parallel to form a parallel power supply system. However, parallel PCSs often generate switching frequency secondary currents and power frequency currents, necessitating carrier and power frequency synchronization.

[0003] However, the carrier synchronization in the related art does not have an interconnected signal synchronization method, so that the voltage sampling accuracy is required to be high, and there is a problem of inaccurate synchronization in actual use. Summary of the Invention

[0004] The main technical problem solved by this application is to provide a synchronization control method, a synchronization control circuit and an electronic device, which can solve the problem in the related technology that the carrier synchronization has high requirements for voltage sampling accuracy and there is inaccurate synchronization in actual use.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a synchronous control method, which is applied to the synchronous control of an energy storage conversion circuit, wherein the number of energy storage conversion circuits is at least two, each energy storage conversion circuit is coupled to a synchronous control circuit, the DC side of each energy storage conversion circuit is used to couple with a DC power supply, and the AC sides of each energy storage conversion circuit are connected in parallel to each other for coupling with an AC load, wherein the synchronous control method includes: the synchronous control circuit obtains a first carrier signal and a first power supply output signal in any energy storage conversion circuit; within each power frequency cycle of the first power supply output signal, when the first carrier signal passes through zero, the second carrier signal in each other energy storage conversion circuit is subjected to carrier synchronous adjustment; when the first power frequency voltage phase of the first power supply output signal passes through zero in a negative direction, the second power supply output signal of each other energy storage conversion circuit is subjected to power frequency synchronous adjustment.

[0006] Among them, when the first carrier signal passes through zero, the carrier synchronization adjustment of the second carrier signal in each other energy storage conversion circuit includes: detecting whether the first power frequency voltage phase is greater than the first voltage phase; if the first power frequency voltage phase is greater than the first voltage phase, using the system clock and the first counting cycle value, the first counting direction value and the first carrier count value of the first carrier signal to obtain a first time difference; delaying the first time difference to perform carrier synchronization adjustment on the second carrier signal in each other energy storage conversion circuit; or, delaying the first time difference to send a carrier synchronization signal to each other energy storage conversion circuit, so that each other energy storage conversion circuit performs carrier synchronization adjustment on its second carrier signal.

[0007] Among them, when the first power frequency voltage phase of the first power supply output signal crosses zero in a negative direction, the power frequency synchronous adjustment of the second power supply output signal of each other energy storage conversion circuit includes: detecting whether the first power frequency voltage phase is greater than the second voltage phase; wherein the second voltage phase is greater than the first voltage phase; if the first power frequency voltage phase is greater than the second voltage phase, using the first power frequency voltage phase and the first angular frequency of the first power supply output signal to obtain a second time difference; delaying the second time difference to perform power frequency synchronous adjustment on the second power supply output signal of each other energy storage conversion circuit; or, delaying the second time difference to send a power frequency synchronization signal to each other energy storage conversion circuit, so that each other energy storage conversion circuit performs power frequency synchronous adjustment on its second power supply output signal.

[0008] Among them, the carrier synchronization adjustment of the second carrier signal in each other energy storage conversion circuit includes: obtaining the second counting period value, the second counting direction value and the second carrier count value of the second carrier signal in each other energy storage conversion circuit; detecting whether each second carrier count value is 0; if there is a second carrier count value that is not 0, detecting whether the second counting direction value corresponding to the second carrier count value that is not 0 is 1; if the second counting direction value corresponding to the second carrier count value that is not 0 is 1, the corresponding second counting period value is increased by a first set value; if the second counting direction value corresponding to the second carrier count value that is not 0 is not 1, the corresponding second counting period value is reduced by the first set value.

[0009] Among them, the power frequency synchronous adjustment of the second power supply output signal of each other energy storage conversion circuit includes: obtaining the second power frequency voltage phase of the second power supply output signal in each other energy storage conversion circuit; detecting whether each second power frequency voltage phase is 0; if there is a second power frequency voltage phase that is not 0, detecting whether the second power frequency voltage phase that is not 0 is less than π; if the second power frequency voltage phase that is not 0 is less than π, reducing the second angular frequency of the corresponding second power supply output signal by a second set value; if the second power frequency voltage phase that is not 0 is not less than π, increasing the second angular frequency of the corresponding second power supply output signal by a second set value.

[0010] In which, the synchronous control circuit includes a signal processing subcircuit and a bus transceiver subcircuit, the signal processing subcircuit is coupled to each energy storage conversion circuit and the bus transceiver subcircuit, the bus transceiver subcircuit is used to couple with the synchronous bus subcircuit, the synchronous bus subcircuit is coupled to each energy storage conversion circuit, and when the first power frequency voltage phase of the first power supply output signal passes through zero in a negative direction, the second power supply output signal of each other energy storage conversion circuit is subjected to power frequency synchronous adjustment, including: the signal processing subcircuit sends a first logic level signal to the bus transceiver subcircuit in response to the first carrier signal passing through zero; the bus transceiver subcircuit adjusts the differential output signal sent to the synchronous bus subcircuit from a recessive level state to a dominant level state in response to the first logic level signal, so that the synchronous bus level in the synchronous bus subcircuit is adjusted from a low level to a high level; each other energy storage conversion circuit performs carrier synchronous adjustment on its second carrier signal in response to the rising edge of the synchronous bus level.

[0011] Among them, in response to the negative zero crossing of the first power frequency voltage phase of the first power supply output signal, the power frequency synchronous adjustment of the second power supply output signal of each other energy storage conversion circuit includes: the signal processing subcircuit sends a second logic level signal to the bus transceiver subcircuit in response to the negative zero crossing of the first power frequency voltage phase of the first power supply output signal; the bus transceiver subcircuit adjusts the differential output signal from a dominant level state to a recessive level state in response to the second logic level signal, so that the synchronous bus level is adjusted from a high level to a low level; each other energy storage conversion circuit is used to perform power frequency synchronous adjustment on its second power supply output signal in response to the falling edge of the synchronous bus level.

[0012] Among them, the number of synchronous control circuits is at least two, and they are respectively arranged in each energy storage conversion circuit. Before the step of the signal processing subcircuit sending the first logic level signal to the bus transceiver subcircuit in response to the zero crossing of the first carrier signal, it also includes: each synchronous control circuit detects whether the local machine is the host; if the synchronous control circuit is the host, the signal processing subcircuit in the synchronous control circuit sends the first logic level signal to the bus transceiver subcircuit in response to the zero crossing of the first carrier signal; sends the second logic level signal to the bus transceiver subcircuit in response to the negative zero crossing of the first power supply output signal's first power frequency voltage phase; if the synchronous control circuit is not the host, the signal processing subcircuit in the synchronous control circuit outputs a high impedance state to the bus transceiver subcircuit.

[0013] Among them, before the step of the signal processing subcircuit sending the first logic level signal to the bus transceiver subcircuit in response to the first carrier signal crossing zero, it also includes: the signal processing subcircuit outputs a high-impedance state to the bus transceiver subcircuit, and sets the prohibition of timer interrupt, prohibition of carrier synchronization, prohibition of power frequency synchronization, configuration of external interrupt as falling edge trigger, and enabling external interrupt.

[0014] Among them, the number of synchronous control circuits is at least two, and they are respectively arranged in each energy storage conversion circuit. Before the step of obtaining the first carrier signal and the first power supply output signal in any energy storage conversion circuit, it also includes: each synchronous control circuit detects whether the local machine is the host; obtaining the first carrier signal and the first power supply output signal in any energy storage conversion circuit includes: if the synchronous control circuit is the host, the signal processing subcircuit in the synchronous control circuit obtains the first carrier signal and the first power supply output signal in the corresponding energy storage conversion circuit.

[0015] Among them, the synchronous control method also includes: if the synchronous control circuit is not the host, the signal processing subcircuit in the synchronous control circuit detects whether the external interrupt is triggered by a falling edge; if the external interrupt is triggered by a falling edge, the second carrier signal in the corresponding other energy storage conversion circuit is subjected to carrier synchronization adjustment; the external interrupt is configured to be triggered by a rising edge; if the external interrupt is triggered by a rising edge, the second power supply output signal of the corresponding other energy storage conversion circuit is subjected to industrial frequency synchronization adjustment; and the external interrupt is configured to be triggered by a falling edge.

[0016] To solve the above technical problems, another technical solution adopted by the present application is to provide a synchronous control circuit, wherein the synchronous control circuit is coupled to at least two energy storage conversion circuits, wherein the DC side of each energy storage conversion circuit is used to couple with a DC power supply, and the AC sides of each energy storage conversion circuit are connected in parallel to couple with an AC load;

[0017] The synchronous control circuit uses any of the above-mentioned synchronous control methods to achieve synchronous control of at least two energy storage and current conversion circuits.

[0018] In order to solve the above technical problems, another technical solution adopted in this application is: to provide an electronic device, wherein the electronic device includes a shell and a synchronization control circuit connected to the shell; wherein the synchronization control circuit is the synchronization control circuit described above.

[0019] The beneficial effect of the present application is that, different from the prior art, the synchronous control method provided by the present application obtains the first carrier signal and the first power supply output signal of any one of at least two energy storage conversion circuits, so that within each power frequency cycle of the first power supply output signal, when the first carrier signal passes through zero, the second carrier signal in each other energy storage conversion circuit is subjected to carrier synchronous adjustment, and when the first power frequency voltage phase of the first power supply output signal passes through zero in a negative direction, the second power supply output signal of each other energy storage conversion circuit is subjected to power frequency synchronous adjustment, thereby realizing the interconnected signal carrier synchronization mode between each energy storage conversion circuit, effectively improving the carrier synchronization accuracy, and avoiding the problem of relying on voltage sampling to achieve carrier synchronization in the carrier synchronization mode without interconnected signals, which requires high voltage sampling accuracy; and by achieving both carrier synchronization and power frequency synchronization through the same synchronous control circuit, it can also effectively reduce hardware costs and software overheads. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0021] Figure 1 This is a flow chart of the first embodiment of the synchronization control method of the present application;

[0022] Figure 2 It is a structural diagram of the first embodiment of the synchronous control circuit of the present application;

[0023] Figure 3 1 is a waveform diagram of a carrier signal and a counting direction according to an embodiment;

[0024] Figure 4 yes Figure 1 A schematic diagram of a flow chart of an embodiment of S12;

[0025] Figure 5 yes Figure 1 A schematic diagram of a flow chart of an embodiment of S13;

[0026] Figure 6 yes Figure 1 A schematic diagram of a flow chart of another embodiment of S12;

[0027] Figure 7 It is a structural diagram of an embodiment of an energy storage current conversion circuit;

[0028] Figure 8 yes Figure 7 A schematic structural diagram of a second embodiment of a synchronous control circuit in a medium energy storage converter circuit;

[0029] Figure 9 yes Figure 1 A schematic flow chart of another embodiment of S13;

[0030] Figure 10 This is a flow chart of the second embodiment of the synchronization control method of the present application;

[0031] Figure 11 1 is a waveform diagram of a normalized power frequency voltage signal, a carrier signal, and a synchronous bus level according to an embodiment;

[0032] Figure 12 This is a flowchart of the third embodiment of the synchronization control method of the present application;

[0033] Figure 13 It is a structural diagram of an embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0035] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features identified. Therefore, features specified as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional designations (such as up, down, left, right, front, back, etc.) in the embodiments of this application are intended only to illustrate the relative positional relationships and movement of components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional designations will also change accordingly. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to such process, method, product, or apparatus.

[0036] Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] The present application is described in detail below with reference to the accompanying drawings and implementation methods.

[0038] Please refer to Figure 1 and Figure 2 ,in, Figure 1 This is a flow chart of the first embodiment of the synchronous control method of the present application. Figure 2 This is a schematic diagram of the structure of the first embodiment of the synchronous control circuit of the present application. Specifically, it can include the following steps:

[0039] S11: The synchronous control circuit obtains a first carrier signal and a first power supply output signal in any energy storage conversion circuit.

[0040] It is understandable that the synchronization control method in this embodiment is specifically applied to Figure 2 In the synchronous control method of the first energy storage converter circuit 301 shown, the number of the first energy storage converter circuit 301 is at least two, each first energy storage converter circuit 301 is coupled to the first synchronous control circuit 100, the DC side of each first energy storage converter circuit 301 is coupled to a DC power supply 401, and the AC sides of each first energy storage converter circuit 301 are connected in parallel to each other for coupling to the AC load 501; wherein, the first synchronous control circuit 100 adopts the synchronous control method described in any one of the items herein to control the first energy storage converter circuit 301.

[0041] It is worth noting that the first energy storage conversion circuit 301 refers to a circuit that can convert the AC power of the power grid into stable DC power for charging the DC power supply 401, and can also invert the DC power of the DC power supply 401 into AC power, feed it back to the power grid or directly power the AC load 501, so as to realize the mutual conversion between AC power and DC power.

[0042] The DC power supply 401 can specifically be any reasonable DC power supply such as a battery, a DC voltage regulator, a photovoltaic power supply, an energy storage power supply, etc. that has a DC output or is charged using DC. It can also be a power regulation circuit that receives and converts and regulates any reasonable upper power supply such as a battery, a DC voltage regulator, a photovoltaic power supply, an energy storage power supply, etc. to obtain a DC power supply output. This embodiment does not impose any restrictions on this.

[0043] The AC load 501 can specifically be any reasonable AC power source or load such as a power grid, photovoltaic power supply, independent generator, AC motor, etc. that has an AC output or operates using AC. It can also be a power regulation circuit that receives and converts and regulates any reasonable upper power source such as a power grid, photovoltaic power supply, independent generator, etc. to obtain an AC power output. This embodiment does not impose any restrictions on this.

[0044] The first synchronous control circuit 100 may be independent of each first energy storage and power conversion circuit 301 , or may be integrated into any or all first energy storage and power conversion circuits 301 , which is not limited in this application.

[0045] In some embodiments, the first synchronous control circuit 100 may specifically include a control chip, an MCU (MicroController Unit) circuit, a CPU (Central Processing Unit), a single-chip microcomputer, a field programmable gate array, a programmable logic device, a discrete gate or transistor logic device, discrete hardware, and any other reasonable circuit unit with signal processing function, and this application does not limit this.

[0046] For ease of understanding, taking the example of m energy storage conversion circuits, namely energy storage conversion circuit 1, energy storage conversion circuit 2, ..., energy storage conversion circuit m, it can be seen that the AC sides of each energy storage conversion circuit are connected in parallel to each other for coupling with the AC load 501, and the DC sides of energy storage conversion circuit 1, energy storage conversion circuit 2, ..., energy storage conversion circuit m are respectively coupled with DC power supply 1, DC power supply 2, ..., DC power supply m, and energy storage conversion circuit 1, energy storage conversion circuit 2, ..., energy storage conversion circuit m are all connected to the first synchronous control circuit 100.

[0047] Furthermore, the term "coupled" as used herein encompasses both direct and indirect connection methods. Therefore, if a first circuit is described as being coupled to a second circuit, this means that the first circuit may be directly connected to the second circuit via electrical connection, wireless transmission, optical transmission, or other signal connection methods, or may be indirectly connected to the second circuit via other circuits or connection methods.

[0048] Specifically, the first synchronization control circuit 100 samples and obtains the first carrier signal and the first power supply output signal from any one of the at least two first energy storage conversion circuits 301, so as to determine the first carrier signal and the first power supply output signal as the basis for carrier synchronization and power frequency synchronization. The first energy storage conversion circuit 301 can be understood as the host, and the other first energy storage conversion circuits 301 in the at least two first energy storage conversion circuits 301 except the host can be understood as slaves. The second carrier signal and the second power supply output signal in each slave are respectively used as the first carrier signal and the first power supply output signal as the reference targets for carrier synchronization adjustment and power frequency synchronization adjustment.

[0049] The first carrier signal / second carrier signal can be understood as a carrier signal in a PWM (Pulse Width Modulation) technology where each first energy storage converter circuit 301 adjusts the switching state of its internal switching sub-circuit to achieve rectification or inversion.

[0050] The first power supply output signal / second power supply output signal can be understood as the power supply output signal provided by each first energy storage conversion circuit 301 to the DC power supply 401 or the AC load 501, reflecting the actual situation of each first energy storage conversion circuit 301 supplying power to the DC power supply 401 or the AC load 501.

[0051] S12: In each power frequency cycle of the first power supply output signal, when the first carrier signal passes through zero, perform carrier synchronization adjustment on the second carrier signal in each other energy storage conversion circuit.

[0052] The first synchronous control circuit 100 triggers carrier synchronization adjustment when the first carrier signal passes through zero in each power frequency cycle of the first power supply output signal, that is, the second carrier signal in each other first energy storage conversion circuit 301 is adjusted to be synchronized with the first carrier signal.

[0053] Among them, the first synchronous control circuit 100 can specifically adjust the second carrier signal once at any zero crossing point in the first carrier signal within each power frequency cycle, or can adjust the second carrier signal once at any 2, 3 or 4 or any other reasonable number of zero crossing points in the first carrier signal for each interval setting time; and the first synchronous control circuit 100 can also correspond to any 1, 2 or 3 or any other reasonable number of phases in the first power frequency voltage of the first power supply output signal, such as any reasonable phase of 1 / 3π, π or 11π / 6, and adjust the second carrier signal once at the zero crossing point of the nearest first carrier signal; the second carrier signal can specifically be adjusted 1, 2 or 3 times or any other reasonable number of times, and the second carrier signal can be adjusted to be synchronized with the first carrier signal corresponding to any reasonable number of power frequency cycles such as 1, 2 or 3, and this application does not limit this.

[0054] See also Figure 3 , Figure 3 1 is a waveform diagram of a carrier signal and a counting direction according to an embodiment.

[0055] It is understandable that each first energy storage conversion circuit 301 specifically includes a PWM control subcircuit, which includes a PWM counter. The PRD (‌Period Register, counting period value) of the PWM counter can be set and configured to a continuous increase or decrease counting mode. The PWM counter counts up or down by one with the SYSCLK (System Clock‌, system clock, frequency range is 10MHz~500MHz) in the PWM control subcircuit as the beat, increasing from 0 to the counting period value PRD, and then decreasing from the counting period value PRD to 0, repeatedly increasing and decreasing the count, and outputting a counting direction value, where the increasing count is 1 and the decreasing count is 0.

[0056] The carrier signal refers to a waveform of a carrier count value of a PWM counter that changes with time, and the count period values ​​PRD of all parallel-connected first energy storage converter circuits 301 are set to the same value.

[0057] Carrier synchronization means that at the same time, the carrier count values ​​and counting direction values ​​of the PWM counters of different first energy storage converter circuits 301 are the same, that is, the first carrier count value and the first counting direction value of the first carrier signal are the same as the second carrier count value and the second counting direction value of the second carrier signal, respectively.

[0058] S13: When the first power frequency voltage phase of the first power supply output signal crosses zero in a negative direction, perform power frequency synchronous adjustment on the second power supply output signal of each other energy storage conversion circuit.

[0059] Specifically, the first synchronous control circuit 100 triggers the power frequency synchronization adjustment when the first power frequency voltage phase of the first power supply output signal crosses zero in a negative direction within each power frequency cycle of the first power supply output signal, that is, the second power supply output signal in each other first energy storage conversion circuit 301, the slave machine, is adjusted to be synchronized with the first power supply output signal at a position where the phase of the first power supply output signal is 2π.

[0060] Among them, the second power supply output signal can be adjusted by any reasonable number of times, such as 1, 2 or 3 times, that is, the second power supply output signal is adjusted to be synchronized with the first power supply output signal corresponding to any reasonable number of power frequency cycles, such as 1, 2 or 3 times. This application does not limit this.

[0061] It is understandable that the power supply output signal can be understood as a sinusoidal AC voltage signal supplied by each first energy storage converter circuit 301 to the AC load 501, and the expression is:

[0062] U=Um*sinθ (Formula 1); θ=mod[(ωt+φ), 2π] (Formula 2);

[0063] Wherein, Um is the peak value of the sinusoidal AC voltage signal, ω is the angular frequency, t is time, φ is the initial phase, Um and ω of all parallel first energy storage conversion circuits 301 are initialized to fixed values, θ is the power frequency voltage phase, and mod is the remainder function, that is, the power frequency voltage phase θ is the remainder of ωt+φ divided by 2π.

[0064] Power frequency synchronization means that at the same time, the power frequency voltage phases θ of different first energy storage conversion circuits 301 are the same, that is, the first power frequency voltage phase of the first power supply output signal is the same as the second power frequency voltage phase of the second power supply output signal.

[0065] The above scheme, through the first synchronous control circuit 100, implements interconnected signal carrier synchronization between each first energy storage converter circuit 301, effectively improving carrier synchronization accuracy and avoiding the high voltage sampling accuracy requirements of carrier synchronization without interconnected signal carrier synchronization, which relies on voltage sampling. Furthermore, by implementing both carrier synchronization and power frequency synchronization through the same first synchronous control circuit 100, hardware costs and software overhead can be effectively reduced. Carrier synchronization and power frequency synchronization regulation ensure consistency between the multiple first energy storage converter circuits 301, improving the stability and reliability of the entire system. Synchronous operation between each first energy storage converter circuit 301 helps to more evenly distribute the load, avoid overloading or underloading individual converters, and extend equipment life. Carrier synchronization regulation reduces harmonic interference generated between different converters, improves power quality, and protects sensitive equipment. By setting clear synchronization trigger points and regulation mechanisms, the design complexity of the control system is simplified and development costs are reduced. This synchronous control method ensures efficient collaboration between multiple first energy storage conversion circuits 301 through precise carrier synchronization adjustment and industrial frequency synchronization adjustment, thereby improving the overall performance and stability of the system. It is not only suitable for distributed energy systems and microgrid environments, but can also be widely used in various industrial occasions that require high-precision power supply.

[0066] Please continue reading Figure 4 , Figure 4 yes Figure 1 In one embodiment, the synchronous control method of the present application includes, in addition to the above steps S11-S13, further including some more specific steps. Specifically, the above step S12 may further include the following steps:

[0067] S1211: Acquire a second counting period value, a second counting direction value, and a second carrier count value of a second carrier signal in each other energy storage conversion circuit.

[0068] Specifically, the first synchronous control circuit 100 reads the second counting period value, the second counting direction value, and the second carrier counting value of the second carrier signal of each slave at the current moment from each other first energy storage converter circuit 301 .

[0069] S1212: Detect whether each second carrier count value is 0.

[0070] It can be understood that the first synchronization control circuit 100 specifically reads each second carrier count value when the first carrier signal passes through zero, so that when at least some of the second carrier count values ​​are 0, it can be determined that the slave with the second carrier count value of 0 has achieved carrier synchronization with the host, thereby being able to determine the carrier synchronization status of each slave based on the detection of whether each second carrier count value is 0.

[0071] If each second carrier count value is 0, execute S1211; if there is a second carrier count value that is not 0, execute S1213.

[0072] S1213: Detect whether the second counting direction value corresponding to the second carrier count value that is not 0 is 1.

[0073] When the first synchronization control circuit 100 determines that the second carrier count value is not 0, it needs to further determine whether the second carrier count value that is not 0 is currently counting up or counting down, so as to detect whether the second counting direction value corresponding to the second carrier count value that is not 0 is 1.

[0074] If the second counting direction value corresponding to the second carrier count value that is not 0 is 1, S1214 is executed; if the second counting direction value corresponding to the second carrier count value that is not 0 is 1, S1215 is executed.

[0075] S1214: Increase the corresponding second counting period value by the first set value.

[0076] It can be understood that when it is determined that the second counting direction value corresponding to the second carrier count value that is not 0 is 1, the corresponding second carrier count value is an incremental count. In order to make the second carrier count value the same as the first carrier count value faster, the second counting cycle value can be increased by the first set value, so that the second carrier count value takes longer to reach the second counting cycle value than the first carrier count value, so that the second carrier count value can be gradually adjusted to the same as the first carrier count value by any reasonable number of times such as 1, 2 or 3 times to achieve carrier synchronization.

[0077] S1215: Decrease the corresponding second counting period value by the first set value.

[0078] Similarly, when it is determined that the second counting direction value corresponding to the second carrier count value that is not 0 is 0, the corresponding second carrier count value is a decrement count. In order to make the second carrier count value the same as the first carrier count value faster, the second counting cycle value can be reduced by the first set value, so that the second carrier count value takes a shorter time to reach the second counting cycle value than the first carrier count value, so that the second carrier count value can be gradually adjusted to the same as the first carrier count value by any reasonable number of times such as 1, 2 or 3 times to achieve carrier synchronization.

[0079] In some embodiments, the first setting value can be any reasonable value such as 1, 2 or 3, so as to achieve carrier synchronization as quickly as possible while effectively adjusting the second carrier count value to the same as the first carrier count value. This application does not limit this.

[0080] See also Figure 5 , Figure 5 yes Figure 1 In one embodiment, the synchronous control method of the present application includes not only the above steps S11 to S13, but also some more specific steps. Specifically, the above step S13 may further include the following steps:

[0081] S1311: Obtain a second power frequency voltage phase of a second power supply output signal in each other energy storage conversion circuit.

[0082] Specifically, the first synchronous control circuit 100 obtains the second power supply output signal from each other first energy storage converter circuit 301 , ie, each slave, to read the second power frequency voltage phase of the second power supply output signal of each slave at the current moment.

[0083] S1312: Detect whether each second power frequency voltage phase is 0.

[0084] It can be understood that the first synchronization control circuit 100 specifically reads each second power frequency voltage phase when the first power supply output signal's first power frequency voltage phase passes through zero in a negative direction, so that when at least part of the second power frequency voltage phase is 0, it can be determined that the slave machine with the second power frequency voltage phase of 0 has achieved carrier synchronization with the host machine, thereby being able to determine the power frequency synchronization status of each slave machine based on the detection of whether each second power frequency voltage phase is 0.

[0085] If each second power frequency voltage phase is 0, execute S1311; if there is a second power frequency voltage phase that is not 0, execute S1313.

[0086] S1313: Detect whether the second power frequency voltage phase that is not 0 is less than π.

[0087] When the first synchronous control circuit 100 determines that the second power frequency voltage phase is not 0, it needs to further determine whether the non-zero second power frequency voltage phase is less than π to determine whether to adopt phase increasing adjustment or phase decreasing adjustment.

[0088] If the second power frequency voltage phase is not zero and is less than π, then S1314 is executed; if the second power frequency voltage phase is not zero and is not less than π, then S1315 is executed.

[0089] S1314: Reduce the second angular frequency of the corresponding second power supply output signal by a second set value.

[0090] It can be understood that when it is determined that the second power frequency voltage phase that is not zero is less than π, in order to make the corresponding second power frequency voltage phase become the same as the first power frequency voltage phase more quickly, the second angular frequency of the second power supply output signal can be reduced by a second set value, so that the second power frequency voltage phase takes a shorter time to reach 0 or 2π than the first power frequency voltage phase, so that the second power frequency voltage phase can be gradually adjusted to be the same as the first power frequency voltage phase by any reasonable number of times such as 1, 2 or 3 times to achieve power frequency synchronization.

[0091] S1315: Increase the second angular frequency of the corresponding second power supply output signal by a second set value.

[0092] Similarly, when it is determined that the second power frequency voltage phase that is not 0 is not less than π, in order to make the corresponding second power frequency voltage phase become the same as the first power frequency voltage phase more quickly, the second angular frequency of the second power supply output signal can be increased by a second set value, so that the second power frequency voltage phase takes a faster time to reach 0 or 2π than the first power frequency voltage phase, so that the second power frequency voltage phase can be gradually adjusted to be the same as the first power frequency voltage phase by any reasonable number of times such as 1, 2 or 3 times to achieve power frequency synchronization.

[0093] See also Figure 6 , Figure 6 yes Figure 1 Flowchart of another embodiment of S12. In one embodiment, the synchronization control method of the present application includes, in addition to the above S11-S13, further includes some more specific steps. Specifically, the above S12 may further include the following steps:

[0094] S1221: The signal processing sub-circuit sends a first logic level signal to the bus transceiver sub-circuit in response to the first carrier signal crossing zero.

[0095] Please refer to Figure 7 and Figure 8 ,in, Figure 7 It is a structural diagram of an embodiment of an energy storage current conversion circuit. Figure 8 yes Figure 7 A structural diagram of the second embodiment of the synchronous control circuit in the energy storage conversion circuit.

[0096] In one embodiment, the second synchronous control circuit 200 specifically includes a signal processing sub-circuit 201 and a bus transceiver sub-circuit 202. The signal processing sub-circuit 201 is coupled to each second energy storage conversion circuit 302 and the bus transceiver sub-circuit 202. The bus transceiver sub-circuit 202 is used to couple with the synchronous bus sub-circuit 601. The synchronous bus sub-circuit 601 is coupled to each second energy storage conversion circuit 302.

[0097] In some embodiments, the signal processing sub-circuit 201 can specifically be any reasonable circuit such as a single-chip microcomputer with an I / O port, a timer and an external interrupt function, a DSP (Digital Signal Processing) chip, an ARM (a processor chip based on a reduced instruction set computer architecture), etc., and this application does not limit this.

[0098] For ease of understanding, taking the second energy storage conversion circuits 302 as an example, in which there are specifically m second energy storage conversion circuits 302, namely second energy storage conversion circuit 1, second energy storage conversion circuit 2, ..., second energy storage conversion circuit m, it can be seen that the external interfaces of each second energy storage conversion circuit 302 include an AC side interface, N represents the neutral line, L is a unified representation of single-phase and three-phase systems, L represents the live line in a single-phase system, and is a simplified representation of the three phase lines in a three-phase system); a DC side interface, + represents the positive pole, and - represents the negative pole; a synchronous bus interface, the first synchronous bus Sync_H represents the bus high, and the second synchronous bus Sync_L represents the bus low. The DC side interface of each second energy storage converter circuit 302 is respectively connected to a DC power source 401. For example, the DC side interfaces of the second energy storage converter circuit 1, the second energy storage converter circuit 2, ..., and the second energy storage converter circuit m are respectively connected to the DC power sources Dt1, Dt2, ..., and Dtm. The L lines and N lines of the AC side interfaces of each second energy storage converter circuit 302 are connected in parallel to respectively connect to the AC load 501, i.e., the opposite ends of the AC load Rs. The first synchronous bus Sync_H and the second synchronous bus Sync_L of each second energy storage converter circuit 302 are connected in parallel to respectively connect to the opposite ends of a synchronous resistor Rt connected in parallel at the beginning and end of the synchronous bus sub-circuit 601. The resistance of the synchronous resistor Rt is typically 120Ω.

[0099] Among them, the first synchronous bus Sync_H and the second synchronous bus Sync_L of each second energy storage conversion circuit 302 are connected in parallel to respectively connect to the first differential bus interface CAN_H and the second differential bus interface CAN_L of the bus transceiver sub-circuit 202. The receiving interface RX (Receive) signal interface of the bus transceiver sub-circuit 202 is connected to the external interrupt signal input port XINT of the signal processing sub-circuit 201, and the transmitting interface TX (Transmit) signal interface of the bus transceiver sub-circuit 202 is connected to the synchronous signal transmission IO (Input / Output Port, data exchange interface) port of the signal processing sub-circuit 201.

[0100] The bus transceiver sub-circuit 202 is used to convert the logic level signal input by the transmitting interface TX into a differential level signal output between the first differential bus interface CAN_H and the second differential bus interface CAN_L, and at the same time convert the differential level signal received between the first differential bus interface CAN_H and the second differential bus interface CAN_L into a logic level signal output by the receiving interface RX.

[0101] Among them, the level conversion correspondence is: the logic level high level corresponds to the differential recessive state, and the logic level low level corresponds to the differential dominant state. When the transmit interface TX input is in a high-impedance state and there is no input signal between the first differential bus interface CAN_H and the second differential bus interface CAN_L, the output between the first differential bus interface CAN_H and the second differential bus interface CAN_L is a recessive state.

[0102] Note: The dominant state is a state in which the differential voltage between the first differential bus interface CAN_H and the second differential bus interface CAN_L is 2V, and the recessive state is a state in which the differential voltage between the first differential bus interface CAN_H and the second differential bus interface CAN_L is 0V. Of course, in other embodiments, the dominant state may be any reasonable relatively high-level state such as 3V or 5V, and the recessive state may be any reasonable relatively low-level state such as 0.5V or 1V, and this application does not limit this.

[0103] In some embodiments, the second synchronous control circuit 200 can be specifically independent of each second energy storage conversion circuit 302, or it can be integrated into each second energy storage conversion circuit 302, and when the second synchronous control circuit 200 is integrated into each second energy storage conversion circuit 302, the signal processing sub-circuit 201 in the second synchronous control circuit 200 corresponding to the host can remove the external interrupt signal input port XINT, and the corresponding bus transceiver sub-circuit 202 can remove the receiving interface RX signal interface, and the signal processing sub-circuit 201 in each second synchronous control circuit 200 corresponding to the slave can remove the synchronous signal sending IO port, and the corresponding bus transceiver sub-circuit 202 can remove the sending interface TX signal interface, so as to save interface overhead and reduce hardware cost; of course, each second synchronous control circuit 200 can also be the same, and all are as follows Figure 8 The circuit shown, that is, retains various signal interfaces, which is not limited in this application.

[0104] Specifically, the signal processing subcircuit 201 detects the zero crossing point of the first carrier signal in each power frequency cycle of the first power supply output signal, and sends the first logic level signal to the bus transceiver subcircuit 202 in response to the zero crossing point of the first carrier signal.

[0105] S1222: The bus transceiver sub-circuit adjusts the differential output signal sent to the synchronous bus sub-circuit from a recessive level state to a dominant level state in response to the first logic level signal, so that the synchronous bus level in the synchronous bus sub-circuit is adjusted from a low level to a high level.

[0106] The bus transceiver sub-circuit 202 is used to receive the first logic level signal sent by the signal processing sub-circuit 201, and in response to the first logic level signal, adjust the differential output signal sent to the synchronization bus sub-circuit 601 from a recessive level state to a dominant level state, that is, to increase the level state of the differential level signal between the first differential bus interface CAN_H and the second differential bus interface CAN_L, so that the synchronization bus level in the synchronization bus sub-circuit 601, that is, the voltage signal across the synchronization resistor Rt, is adjusted from a low level to a high level.

[0107] S1223: Each other energy storage conversion circuit performs carrier synchronization adjustment on its second carrier signal in response to the rising edge of the synchronous bus level.

[0108] Among them, each other second energy storage conversion circuit 302, that is, the slave is used to receive the synchronous bus level on the synchronous bus sub-circuit 601, and respond to the rising edge of the synchronous bus level, that is, to perform carrier synchronization adjustment on its second carrier signal from a low level to a high level, so that the second carrier signal is the same as the first carrier signal in the host.

[0109] See also Figure 9 , Figure 9 yes Figure 1 Flowchart of another embodiment of S13 in FIG. In one embodiment, the synchronization control method of the present application includes, in addition to the above S11-S13, further including some more specific steps. Specifically, the above S13 may further include the following steps:

[0110] S1321: The signal processing sub-circuit sends a second logic level signal to the bus transceiver sub-circuit in response to the first power frequency voltage phase of the first power supply output signal crossing zero in a negative direction.

[0111] It can be understood that the signal processing sub-circuit 201 detects the negative zero-crossing point of the first power frequency voltage phase of the first power supply output signal in each power frequency cycle of the first power supply output signal, that is, performs phase detection on the first power frequency voltage, and sends a second logic level signal to the bus transceiver sub-circuit 202 in response to the first power frequency voltage phase being 0 or 2π.

[0112] S1322: The bus transceiver sub-circuit adjusts the differential output signal from a dominant level state to a recessive level state in response to the second logic level signal, so as to adjust the synchronous bus level from a high level to a low level.

[0113] The bus transceiver sub-circuit 202 is used to receive the second logic level signal sent by the signal processing sub-circuit 201, and in response to the second logic level signal, adjust the differential output signal sent to the synchronization bus sub-circuit 601 from a dominant level state to a recessive level state, that is, lower the level state of the differential level signal between the first differential bus interface CAN_H and the second differential bus interface CAN_L, so that the synchronization bus level in the synchronization bus sub-circuit 601, that is, the voltage signal across the synchronization resistor Rt, is adjusted from a high level to a low level.

[0114] S1323: Each other energy storage and current conversion circuit is configured to perform power frequency synchronous regulation on its second power supply output signal in response to a falling edge of the synchronous bus level.

[0115] Among them, each other second energy storage conversion circuit 302, that is, the slave is used to receive the synchronous bus level on the synchronous bus sub-circuit 601, and respond to the rising edge of the synchronous bus level, that is, to adjust its second carrier signal from a high level to a low level in industrial frequency synchronization, so that the second power supply output signal is the same as the first power supply output signal in the host.

[0116] See also Figure 10 and Figure 11 ,in, Figure 10 This is a flow chart of the second embodiment of the synchronous control method of the present application. The synchronous control method of this embodiment is Figure 1 A flowchart of a detailed implementation of the synchronous control method in FIG. 1 specifically includes the following steps:

[0117] S21: The synchronous control circuit obtains a first carrier signal and a first power supply output signal in any energy storage conversion circuit.

[0118] Among them, S21 and Figure 1 For details, please refer to S11 and its related text descriptions, which will not be repeated here.

[0119] S22: Detect whether the first power frequency voltage phase is greater than the first voltage phase.

[0120] Specifically, the synchronous control circuit 200 performs phase detection on the first power frequency voltage of the first power supply output signal to determine whether the phase of the first power frequency voltage is greater than the first voltage phase.

[0121] If the first power frequency voltage phase is greater than the first voltage phase, S23 is executed; if the first power frequency voltage phase is not greater than the first voltage phase, S21 is executed.

[0122] S23: Obtain a first time difference value using the system clock and the first counting period value, the first counting direction value, and the first carrier count value of the first carrier signal.

[0123] The second synchronization control circuit 200 reads the current phase value θ of the first power frequency voltage. When θ exceeds the first voltage phase, it reads the first count period value, first count direction value, and first carrier count value of the first carrier signal at the current moment. The first count direction value defines an intermediate variable k, with k set to 1 when the carrier counts up and k = 0 when the carrier counts down. The system clock is used to calculate the first time difference ΔTc between the current moment and the next zero-crossing moment of the first carrier count value. This first time difference ΔTc is written into a timer period, and the timer period interrupt is enabled. In the timer interrupt service function, the synchronous bus level is manipulated from recessive to dominant.

[0124] △Tc=[PRD1*(k1+1)-CNT1] / SYSCLK (Equation 3); where PRD1 is the first counting period value, k1 is the first counting direction value, CNT1 is the first carrier count value, and SYSCLK is the system clock.

[0125] S24: Delay the first time difference to perform carrier synchronization adjustment on the second carrier signal in each other energy storage conversion circuit.

[0126] The second synchronization control circuit 200 operates the synchronization bus level from implicit to explicit in the timer interrupt service function, that is, delays the first time difference to perform carrier synchronization adjustment on the second carrier signal in each other second energy storage conversion circuit 302, so that the second carrier signal is gradually close to or the same as the first carrier signal.

[0127] S25: Detect whether the first power frequency voltage phase is greater than the second voltage phase.

[0128] The synchronous control circuit performs phase detection on the first power frequency voltage of the first power supply output signal in real time to determine whether the phase of the first power frequency voltage is greater than the phase of the second voltage.

[0129] The second voltage phase is greater than the first voltage phase.

[0130] If the first power frequency voltage phase is greater than the second voltage phase, S26 is executed; if the first power frequency voltage phase is not greater than the second voltage phase, S21 is executed.

[0131] S26: Obtain a second time difference using the first power frequency voltage phase and the first angular frequency of the first power supply output signal.

[0132] The second synchronous control circuit 200 reads the phase value θ of the first power frequency voltage at the current moment. When the first power frequency voltage phase θ exceeds the second voltage phase, it calculates the time difference △Tm between the current moment and the moment when the first power frequency voltage phase reaches 2π, writes △Tm into the timer cycle and enables the timer cycle interrupt, and operates the synchronous bus level from dominant to recessive in the timer interrupt service function.

[0133] △Tm=(2π-θ1) / ω1 (Equation 4); where θ1 is the first power frequency voltage phase, and ω1 is the first angular frequency.

[0134] See also Figure 11 , Figure 11 1 is a waveform diagram of a normalized power frequency voltage signal, a carrier signal, and a synchronous bus level according to an embodiment.

[0135] Among them, the power frequency voltage signal is a sine wave with a frequency range of 45Hz~65Hz, and the carrier signal is a triangle wave with a frequency range of 1kHz~100kHz.

[0136] The second synchronization control circuit 200 sends a carrier synchronization signal and an industrial frequency synchronization signal to the synchronous bus sub-circuit 601 in sequence within one industrial frequency cycle. Considering that in some application scenarios, the bus transceiver sub-circuit 202 has a dominant level timeout protection function, the differential level signal between the first differential bus interface CAN_H and the second differential bus interface CAN_L cannot output a dominant level for a long time, that is, the synchronous bus level cannot maintain a high level for a long time, such as the time length for which the synchronous bus level maintains a high level does not exceed any reasonable time length such as 270us, 300us or 320us, and is preferably 300us. This application does not limit this.

[0137] Correspondingly, the difference between the second voltage phase and the first voltage phase needs to correspond to the time interval between the rising edge and the falling edge of the synchronous bus level. When the synchronous bus level cannot maintain a high level for more than 300us, the difference between the second voltage phase and the first voltage phase also needs to be no greater than 2π*(20-0.3) / 20=1.97π, thereby effectively expanding the application range of the second synchronous control circuit 200.

[0138] In some embodiments, the first voltage phase can be any reasonable phase value such as 11π / 6 or 11π / 7, and the second voltage phase corresponds to any reasonable phase value such as 23π / 12 or 23π / 13, which is not limited in this application.

[0139] S27: Delay the second time difference to perform power frequency synchronous adjustment on the second power supply output signal of each other energy storage conversion circuit.

[0140] The second synchronization control circuit 200 operates the synchronization bus level from dominant to recessive in the timer interrupt service function, that is, delays the second time difference to perform power frequency synchronization adjustment on the second power supply output signal in each other second energy storage conversion circuit 302, so that the second power supply output signal is gradually close to or the same as the first power supply output signal.

[0141] Furthermore, in one embodiment, the above S24 can be specifically replaced by: delaying the first time difference to send a carrier synchronization signal to each other second energy storage converter circuit 302, that is, a carrier synchronization trigger signal, such as a rising edge level change, so that each other second energy storage converter circuit 302 performs carrier synchronization adjustment on its second carrier signal, that is, the carrier synchronization adjustment is performed by each other second energy storage converter circuit 302, rather than by the second synchronization control circuit 200.

[0142] Furthermore, in one embodiment, the above S27 can be specifically replaced by: delaying the second time difference to send an industrial frequency synchronization signal to each other second energy storage converter circuit 302, that is, a trigger signal for industrial frequency synchronization, such as a falling edge level change, so that each other second energy storage converter circuit 302 performs industrial frequency synchronization adjustment on its second power supply output signal, that is, the industrial frequency synchronization adjustment is performed by each other second energy storage converter circuit 302, rather than by the second synchronization control circuit 200.

[0143] See also Figure 12 , Figure 12 This is a flow chart of the third embodiment of the synchronous control method of the present application. The synchronous control method of this embodiment is Figure 1 A flowchart of a detailed implementation of the synchronous control method in FIG. 1 specifically includes the following steps:

[0144] S31: Each synchronous control circuit detects whether the local unit is the host unit.

[0145] It is understandable that the number of the second synchronous control circuit 200 is at least two, and specifically, they can be respectively provided in each second energy storage conversion circuit 302, and each second synchronous control circuit 200 and each second energy storage conversion circuit 302 are respectively as follows: Figure 8 and Figure 7 In order to distinguish the different execution control methods of carrier synchronization and power frequency synchronization of each second synchronous control circuit 200 corresponding to each second energy storage conversion circuit 302, any one of the second synchronous control circuits 200 can be set as the master, and the other second synchronous control circuits 200 can be slaves. Alternatively, each second synchronous control circuit 200 can determine whether to be the master or slave according to certain logical rules, so that one second synchronous control circuit 200 is the master in the parallel system and the other second synchronous control circuits 200 are slaves. This application does not limit this.

[0146] Specifically, each second synchronization control circuit 200 detects whether the local device is the master.

[0147] If the second synchronous control circuit 200 is the host, S32 is executed; if the second synchronous control circuit 200 is not the host, S37 is executed.

[0148] S32: The signal processing subcircuit in the synchronous control circuit obtains the first carrier signal and the first power supply output signal in the corresponding energy storage conversion circuit.

[0149] It is understandable that when the second synchronous control circuit 200 is the host, its signal processing subcircuit 201 will obtain the corresponding second energy storage conversion circuit 302, that is, the first carrier signal and the first power supply output signal in the second energy storage conversion circuit 302 connected thereto.

[0150] S33: The signal processing sub-circuit in the synchronous control circuit sends a first logic level signal to the bus transceiver sub-circuit in response to the first carrier signal crossing zero.

[0151] The signal processing subcircuit 201 in the second synchronous control circuit 200 detects the zero crossing point of the first carrier signal in each power frequency cycle of the first power supply output signal, and sends a first logic level signal to the bus transceiver subcircuit 202 in response to the zero crossing point of the first carrier signal.

[0152] S34: The bus transceiver sub-circuit adjusts the differential output signal sent to the synchronous bus sub-circuit from a recessive level state to a dominant level state in response to the first logic level signal, so that the synchronous bus level in the synchronous bus sub-circuit is adjusted from a low level to a high level.

[0153] The bus transceiver sub-circuit 202 is used to receive the first logic level signal sent by the signal processing sub-circuit 201, and in response to the first logic level signal, adjust the differential output signal sent to the synchronization bus sub-circuit 601 from a recessive level state to a dominant level state, that is, to increase the level state of the differential level signal between the first differential bus interface CAN_H and the second differential bus interface CAN_L, so that the synchronization bus level in the synchronization bus sub-circuit 601, that is, the voltage signal across the synchronization resistor Rt, is adjusted from a low level to a high level.

[0154] S35: Sending a second logic level signal to the bus transceiver sub-circuit in response to the first power frequency voltage phase of the first power supply output signal crossing zero in a negative direction.

[0155] The signal processing sub-circuit 201 detects the negative zero-crossing point of the first power frequency voltage phase of the first power supply output signal in each power frequency cycle of the first power supply output signal, that is, performs phase detection on the first power frequency voltage, and sends a second logic level signal to the bus transceiver sub-circuit 202 in response to the first power frequency voltage phase being 0 or 2π.

[0156] S36: The bus transceiver sub-circuit adjusts the differential output signal from a dominant level state to a recessive level state in response to the second logic level signal, so as to adjust the synchronous bus level from a high level to a low level.

[0157] The bus transceiver sub-circuit 202 is used to receive the second logic level signal sent by the signal processing sub-circuit 201, and in response to the second logic level signal, adjust the differential output signal sent to the synchronization bus sub-circuit 601 from a dominant level state to a recessive level state, that is, lower the level state of the differential level signal between the first differential bus interface CAN_H and the second differential bus interface CAN_L, so that the synchronization bus level in the synchronization bus sub-circuit 601, that is, the voltage signal across the synchronization resistor Rt, is adjusted from a high level to a low level.

[0158] S37: The signal processing sub-circuit in the synchronous control circuit detects whether the external interrupt is triggered by a falling edge.

[0159] It is understandable that when the second synchronous control circuit 200 is a slave, its signal processing sub-circuit 201 will detect whether the external interrupt is triggered by a falling edge.

[0160] If the external interrupt of the signal processing subcircuit 201 in the second synchronous control circuit 200 is triggered by a falling edge, S38 is executed; if the external interrupt of the signal processing subcircuit 201 in the second synchronous control circuit 200 is not triggered by a falling edge, S310 is executed.

[0161] S38: Perform carrier synchronization adjustment on the second carrier signal in the corresponding other energy storage conversion circuit.

[0162] It can be understood that when the signal processing sub-circuit 201 detects that the external interrupt is triggered by a falling edge, that is, when the signal processing sub-circuit 201 detects that the synchronous bus level is adjusted from a high level to a low level, the second carrier signal in the corresponding second energy storage conversion circuit 302 is subjected to carrier synchronization adjustment so that the second carrier signal is gradually close to or the same as the first carrier signal.

[0163] S39: Configure external interrupt as rising edge triggered.

[0164] The signal processing sub-circuit 201 configures the external interrupt as rising edge trigger, waiting to respond to the rising edge trigger, that is, when the synchronous bus level is adjusted from a low level to a high level, the second power supply output signal in the corresponding other second energy storage conversion circuit 302 is synchronously adjusted at the industrial frequency.

[0165] S310: Perform power frequency synchronous regulation on the second power supply output signals of the corresponding other energy storage conversion circuits.

[0166] It can be understood that when the signal processing sub-circuit 201 detects that the external interrupt is triggered by a rising edge, that is, when the signal processing sub-circuit 201 detects that the synchronous bus level is adjusted from a low level to a high level, the second power supply output signal in the corresponding other second energy storage conversion circuit 302 is adjusted synchronously with the industrial frequency, so that the second power supply output signal and the first power supply output signal are gradually close to or the same.

[0167] S311: Configure the external interrupt to be triggered by the falling edge.

[0168] The signal processing sub-circuit 201 configures the external interrupt as falling edge triggered, waiting to respond to the falling edge trigger, that is, when the synchronous bus level is adjusted from a high level to a low level, to perform carrier synchronization adjustment on the second carrier signal in the corresponding other second energy storage conversion circuit 302.

[0169] Furthermore, in one embodiment, in the above S311 , it specifically includes: the signal processing sub-circuit 201 in the second synchronization control circuit 200 outputs a high impedance state to the bus transceiver sub-circuit 202 .

[0170] It is understandable that when the second synchronization control circuit 200 is the host, in order to avoid external signals interfering with its signal processing sub-circuit 201, the signal processing sub-circuit 201 can output a high-impedance state to its bus transceiver sub-circuit 202 to prohibit receiving signals from the bus transceiver sub-circuit 202, so as to ensure the stability of carrier synchronization and power frequency synchronization.

[0171] Furthermore, in one embodiment, before the above-mentioned S31, it specifically includes: the signal processing sub-circuit 201 in each second synchronization control circuit 200 outputs a high-impedance state to its bus transceiver sub-circuit 202, and sets the prohibition of timer interrupt, prohibition of carrier synchronization, prohibition of power frequency synchronization, configuration of external interrupt as falling edge trigger, and enablement of external interrupt, that is, power-on initialization is performed to eliminate the adverse effects of the last executed carrier synchronization and power frequency synchronization on this time.

[0172] This application also provides an electronic device, see Figure 13 , Figure 131 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 40 includes a housing 41 and a third synchronization control circuit 42 connected to the housing 41 .

[0173] It should be noted that the third synchronous control circuit 42 described in this embodiment is the first synchronous control circuit 100 or the second synchronous control circuit 200 described in any one of the above embodiments. Figures 1-12 And the related text content will not be repeated here.

[0174] The beneficial effect of the present application is that, different from the prior art, the synchronous control method provided by the present application obtains the first carrier signal and the first power supply output signal of any one of at least two energy storage conversion circuits, so that within each power frequency cycle of the first power supply output signal, when the first carrier signal passes through zero, the second carrier signal in each other energy storage conversion circuit is subjected to carrier synchronous adjustment, and when the first power frequency voltage phase of the first power supply output signal passes through zero in a negative direction, the second power supply output signal of each other energy storage conversion circuit is subjected to power frequency synchronous adjustment, thereby realizing the interconnected signal carrier synchronization mode between each energy storage conversion circuit, effectively improving the carrier synchronization accuracy, and avoiding the problem of relying on voltage sampling to achieve carrier synchronization in the carrier synchronization mode without interconnected signals, which requires high voltage sampling accuracy; and by achieving both carrier synchronization and power frequency synchronization through the same synchronous control circuit, it can also effectively reduce hardware costs and software overheads.

[0175] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A synchronous control method, applied to the synchronous control of an energy storage converter circuit, wherein the number of the energy storage converter circuits is at least two, each of the energy storage converter circuits is coupled to a synchronous control circuit, the DC side of each energy storage converter circuit is used to couple to a DC power supply, and the AC sides of each energy storage converter circuit are connected in parallel to couple to an AC load, characterized in that: The synchronization control method comprises: The synchronous control circuit obtains the first carrier signal and the first power supply output signal in any one of the energy storage and current conversion circuits; In each power frequency cycle of the first power supply output signal, when the first carrier signal passes through zero, carrier synchronization adjustment is performed on the second carrier signal in each other energy storage conversion circuit; wherein, when the first carrier signal passes through zero, carrier synchronization adjustment is performed on the second carrier signal in each other energy storage conversion circuit, including: detecting whether the first power frequency voltage phase is greater than the first voltage phase; if the first power frequency voltage phase is greater than the first voltage phase, obtaining a first time difference by using the system clock and the first counting cycle value, the first counting direction value and the first carrier count value of the first carrier signal; delaying the first time difference to perform carrier synchronization adjustment on the second carrier signal in each of the other energy storage conversion circuits; or, delaying the first time difference to send a carrier synchronization signal to each of the other energy storage conversion circuits, so that each of the other energy storage conversion circuits performs carrier synchronization adjustment on its second carrier signal; When the first power frequency voltage phase of the first power supply output signal passes through zero in a negative direction, power frequency synchronous adjustment is performed on the second power supply output signal of each of the other energy storage conversion circuits.

2. The synchronous control method according to claim 1, characterized in that: When the first power frequency voltage phase of the first power supply output signal passes through zero in a negative direction, performing power frequency synchronous adjustment on the second power supply output signal of each of the other energy storage conversion circuits includes: Detecting whether the first power frequency voltage phase is greater than the second voltage phase; wherein the second voltage phase is greater than the first voltage phase; If the first power frequency voltage phase is greater than the second voltage phase, obtaining a second time difference using the first power frequency voltage phase and the first angular frequency of the first power supply output signal; Delay the second time difference to perform industrial frequency synchronous adjustment on the second power supply output signal of each of the other energy storage conversion circuits; or, delay the second time difference to send an industrial frequency synchronization signal to each of the other energy storage conversion circuits, so that each of the other energy storage conversion circuits performs industrial frequency synchronous adjustment on its second power supply output signal.

3. The synchronous control method according to claim 1, characterized in that: The performing carrier synchronization adjustment on the second carrier signal in each other energy storage conversion circuit includes: Obtaining a second counting period value, a second counting direction value, and a second carrier count value of a second carrier signal in each of the other energy storage conversion circuits; detecting whether each second carrier count value is 0; If the second carrier count value is not 0, detecting whether the second counting direction value corresponding to the second carrier count value that is not 0 is 1; If the second counting direction value corresponding to the second carrier count value that is not 0 is 1, the corresponding second counting period value is increased by a first set value; If the second counting direction value corresponding to the second carrier count value that is not 0 is not 1, the corresponding second counting period value is reduced by the first set value.

4. The synchronous control method according to claim 1, characterized in that: The performing power frequency synchronous adjustment on the second power supply output signal of each of the other energy storage conversion circuits includes: Obtaining a second power frequency voltage phase of a second power supply output signal in each of the other energy storage conversion circuits; Detecting whether the phase of each of the second power frequency voltages is 0; If the second power frequency voltage phase is not 0, detecting whether the second power frequency voltage phase that is not 0 is less than π; If the second power frequency voltage phase which is not zero is less than π, reducing the second angular frequency of the corresponding second power supply output signal by a second set value; If the second power frequency voltage phase which is not zero is not less than π, the second angular frequency of the corresponding second power supply output signal is increased by the second set value.

5. The synchronous control method according to claim 1, characterized in that: The synchronous control circuit includes a signal processing subcircuit and a bus transceiver subcircuit, the signal processing subcircuit is coupled to each of the energy storage converter circuits and the bus transceiver subcircuit, the bus transceiver subcircuit is used to couple to a synchronous bus subcircuit, and the synchronous bus subcircuit is coupled to each of the energy storage converter circuits. When the first carrier signal passes through zero, performing carrier synchronization adjustment on the second carrier signal in each other energy storage converter circuit includes: The signal processing subcircuit sends a first logic level signal to the bus transceiver subcircuit in response to the first carrier signal crossing zero; The bus transceiver sub-circuit adjusts the differential output signal sent to the synchronous bus sub-circuit from a recessive level state to a dominant level state in response to the first logic level signal, so that the synchronous bus level in the synchronous bus sub-circuit is adjusted from a low level to a high level; Each of the other energy storage and current conversion circuits performs carrier synchronization adjustment on its second carrier signal in response to the rising edge of the synchronous bus level.

6. The synchronous control method according to claim 5, characterized in that: When the first power frequency voltage phase of the first power supply output signal passes through zero in a negative direction, performing power frequency synchronous adjustment on the second power supply output signal of each of the other energy storage conversion circuits includes: The signal processing subcircuit sends a second logic level signal to the bus transceiver subcircuit in response to the first power frequency voltage phase of the first power supply output signal crossing zero in a negative direction; The bus transceiver sub-circuit adjusts the differential output signal from the dominant level state to the recessive level state in response to the second logic level signal, so that the synchronous bus level is adjusted from the high level to the low level; Each of the other energy storage and current conversion circuits is used to perform power frequency synchronous regulation on its second power supply output signal in response to the falling edge of the synchronous bus level.

7. The synchronous control method according to claim 6, characterized in that: There are at least two synchronous control circuits, and each synchronous control circuit is correspondingly provided in each energy storage conversion circuit. Before the step of the signal processing subcircuit sending the first logic level signal to the bus transceiver subcircuit in response to the first carrier signal crossing zero, the step further includes: Each of the synchronous control circuits detects whether the local device is a host; If the synchronous control circuit is a host, the signal processing subcircuit in the synchronous control circuit sends a first logic level signal to the bus transceiver subcircuit in response to the first carrier signal crossing zero; sending a second logic level signal to the bus transceiver sub-circuit in response to a negative zero crossing of a first power frequency voltage phase of the first power supply output signal; If the synchronous control circuit is not the host, the signal processing subcircuit in the synchronous control circuit outputs a high impedance state to the bus transceiver subcircuit.

8. The synchronous control method according to claim 6, characterized in that: Before the step of the signal processing sub-circuit sending the first logic level signal to the bus transceiver sub-circuit in response to the first carrier signal crossing zero, the method further includes: The signal processing subcircuit outputs a high impedance state to the bus transceiver subcircuit, and sets the timer interrupt to be disabled, the carrier synchronization to be disabled, the power frequency synchronization to be disabled, the external interrupt to be configured as falling edge triggered, and the external interrupt to be enabled.

9. The synchronous control method according to claim 6, characterized in that: There are at least two synchronous control circuits, and each of the synchronous control circuits is correspondingly provided in each of the energy storage conversion circuits. The obtaining of the first carrier signal and the first power supply output signal in any of the energy storage conversion circuits includes: Each of the synchronous control circuits detects whether the local device is a host; The obtaining of the first carrier signal and the first power supply output signal in any one of the energy storage conversion circuits includes: If the synchronous control circuit is a host, the signal processing subcircuit in the synchronous control circuit obtains the first carrier signal and the first power supply output signal in the corresponding energy storage conversion circuit.

10. The synchronous control method according to claim 9, characterized in that: The synchronization control method further includes: If the synchronous control circuit is not the host, the signal processing subcircuit in the synchronous control circuit detects whether the external interrupt is triggered by a falling edge; If the external interrupt is triggered by the falling edge, performing carrier synchronization adjustment on the second carrier signal in the other energy storage conversion circuit corresponding thereto; Configure the external interrupt to be triggered by a rising edge; If the external interrupt is triggered by the rising edge, the second power supply output signal of the other energy storage conversion circuit corresponding thereto is subjected to power frequency synchronous adjustment; Configure the external interrupt to be triggered by a falling edge.

11. A synchronous control circuit, characterized in that: The synchronous control circuit is coupled to at least two of the energy storage conversion circuits, wherein the DC side of each of the energy storage conversion circuits is used to couple with a DC power supply, and the AC sides of each of the energy storage conversion circuits are connected in parallel to couple with an AC load; The synchronous control circuit uses the synchronous control method according to any one of claims 1 to 10 to achieve synchronous control of at least two of the energy storage converter circuits.

12. An electronic device, characterized in that: The electronic device includes a housing and a synchronization control circuit connected to the housing; Wherein, the synchronous control circuit is the synchronous control circuit as claimed in claim 11.

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