A brushless DC motor synchronous rectification speed regulation circuit

Abstract

The application discloses a brushless direct current motor synchronous rectification speed regulation circuit, which comprises a synchronous rectification speed regulation controller, a trapezoidal controller, a gate electrode controller and a bridge driver integrated on the same chip, wherein the synchronous rectification speed regulation controller comprises a synchronous rectification comparator, a rectification time regulator, a dead time insertion module, an interlock protection module, an anti-misjudgment module, a detection signal gating unit, a state machine, a digital-to-analog converter and a dead time generator. The application adopts the built-in synchronous rectification speed regulation controller module to control the current flowing through the motor, the rectification ripple can be adjusted, the dead time affecting the rectification efficiency is optimized, the motor driving efficiency is improved, the speed regulation of the brushless motor can be realized by using simple external devices, and the use threshold is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit and motor control technology, and particularly relates to a high-efficiency brushless DC motor synchronous rectification speed regulation circuit. BACKGROUND

[0002] A DC motor is a device for converting electric energy into mechanical energy by using a DC power supply. As an important type of DC motor, a brushless DC motor is gradually replacing a brush DC motor due to its advantages of quietness, high efficiency, long service life, etc. and has a wide range of applications, such as industrial control, automotive industry, consumer electronics, and many other fields. The operation of a brushless DC motor requires a corresponding motor driving chip. In general, the mainstream electrical structure of a brushless DC motor is a Y-type inductive structure, and a common driver structure is a three-phase bridge driver. The main components of a motor driving chip are a motor controller and a bridge driver. The bridge driver is directly connected to a brushless DC motor to achieve the driving of the motor, and the motor controller is responsible for controlling the bridge driver to achieve electronic commutation and speed control of the brushless motor.

[0003] The motor controller needs to achieve electronic commutation. Since the back electromotive force waveform of a brushless DC motor is trapezoidal, the commonly used commutation method is trapezoidal control. However, basic trapezoidal control can only make the brushless DC motor run normally and cannot achieve speed regulation of the motor. Speed control depends on the number of motor poles and load current, and is generally achieved by changing the motor supply frequency.

[0004] The traditional brushless DC motor speed regulation scheme, such as the document [J. A. Prakosa, D. V. Samokhvalov, G. R. V. Ponce and F. Sh. Al-Mahturi, "Speed Control of Brushless DC Motor for QuadCopter Drone Ground Test," 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), Saint Petersburg and Moscow, Russia, 2019, pp. 644-648] and the document [N. R. Raipure, R. T. Ugale and B. N. Chaudhari, "Solar Powered BLDC Motor Drive for Wide Speed Range Electric Vehicle Application," 2018 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), Chennai, India, 2018, pp. 1-6], the control system structure is as shown in Figure 1 The external programmable device such as MCU is used to realize the trapezoidal control of the motor, and the internal pulse width modulation (PWM) controller is used to control the motor current, and then the speed regulation is realized; the advantage of using external programmable controller is easy to develop and realize, and the PWM controller integrated in these programmable devices is easy to realize speed control. However, it is difficult for the external controller to obtain the working state of the bridge drive, in order to prevent the high and low sides of the bridge drive from being turned on at the same time, a fixed dead time must be inserted at the moment of alternating turn-on of the high and low side power tubes, but this will bring additional efficiency loss; at the same time, the development of external controller needs to have a deep understanding of the brushless DC motor control principle and implementation scheme, and the requirement threshold for users is high. SUMMARY

[0005] In view of the above, the present application provides a high-efficiency brushless DC motor synchronous rectification speed regulation circuit, which adopts a built-in high-efficiency synchronous rectification controller to provide optimal dead time, improve motor drive efficiency, and use simple external devices to realize speed regulation of the brushless motor, thereby reducing the use threshold.

[0006] The application discloses a high-efficiency synchronous rectification speed regulation circuit for a brushless direct current motor, which comprises a synchronous rectification speed regulation controller, a trapezoidal controller, a gate controller and a bridge driver integrated on the same chip.

[0007] The trapezoidal controller provides three-phase switch control signals and three-phase enable signals to the gate controller, and controls the bridge driver to realize six-step trapezoidal control of the brushless direct current motor through the gate controller, and provides the three-phase enable signals to the synchronous rectification speed regulation controller to select the phase to be controlled.

[0008] The synchronous rectification controller obtains three-phase switch state signals of the bridge driver from the chip, provides synchronous rectification control signals to the gate controller, and controls the bridge driver to switch between freewheeling and rectification states through the gate controller to adjust the driving current of the bridge driver.

[0009] The gate controller selects the three-phase switch control signals and the synchronous rectification control signals according to the three-phase enable signals, and thus provides three-phase switch driving signals to the bridge driver.

[0010] The bridge driver amplifies the three-phase switch driving signals to control the on-off of internal power switch devices, and thus drives the brushless direct current motor to realize electronic commutation and speed regulation.

[0011] Further, the synchronous rectification speed regulation controller comprises:

[0012] A detection signal selection unit selects a phase switch state signal from the three-phase switch state signals according to the three-phase enable signals, and the phase switch state signal comprises a high-side transistor state signal HO and a low-side transistor state signal LO of the phase.

[0013] A synchronous rectification comparator collects a direct current feedback voltage of the bridge driver through an external sampling resistor, compares the direct current feedback voltage with a reference voltage, and generates a comparison signal.

[0014] A rectification time regulator outputs a control signal SR_Ctrl with a fixed pulse width when detecting a rising edge of the comparison signal, and the pulse width is adjusted by an external timing capacitor.

[0015] A dead time insertion module detects the rising edge of the control signal SR_Ctrl in two paths and inserts a dead time through delay, and generates a synchronous rectification high-side control signal HI and a synchronous rectification low-side control signal LI.

[0016] A state machine determines the optimal dead time by judging the signals SR_Ctrl, LO, HO, LI and HI, and thus outputs corresponding data signals.

[0017] A digital-to-analog converter is used for converting the data signals into analog levels.

[0018] The dead time generator generates corresponding dead time according to the analog level, and provides the dead time to the dead time insertion module.

[0019] Further, when the trapezoidal controller controls the low-side tube of a certain phase in the bridge driver to be turned on, the trapezoidal controller outputs the enable signal of the phase to be high level, and the detection signal gating unit gates the switch state signal of the phase according to the enable signal.

[0020] Further, the synchronous rectification speed regulation controller further comprises a false judgment prevention module, which is configured to detect the rising edge of the low-side tube state signal LO and generate a fixed time length shielding pulse signal to be provided to the rectification time regulator, so as to shield the rectification time regulator temporarily when the corresponding low-side tube is turned on, and prevent the false work caused by the false judgment of the synchronous rectification comparator.

[0021] Further, the rectification time regulator comprises an RS latch RS1, a three-input AND gate AND4, two-input AND gates AND1-AND3, an OR gate OR1, buffers BUF1 and BUF2, inverters INV1 and INV2, comparators CMP1 and CMP2, PMOS tubes PM1 and PM2, an NMOS tube NM1, and resistors R C , wherein the first input end of AND1 is connected with the comparison signal, the second input end of AND1 and the output end of INV2 and the first input end of AND3 are connected, the input end of INV2 is connected with the shielding pulse signal, the output end of AND1 is connected with the S input end of RS1 and the first input end of AND4, the R input end of RS1 is connected with the third input end of AND4 and the output end of INV1, the Q output end of RS1 is connected with the second input end of AND4, the output end of AND4 is connected with the first input end of OR1, the second input end of OR1 is connected with the output end of AND2, the output end of OR1 is connected with the input end of BUF1, the output end of BUF1 is connected with the gate of PM1, the gate of PM2 and the gate of NM1, the source electrode of PM1 is connected with the power voltage V CC , the drain electrode of PM1 and the drain electrode of NM1, the positive input end of CMP1 and one end of the timing capacitor are connected, the source electrode of NM1 is connected with the ground, the other end of the timing capacitor is connected with one end of R C , the drain electrode of PM2 and the inverting input end of CMP2, the other end of R C is connected with the source electrode of PM2 and connected with the power voltage V CC , the positive input end of CMP2 and the inverting input end of CMP1 are connected with the threshold voltage V THThe output end of the CMP1 is connected with the first input end of the AND2 and the input end of the INV1, the output end of the CMP2 is connected with the second input end of the AND2 and the second input end of the AND3, the output end of the AND3 is connected with the input end of the BUF2, and the output end of the BUF2 generates the control signal SR_Ctrl.

[0022] Further, the dead time inserting module comprises a buffer BUF3, an inverter INV3, rising edge detecting modules S1 and S2, delay modules D1 and D2, and two-input AND gates AND5 and AND6, wherein the input end of the BUF3 is connected with the input end of the INV3 with the control signal SR_Ctrl, the output end of the BUF3 is connected with the input end of the S1 and the second input end of the AND5, the output end of the S1 is connected with the input end of the D1, the output end of the D1 is connected with the first input end of the AND5, the output end of the AND5 generates the synchronous rectification high-side control signal HI, the output end of the INV3 is connected with the input end of the S2 and the second input end of the AND6, the output end of the S2 is connected with the input end of the D2, the output end of the D2 is connected with the first input end of the AND6, and the output end of the AND6 generates the synchronous rectification low-side control signal LI.

[0023] Further, the judging logic of the state machine is that: first, a fixed data signal DATA is set to represent the dead time, and then the control signal SR_Ctrl is detected.

[0024] If the rising edge of the SR_CTRL is detected, it indicates that the bridge driver switches from the freewheeling state to the rectification state, and the state machine further detects the sequence of the LO falling edge and the HI rising edge: if the HI rising edge is detected first, it indicates that the dead time is smaller, and the data signal DATA is increased by 1 bit; if the LO falling edge is detected first, it indicates that the dead time is larger, and the data signal DATA is decreased by 1 bit.

[0025] If the falling edge of the SR_CTRL is detected, it indicates that the bridge driver switches from the rectification state to the freewheeling state, and the state machine further detects the sequence of the HO falling edge and the LI rising edge: if the LI rising edge is detected first, it indicates that the dead time is smaller, and the data signal DATA is increased by 1 bit; if the HO falling edge is detected first, it indicates that the dead time is larger, and the data signal DATA is decreased by 1 bit.

[0026] In the next control period, the control signal SR_Ctrl is detected again, and the dead time is adjusted according to the above-mentioned manner, so as to continuously optimize the dead time.

[0027] Further, the synchronous rectification speed regulation controller further comprises an interlock protection module for preventing the high-side transistor and the low-side transistor in the bridge driver from being simultaneously turned on due to too small dead time insertion; the interlock protection module comprises inverters INV4 and INV5, and NOR gates NOR1 and NOR2, wherein the input end of the INV4 is connected with the synchronous rectification high-side control signal HI, the output end of the INV4 is connected with the first input end of the NOR1, the second input end of the NOR1 is connected with the low-side transistor state signal LO, the output end of the NOR1 generates the synchronous rectification high-side control signal HC, the input end of the INV5 is connected with the synchronous rectification low-side control signal LI, the output end of the INV5 is connected with the second input end of the NOR2, the first input end of the NOR2 is connected with the high-side transistor state signal HO, and the output end of the NOR2 generates the synchronous rectification low-side control signal LC, and HC and LC are further provided to the gate controller.

[0028] Based on the above technical solution, the application has the following beneficial technical effects:

[0029] 1. High efficiency; the built-in synchronous rectification speed regulation controller module is used to control the current flowing through the motor, the rectification ripple is adjustable, the dead time affecting the rectification efficiency is optimized, the current control efficiency is higher compared with the traditional PWM modulation technology, and the speed regulation capacity is better.

[0030] 2. Simple speed regulation mode; the motor speed can be regulated only by using an external sampling resistor and a voltage source, and the difficulty of use is lower and the development is more convenient compared with the PWM control using the MCU. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a system structure block diagram of the traditional brushless direct current motor speed regulation scheme.

[0032] Figure 2 It is a structure block diagram of the brushless direct current motor synchronous rectification speed regulation circuit in the embodiment of the application.

[0033] Figure 3 It is a circuit structure schematic diagram of the synchronous rectification speed regulation controller in the embodiment of the application.

[0034] Figure 4 It is a circuit structure schematic diagram of the rectification time regulator in the embodiment of the application.

[0035] Figure 5 It is a judgment flow schematic diagram of the state machine in the embodiment of the application. DETAILED DESCRIPTION

[0036] In order to more specifically describe the application, the technical solutions of the application are described in detail in combination with the drawings and the specific embodiments.

[0037] Trapezoidal control is the most commonly used control scheme for brushless DC motors. It has six operating states, in which only one phase's high-side transistor and another phase's low-side transistor of the bridge driver are turned on, forming a loop with the motor windings. Basic trapezoidal control cannot control motor speed; to achieve speed regulation, the current flowing through the stator (i.e., the output current of the bridge driver) must be controlled. Traditional brushless DC motor speed control schemes include... Figure 1 As shown, the motor current is controlled by the PWM controller inside the MCU. Traditional PWM speed regulation schemes using MCU control cannot detect the working status of the bridge driver in real time due to the use of discrete components. The switching between rectification and freewheeling requires a fixed dead time, resulting in efficiency loss.

[0038] The synchronous rectification speed control circuit of the brushless DC motor of the present invention integrates the synchronous rectification speed control controller, the trapezoidal controller, the gate controller and the bridge driver on the same chip. The synchronous rectification speed control controller circuit can detect the gate state signal of the high-side transistor driven by the high-side gate and the gate state signal of the low-side transistor driven by the low-side gate in the bridge driver at all times, optimize the dead time and achieve higher rectification efficiency.

[0039] like Figure 2 As shown, the brushless DC motor synchronous rectification speed control circuit of the present invention includes a synchronous rectification speed control controller, a trapezoidal controller, a gate controller, and a bridge driver. The input port VSW of the synchronous rectification speed control controller and the drive ground port PGND of the bridge driver are both connected to the sampling resistor R. S On one side, R S The other side is grounded, and the input port VREF of the synchronous rectifier speed controller is connected to the reference power supply V. REF V REF The other side is grounded. The ports CP and CN of the synchronous rectification speed controller are connected to the two ends of the timing capacitor C1, respectively. The output signals HC and LC of the synchronous rectification speed controller are connected to the input of the gate controller.

[0040] The trapezoidal controller outputs signals EN1, EN2, EN3, H1, L1, H2, L2, H3, and L3, all of which are input to the gate controller. EN1, EN2, and EN3 are input to the synchronous rectification speed controller.

[0041] The gate controller has three phases, wherein the first phase includes two two-way multiplexing gates MUX1 and MUX2 and two buffers BUF1 and BUF2, HC as the 1-way input of MUX1, H1 as the 0-way input of MUX1, LC as the 1-way input of MUX2, L1 as the 0-way input of MUX2, the two multiplexing gates are enabled by EN1, the output of MUX1 is connected to the input of BUF1, the output of BUF1 is HC1 signal, the output of MUX2 is connected to the input of BUF2, and the output of BUF2 is LC1 signal; the other two phases have the same structure as the first phase, the input signals of the second phase are H2, HC, L2 and LC respectively, and the output signals are HC2 and LC2; the input signals of the third phase are H3, HC, L3 and LC respectively, and the output signals are HC3 and LC3.

[0042] The bridge driver has three phases, wherein the first phase includes a high-side gate drive module, a low-side gate drive module and two N-type LDMOS tubes ND1 and ND2. HC1 signal is input to the high-side gate drive module, and LC1 signal is input to the low-side gate drive module. The high-side gate drive module outputs high-side tube gate state signal HO1, HO1 is high when the corresponding high-side MOS tube is turned on, and vice versa, which is connected to the gate of ND1 to control its conduction and turn-off; the low-side gate drive module outputs low-side tube gate state signal LO1, LO1 is high when the corresponding low-side MOS tube is turned on, and vice versa, which is connected to the gate of ND2 to control its conduction and turn-off. The source of ND1 is connected to the drain of ND2, and is connected to the output port OUT1. The drain of ND1 is connected to the drive power port VM, and the source of ND2 is connected to the drive ground port PGND; the other two phases have the same structure as the first phase, the input of the second phase is HC2 and LC2 respectively, the output is HO2, LO2 and OUT2 respectively, the drive power port is VM, and the drive ground port is PGND; the input of the third phase is HC3 and LC3 respectively, the output is HO3, LO3 and OUT3 respectively, the drive power port is VM, and the drive ground port is PGND; the outputs OUT1, OUT2 and OUT3 of the bridge driver are directly connected to the brushless DC motor.

[0043] When the ladder controller controls the bridge driver to be in one of the six working states, the ladder controller enables the gate driver of the phase with low-side conduction, and the synchronous rectification speed control controller controls the phase, and the other two phases are still controlled by the ladder controller.

[0044] As Figure 2As shown, taking the trapezoidal controller controlling the high-side transistor of the second phase and the low-side transistor of the first phase to conduct as an example, the gate controller input signal of the first phase is selected by MUX1 and MUX2 to select the HC and LC signals, that is, the first phase of the bridge drive is controlled by the synchronous rectification speed controller. When the motor is in freewheeling mode, the motor current will increase, and at this time, the current will be controlled by the external sampling resistor R. S The bridge drive current is sampled, and when the current exceeds the VREF port voltage V... ref During this time, the synchronous rectification speed controller will control the bridge drive to switch from freewheeling mode to synchronous rectification mode for a certain period of time, and then return to freewheeling mode after the time is up. This limits the motor current to V. ref / R S This allows for control of the motor current; therefore, only V needs to be changed. ref The value can change the motor current, thereby achieving speed regulation of the brushless DC motor.

[0045] To achieve the above rectification process, the synchronous rectification speed controller in this embodiment is as follows: Figure 3 As shown, it includes a synchronous rectification comparator, a rectification time regulator, a misjudgment prevention module, a dead time insertion module, an interlock protection module, a detection signal gating unit, a state machine, a digital-to-analog converter, and a dead time generator.

[0046] The output signals EN1, EN2, EN3, HO1, LO1, HO2, LO2, HO3, and LO3 of the trapezoidal controller are input to the detection signal selection unit to control its output HO and LO signals. Taking the trapezoidal controller controlling the second phase high-side tube to be turned on and the first phase low-side tube to be turned on as an example, at this time, the HO and LO signals respectively select the HO1 and LO1 signals to detect the switching status of the first phase ND1 and ND2.

[0047] The positive input of the synchronous rectifier comparator is connected to the sampling resistor R through the VSW port. S The negative input is connected to the reference voltage V through the VREF port. ref When the VSW port level is lower than V ref When the motor is in freewheeling mode, the motor current increases, and the voltage at the VSW port rises. When the VSW port level is greater than Vref, the synchronous rectifier comparator output signal CMP changes from low to high. At this time, the rectifier time regulator output signal SR_Ctrl outputs a time value of T. SD The high level, T SD The rectification time of the synchronous rectifier comparator is adjustable. When this signal is high, HI is high and LI is low, the high-side transistor of the first phase in the bridge drive is turned on, and the synchronous rectification state is entered. When this signal is low, HI is low and LI is high, the low-side transistor of the first phase in the bridge drive is turned on, and the freewheeling state is entered.

[0048] TSD The size of the rectification time is regulated by a rectification time regulator and an off-chip timing capacitor C1, as shown in Figure 4 The rectification time regulator includes an RS latch RS1, a three-input AND gate AND4, three two-input AND gates AND1, AND2 and AND3, a two-input OR gate OR1, two buffers BUF1 and BUF2, two inverters INV1 and INV2, two comparators CMP1 and CMP2, two PMOS transistors PM1 and PM2, an NMOS transistor NM1, a resistor R C The power supply of the circuit is V CC , the ground level is GND, and the threshold level is V TH When the input IN signal is at a low level, PM1 and PM2 are turned on, and NM1 is turned off, at which time the voltages at the CN and CP ports are V CC , and the output signal OUT is at a low level; when a rising edge of the input signal is detected, PM1 and PM2 are turned off, and NM1 is turned on, so as to pull the voltage at the CN port to GND. Since the voltage across the capacitor C1 cannot change abruptly, the voltage at the CP port follows the voltage at the CN port, and then C1 is charged by the power supply V CC through the resistor R C , and OUT becomes high. After a time of T SD , the CP level is charged to V TH , PM1 and PM2 are turned on again, the voltages at the CN and CP ports are clamped to VCC, and the OUT level becomes low again. The expression of T SD is as follows:

[0049]

[0050] The rectification time T SD can be regulated by adjusting the capacitance of C1. A suitable capacitance value can be selected according to different models of brushless DC motors, and a suitable rectification time can be selected.

[0051] The SR_Ctrl signal needs to enter a dead time insertion module to generate corresponding HI and LI signals. The dead time insertion module includes a buffer BUF3, an inverter INV3, two rising edge detection modules, two delay modules, and two two-input AND gates AND5 and AND6. The module will have a fixed delay for the opening of two signals to generate a dead time and generate corresponding HI and LI signals. The delay module determines the size of the dead time, and the size of the delay is determined by the dead time generator.

[0052] The optimal dead time varies under the influence of temperature, process, and voltage. The insertion of a fixed dead time will cause efficiency loss. Therefore, the state machine provides the optimal dead time by judging the SR_Ctrl, LO, HO, LI, and HI signals and outputs the corresponding data signal DATA, which is converted into a level V DT by a digital-to-analog converter. The dead time generator generates the corresponding dead time T D and provides it to the delay module in the dead time insertion module.

[0053] The judgment process of the state machine is shown in Figure 5 : When the synchronous rectification speed control device is powered on, the state machine first sets a fixed dead time through the digital-to-analog converter. Then, the state machine detects the SR_CTRL control signal. If the state machine detects the rising edge of SR_CTRL, it indicates that the bridge drive switches from freewheeling to rectification. At this time, ND2 is closed and ND1 is opened in Figure 2 . The state machine detects the sequence of the falling edge of LO and the rising edge of HI. If the rising edge of HI is detected first, it indicates that the dead time is small, and the state machine outputs DATA to increase by 1 bit. If the falling edge of LO is detected first, it indicates that the dead time is large, and the state machine outputs DATA to decrease by 1 bit. If the state machine detects the falling edge of SR_CTRL, it indicates that the bridge drive switches from rectification to freewheeling. At this time, ND1 is closed and ND2 is opened in Figure 2 . The state machine detects the sequence of the falling edge of HO and the rising edge of LI. If the rising edge of LI is detected first, it indicates that the dead time is small, and the state machine outputs DATA to increase by 1 bit. If the falling edge of HO is detected first, it indicates that the dead time is large, and the state machine outputs DATA to decrease by 1 bit. Then, the next round of judgment is performed. Through continuous feedback judgment, the state machine dynamically adjusts the output DATA and then adjusts the dead time, so as to obtain the optimal dead time and reduce efficiency loss.

[0054] To prevent damage caused by too small dead time, the synchronous rectification speed control device has an interlock protection module to realize anti-feedthrough function. When the HO signal is high, the low-side control signal is not allowed to send a pilot signal. Similarly, when the LO signal is high, the high-side signal is also limited.

[0055] The LI and HI signals are input into the interlock protection module, and the interlock protection module receives the LO and HO from the detection signal gating unit. The interlock protection module comprises two inverters INV4 and INV5, two two-input NOR gates NOR1 and NOR2, when the HO signal is high, it represents that the high-side transistor is open, at this time, the LI signal is not allowed to pass; when the LO signal is high, it represents that the low-side transistor is open, at this time, the HI signal is not allowed to pass, which is used for preventing the high-side and low-side transistors from being turned on at the same time. The control signals HC and LC output from the interlock protection module are input into the gate controller, so as to realize the control of the bridge drive.

[0056] In conclusion, the brushless DC motor synchronous rectification speed regulation circuit can provide flexible rectification time according to the dynamic optimization of dead time, and can flexibly adjust the motor speed through an external reference voltage, the speed regulation mode is simple, and has high efficiency.

[0057] The above description of the embodiments is for facilitating the understanding and application of the present application by the ordinary skilled in the art, and the skilled in the art can easily make various modifications to the above embodiments, and apply the general principles described herein to other embodiments without creative labor. Therefore, the present application is not limited to the above embodiments, and the improvements and modifications of the present application made by the skilled in the art according to the disclosure of the present application should be within the protection scope of the present application.

Claims

1. A synchronous rectification speed control circuit for a brushless DC motor, characterized in that: This includes a synchronous rectification speed controller, a ladder controller, a gate controller, and a bridge driver integrated on the same chip, wherein: The trapezoidal controller provides three-phase switch control signals and three-phase enable signals to the gate controller. The gate controller controls the bridge driver to achieve six-step trapezoidal control of the brushless DC motor. At the same time, it provides three-phase enable signals to the synchronous rectifier speed controller to select the phase to be controlled. The synchronous rectification speed controller obtains the three-phase switching status signal of the bridge driver from the chip and provides synchronous rectification control signal to the gate controller. The gate controller controls the bridge driver to switch between freewheeling and rectification states and adjusts the drive current of the bridge driver. The gate controller selects the three-phase switch control signal and the synchronous rectification control signal according to the three-phase enable signal, thereby providing the three-phase switch drive signal to the bridge driver; The bridge driver amplifies the power of the three-phase switch drive signal to control the on / off state of the internal power switching devices, thereby driving the brushless DC motor to achieve electronic commutation and speed regulation. The synchronous rectification speed controller includes: The detection signal gating unit selects one phase switch status signal from the three-phase switch status signals according to the three-phase enable signal, including the high-side tube status signal HO and the low-side tube status signal LO of that phase. The synchronous rectifier comparator acquires the DC feedback voltage of the bridge driver through an external sampling resistor, compares it with a reference voltage, and generates a comparison signal. The rectifier timing regulator outputs a control signal SR_Ctrl with a fixed pulse width when it detects the rising edge of the comparison signal. The pulse width is adjusted by an external timing capacitor. The dead time insertion module performs rising edge detection on the control signal SR_Ctrl in two ways and inserts dead time through delay to generate synchronous rectification high-side control signal HI and synchronous rectification low-side control signal LI. The state machine determines the optimal dead time by judging the signals SR_Ctrl, LO, HO, LI, and HI, and then outputs the corresponding data signals. A digital-to-analog converter is used to convert data signals into analog levels. The dead time generator generates the corresponding dead time based on the analog level and provides it to the dead time insertion module.

2. The brushless DC motor synchronous rectification speed control circuit according to claim 1, characterized in that: When the ladder controller controls the low-side transistor of a certain phase in the bridge driver to turn on, it outputs an enable signal for that phase at a high level. The detection signal gating unit selects the switching state signal of that phase according to the enable signal.

3. The brushless DC motor synchronous rectification speed control circuit according to claim 1, characterized in that: The synchronous rectification speed controller also includes a misjudgment prevention module, which is used to detect the rising edge of the low-side tube status signal LO and generate a shielding pulse signal of fixed duration to provide to the rectification time regulator. When the corresponding low-side tube is turned on, it will briefly shield the rectification time regulator to prevent the synchronous rectification comparator from misjudging and causing erroneous operation.

4. The brushless DC motor synchronous rectification speed control circuit according to claim 3, characterized in that: The rectifier timing regulator includes an RS latch RS1, a three-input AND gate AND4, two-input AND gates AND1~AND3, an OR gate OR1, buffers BUF1 and BUF2, inverters INV1 and INV2, comparators CMP1 and CMP2, PMOS transistors PM1 and PM2, an NMOS transistor NM1, and a resistor R. C The first input of AND1 is connected to the comparison signal. The second input of AND1 is connected to the output of INV2 and the first input of AND3. The input of INV2 is connected to the shielding pulse signal. The output of AND1 is connected to the S input of RS1 and the first input of AND4. The R input of RS1 is connected to the third input of AND4 and the output of INV1. The Q output of RS1 is connected to the second input of AND4. The output of AND4 is connected to the first input of OR1. The second input of OR1 is connected to the output of AND2. The output of OR1 is connected to the input of BUF1. The output of BUF1 is connected to the gates of PM1, PM2, and NM1. The source of PM1 is connected to the power supply voltage V. CC The drain of PM1 is connected to the drain of NM1, the non-inverting input of CMP1, and one end of the timing capacitor. The source of NM1 is grounded, and the other end of the timing capacitor is connected to R. C One end of R is connected to the drain of PM2 and the inverting input of CMP2. C The other end is connected to the source of PM2 and connected to the power supply voltage V. CC The non-inverting input of CMP2 and the inverting input of CMP1 are connected to the threshold voltage V. TH The output of CMP1 is connected to the first input of AND2 and the input of INV1. The output of CMP2 is connected to the second input of AND2 and the second input of AND3. The output of AND3 is connected to the input of BUF2. The output of BUF2 generates the control signal SR_Ctrl.

5. The brushless DC motor synchronous rectification speed control circuit according to claim 1, characterized in that: The dead-time insertion module includes a buffer BUF3, an inverter INV3, rising edge detection modules S1 and S2, delay modules D1 and D2, and two-input AND gates AND5 and AND6. The input of BUF3 is connected to the input of INV3 with the control signal SR_Ctrl. The output of BUF3 is connected to the input of S1 and the second input of AND5. The output of S1 is connected to the input of D1. The output of D1 is connected to the first input of AND5. The output of AND5 generates a synchronous rectification high-side control signal HI. The output of INV3 is connected to the input of S2 and the second input of AND6. The output of S2 is connected to the input of D2. The output of D2 is connected to the first input of AND6. The output of AND6 generates a synchronous rectification low-side control signal LI.

6. The brushless DC motor synchronous rectification speed control circuit according to claim 1, characterized in that: The state machine's decision logic is as follows: First, a fixed data signal DATA is set to represent the dead time, and then the control signal SR_Ctrl is detected. If the rising edge of SR_Ctrl is detected, it indicates that the bridge driver is switching from freewheeling mode to rectification mode. The state machine then checks the order of the falling edge of LO and the rising edge of HI: if the rising edge of HI is detected first, it means that the dead time is small, so the data signal DATA is incremented by 1 bit; if the falling edge of LO is detected first, it means that the dead time is large, so the data signal DATA is decremented by 1 bit. If a falling edge of SR_Ctrl is detected, it indicates that the bridge driver is switching from rectification mode to freewheeling mode. The state machine then detects the order of the falling edge of HO and the rising edge of LI: if the rising edge of LI is detected first, it indicates that the dead time is small, so the data signal DATA is incremented by 1 bit; if the falling edge of HO is detected first, it indicates that the dead time is large, so the data signal DATA is decremented by 1 bit. In the next control cycle, the control signal SR_Ctrl is re-detected and the dead time is adjusted in the manner described above, thereby continuously optimizing it.

7. The brushless DC motor synchronous rectification speed control circuit according to claim 1, characterized in that: The synchronous rectification speed controller also includes an interlock protection module to prevent the high-side transistor and low-side transistor in the bridge driver from being simultaneously turned on due to an excessively small dead time insertion. The interlock protection module includes inverters INV4 and INV5 and NOR1 and NOR2. The input of INV4 is connected to the synchronous rectification high-side control signal HI, and the output of INV4 is connected to the first input of NOR1. The second input of NOR1 is connected to the low-side transistor status signal LO, and the output of NOR1 generates the synchronous rectification high-side control signal HC. The input of INV5 is connected to the synchronous rectification low-side control signal LI, and the output of INV5 is connected to the second input of NOR2. The first input of NOR2 is connected to the high-side transistor status signal HO, and the output of NOR2 generates the synchronous rectification low-side control signal LC, which is then provided to the gate controller.

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