A storage device, a control method thereof, and a manufacturing method thereof

Abstract

The present application provides a storage device, a control method thereof, and a manufacturing method thereof, relating to the field of semiconductor technology. One storage unit of the storage device provided by the present application has two sub-units and is interconnected through a drain. By configuring different voltage signals, the threshold voltages stored in each sub-unit can be independently read, so that each sub-unit has an independent storage capacity, thereby improving the storage capacity of a single storage unit in the storage device and enabling the storage device to store more information. In addition, the two sub-units can be a P-type storage sub-unit and an N-type storage sub-unit respectively, forming a complementary semiconductor structure, thus having better electrical performance and stability.

Description

Technical Field

[0001] This application relates to semiconductor technology, and particularly to a storage device, a control method thereof, and a manufacturing method thereof. Background Art

[0002] In the field of data storage, non-volatile memories based on metal-oxide-semiconductor (MOSFET) have wide applications. Among them, the non-volatile memory based on MOSFET has a floating gate and can store charges / holes through the floating gate effect, thereby forming the threshold voltage of the memory, so that the memory operates at the threshold voltage. In application, the threshold voltage can be used as data, and the data can be read by reading the threshold voltage.

[0003] Therefore, how to further improve the storage performance of the non-volatile memory based on MOSFET is a technical problem that those skilled in the art need to solve urgently. Summary of the Invention

[0004] In view of this, embodiments of this application provide a storage device, a control method thereof, and a manufacturing method thereof. In this application, an N-type storage sub-unit and a P-type storage sub-unit are integrated in the storage unit of the storage device and are connected with a common drain, so that each storage sub-unit has an independent storage ability, and a complementary semiconductor structure is formed, improving the electrical properties and stability of the device.

[0005] In the first aspect, this application provides a storage device. The storage device includes a plurality of storage units. Each storage unit includes an N-type storage sub-unit, a P-type storage sub-unit, and a control lead. Among them, the N-type storage sub-unit is disposed on the first side of the isolation trench in the substrate, and the N-type drain of the N-type storage sub-unit is close to the isolation trench. The P-type storage sub-unit is disposed on the second side of the isolation trench in the substrate, and the P-type drain of the P-type storage sub-unit is close to the isolation trench. The control lead includes a common drain lead connected to both the N-type drain and the P-type drain, an N-type source lead connected to the N-type source of the N-type storage sub-unit, an N-type gate lead connected to the N-type gate of the N-type storage sub-unit, a P-type source lead connected to the P-type source of the P-type storage sub-unit, and a P-type gate lead connected to the P-type gate of the P-type storage sub-unit.

[0006] In the second aspect, this application provides a storage structure, which includes a doped substrate, a source, a drain, a control gate, and a floating gate. The source and the drain are disposed at both ends of the doped substrate, and the control gate is disposed between the source and the drain. The floating gate is disposed under the control gate and embedded in the substrate. The floating gate includes at least two extending portions, and the at least two extending portions extend into the substrate.

[0007] In a third aspect, the present application provides a control method for a storage device, which is applied to the storage device described in the first aspect. The control method includes a method for reading the threshold voltage from a target storage subunit among the N-type storage subunits and P-type storage subunits in the storage device, including: controlling the storage device to be in a read state corresponding to the target storage subunit; applying a scanning voltage to the gate lead of the target storage subunit; and determining the actual scanning voltage at the conduction moment as the threshold voltage in response to the source and drain of the target storage subunit being turned on.

[0008] In a fourth aspect, the present application provides a manufacturing method for a storage device, the manufacturing method including: providing a substrate, wherein the substrate includes N-type storage subunits, P-type storage subunits, and isolation trenches, the N-type storage subunits and P-type storage subunits are arranged on both sides of the isolation trenches, the N-type drain of the N-type storage subunit is close to the isolation trench, and the P-type drain of the P-type storage subunit is close to the isolation trench; depositing a lead dielectric layer on the substrate; etching the lead dielectric layer to form a lead groove penetrating the lead dielectric layer; filling the lead groove to form a control lead of the storage device, wherein the control lead includes a common drain lead connected to both the N-type drain and the P-type drain, an N-type source lead connected to the N-type source of the N-type storage subunit, an N-type gate lead connected to the N-type gate of the N-type storage subunit, a P-type source lead connected to the P-type source of the P-type storage subunit, and a P-type gate lead connected to the P-type gate of the P-type storage subunit.

[0009] Based on the storage device, its control method, and manufacturing method provided by the embodiments of the present application, a storage unit of the storage device provided by the present application has two subunits and is interconnected through the drain. By configuring different voltage signals, the threshold voltages stored in each subunit can be independently read, so that each subunit has an independent storage capacity, thereby improving the storage capacity of a single storage unit in the storage device and enabling the storage device to store more information. In addition, the two subunits can be a P-type storage subunit and an N-type storage subunit respectively, forming a complementary semiconductor structure, thus having better electrical performance and stability. Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 It is a schematic structural diagram of a storage unit provided by some embodiments of the present application.

[0012] Figure 2It is another structural schematic diagram of a storage unit provided by some embodiments of the present application.

[0013] Figure 3 It is an exemplary flowchart of a method for reading a threshold voltage provided by some embodiments of the present application.

[0014] Figure 4 It is an exemplary flowchart of a method for adjusting a threshold voltage provided by some embodiments of the present application.

[0015] Figure 5 It is an exemplary flowchart of a method for manufacturing a storage device provided by some embodiments of the present application.

[0016] Figure 6 It is a schematic diagram of a substrate having storage sub-units provided by some embodiments of the present application.

[0017] Figure 7 It is a schematic diagram of a lead dielectric layer provided by some embodiments of the present application.

[0018] Figure 8 It is a structural schematic diagram of a storage structure provided by some embodiments of the present application.

[0019] Figure 9 It is another structural schematic diagram of a storage structure provided by some embodiments of the present application.

[0020] Figure 10 It is a structural schematic diagram of a storage unit with a fully embedded floating gate provided by some embodiments of the present application.

[0021] Wherein, 100, storage unit; 110, N-type storage sub-unit; 120, P-type storage sub-unit; 130, isolation trench; 111, N-type drain; 112, N-type source; 113, N-type gate; 121, P-type drain; 122, P-type source; 123, P-type gate; 141, common drain lead; 142, N-type source lead; 143, N-type gate lead; 144, P-type source lead; 145, P-type gate lead; 150, drain connection structure; 160, substrate; 170, lead dielectric layer; 171, lead groove; 200, storage structure; 210, doped substrate; 220, source; 230, drain; 240, control gate; 250, floating gate; 251, extension; 252, connection part; 2521, driving surface; 2522, extension surface; 231, drain lead; 221, source lead; 241, first isolation layer; 242, second isolation layer. Detailed implementation manners

[0022] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The form, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0024] In the present invention, it should be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes, and cannot be understood as indicating or implying relative importance.

[0025] Exemplary storage device:

[0026] In practical applications, a storage device often has multiple storage units, and each storage unit can store data. Among them, the storage device provided in the present application can be a MOSFET-based non-volatile memory. Among them, the threshold voltage in the storage unit can be used as the stored data, and the data can be read by reading the threshold voltage. For example, the actual data corresponding to different threshold voltage values can be determined first, and by reading the threshold voltage and combining the correspondence between the actual data and the threshold voltage value, the actual data stored in the storage unit can be determined.

[0027] To improve the storage capacity of a single storage unit, the present application integrates an N-type storage subunit and a P-type storage subunit in a storage unit. Among them, both the N-type storage subunit and the P-type storage subunit are non-volatile MOSFET memories based on the floating gate structure.

[0028] The N-type storage subunit can be an N-type metal oxide semiconductor, and the conductivity of the N-type storage subunit mainly depends on free electrons. When the gate voltage (VGS) of the N-type storage subunit is higher than the threshold voltage, the N-type storage subunit conducts. The data recorded by the N-type storage subunit can be reflected by the threshold voltage when the N-type storage subunit conducts.

[0029] Among them, the substrate of the N-type storage sub-unit is doped with P-type ions, and the source and drain of the N-type storage sub-unit are N-type ion doping regions. Among them, the threshold voltage recorded by the N-type storage sub-unit is a positive voltage.

[0030] The P-type storage sub-unit can be a P-type metal oxide semiconductor, and the conductivity of the P-type storage sub-unit mainly depends on holes. When the gate voltage (VGS) of the P-type storage sub-unit is lower than the threshold voltage, the P-type storage sub-unit conducts. The data recorded by the P-type storage sub-unit can be reflected by the threshold voltage when the P-type storage sub-unit conducts.

[0031] Among them, the substrate of the P-type storage sub-unit is doped with N-type ions, and the source and drain of the P-type storage sub-unit are P-type ion doping regions. Among them, the threshold voltage recorded by the P-type storage sub-unit is a negative voltage.

[0032] In practical applications, the aforementioned N-type storage sub-unit and P-type storage sub-unit can be OTP (one time programming) devices with non-rewritable threshold voltages, or MTP (multi time programming) devices that can rewrite threshold voltages. Among them, the subsequent content of this application will take the MTP device as an example for illustration. If there is an actual need, it can also be partially replaced with an OTP device and corresponding adaptations can be made.

[0033] To construct the N-type storage sub-unit and the P-type storage sub-unit into a storage cell, this application interconnects the drains of the N-type storage sub-unit and the P-type storage sub-unit, so that the N-type storage sub-unit and the P-type storage sub-unit can store data independently. To further illustrate the storage cell provided by this application, this application also provides a schematic structural diagram of a storage cell.

[0034] As Figure 1 shown, the storage cell 100 may include an N-type storage sub-unit 110, a P-type storage sub-unit 120, an isolation trench 130, and a control lead. Among them, the N-type storage sub-unit 110 and the P-type storage sub-unit 120 may be respectively disposed on both sides of the isolation trench 130.

[0035] Continuing from the above, both the N-type storage sub-unit 110 and the P-type storage sub-unit 120 are non-volatile MOSFET memories. Then the N-type storage sub-unit 110 includes an N-type drain 111, an N-type source 112, and an N-type gate 113. Among them, the N-type gate 113 may include a control gate (Poly Control Gate) and a floating gate (Floating Gate) to achieve the recording of the threshold voltage. Correspondingly, the P-type storage sub-unit 120 includes a P-type drain 121, a P-type source 122, and a P-type gate 123.

[0036] To achieve the interconnection of the N-type drain 111 of the N-type memory sub-unit 110 and the P-type drain 121 of the P-type memory sub-unit 120, the N-type drain 111 of the N-type memory sub-unit 110 is disposed close to the isolation trench 130 and the P-type drain 121 of the P-type memory sub-unit 120 is disposed close to the isolation trench 130.

[0037] Accordingly, the aforementioned control lead can include a common drain lead 141 that is connected to both the N-type drain 111 and the P-type drain 121.

[0038] In some embodiments, to achieve the connection of the common drain lead 141 to both the N-type drain 111 and the P-type drain 121. In Figure 1 the shown memory cell 100, the memory cell 100 may further include a drain connection structure 150 that spans across the isolation trench 130 to connect the P-type drain 121 and the N-type drain 111. Accordingly, the common drain lead 141 can be electrically connected to the drain connection structure 150 to achieve simultaneous connection to the P-type drain 121 and the N-type drain 111.

[0039] In some embodiments, to simplify the internal structure, the common drain lead 141 can also omit the drain connection structure 150 by adjusting the width. To further illustrate this situation, the present application also includes another schematic diagram of the structure of the memory cell ( Figure 2 ). As Figure 2 shown, the common drain lead 141 has a certain width in the transverse direction, so as to span across the isolation trench 130 in the transverse direction and connect to the P-type drain 121 and the N-type drain 111 simultaneously.

[0040] As Figure 1 shown, the control lead can also include other leads for the N-type memory sub-unit 110 and the P-type memory sub-unit 120. Specifically, the control lead further includes an N-type source lead 142 connected to the N-type source 112 of the N-type memory sub-unit 110, an N-type gate lead 143 connected to the N-type gate 113 of the N-type memory sub-unit 110, a P-type source lead 144 connected to the P-type source 122 of the P-type memory sub-unit 120, and a P-type gate lead 145 connected to the P-type gate 123 of the P-type memory sub-unit 120.

[0041] In addition, the control lead can also include an N-type substrate lead (not visible in the figure) connected to the doped substrate of the N-type memory sub-unit 110 and a P-type substrate lead (not visible in the figure) connected to the doped substrate of the P-type memory sub-unit 120. To clearly show the names of some structures, in Figure 1In the drawing and subsequent drawings, the names in the structure will have a background color added to avoid the influence of the shading of the structure where they are located on the display of the names, and shading will be set under some names. It should be noted that this shading does not mean a structure that needs to be set additionally, but is only a display style for clear text content.

[0042] Exemplary control method for a storage device:

[0043] In practical applications, the operating state of the storage unit 100 can be controlled by controlling the voltages of the respective specific leads in the control leads, thereby realizing operations such as data reading.

[0044] Specifically, based on the storage principle of the non-volatile MOSFET memory, the reading process of the N-type storage sub-unit 110 is as follows:

[0045] When the driving voltage of the N-type gate lead 143 is the same as (or greater than) the threshold voltage stored in the N-type storage sub-unit 110 and the storage unit 100 is in the N-type reading state, the common drain lead 141 and the N-type source lead 142 are conducting. Among them, when a positive voltage is applied to the common drain lead 141 and a voltage greater than that of the common drain lead 141 is also applied to the P-type substrate lead, the storage unit 100 is in the N-type reading state.

[0046] Only as an exemplary illustration, when the storage unit 100 is in the N-type reading state, the N-type source voltage (VsN), the N-type substrate voltage (VbN), the P-type gate voltage (VgP), and the P-type source voltage (VsP) are all 0. The drain voltage (VdN / VdP) = 1.1v < the P-type substrate voltage (VbP) = 2.2v. At this time, if the N-type gate voltage (VgN) ≥ the threshold voltage, the N-type storage sub-unit 110 conducts (that is, the common drain lead 141 and the N-type source lead 142 conduct).

[0047] Similar to the aforementioned N-type storage sub-unit 110, the reading process of the P-type storage sub-unit 120 is as follows:

[0048] When the driving voltage of the P-type gate lead 145 is the same as (or less than) the threshold voltage stored in the P-type storage sub-unit 120 and the storage unit 100 is in the P-type reading state, the common drain lead 141 and the P-type source lead 144 are conducting. When a negative voltage is applied to the common drain lead 141 and a voltage less than that of the common drain lead 141 is also applied to the N-type substrate lead, the storage unit 100 is in the P-type reading state.

[0049] For illustrative purposes only, when the storage unit 100 is in the P-type read state, the N-type gate voltage (VgN), N-type source voltage (VsN), P-type source voltage (VsP), and P-type substrate voltage (VbP) are all 0. The drain voltage (VdN / VdP) = -1.1V > the N-type substrate voltage (VbN) = -2.2V. At this time, if the P-type gate voltage (VgP) ≤ the threshold voltage, the P-type storage sub-unit 120 conducts (i.e., the common drain lead 141 conducts with the P-type source lead 144).

[0050] It should be noted that, in this application, without additional explanation, the magnitude comparison of voltages is calculated with signs. For example, -1.1V > -2.2V.

[0051] As Figure 1 shown, both the N-type gate 113 and the P-type gate 123 include a control gate and a floating gate stacked, so the N-type storage sub-unit 110 and the P-type storage sub-unit 120 can also be used as erasable non-volatile MOSFET memories, thus supporting the writing and erasing of the threshold voltage.

[0052] Based on the storage principle of the erasable non-volatile MOSFET memory, the process of writing the threshold voltage of the N-type storage sub-unit 110 is as follows:

[0053] When the driving voltage of the N-type gate lead 143 is the writing voltage and the storage unit 100 is in the N-type writing state, electrons are sucked into the floating gate of the N-type storage sub-unit 110 to form the threshold voltage. Among them, the writing voltage is generally a high voltage (such as 9.5V). The N-type writing state is similar to the aforementioned N-type read state, and it is necessary to ensure that a positive voltage is applied to the common drain lead 141 and a voltage greater than that of the common drain lead 141 is also applied to the P-type substrate lead, but the specific voltage values are different.

[0054] For illustrative purposes only, when the storage unit 100 is in the N-type writing state, the N-type source voltage (VsN), N-type substrate voltage (VbN), P-type gate voltage (VgP), and P-type source voltage (VsP) are all 0. The drain voltage (VdN / VdP) = 3.8V < the P-type substrate voltage (VbP) = 5.8V. At this time, if a high voltage (such as 9.5V) is applied to the N-type gate voltage (VgN), then at this time, electrons are sucked into the floating gate of the N-type storage sub-unit 110 to change the threshold voltage to form the threshold voltage to be memorized. Among them, the adjustment value of the threshold voltage is generally related to the time when a high voltage is applied to the N-type gate voltage (VgN), and the specific relationship can be determined by laboratory measurement to guide data writing in subsequent work.

[0055] Correspondingly, the process of writing the threshold voltage of the P-type storage sub-unit 120 is as follows:

[0056] When the driving voltage of the P-type gate lead 145 is the write voltage and the storage cell 100 is in the P-type write state, holes are sucked into the floating gate of the P-type storage sub-cell 120 to form a threshold voltage. Among them, the threshold voltage of the P-type storage sub-cell 120 is generally negative. The write voltage of the P-type gate lead 145 is generally a negative voltage with a relatively large absolute value (such as -9.5V). The P-type write state is similar to the aforementioned P-type read state, and it is necessary to ensure that a negative voltage is applied to the common drain lead 141 and a negative voltage smaller than that of the common drain lead 141 is also applied to the N-type substrate lead, but the specific voltage values are different.

[0057] Only as an exemplary illustration, when the storage cell 100 is in the P-type write state, the N-type gate voltage (VgN), N-type source voltage (VsN), P-type source voltage (VsP), and P-type substrate voltage (VbP) are all 0. The drain voltage (VdN / VdP) = -3.8V > the N-type substrate voltage (VbN) = -5.8V. At this time, if a negative voltage with a relatively large absolute value (such as -9.5V) is applied to the P-type gate voltage (VgP), then at this time, holes are sucked into the floating gate of the P-type storage sub-cell 120 to change the threshold voltage to form the threshold voltage that needs to be memorized.

[0058] Based on the storage principle of the erasable non-volatile MOSFET memory, the process of erasing the threshold voltage of the N-type storage sub-cell 110 is as follows:

[0059] When the driving voltage of the N-type gate lead 143 is the erase voltage and the storage cell 100 is in the N-type erase state, electrons are released from the floating gate of the N-type storage sub-cell 110 to erase the threshold voltage. Among them, when the storage cell 100 is in the N-type erase state, the N-type source voltage (VsN), N-type substrate voltage (VbN), and drain voltage (VdN / VdP) are all greater than the maximum value of the threshold voltage value range, and the P-type substrate voltage (VbP) is greater than the drain voltage (VdN / VdP). At this time, the N-type gate voltage (VgN) is in a negative voltage, so that electrons are released from the floating gate to erase the threshold voltage.

[0060] Only as an exemplary illustration, when the storage cell 100 is in the N-type erase state, when the threshold voltage of the N-type storage sub-cell 110 is 0 - 6V, the N-type source voltage (VsN) = the N-type substrate voltage (VbN) = the drain voltage (VdN / VdP) = 7.7V < the P-type substrate voltage (VbP) = 8.8V. Then at this time, the driving voltage of the N-type gate lead 143 (i.e., the N-type gate voltage (VgN)) = -8.1V, so that electrons are released from the floating gate to erase the threshold voltage.

[0061] Similar to the process of erasing the threshold voltage of the aforementioned N-type storage sub-cell 110, the process of erasing the threshold voltage of the P-type storage sub-cell 120 is as follows:

[0062] When the driving voltage of the P-type gate lead 145 is the erasing voltage and the memory cell 100 is in the P-type erasing state, the floating gate of the P-type memory sub-cell 120 releases holes to erase the threshold voltage. Among them, when the memory cell 100 is in the P-type erasing state, the drain voltage (VdN / VdP), the P-type source voltage (VsP), and the P-type substrate voltage (VbP) are all less than the minimum value of the threshold voltage value range, and the N-type substrate voltage (VbN) is less than the drain voltage (VdN / VdP).

[0063] Only as an illustrative example, when the memory cell 100 is in the N-type erasing state and the threshold voltage of the P-type memory sub-cell 120 is 0 - 6V, the P-type source voltage (VsP) = the P-type substrate voltage (VbP) = the drain voltage (VdN / VdP) = -7.7V > the P-type substrate voltage (VbP) = -8.8V. At this time, the driving voltage of the P-type gate lead 145 (i.e., the P-type gate voltage (VgP)) = 8.1V, so that the floating gate releases holes to erase the threshold voltage.

[0064] In some embodiments, in practical applications, the aforementioned writing threshold voltage can be regarded as a process of increasing the absolute value of the threshold voltage value (making the threshold voltage farther from 0V), and the erasing threshold voltage can be regarded as a process of reducing the absolute value of the threshold voltage value (making the threshold voltage closer to 0V).

[0065] When actually adjusting the threshold voltage, erasing can be performed first and then writing based on the aforementioned process. As an alternative, one of erasing and writing can also be directly selected based on the difference in the threshold voltage.

[0066] In some embodiments, after writing / erasing is completed, the threshold voltage can be inspected. Here, the memory cell 100 can be in the corresponding reading state, and a scanning voltage is applied to its gate to determine the actual threshold voltage.

[0067] Considering that the aforementioned process only illustrates that the memory sub-cell conducts under the corresponding conditions. When actually reading the threshold voltage, a scanning voltage can be applied to the gate starting from 0V to determine the gate voltage when the memory sub-cell conducts and record it as the read threshold voltage.

[0068] Only as an illustrative example, for the voltage schematic values of each state in the aforementioned process, please refer to the following table:

[0069]

[0070] Based on the different control states of the aforementioned memory sub-cells, the present application also provides a control method for each memory cell 100 in a memory device, which may specifically include a threshold voltage reading method ( Figure 3 ), and a threshold voltage adjustment method (Figure 4 ).

[0071] As Figure 3 shown, process P300 may include the following steps:

[0072] S310. Determine a target storage sub - unit from N - type storage sub - units and P - type storage sub - units.

[0073] S320. Control the storage unit to be in the read state corresponding to the target storage sub - unit.

[0074] S330. Apply a scanning voltage to the gate lead of the target storage sub - unit.

[0075] S340. In response to the source and drain of the target storage sub - unit being turned on, determine the gate voltage at the turn - on moment and use it as the threshold voltage of the target storage sub - unit.

[0076] In the foregoing S310, the target storage sub - unit may be the storage sub - unit for data reading. In practical applications, each storage sub - unit in a storage unit of the present application works independently, but only one storage sub - unit can be controlled at a time. Thus, during the use of the storage device provided in the present application, the related device needs to first determine the target storage sub - unit to be controlled.

[0077] In some embodiments, the selection of each storage sub - unit can also be based on its actual properties. Among them, for storage tasks that require fast response, N - type storage sub - units can be called. For storage tasks with low speed requirements but high stability requirements, P - type storage sub - units can be preferentially called.

[0078] After determining the foregoing target storage sub - unit, the voltage of the control lead can be adjusted to make the storage unit in the read state corresponding to the target storage sub - unit. The specific voltage application situation can refer to the relevant description of the foregoing read state.

[0079] Based on the foregoing content, it can be known that the threshold voltage of the N - type storage sub - unit is positive and the N - type storage sub - unit conducts when the voltage is greater than the threshold voltage, while the threshold voltage of the P - type storage sub - unit is negative and the P - type storage sub - unit conducts when the voltage is less than the threshold voltage. Then, when performing voltage scanning, the scanning can start from 0V, and as the absolute value of the scanning voltage gradually increases. Thus, when the corresponding target storage sub - unit is turned on, the gate voltage value at this moment is the threshold voltage.

[0080] As Figure 4 shown, the threshold voltage adjustment process P400 may include the following steps:

[0081] S410. Determine a target storage sub - unit from N - type storage sub - units and P - type storage sub - units.

[0082] S420. Determine the current threshold voltage of the target storage sub - unit.

[0083] S430. Determine the target operation and the process parameters of the target operation from the write operation and the erase operation based on the desired threshold voltage and the current threshold voltage.

[0084] S440. Perform the target operation on the target storage sub - unit based on the process parameters of the target operation.

[0085] The aforementioned S410 is similar to the aforementioned S310 and will not be elaborated here. The aforementioned S420 can be implemented based on the steps of the aforementioned P400.

[0086] Continuing from the above, the aforementioned write threshold voltage can be understood as increasing the absolute value of the threshold voltage, and the erase threshold voltage can be understood as decreasing the absolute value of the threshold voltage. Then, after determining the desired threshold voltage, the voltage adjustment value (= desired threshold voltage - current threshold voltage) can be determined first. If it is positive, the absolute value of the threshold voltage needs to be increased, and a write operation can be used. If it is negative, the absolute value of the threshold voltage needs to be decreased, and an erase operation can be used.

[0087] Before the actual use of the storage device, the influence of different process parameters (such as process duration) on the threshold voltage can be calibrated through experiments. Then, when performing the aforementioned S430, appropriate process parameters can be determined based on the specific value of the aforementioned voltage adjustment value, so as to perform the corresponding target operation to adjust the threshold voltage of the target storage sub - unit from the current threshold voltage to the desired threshold voltage.

[0088] In some embodiments, after performing the aforementioned adjustment operation, the threshold voltage can be detected again to determine whether the adjustment is completed. And when the adjustment is not completed, the aforementioned P400 is re - executed until the threshold voltage is adjusted to the desired threshold voltage.

[0089] In some embodiments, the adjustment of the threshold voltage can also be achieved by re - writing. That is, an erase operation can be first performed on the target storage sub - unit, and then a write operation is performed based on the desired threshold voltage, so that the threshold voltage of the target storage sub - unit is the desired threshold voltage.

[0090] Exemplary manufacturing method of the storage device:

[0091] To form the storage unit (such as storage unit 100) of the aforementioned storage device, the present application also provides a manufacturing method of the storage unit. The following will be combined with Figures 5 - 7 to illustrate the manufacturing method of the storage unit. Among them, Figure 5 reflects the flowchart of the manufacturing method. Figure 6 can reflect the substrate for processing. Figure 7 can reflect the substrate with a lead dielectric layer.

[0092] As shown Figure 5 in, the process P500 of the preparation method may include the following steps:

[0093] S510. Provide a substrate.

[0094] S520. Deposit a lead dielectric layer on the substrate.

[0095] S530. Etch the lead dielectric layer to form a lead groove penetrating the lead dielectric layer.

[0096] S540. Fill the lead groove to form a control lead of the memory device.

[0097] The substrate in the foregoing S510 may be provided with N-type memory sub-units, P-type memory sub-units, and isolation trenches. As shown Figure 6 in, an N-type memory sub-unit 110, a P-type memory sub-unit 120, and an isolation trench 130 are provided on the substrate 160.

[0098] Among them, the substrate 160 may be processed by metal ion doping to form a P-type doped substrate (i.e., P-Well) at the N-type memory sub-unit 110 and an N-type doped substrate (i.e., N-Well) at the P-type memory sub-unit 120.

[0099] This application does not limit the preparation method of the substrate 160, which can be implemented according to the existing semiconductor (especially CMOS) preparation process. As long as it can provide suitable N-type memory sub-units 110, P-type memory sub-units 120, and isolation trenches 130.

[0100] For example, two N-type lightly doped regions (NLDD) may be formed in the N-type memory sub-unit 110 of the substrate 160, and an N-type doped region (N+) is formed on the N-type lightly doped region. The N-type doped region may serve as an N-type source electrode and an N-type drain electrode (the N-type drain electrode is close to the isolation trench 130). Similarly, the P-type memory sub-unit 120 may form a P-type lightly doped region (PLDD) on the N-type substrate and is further provided with a P-type doped region (P+).

[0101] To further optimize the lead performance, a metal silicide layer (such as a low-resistance NIPTSi2, abbreviated as NISI) layer may be formed on the surface of the region to be connected to the lead to optimize the lead performance. Specifically, Figure 6 in, an NISI layer may be formed on the surfaces of the source electrode, the drain electrode, and the gate electrode (i.e., the control gate). Among them, the control gate may be formed of polysilicon and is denoted as a polycrystalline control gate (Poly Control Gate).

[0102] In addition, an isolation layer formed of silicon nitride and oxide can be provided between the control gate and the floating gate, and on the side of the control gate, which is not shown in Figure 6 The foregoing structures (such as lightly doped regions, NISI, isolation layers, etc.) can be implemented based on the prior art and will not be elaborated here.

[0103] Based on Figure 6 the substrate shown, silicon oxide can be deposited to form a lead dielectric layer. Among them, considering the thickness of the lead dielectric layer, when forming the lead dielectric layer, chemical vapor deposition (such as depositing 200A) can be performed first, and then ILD deposition (such as depositing 2100A) can be performed. Considering Figure 5 the uneven deposition surface shown, chemical mechanical polishing (CMP) treatment can be performed after redeposition to form a flat surface.

[0104] After redepositing to form the lead dielectric layer, the lead positions in the lead dielectric layer can be etched to form lead grooves penetrating the lead dielectric layer corresponding to each lead position (such as Figure 7 ). As Figure 7 shown, a lead dielectric layer 170 is formed on the substrate 160, and a plurality of lead grooves 171 are formed in the lead dielectric layer 170.

[0105] In particular, in the present application, considering the common drain design of the N-type storage sub-unit 110 and the P-type storage sub-unit 120, the lead groove can be formed as a groove that straddles the isolation trench 130 and exposes the drains of the N-type storage sub-unit 110 and the P-type storage sub-unit 120.

[0106] In some embodiments, considering that the connection of the drains of the foregoing N-type storage sub-unit 110 and P-type storage sub-unit 120 can also be achieved through a drain connection structure. Then, the drain connection structure can be formed first after the foregoing S510, and then the subsequent steps can be executed. At this time, the width of the lead corresponding to the drain connection structure can be determined based on the conventional setting and does not need to straddle the isolation trench.

[0107] In some embodiments, the foregoing S530 can be executed through a mask layer. Exemplarily, 1900A of a-C (diamond-like carbon film) can be deposited on the foregoing lead dielectric layer, then an anti-reflection coating (220A of ARC SION + 50A of oxide (OX)) can be deposited, and finally 200A of a bottom anti-reflection coating (BARC) can be deposited, and finally 1000A of photoresist can be coated. Then, the photoresist is exposed and developed based on the lead positions to expose the surface to be etched (that is, this area is not coated with photoresist).

[0108] Based on the foregoing mask layer, multi-step etching can be performed to obtain the foregoing Figure 7The results shown. Among them, after etching, the residual polymer in the groove can be cleaned.

[0109] Based on Figure 7 the structure shown, performing the aforementioned S540 can form a control lead to form Figure 2 the storage unit shown. Among them, when forming the control lead, it is generally necessary to deposit metal on the aforementioned lead groove 171 and grind the surface to form the corresponding lead. Specifically, 100A of titanium (TI) and 50A of titanium nitride (TIN) can be deposited first, then tungsten (W) is filled, and chemical mechanical polishing is performed to form the aforementioned Figure 2 structure shown.

[0110] Based on the aforementioned process, each storage unit of the storage device provided by the present application can be formed. Subsequently, a specific wire drawing and wiring process can be performed to prepare the corresponding storage chip. More content about the subsequent process will not be elaborated here.

[0111] Exemplary storage structure:

[0112] To further optimize the performance of the storage unit, the present application also optimizes the specific structure of each specific storage sub-unit. Specifically, the floating gate in the aforementioned storage sub-unit can adopt an embedded structure and be embedded in the substrate, thereby increasing the contact area between the floating gate and the substrate and improving its ability to attract electrons / holes.

[0113] Thus, the present application also provides a storage structure ( Figure 8 ) where both the aforementioned P-type storage sub-unit and N-type storage sub-unit can adopt this design (for the storage device adopting this design, reference can be made to Figure 10 ) to improve the threshold voltage write / erase speed.

[0114] As Figure 8 shown, the storage structure 200 can include a doped substrate 210, a source electrode 220, a drain electrode 230, a control gate 240, and a floating gate 250. The source electrode 220 and the drain electrode 230 are disposed at both ends of the doped substrate 210, and the control gate 240 is disposed between the source electrode 220 and the drain electrode 230. The floating gate 250 is disposed below the control gate 240 and is embedded in the doped substrate 210. The floating gate 250 includes at least two extending portions 251, and the at least two extending portions 251 extend into the substrate.

[0115] Among them, the foregoing doped substrate 210, source electrode 220, and drain electrode 230 can be determined according to the actual type. If the foregoing storage structure 200 is configured as a P-type storage sub-unit, the foregoing doped substrate 210 can be an N-type doped substrate, and the source electrode 220 and drain electrode 230 can be constructed based on P-type doped regions on the surface of the N-type doped substrate. If the foregoing storage structure 200 is configured as an N-type storage sub-unit, the foregoing doped substrate 210 can be a P-type doped substrate, and the source electrode 220 and drain electrode 230 can be constructed based on N-type doped regions on the surface of the P-type doped substrate.

[0116] The foregoing floating gate 250 being embedded in the doped substrate 210 can mean that at least a part of the structure of the floating gate 250 is disposed within the doped substrate 210. As Figure 8 shown, the extension portion 251 of the floating gate 250 can be completely disposed within the doped substrate 210.

[0117] The extension portion 251 generally presents as a filling structure of a trench in the doped substrate 210. That is, to form the extension portion 251, a plurality of trenches can be formed in the doped substrate 210, so as to form the floating gate 250 by filling in the trenches, and the filling structure corresponding to the trench in the floating gate 250 is denoted as the extension portion 251.

[0118] When the floating gate 250 sucks in electrons / holes, the foregoing extension portion 251 and the doped substrate 210 can form a relatively large contact area, thereby improving the efficiency of the foregoing sucking-in process.

[0119] In some embodiments, to connect the foregoing at least two extension portions 251, the floating gate 250 can further include a connection structure for the extension portions 251. This connection structure can connect each of the extension portions 251. Specifically, it can be disposed at various parts of the extension portion 251 according to needs.

[0120] In some embodiments, for the convenience of corresponding to the control gate 240, the foregoing connection structure can be disposed close to the control gate 240. That is, the floating gate 250 can further include a connection portion 252. The connection portion 252 is disposed below the control gate 240 (i.e., close to the control gate 240 and far from the bottom surface of the doped substrate 210), and includes a driving surface 2521 facing the control gate 240 and an extension surface 2522 facing the substrate. At least two extension portions 251 extend from the extension surface 2522 in a direction away from the connection portion 252 towards the substrate (such as the bottom surface of the doped substrate 210).

[0121] In some embodiments, considering the nature of the control gate 240, isolation structures should be formed on both its side and bottom surfaces. Also, considering that the control gate 240 is generally disposed above the doped substrate 210, its side is generally the drain lead 231 and the source lead 221. To ensure the electrical properties of the control gate 240, a first isolation layer 241 is provided between the control gate 240 and the floating gate 250, and a second isolation layer 242 is provided between the control gate 240 and the source lead 221. A second isolation layer 242 is also provided between the control gate 240 and the drain lead 231. Among them, both the first isolation layer 241 and the second isolation layer 242 include at least one oxide isolation layer (such as silicon oxide) and at least one nitride isolation layer.

[0122] Exemplarily, the first isolation layer 241 includes one layer of silicon oxide and one layer of silicon nitride. The second isolation layer 242 includes three layers of silicon oxide and two layers of silicon nitride.

[0123] To further improve the anti-interference ability of the floating gate, the floating gate 250 can be completely embedded in the aforementioned doped substrate 210. For this purpose, the present application also provides a structural schematic diagram of another storage structure ( Figure 9 ).

[0124] As Figure 9 shown, the connecting portion 252 of the floating gate 250 is embedded in the doped substrate 210, making the driving surface 2521 flush with the substrate surface of the doped substrate 210.

[0125] Thus, the floating gate 250 is completely sunk into the doped substrate 210 to store signals. On the one hand, burying the floating gate 250 increases the anti-interference ability of the device. On the other hand, increasing the contact area between the floating gate 250 and the doped substrate 210 (such as the side surface of the connecting portion 252), signals can be written into the floating gate 250 from multiple dimensions, thereby increasing the writing speed. At the same time, the channel length of the semiconductor device is increased, avoiding the short-channel effect caused by the reduction of the device size due to process progress.

[0126] Alternatively, the aforementioned connecting portion 252 can be further embedded in the doped substrate 210, so that the first isolation layer or the control gate is embedded in the doped substrate 210.

[0127] In some embodiments, the aforementioned Figure 9 shown storage structure can be combined with the aforementioned Figure 2 shown storage device. At this time, the structure of the storage device can be referred to Figure 10 . That is Figure 10 in, the N-type gate of the N-type storage sub-unit and the P-type gate of the P-type storage sub-unit both present the combination of the embedded floating gate and the control gate as Figure 9 shown.

[0128] In some embodiments, the present application also provides aFigure 9 The manufacturing method of the storage structure shown. When forming Figure 9 the storage structure shown, it can be achieved through the following steps:

[0129] First, provide a substrate and form isolation trenches on the substrate. Among them, the substrate is generally a silicon substrate, and the isolation trenches can be achieved by etching based on a mask layer and filling with silicon oxide, which will not be elaborated here.

[0130] Next, perform ion doping on the substrate to form a doped substrate. Among them, the specific doping ions can be selected according to actual needs. For the combination of the aforementioned PMOS and NMOS, step-by-step doping can be performed based on a mask layer.

[0131] Next, etch the substrate to form a first trench. Among them, the first trench corresponds to the connection part 252 mentioned above, and it can also be achieved by mask etching. Figure 9 in.

[0132] Next, etch the first trench to form at least two second trenches. Among them, the second trenches correspond to Figure 9 the extension part 251 in, and are formed on the basis of the aforementioned first trench, and it can also be achieved by mask etching.

[0133] Next, fill the first trench and the second trenches to form a floating gate. When filling the floating gate, a gate oxide layer (about 23A) can be formed first, then polysilicon (poly) is deposited, and chemical mechanical polishing is performed.

[0134] Next, form a control gate and a first isolation layer between the control gate and the floating gate. When performing, an isolation layer (first a layer of silicon oxide and then a layer of silicon nitride) and the polysilicon of the control gate can be deposited first. Then, mask etching is used to form the control gate and the first isolation layer.

[0135] Next, source and drain electrodes can be formed. Specifically, a lightly doped region can be formed first and then a doped region. Among them, PLDD is generally achieved by sequentially injecting Ge, C, and AS (pockect) to a certain depth. NLDD is generally achieved by sequentially injecting Ge, C, and B (pockect) to a certain depth. The N+ region is mainly sequentially injected with P\GE\P\As\F to a certain depth. The P+ region is mainly sequentially injected with Ge\B\BF2 to a certain depth.

[0136] Next, a metal silicide layer (such as low-resistance NIPTSi2, abbreviated as NISI) is formed on the surfaces of the source, drain, and control gate.

[0137] Subsequently, subsequent processing can be referred to the aforementioned Figure 5 manufacturing process, which will not be elaborated here.

[0138] In some embodiments, the second isolation layer on the side of the control gate can be formed during the process of forming the source and drain. For example, a layer of silicon oxide can be first formed on the side of the control gate, then a layer of silicon nitride is formed on the side, and then the preparation process of the aforementioned lightly doped region is performed. After completing this preparation process, a layer of silicon oxide and a layer of silicon nitride are formed on the side of the control gate, and in the subsequent lead process, another layer of silicon oxide (i.e., part of the dielectric material is retained on the side) is formed to form the second isolation layer.

[0139] Technical effects:

[0140] In summary, in the storage device, its control method and manufacturing method provided by the present application, the following unexpected effects are achieved:

[0141] ① A storage unit of the storage device provided by the present application has two sub-units and is interconnected through the drain. By configuring different voltage signals, the threshold voltages stored in each sub-unit can be independently read, so that each sub-unit has an independent storage capacity, thereby improving the storage capacity of a single storage unit in the storage device and enabling the storage device to store more information.

[0142] ② The two sub-units in a storage unit can be a P-type storage sub-unit and an N-type storage sub-unit respectively, forming a complementary semiconductor structure, thus having better electrical performance and stability.

[0143] ③ Each storage sub-unit can be set based on the floating gate, so that non-volatile multiple compilations can be achieved, different working voltages can be realized, and the working voltage after writing can also be erased according to requirements.

[0144] ④ The aforementioned storage unit is provided with a P-type storage sub-unit and an N-type storage sub-unit. Different data have different storage effects to adapt to different storage requirements.

[0145] ⑤ The present application also optimizes the read-write-erase process of the storage unit. Especially when the threshold voltage changes, an operation can be directly performed according to the adjusted threshold voltage, which improves the speed of the threshold voltage change process.

[0146] ⑥ The present application optimizes the floating gate structure so that the floating gate structure has multiple extension parts extending towards the substrate, thereby increasing the contact area between the floating gate and the substrate and increasing the writing speed.

[0147] ⑦ By setting the extension parts, the channel length of the semiconductor device is also increased, avoiding the short-channel effect caused by the reduction of the device size due to the progress of the process.

[0148] ⑧ The floating gate of the present application can completely sink into the doped substrate to store signals. Thereby, the anti-interference ability of the device is increased by burying the floating gate, and the contact area between the floating gate and the doped substrate (such as the side surface of the connecting portion) is further increased. Signals can be written into the floating gate from multiple dimensions, thereby increasing the writing speed.

[0149] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A storage device, characterized in that, The storage device includes a plurality of memory cells, and the memory cells include: An N-type memory sub-cell, disposed on a first side of an isolation trench in a substrate and an N-type drain of the N-type memory sub-cell is close to the isolation trench; A P-type memory sub-cell, disposed on a second side of the isolation trench in the substrate and a P-type drain of the P-type memory sub-cell is close to the isolation trench; and Control leads, the control leads include a common drain lead connected to both the N-type drain and the P-type drain, an N-type source lead connected to an N-type source of the N-type memory sub-cell, an N-type gate lead connected to an N-type gate of the N-type memory sub-cell, a P-type source lead connected to a P-type source of the P-type memory sub-cell, and a P-type gate lead connected to a P-type gate of the P-type memory sub-cell; The N-type gate of the N-type memory sub-cell and the P-type gate of the P-type memory sub-cell both include a control gate and a floating gate, the control gate is electrically connected to the gate lead and is disposed between the source lead and the drain lead, and the floating gate is disposed below the control gate and is embedded in the substrate; When the memory cell is in an N-type write state, electrons are sucked into the floating gate of the N-type memory sub-cell to form a threshold voltage, and in the N-type write state, the positive voltage amplitude at the N-type gate lead is greater than the positive voltage amplitude at the substrate of the P-type memory sub-cell and greater than the positive voltage amplitude at the common drain lead; When the memory cell is in a P-type write state, holes are sucked into the floating gate of the P-type memory sub-cell to form a threshold voltage, and in the P-type write state, the negative voltage amplitude at the P-type gate lead is greater than the negative voltage amplitude at the substrate of the N-type memory sub-cell and greater than the negative voltage amplitude at the common drain lead.

2. The storage device according to claim 1, characterized in that, The floating gate includes at least two extending portions, and the at least two extending portions extend into the substrate.

3. The storage device according to claim 2, characterized in that, The floating gate further includes a connecting portion, the connecting portion is disposed below the control gate, includes a driving surface facing the control gate and an extending surface facing the substrate, and the at least two extending portions extend from the extending surface into the substrate in a direction away from the connecting portion.

4. The storage device according to claim 3, characterized in that The connecting portion is embedded in the substrate to make the driving surface flush with the substrate surface of the substrate.

5. The storage device according to claim 2, wherein A first isolation layer is disposed between the control gate and the floating gate, a second isolation layer is disposed between the control gate and the source lead, and the second isolation layer is disposed between the control gate and the drain lead. Among them, the first isolation layer and the second isolation layer both include at least one oxide isolation layer and at least one silicon nitride isolation layer.

6. The storage device according to claim 1, wherein The storage device further includes a drain connection structure that spans the isolation trench to connect the P-type drain and the N-type drain, and the common drain lead is electrically connected to the drain connection structure to be connected to both the P-type drain and the N-type drain simultaneously.

7. The storage device according to claim 1, characterized in that, The common drain lead laterally spans the isolation trench to be connected to both the P-type drain and the N-type drain simultaneously.

8. A control method for a storage device, characterized in that Applied to the storage device described in any one of claims 1 to 7, the control method includes a method for reading the threshold voltage from a target storage sub-unit among the N-type storage sub-units and P-type storage sub-units of a storage cell, including: Controlling the storage cell to be in the read state corresponding to the target storage sub-unit; Applying a scanning voltage to the gate lead of the target storage sub-unit; In response to the source and drain of the target storage sub-unit being turned on, determining the actual scanning voltage at the turn-on moment and using it as the threshold voltage.

9. The control method according to claim 8, wherein The control method further includes; Determining the current threshold voltage of the target storage sub-unit; Determining a target operation and process parameters of the target operation from write operations and erase operations based on the desired threshold voltage and the current threshold voltage; Performing the target operation on the target storage sub-unit based on the process parameters of the target operation.

10. A method for manufacturing a storage device, characterized in that, The preparation method includes: Providing a substrate, wherein the substrate includes N-type storage sub-units, P-type storage sub-units, and isolation trenches. The N-type storage sub-units and the P-type storage sub-units are arranged on both sides of the isolation trench. The N-type drain of the N-type storage sub-unit is close to the isolation trench, and the P-type drain of the P-type storage sub-unit is close to the isolation trench. The N-type gate of the N-type storage sub-unit and the P-type gate of the P-type storage sub-unit both include a control gate and a floating gate. The control gate is electrically connected to the gate lead and is arranged between the source lead and the drain lead. The floating gate is arranged below the control gate and is embedded in the substrate; Depositing a lead dielectric layer on the substrate; Etching the lead dielectric layer to form a lead groove penetrating the lead dielectric layer; Filling the lead groove to form the control leads of the storage device, wherein the control leads include a common drain lead connected to both the N-type drain and the P-type drain, an N-type source lead connected to the N-type source of the N-type storage sub-unit, an N-type gate lead connected to the N-type gate of the N-type storage sub-unit, a P-type source lead connected to the P-type source of the P-type storage sub-unit, and a P-type gate lead connected to the P-type gate of the P-type storage sub-unit. The storage device includes a plurality of storage cells, and the storage cell includes the N-type storage sub-unit, the P-type storage sub-unit, and the control leads; When the storage cell is in the N-type write state, electrons are sucked into the floating gate of the N-type storage sub-unit to form a threshold voltage, and in the N-type write state, the positive voltage amplitude at the N-type gate lead is greater than the positive voltage amplitude at the substrate of the P-type storage sub-unit, which is greater than the positive voltage amplitude at the common drain lead; When the storage cell is in the P-type write state, holes are sucked into the floating gate of the P-type storage sub-unit to form a threshold voltage, and in the P-type write state, the negative voltage amplitude at the P-type gate lead is greater than the negative voltage amplitude at the substrate of the N-type storage sub-unit, which is greater than the negative voltage amplitude at the common drain lead.

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