SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device for enhancing gate oxide reliability and preparation method

Abstract

The invention discloses a SiC MOSFET device for enhancing gate oxide reliability and a preparation method, and relates to the technical field of semiconductors. The P + region and the gate bottom oxide layer are sequentially formed in the N-region, the gate bottom oxide layer can remarkably improve the reliability of the gate oxide bottom under the condition that the on resistance of the device is not affected, and the gate bottom oxide layer can also reduce the Crss stray capacitance of a chip, so that high-frequency application of the device is facilitated; and the P + region is utilized to shield the electric field at the bottom of the gate oxide, so that the gate oxide reliability can be further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC MOSFET device with enhanced gate oxide reliability and a preparation method thereof. Background Art

[0002] Silicon carbide metal oxide semiconductor field effect transistor SiC MOSFET has the characteristics of low on-resistance, high frequency, high voltage, etc. and is widely used in electric vehicles, rail transportation, smart grids and other fields, and has become one of the hot spots in current power device research. However, compared with Si IGBT, the defect density of SiC / SiO2 interface is 1-2 orders of magnitude higher than that of Si / SiO2. The higher defect density will cause a significant reduction in the quality of gate oxide, resulting in serious reliability problems in the actual application of the device. This has become a key bottleneck for the large-scale practical application of SiC MOSFET devices.

[0003] SiC MOSFET is divided into planar type and trench type. Although planar silicon carbide MOS has simple process, good cell consistency and high avalanche energy, when the current is confined to the narrow N region near the P body region, it will produce JFET effect, increase the on-state resistance, and have large parasitic capacitance. Therefore, how to solve the gate oxide quality, JFET effect and parasitic capacitance of SiCMOSFET is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above problems, the present invention provides a SiC MOSFET device and a preparation method for improving gate oxide reliability, which can improve gate oxide bottom reliability and reduce chip Crss parasitic capacitance.

[0005] The technical solution of the present invention is: A method for preparing a SiC MOSFET device with enhanced gate oxide reliability comprises the following steps: S100, in N + The N-type buffer layer and N-type - drift layer; S200, in N - The top surface of the drift layer is formed by ion implantation of N - Area, and in N - A P-well region is formed inside the region by ion implantation; S300, sequentially forming a connected NP region and a PP region on the top surface of the P-well region by ion implantation; S400, in N - The top surface of the region is dry-etched to form a trench region, and P + region and gate bottom oxide layer; S500, forming a gate oxide layer on the sidewall and top of the trench region by thermal oxidation; S600, forming a T-shaped Poly layer on the gate bottom oxide layer and the gate oxide layer by multiple depositions to be led out as a gate electrode; S700, forming a dielectric layer on the Poly layer by deposition to isolate the gate electrode and the source electrode metal; S800, forming a source ohmic contact alloy layer on the NP region and the PP region by metal sputtering, and then completing metallization annealing; S900, forming a source metal layer on the dielectric layer and the source ohmic contact alloy layer as a source electrode lead; S1000, in N + The substrate layer is thinned, and a drain metal layer is formed by sputtering and metal evaporation to be led out as a drain electrode.

[0006] Specifically, in step S100, N + The substrate layer is doped with N ions with a doping concentration of 1e 19 cm -2 ±10%.

[0007] Specifically, in step S100, the N-type buffer layer is doped with N ions at a doping concentration of 1e 18 cm -2 ±10%.

[0008] Specifically, in step S100, N - The drift layer is doped with N ions with a doping concentration of 8e 15 -2e 16 cm -2 , thickness is 5-15um.

[0009] Specifically, in step S200, N - The N ion doping concentration is 5e 16 -1e 17 cm -2 , the P-well region is doped with Al ions, and the doping concentration is 1e 17 -1e 18 cm -2 .

[0010] Specifically, in step S300, the NP region is doped with N ions at a doping concentration of 1e 18 -1e 19 cm -2 ; The PP region is doped with Al ions at a doping concentration of 1e 18 -1e 19 cm -2 .

[0011] Specifically, in step S400, P+ The region is doped with Al ions, and the doping concentration is 1e 18 -1e 19 cm -2 .

[0012] Specifically, in step S400 , the thickness of the gate oxide layer is between 40 nm and 60 nm.

[0013] Specifically, in step S400, the thickness of the gate bottom oxide layer is between 200-500 nm.

[0014] A SiC MOSFET device with enhanced gate oxide reliability, comprising a drain metal layer, an N + Substrate layer, N-type buffer layer, N - A drift layer, a source ohmic contact alloy layer and a source metal layer; The N - The drift layer contains: N - Area, from the N - The top surface of the drift layer extends downward, with the N - A spacing is provided between the bottom surfaces of the drift layers; The P-well area has several - The top surface of the zone extends downward; NP regions, provided with a plurality of NP regions, extending downward from the top surface of the P-well region respectively; A PP region is provided, each extending downward from the top surface of the P-well region and located at the side of the NP region; P + area, located in the N - The bottom surface of the N - Drift layer connection; The gate bottom oxide layer is located at the P + Top surface of the area; The gate oxide layer is provided with a pair of gate oxide layers, which pass through the NP region, the P-well region and the N - The top surface of the region extends downward to the top surface of the gate bottom oxide layer; A Poly layer covers the gate bottom oxide layer (10) and the top surface of the gate oxide layer; a dielectric layer is provided on the top surface of the Poly layer, and the side of the dielectric layer extends downward to the top surface of the NP region.

[0015] The present invention improves the gate oxide quality of SiC MOSFET devices: The first step of the gate oxide structure is to form a gate bottom oxide layer using a deposition process, and then the second step is to form a gate oxide layer structure using a dry oxygen thermal oxidation process. The gate bottom oxide layer can significantly improve the reliability of the gate bottom without affecting the on-resistance of the device, and the gate bottom oxide layer can also reduce the Crss parasitic capacitance of the chip, which is beneficial to the high-frequency application of the device; then use P + The electric field at the bottom of the gate oxide can be shielded in the region, which can further improve the gate oxide reliability.

[0016] The present invention improves the JEFT region current-carrying capacity of SiC MOSFET devices: The L-shaped gate oxide layer is used. The horizontal part of the gate oxide layer is responsible for the channel switch. The structure is the same as that of the conventional device. However, during the opening process, the vertical part of the gate electrode will attract electrons to gather, increase the carrier concentration in the JEFT region, improve the current capacity, and improve the JEFT effect in the working state; during the shutdown process, the vertical part of the gate electrode will repel electrons, reducing the N - The concentration of the region can also reduce the leakage between the source and drain electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural schematic diagram of step S100 of the present invention; Figure 2 It is a structural schematic diagram of step S200 of the present invention; Figure 3 It is a structural schematic diagram of step S300 of the present invention; Figure 4 is a schematic structural diagram of step S400 of the present invention; Figure 5 is a schematic structural diagram of step S500 of the present invention; Figure 6 is a schematic diagram of the structure of step S600 of the present invention; Figure 7 is a schematic diagram of the structure of step S700 of the present invention; Figure 8 is a structural schematic diagram of step S800 of the present invention; Fig. 9 is a structural schematic diagram of step S900 of the present invention; Fig.10 is a structural schematic diagram of step S1000 of the present invention; Fig.11 is a structural schematic diagram of step S1100 of the present invention; Fig.12 is a schematic diagram of the structure of step S1200 of the present invention; Fig.13 is a schematic diagram of the structure of step S1300 of the present invention; Fig.14It is a structural schematic diagram of step S1400 of the present invention; Fig.15 It is a structural schematic diagram of step S1500 of the present invention; In the figure, 1 is N + Substrate layer, 2 is N-type buffer layer, 3 is N - Drift layer, 4 is N - area, 5 is the P-well area, 6 is the NP area, 7 is the PP area, 8 is the trench area, 9 is the P + Region, 10 is a gate bottom oxide layer, 11 is a gate oxide layer, 12 is a Poly layer, 13 is a dielectric layer, 14 is a source ohmic contact alloy layer, 15 is a source metal layer, and 16 is a drain metal layer. DETAILED DESCRIPTION

[0018] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0019] A method for preparing a SiC MOSFET device with enhanced gate oxide reliability comprises the following steps: S100, refer to Figure 1 As shown, in heavily doped N + An N-type buffer layer 2 is grown on the substrate layer 1; N in step S100 + Substrate layer 1 is doped with N ions, with a thickness of 360-400um and a doping concentration of 1e 19 cm -2 ±10%, the N-type buffer layer is also doped with N ions, with a thickness of 0.8-1.2um and a doping concentration of 1e 18 cm -2 ±10%.

[0020] S200, refer to Figure 2 As shown, a layer of N type buffer layer 2 is epitaxially grown. - Drift layer 3; Step S200 once N - The drift layer 3 is doped with N ions at a doping concentration of 8e 15 -1e 16 cm -2 , thickness is 5-15um.

[0021] S300, refer to Figure 3 As shown, in N - The top surface of the drift layer 3 is formed by ion implantation of N - Zone 4; N in step S300 -Region 4 is doped with N ions at a doping concentration of 5e 16 -1e 17 cm -2 .

[0022] S400, refer to Figure 4 As shown, in N - A P-well region 5 is formed on the top surface of region 4 by ion implantation; The P-well region 5 in step S300 is doped with Al ions at a doping concentration of 1e 17 -1e 18 cm -2 .

[0023] S500, refer to Figure 5 As shown, an NP region 6 is formed on the top surface of the P-well region 5 by ion implantation; The NP region 6 in step S500 is doped with N ions at a doping concentration of 1e 18 -1e 19 cm -2 , the implantation depth is less than the depth of P-well region 5.

[0024] S600, refer to Figure 6 As shown, a PP region 7 connected to the NP region 6 is formed on the top surface of the P-well region 5 by ion implantation; The PP region 7 in step S600 is doped with Al ions at a doping concentration of 1e 18 -1e 19 cm -2 , the implantation depth is less than the depth of P-well area 5 S700, reference Figure 7 As shown, a trench region 8 is formed on the upper surface of the P-well region 5 by dry etching; The etching depth of the trench region 8 in step S700 is less than the depth of the P-well region 5 .

[0025] S800, reference Figure 8 As shown, P is formed at the bottom of the trench region 8 by ion implantation. + Zone 9, high temperature ion activation after implantation; P in step S800 + Region 9 is doped with Al ions at a doping concentration of 1e 18 -1e 19 cm -2 , activation annealing temperature is 1650-1750℃, and annealing time is 10-30min.

[0026] S900, refer to Fig. 9 As shown, in P +The top surface of region 9 forms a gate bottom oxide layer 10 by depositing oxide; The thickness of the gate bottom oxide layer 10 in step S900 is 200-500 nm, which is much larger than the gate oxide layer 11 .

[0027] S1000, refer to Fig.10 As shown, a gate oxide layer 11 is formed on the sidewall and top of the trench region 8 by a dry oxygen thermal oxidation process, and a channel is formed at the interface with the P-well region 5; In step S1000 , the gate oxide layer 11 is grown at a temperature of 1250-1350° C. and a thickness of 40-60 nm. It needs to be annealed in a NO atmosphere at a temperature of 1250° C. for 1 hour to improve the compactness of the gate oxide layer 11 and reduce defects.

[0028] S1100, reference Fig.11 As shown, a Poly layer 12 is formed on the gate bottom oxide layer 10 and the gate oxide layer 11 by depositing polysilicon, and a gate electrode is led out; S1200, refer to Fig.12 As shown, a dielectric layer 13 is formed by depositing oxide on the Poly layer 12 to isolate the gate electrode and the source electrode metal; S1300, refer to Fig.13 As shown, a source ohmic contact alloy layer 14 is formed on the NP region 6 and the PP region 7 by sputtering Ni or other metals; In step S1300 , the source ohmic contact alloy layer 14 is annealed at a temperature of 1000° C. for 5 minutes to form an alloy and achieve an ohmic contact effect.

[0029] S1400, reference Fig.14 As shown, a source metal layer 15 is formed on the source ohmic contact alloy layer 14 and the dielectric layer 13 by sputtering Ti / AlCu or other metals to lead out the source electrode; S1500, refer to Fig.15 As shown, in N + The back side of the substrate layer 1 is thinned to reduce N + The substrate layer 1 is 1000 mm thick, and then Ni metal is sputtered and Ti / Ni / Ag metal is evaporated to form a drain metal layer 16 to lead out a drain electrode.

[0030] In step S1500, the drain metal layer 16 needs to be laser annealed after Ni metal sputtering, and the laser energy is 2-4mJ / cm 2 ; Later, multiple layers of metals such as Ti / Ni / Ag are evaporated, or other metals can be used, with a total thickness of 1.4-2um.

[0031] A SiC MOSFET device with enhanced gate oxide reliability, comprising a drain metal layer 16, an N + Substrate layer 1, N-type buffer layer 2, N - Drift layer 3, source ohmic contact alloy layer 14 and source metal layer 15; The N - The drift layer 3 is provided with: N - Zone 4, from the N - The top surface of the drift layer 3 extends downward, and the N - A gap is provided between the bottom surfaces of the drift layer 3; The P-well area 5 is provided with several - The top surface of region 4 extends downward and is connected to the N - The bottom surface of zone 4 is flat; A plurality of NP regions 6 are provided, each extending downward from the top surface of the P-well region 5 and having a spacing with the bottom surface of the P-well region 5; A plurality of PP regions 7 are provided, each extending downward from the top surface of the P-well region 5 and located at the side of the NP region 6; a gap is provided between the bottom surface of the PP region 7 and the bottom surface of the P-well region 5; P + Area 9, located in the N - In zone 4, the bottom surface is connected to the N - The bottom surface of zone 4 is flush; The gate bottom oxide layer 10 is located at the P + The top surface of the gate bottom oxide layer 10 is located at N - below the top surface of zone 4; The gate oxide layer 11 is provided with a pair of gate oxide layers, which respectively pass through the NP region 6, the P-well region 5 and the N - The top surface of the region 4 extends downward to the top surface of the gate bottom oxide layer 10; a pair of gate oxide layers 11 are provided with a spacing; in this case, the gate oxide layer 11 is in an L-shaped structure; The Poly layer 12 has a T-shaped cross section and covers the top surfaces of the gate bottom oxide layer 10 and the gate oxide layer 11 . A dielectric layer 13 is provided on the top surface of the Poly layer 12 , and the side of the dielectric layer 13 extends downward to the top surface of the NP region 6 .

[0032] The dielectric layer 13 is connected to the NP region 6, the gate oxide layer 11 and the Poly layer 12 respectively.

[0033] There are several source ohmic contact alloy layers 14 , which are respectively located at the sides of the dielectric layer 13 , and the bottom surfaces are respectively connected to the NP region 6 and the PP region 7 .

[0034] The bottom surface of the source metal layer 15 covers the source ohmic contact alloy layer 14 and the dielectric layer 13 .

[0035] The present invention improves the gate oxide quality of SiC MOSFET devices. In the first step, a thicker gate bottom oxide layer 10 (with a thickness of 200-500 nm) is formed by a deposition process. In the second step, a gate oxide layer 11 structure is formed by a dry oxygen thermal oxidation process. The thicker gate bottom oxide layer 10 can significantly improve the reliability of the gate oxide bottom without affecting the on-resistance of the device. The thicker gate bottom oxide layer 10 can also reduce the Crss parasitic capacitance of the chip, which is beneficial to the high-frequency application of the device. At the same time, P + Region 9 shields the electric field at the bottom of the gate oxide, further improving the gate oxide reliability.

[0036] In addition, the present invention also improves the flow capacity of the JEFT region of the SiC MOSFET device. This article adopts an L-shaped gate oxide layer 11, in which the horizontal part is responsible for the channel switch and has the same structure as the conventional planar SiC MOSFET device, but the vertical part of the gate electrode will also attract electrons to gather during the opening process, increase the carrier concentration in the JEFT region, improve the flow capacity, and improve the JEFT effect in the working state; during the shutdown process, the vertical part will repel electrons and reduce N - The concentration of the region can reduce the leakage between the source and drain electrodes.

Claims

1. A method for preparing a SiC MOSFET device with enhanced gate oxide reliability, characterized in that: The steps include: S100, in N + An N-type buffer layer (2) and an N-type - Drift layer (3); S200, in N - The top surface of the drift layer (3) is formed by ion implantation into N - Area (4), and in N - A P-well region (5) is formed inside the region (4) by ion implantation; S300, forming a connected NP region (6) and a PP region (7) in sequence on the top surface of the P-well region (5) by ion implantation; S400, in N - The top surface of the region (4) is dry-etched to form a trench region (8), and P + region (9) and a gate bottom oxide layer (10); S500, forming a gate oxide layer (11) on the sidewalls and top of the trench region (8) by thermal oxidation; S600, forming a T-shaped Poly layer (12) on the gate bottom oxide layer (10) and the gate oxide layer (11) by multiple depositions to serve as a gate electrode lead; S700, forming a dielectric layer (13) on the Poly layer (12) by deposition to isolate the gate electrode and the source electrode metal; S800, forming a source ohmic contact alloy layer (14) on the NP region (6) and the PP region (7) by metal sputtering, and then completing metallization annealing; S900, forming a source metal layer (15) on the dielectric layer (13) and the source ohmic contact alloy layer (14) as a source electrode lead; S1000, in N + The substrate layer (1) is thinned, and a drain metal layer (16) is formed by sputtering and metal evaporation to be led out as a drain electrode.

2. The method for preparing a SiC MOSFET device with enhanced gate oxide reliability according to claim 1, characterized in that: In step S100, N + The substrate layer (1) is doped with N ions at a doping concentration of 1e 19 cm -2 ±10%.

3. The method for preparing a SiC MOSFET device with enhanced gate oxide reliability according to claim 1, characterized in that: In step S100, the N-type buffer layer (2) is doped with N ions at a doping concentration of 1e 18 cm -2 ±10%.

4. The method for preparing a SiC MOSFET device with enhanced gate oxide reliability according to claim 1, characterized in that: In step S100, N - The drift layer (3) is doped with N ions at a doping concentration of 8e 15 -2e 16 cm -2 , thickness is 5-15um.

5. The method for preparing a SiC MOSFET device with enhanced gate oxide reliability according to claim 1, characterized in that: In step S200, N - Region (4) is doped with N ions at a concentration of 5e 16 -1e 17 cm -2 , the P-well region (5) is doped with Al ions at a doping concentration of 1e 17 -1e 18 cm -2 .

6. The method for preparing a SiC MOSFET device with enhanced gate oxide reliability according to claim 1, characterized in that: In step S300, the NP region (6) is doped with N ions at a doping concentration of 1e 18 -1e 19 cm -2 ; The PP region (7) is doped with Al ions at a doping concentration of 1e 18 -1e 19 cm -2 .

7. The method for preparing a SiC MOSFET device with enhanced gate oxide reliability according to claim 1, characterized in that: In step S400, + Region (9) is doped with Al ions at a concentration of 1e 18 -1e 19 cm -2 .

8. The method for preparing a SiC MOSFET device with enhanced gate oxide reliability according to claim 1, characterized in that: In step S400, the thickness of the gate oxide layer (11) is between 40-60 nm.

9. The method for preparing a SiC MOSFET device with enhanced gate oxide reliability according to claim 1, characterized in that: In step S400, the thickness of the gate bottom oxide layer (10) is between 200-500 nm.

10. A SiC MOSFET device with enhanced gate oxygen reliability, prepared by the method for preparing a SiC MOSFET device with enhanced gate oxygen reliability according to any one of claims 1 to 9, characterized in that: The drain metal layer (16), N + Substrate layer (1), N-type buffer layer (2), N - A drift layer (3), a source ohmic contact alloy layer (14) and a source metal layer (15); The N - The drift layer (3) is provided with: N - Area (4), from the N - The top surface of the drift layer (3) extends downward, and the N - A gap is provided between the bottom surfaces of the drift layer (3); The P-well area (5) is provided with a plurality of - The top surface of zone (4) extends downward; A plurality of NP regions (6) are provided, each extending downward from the top surface of the P-well region (5); A PP area (7) is provided, each of which extends downward from the top surface of the P-well area (5) and is located at the side of the NP area (6); P + Area (9), located in the N - In area (4), the bottom surface is connected to the N - Drift layer (3) connection; The gate bottom oxide layer (10) is located at the P + Area (9) top surface; The gate oxide layer (11) is provided with a pair of gate oxide layers, which respectively pass through the NP region (6), the P-well region (5) and the N - The top surface of the region (4) extends downward to the top surface of the gate bottom oxide layer (10); A Poly layer (12) covers the top surfaces of the gate bottom oxide layer (10) and the gate oxide layer (11); a dielectric layer (13) is provided on the top surface of the Poly layer (12), and a side portion of the dielectric layer (13) extends downward to the top surface of the NP region (6).

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