SiCVD MOSFET structure with high-temperature reliability and preparation method thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a SiCVD MOSFET structure with high-temperature reliability, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, a P well layer I, a heavily doped P layer and an N well layer are arranged in the semiconductor epitaxial layer, a second P-well layer and a first heavily doped N layer are arranged on one side of the N-well layer and close to the grid electrode, and the second P-well layer is located between the N-well layer and the first heavily doped N layer. The section contour of the grid electrode is in a T shape, the first heavily-doped N layer further comprises a third heavily-doped N layer, and the third heavily-doped N layer is in contact with the N drift layer. Through the T-shaped gate structure, heat in a gate region can be more uniformly distributed, the heat is prevented from being concentrated at a certain point, and device faults or degradation caused by local high temperature is reduced; moreover, the T-shaped gate structure can optimize the gate resistance and reduce the current required by gate driving.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a SiCVDMOSFET structure with high temperature reliability and a preparation method thereof. Background Art

[0002] The preparation method of high temperature reliability SiC VDMOSFET (vertical bipolar metal oxide semiconductor field effect transistor) involves several key steps. SiC (silicon carbide) as a material has high thermal conductivity, wide bandgap and high breakdown voltage, and is suitable for high temperature, high power and high frequency applications.

[0003] The existing patent discloses a SiC VDMOSFET structure with high power and high temperature reliability (publication number CN118969842A), including a drain, an N+ substrate is arranged above the drain, an N-drift region is arranged above the N+ substrate, a SiO2 passivation layer is located above the gate oxide layer and the gate, three groups of trench buffers are arranged on the P-well region, the three groups of trench buffers are connected, and a variable resistor V is arranged in the N-drift region. In the technology disclosed in the existing patent, in a high temperature environment, the carriers in the drift layer are more active, resulting in insufficient carriers, which increases the resistance of the channel area. In addition, there is a lack of a simple and clear method for judging the high temperature performance of MOS devices. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a SiCVDMOSFET structure with high temperature reliability and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a SiCVDMOSFET structure with high temperature reliability includes a drain, a semiconductor epitaxial layer, a source, a gate, and a gate oxide layer covering the surface of the gate, wherein an N substrate layer, an N drift layer, a P well layer 1, a heavily doped P layer, and an N well layer are arranged inside the semiconductor epitaxial layer, a P well layer 2 and a heavily doped N layer 1 are arranged on one side of the N well layer and close to the gate, and the P well layer 2 is located between the N well layer and the heavily doped N layer 1; The cross-sectional profile of the gate is in a 'T' shape.

[0006] Furthermore, the heavily doped N layer 1 further includes a heavily doped N layer 3, wherein the heavily doped N layer 3 is in contact with the N drift layer.

[0007] Furthermore, a T-shaped groove is etched at the bottom of the gate, wherein the interior of the T-shaped groove is filled with a filling medium.

[0008] Furthermore, the filling medium is one of SiO, P-type polysilicon or N-type polysilicon.

[0009] Furthermore, a heavily doped N layer 2 is formed inside the N drift layer by ion implantation, the cross-sectional profile of the heavily doped N layer 2 is in a 'U' shape, and the cross-sectional thickness of the heavily doped N layer 2 is the same as that of the heavily doped N layer 1.

[0010] A method for preparing a SiCVD MOSFET structure with high temperature reliability comprises the following steps: S1, substrate preparation and substrate surface treatment; S2, gate region doping, and source / drain region formation; S3, gate metallization and source-drain metallization form a SiC VDMOSFET structure; S4. Perform high temperature stress test on SiC VDMOSFET structure to verify the long-term reliability of the device under high temperature conditions.

[0011] Furthermore, in the step S2, phosphorus impurities are doped by ion implantation to form a heavily doped N layer 1.

[0012] Furthermore, in step S4, the high temperature reliability of the SiCVDMOSFET structure is determined according to the change in leakage current after the SiCVDMOSFET structure is heated by 60°C at room temperature, the change in on-resistance after the SiCVDMOSFET structure is heated by 100°C at room temperature, and the temperature change after continuous operation for 5 hours at a voltage exceeding the threshold voltage by 20%, and the following are obtained: In the formula, represents the high temperature reliability coefficient of the tested SiCVDMOSFET structure, The larger the value, the better the high temperature performance of the SiCVDMOSFET structure; Indicates the change in leakage current after the temperature rises by 60°C under normal temperature environment; It indicates the change in on-resistance after the temperature rises by 100°C under normal temperature environment; Indicates the temperature change after continuous operation for 5 hours at a voltage 20% higher than the threshold voltage.

[0013] Furthermore, when When , it means that the SiCVDMOSFET structure tested has excellent high temperature reliability.

[0014] Beneficial effects: 1. The present invention can greatly improve the stability of the device through the design of double channels in series, avoiding the risk of the device being broken down in a high temperature environment.

[0015] 2. The present invention can help distribute the heat in the gate area more evenly through the T-shaped gate structure, avoid heat concentration at a certain point, and reduce device failure or degradation due to local high temperature; and the T-shaped gate structure can usually optimize the gate resistance and reduce the current required for gate drive.

[0016] 3. The present invention enables SiC VDMOSFET to work more effectively at high power density by filling dielectric, reducing heat loss and improving power conversion efficiency. Especially in high temperature environment, the optimization of filling dielectric can ensure stable operation of the device and improve the efficiency of the overall system.

[0017] 4. The present invention provides a higher carrier concentration by heavily doping the second N layer, thereby reducing the resistance of the channel region. When a high current passes through, the on-resistance can be significantly reduced, thereby improving the on-performance of the device.

[0018] 5. The present invention can simply and clearly judge the high temperature performance of the MOS device through the change in leakage current of the SiCVDMOSFET structure after the temperature is increased by 60°C at room temperature, the change in on-resistance after the temperature is increased by 100°C at room temperature, and the temperature change after continuous operation for 5 hours at a voltage exceeding the threshold voltage by 20%. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of Embodiment 1 of the present invention; Figure 2 It is a schematic diagram of the second embodiment of the present invention; Figure 3 It is a schematic diagram of Embodiment 3 of the present invention; Figure 4 It is a schematic diagram of Embodiment 4 of the present invention.

[0020] In the figure: 1. drain; 2. source; 3. gate oxide layer; 4. gate; 5. N substrate layer; 6. N drift layer; 7. P well layer 1; 8. heavily doped P layer; 9. N well layer; 10. P well layer 2; 11. heavily doped N layer 1; 12. filling medium; 13. heavily doped N layer 2; 1101. heavily doped N layer 3. DETAILED DESCRIPTION

[0021] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] like Figure 1-4 As shown, a method for preparing a SiCVD MOSFET structure with high temperature reliability comprises the following steps: Step 1: Substrate preparation and substrate surface treatment.

[0023] Step 2: doping the gate region and forming the source / drain region; using the ion implantation process to dope phosphorus impurities to form a heavily doped N layer 11.

[0024] Step 3: Gate metallization and source-drain metallization form a SiC VDMOSFET structure.

[0025] Step 4: Perform high temperature stress test on the SiC VDMOSFET structure to verify the long-term reliability of the device under high temperature conditions.

[0026] The high temperature reliability of the SiCVDMOSFET structure is determined based on the change in leakage current after the SiCVDMOSFET structure is heated by 60°C at room temperature, the change in on-resistance after the SiCVDMOSFET structure is heated by 100°C at room temperature, and the temperature change after continuous operation for 5 hours at a voltage exceeding the threshold voltage by 20%. In the formula, represents the high temperature reliability coefficient of the tested SiCVDMOSFET structure, The larger the value, the better the high temperature performance of the SiCVDMOSFET structure; Indicates the change in leakage current after the temperature rises by 60°C under normal temperature environment; It indicates the change in on-resistance after the temperature rises by 100°C under normal temperature environment; Indicates the temperature change after continuous operation for 5 hours at a voltage 20% higher than the threshold voltage.

[0027] when When , it means that the SiCVDMOSFET structure tested has excellent high temperature reliability.

[0028] Among them, the high temperature reliability coefficient of any SiCVDMOSFET structure is tested. The change in leakage current of the SiCVDMOSFET structure after heating by 60°C under normal temperature environment is taken as (unit , where normal temperature environment means the device is in an environment of 25℃).

[0029] The change in on-resistance of SiCVD MOSFET structure after heating 100℃ under normal temperature environment is measured (Unit: milliohms).

[0030] The temperature change of SiCVD MOSFET structure after continuous operation for 5 hours at a voltage exceeding the threshold voltage by 20% is measured. (Temperature change = temperature rise ÷ normal ambient temperature). Then we have: Through the above calculation, we can know that the high temperature reliability coefficient of the tested SiCVDMOSFET structure is , which means that the SiCVDMOSFET structure tested has excellent high temperature reliability.

[0031] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a SiCVD MOSFET structure with high temperature reliability is provided, including a drain 1, a semiconductor epitaxial layer, a source 2, a gate 4, and a gate oxide layer 3 covering the surface of the gate 4, an N substrate layer 5, an N drift layer 6, a P well layer 1 7, a heavily doped P layer 8, and an N well layer 9 are provided inside the semiconductor epitaxial layer, a P well layer 2 10 and a heavily doped N layer 1 11 are provided on one side of the N well layer 9 and near the gate 4, and the P well layer 2 10 is located between the N well layer 9 and the heavily doped N layer 1 11. When the gate 4 intervenes in the gate voltage state, a charge channel will be formed at the P well layer 1 7 near the gate 4 and above the P well layer 2 10, and the charge channel can connect the N drift layer 6 and the N well layer 9, thereby allowing the drain 1 to be conductive with the source 2. This series double channel design can greatly improve the stability of the device and avoid the risk of the device being broken down in a high temperature environment.

[0032] Example 2 like Figure 2 As shown, the heavily doped N layer 11 also includes a heavily doped N layer 3 1101, wherein the heavily doped N layer 3 1101 is in contact with the N drift layer 6; the cross-sectional profile of the gate 4 is in a 'T' shape, and the T-shaped gate 4 structure can help distribute the heat in the gate 4 area more evenly, avoid heat concentration at a certain point, and reduce device failure or degradation due to local high temperature; and the T-shaped gate 4 structure can usually optimize the gate 4 resistance and reduce the current required for the gate 4 drive, so that at high temperatures, due to the reduction of the gate resistance, the accuracy and response speed of the gate control can be improved.

[0033] Example 3 like Figure 3 As shown, the bottom of the gate 4 is also etched with a T-shaped groove, wherein the inside of the T-shaped groove is filled with a filling medium 12. The filling medium 12 is one of SiO2, P-type polysilicon or N-type polysilicon. The filling medium 12 allows the SiC VDMOSFET to work more efficiently at high power density, reduce heat loss and improve power conversion efficiency. Especially in high temperature environments, the optimization of the filling medium 12 can ensure stable operation of the device and improve the performance of the overall system.

[0034] Example 4 like Figure 4As shown, a heavily doped N layer 13 is formed inside the N drift layer 6 by ion implantation, and the cross-sectional profile of the heavily doped N layer 13 is in a 'U' shape, and the cross-sectional thickness of the heavily doped N layer 13 is the same as the cross-sectional thickness of the heavily doped N layer 11. The heavily doped N layer 13 reduces the resistance of the channel region by providing a higher carrier concentration. When a high current passes through, the on-resistance can be significantly reduced, and the on-performance of the device can be improved. This helps to improve the overall efficiency of the SiC VDMOSFET, especially in high-power applications. In addition, the heavily doped N layer 13 can effectively adjust the breakdown voltage of the device. Introducing a high-doping concentration N layer between the gate and the drift layer helps to change the distribution of the electric field, thereby optimizing the breakdown voltage of the device. This design helps to improve the voltage tolerance of the device, especially in high-voltage and high-power applications, ensuring that the device works reliably under high voltage.

[0035] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A SiCVD MOSFET structure with high temperature reliability, comprising a drain (1), a semiconductor epitaxial layer, a source (2), a gate (4), and a gate oxide layer (3) covering the surface of the gate (4), wherein an N substrate layer (5), an N drift layer (6), a P well layer (7), a heavily doped P layer (8), and an N well layer (9) are provided inside the semiconductor epitaxial layer, characterized in that: A second P-well layer (10) and a first heavily doped N-layer (11) are provided on one side of the N-well layer (9) and close to the gate (4), and the second P-well layer (10) is located between the N-well layer (9) and the first heavily doped N-layer (11); The cross-sectional profile of the gate (4) is in a 'T' shape.

2. The SiCVD MOSFET structure with high temperature reliability according to claim 1, characterized in that: The heavily doped N layer one (11) further includes a heavily doped N layer three (1101), wherein the heavily doped N layer three (1101) is in contact with the N drift layer (6).

3. The SiCVD MOSFET structure with high temperature reliability according to claim 1, characterized in that: The bottom of the gate (4) is also etched with a T-shaped groove, wherein the interior of the T-shaped groove is filled with a filling medium (12).

4. The SiCVD MOSFET structure with high temperature reliability according to claim 3, characterized in that: The filling medium (12) is one of SiO2, P-type polysilicon or N-type polysilicon.

5. The SiCVD MOSFET structure with high temperature reliability according to claim 1, characterized in that: A heavily doped N layer 2 (13) is formed inside the N drift layer (6) by ion implantation. The cross-sectional profile of the heavily doped N layer 2 (13) is in a "U" shape, and the cross-sectional thickness of the heavily doped N layer 2 (13) is the same as the cross-sectional thickness of the heavily doped N layer 1 (11).

6. A method for preparing a SiCVD MOSFET structure with high temperature reliability, characterized in that: The method for preparing a SiCVD MOSFET structure with high temperature reliability is applied to the SiCVD MOSFET structure with high temperature reliability as claimed in any one of claims 2 to 5, and the method for preparing a SiCVD MOSFET structure with high temperature reliability comprises the following steps: S1, substrate preparation and substrate surface treatment; S2, gate region doping, and source / drain region formation; S3, gate metallization and source-drain metallization form a SiC VDMOSFET structure; S4. Perform high temperature stress test on SiC VDMOSFET structure to verify the long-term reliability of the device under high temperature conditions.

7. The method for preparing a SiCVD MOSFET structure with high temperature reliability according to claim 1, characterized in that: In the step S2, phosphorus impurities are doped by ion implantation to form a heavily doped N layer 1 (11).

8. The method for preparing a SiCVD MOSFET structure with high temperature reliability according to claim 1, characterized in that: In step S4, the high temperature reliability of the SiCVDMOSFET structure is determined based on the change in leakage current after the SiCVDMOSFET structure is heated by 60°C at room temperature, the change in on-resistance after the SiCVDMOSFET structure is heated by 100°C at room temperature, and the temperature change after continuous operation for 5 hours at a voltage exceeding the threshold voltage by 20%, and the following are obtained: In the formula, represents the high temperature reliability coefficient of the tested SiCVDMOSFET structure, The larger the value, the better the high temperature performance of the SiCVDMOSFET structure; It indicates the change in leakage current after the temperature rises by 60°C under normal temperature environment; It indicates the change in on-resistance after the temperature rises by 100°C under normal temperature environment; Indicates the temperature change after continuous operation for 5 hours at a voltage 20% higher than the threshold voltage.

9. The method for preparing a SiCVD MOSFET structure with high temperature reliability according to claim 8, characterized in that: when When , it means that the SiCVDMOSFET structure tested has excellent high temperature reliability.

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