A semiconductor epitaxial structure and a method for preparing the same

Abstract

The present invention discloses a semiconductor epitaxial structure and a preparation method thereof, the preparation method of the semiconductor epitaxial structure comprising: providing a substrate; forming a first conductive type semiconductor layer on one side of the substrate, and patterning the surface of the first conductive type semiconductor layer away from the substrate to form a three-dimensional structure array; performing plasma activation treatment on the surface of the first conductive type semiconductor layer; forming an active layer on the side of the first conductive type semiconductor layer away from the substrate; the material of the active layer includes In, and in the process of forming the active layer, the temperature of the formation environment of the active layer is greater than or equal to a first preset temperature value, and the pressure is greater than or equal to a first preset pressure value; forming a second conductive type semiconductor layer on the side of the active layer away from the substrate. The technical solution provided by the present invention improves the doping efficiency of In, improves the crystal quality of the active layer, reduces the internal stress of the active layer, and improves the luminous efficiency of the active layer with a high In component.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor epitaxial structure and a method for preparing the same. Background Art

[0002] Micro-LEDs are known as the next generation of display devices because of their high responsiveness, high brightness, high contrast, ultra-high resolution, and low power consumption. Although InGaN-based Micro-LEDs have achieved good luminous efficiency in the blue-green light band and have been successfully commercialized in recent years, the red light efficiency of Micro-LEDs is currently very low, especially the In doping efficiency in red-light Micro-LEDs is still seriously insufficient.

[0003] This is mainly because the growth of InGaN materials in quantum wells is generally grown on gallium nitride / sapphire / silicon substrates. Due to the large lattice mismatch, the large compressive stress makes it extremely difficult to grow InGaN films with high In content. The large compressive stress in InGaN makes its quantum confined Stark effect (QCSE) serious, causing the electron-hole pairs to separate spatially, reducing the overlap of wave functions, and causing the luminous efficiency to decrease. In addition, the degree of phase separation in InGaN becomes more serious with the increase of In content and thickness, which makes high In doping extremely difficult, and the InN-rich region formed by phase separation will increase the probability of non-radiative recombination, thereby further reducing the red light efficiency. At the same time, the growth temperature required for InGaN quantum wells (QWs) with high In content is very low, which leads to slow migration of its atoms, causing the surface morphology to deteriorate. Combined with the large lattice mismatch, the quality of its quantum wells is very poor, and ultimately deteriorates the luminous efficiency of red light.

[0004] The current difficulty is to effectively improve the ability to incorporate In components, improve the quality of quantum well crystals, further reduce the internal stress of quantum wells, reduce the QCSE effect of InGaN, and improve the luminescence efficiency of quantum wells with high In components. Summary of the invention

[0005] The embodiment of the present invention provides a semiconductor epitaxial structure and a preparation method thereof, so as to improve the In doping efficiency in the semiconductor epitaxial structure, improve the crystal quality of the active layer, reduce the internal stress of the active layer, and improve the luminous efficiency of the active layer with a high In component.

[0006] According to one aspect of the present invention, there is provided a method for preparing a semiconductor epitaxial structure, comprising:

[0007] providing a substrate;

[0008] Forming a first conductive type semiconductor layer on one side of the substrate, and patterning a surface of the first conductive type semiconductor layer away from the substrate to form a three-dimensional structure array;

[0009] Performing plasma activation treatment on the surface of the first conductive type semiconductor layer having the three-dimensional structure array;

[0010] An active layer is formed on a side of the first conductive type semiconductor layer away from the substrate after the plasma activation treatment; wherein the material of the active layer includes In, and during the process of forming the active layer, the temperature of the formation environment of the active layer is greater than or equal to a first preset temperature value, and the pressure of the formation environment of the active layer is greater than or equal to a first preset pressure value;

[0011] A second conductive type semiconductor layer is formed on a side of the active layer away from the substrate.

[0012] Optionally, the step of performing plasma activation treatment on the surface of the first conductive type semiconductor layer having the three-dimensional structure array includes:

[0013] The surface of the first conductive type semiconductor layer having the three-dimensional structure array is subjected to plasma activation treatment by plasma gas; wherein the plasma gas includes O2 and N2.

[0014] Optionally, in the process of forming the active layer, the temperature range of the formation environment of the active layer is 770° C.~980° C.; the pressure range of the formation environment of the active layer is 50000 Pa~110000 Pa.

[0015] Optionally, patterning the surface of the first conductive type semiconductor layer away from the substrate to form a three-dimensional structure array includes:

[0016] Performing patterning on the surface of the first conductive type semiconductor layer away from the substrate by a photolithography process to form the three-dimensional structure array;

[0017] Among them, the three-dimensional structure array includes multiple three-dimensional structures, and the three-dimensional structures in the three-dimensional structure array include at least one of a cone structure, a triangular pyramid structure, a hexagonal prism structure, a regular quadrangular pyramid structure and a regular hexagonal pyramid structure; the height of the three-dimensional structure ranges from 50nm to 400nm, the diameter or side length of the bottom pattern ranges from 50nm to 500nm, and the distance between two adjacent three-dimensional structures ranges from 50nm to 300nm.

[0018] Optionally, before forming an active layer on a side of the first conductive type semiconductor layer away from the substrate after the plasma activation treatment, the method further comprises:

[0019] forming a pre-well layer on the surface of the first conductive type semiconductor layer after the plasma activation treatment; the pre-well layer is used to reduce the internal stress of the active layer;

[0020] And / or, before forming the second conductivity type semiconductor layer on the side of the active layer away from the substrate, the method further comprises:

[0021] forming an electron blocking layer on a side of the active layer away from the substrate;

[0022] And / or, before forming the first conductive type semiconductor layer on one side of the substrate, the method further includes:

[0023] A buffer layer is formed on one side of the substrate; the buffer layer is located between the substrate and the first conductive type semiconductor layer.

[0024] Optionally, forming a pre-well layer on the surface of the first conductive type semiconductor layer after the plasma activation treatment comprises:

[0025] After the plasma activation treatment, a plurality of In x Ga 1-x N layer and GaN layer composed of a superlattice layer; wherein the pre-well layer comprises a plurality of stacked In x Ga 1-x The superlattice layer consists of N layer and GaN layer; among them, 0.05 <x<0.2;

[0026] The active layer is formed on a side of the first conductive type semiconductor layer away from the substrate after the plasma activation treatment, comprising:

[0027] A plurality of In y Ga 1-y N layer and GaN layer composed of quantum well layer; wherein the active layer comprises a plurality of stacked In y Ga 1-y The quantum well layer consists of N layer and GaN layer; among them, 0.05 <y<0.95。

[0028] Optionally, after forming an active layer on a side of the first conductive type semiconductor layer away from the substrate after the plasma activation treatment, the method further comprises:

[0029] The active layer is subjected to annealing treatment.

[0030] According to another aspect of the present invention, there is provided a semiconductor epitaxial structure, which is formed by the method for preparing a semiconductor epitaxial structure according to any embodiment of the present invention, comprising:

[0031] substrate;

[0032] A first-conduction-type semiconductor layer, located on one side of the substrate; wherein, the surface of the first-conduction-type semiconductor layer away from the substrate includes an array of three-dimensional structures;

[0033] An active layer, located on the side of the first-conduction-type semiconductor layer away from the substrate; wherein, the material of the active layer includes In, the temperature of the formation environment of the active layer is greater than or equal to a first preset temperature value, and the pressure of the formation environment of the active layer is greater than or equal to a first preset pressure value;

[0034] A second-conduction-type semiconductor layer, located on the side of the active layer away from the substrate.

[0035] Optionally, the array of three-dimensional structures includes a plurality of three-dimensional structures, and the three-dimensional structures in the array of three-dimensional structures include at least one of a conical structure, a triangular pyramid structure, a hexagonal prism structure, a regular quadrangular frustum structure, and a regular hexagonal frustum structure;

[0036] The height range of the three-dimensional structure is 50 nm to 400 nm, the diameter or side length of the bottom pattern is in the range of 50 nm to 500 nm, and the distance between adjacent two three-dimensional structures is in the range of 50 nm to 300 nm.

[0037] Optionally, the semiconductor epitaxial structure further includes:

[0038] A pre-well layer, located between the first-conduction-type semiconductor layer and the active layer, and covering the surface of the array of three-dimensional structures and the surface of the first-conduction-type semiconductor layer between the arrays of three-dimensional structures; the pre-well layer includes a plurality of superlattice layers stacked by In x Ga 1-x N layers and GaN layers; wherein, 0.05 < x < 0.2; the active layer includes a plurality of quantum well layers stacked by In y Ga 1-y N layers and GaN layers; wherein, 0.05 < y < 0.95;

[0039] And / or, an electron blocking layer, the electron blocking layer is located on the side of the active layer away from the substrate;

[0040] And / or, a buffer layer, the buffer layer is located between the substrate and the first-conduction-type semiconductor layer.

[0041] The technical solution provided by the embodiment of the present invention can fully release the stress generated by lattice mismatch in the active layer by patterning the surface of the first conductive type semiconductor layer away from the substrate, and introduce a periodic three-dimensional nano-pattern structure, so as to effectively improve the high In component incorporation capability of the active layer material InGaN, and realize the controllable growth of high In components of In0.1Ga0.9N~In0.9Ga0.1N; and this stress release can also reduce the QCSE effect and improve the luminous efficiency of the red light and other high In component InGaN-based active layers; in addition, the three-dimensional nano-pattern structure can enhance the surface energy of the InGaN material in the active layer, making In less likely to aggregate, thereby reducing the phase separation generated by the epitaxial growth of high In component InGaN and improving its heat resistance. By performing plasma activation treatment on the first conductive type semiconductor layer, not only can the organic and inorganic pollutants introduced on the surface be removed, but also more dangling bonds will be generated on the surface of the first conductive type semiconductor layer away from the substrate, which is beneficial to the structural stability of the active layer at high temperature, and the high temperature growth of InGaN will improve the In doping efficiency in the semiconductor epitaxial structure, further improve the quality of the quantum well, and improve the internal quantum efficiency. By utilizing a high-pressure reaction environment, the high volatility of In at high temperatures is suppressed, making it difficult for In to escape from the growth surface during the growth process and reducing the surface migration of In, thereby suppressing the phase separation phenomenon and increasing the adsorption stability of indium atoms on the surface.

[0042] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 is a flow chart of a method for preparing a semiconductor epitaxial structure provided by an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of the cross-sectional structure of a substrate provided in a method for preparing a semiconductor epitaxial structure provided in an embodiment of the present invention;

[0046] Figure 3 It is a schematic cross-sectional structure diagram after a first conductive type semiconductor layer is formed on one side of a substrate in a method for preparing a semiconductor epitaxial structure provided by an embodiment of the present invention;

[0047] Figure 4 It is a schematic cross-sectional structure diagram of a method for preparing a semiconductor epitaxial structure provided by an embodiment of the present invention after patterning a surface of a first conductive type semiconductor layer away from a substrate to form a three-dimensional structure array;

[0048] Figure 5 It is a schematic cross-sectional structure diagram after an active layer is formed on a side of a first conductive type semiconductor layer away from a substrate in a method for preparing a semiconductor epitaxial structure provided by an embodiment of the present invention;

[0049] Figure 6 It is a schematic cross-sectional structure diagram of a method for preparing a semiconductor epitaxial structure provided by an embodiment of the present invention after a second conductive type semiconductor layer is formed on a side of an active layer away from a substrate;

[0050] Figure 7 is a schematic cross-sectional structure diagram of a three-dimensional structure array having a cone shape provided by an embodiment of the present invention;

[0051] Figure 8 is a schematic cross-sectional structure diagram of a three-dimensional structure array in the shape of a regular hexagonal pyramid provided by an embodiment of the present invention;

[0052] Fig. 9 It is a schematic diagram of an electron microscope image after an active layer is formed on one side of a three-dimensional structure array having a cone shape, provided by an embodiment of the present invention;

[0053] Fig.10 is a schematic diagram of a high-angle annular dark-field image of an active layer provided by an embodiment of the present invention;

[0054] Fig.11 This is an element analysis energy spectrum diagram of an active layer provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0057] The embodiment of the present invention provides a method for preparing a semiconductor epitaxial structure. Figure 1 is a flow chart of a method for preparing a semiconductor epitaxial structure provided by an embodiment of the present invention, with reference to Figure 1 , the method for preparing a semiconductor epitaxial structure comprises:

[0058] S10. Provide a substrate.

[0059] Specifically, refer to Figure 2 The substrate 10 may be, for example, a silicon substrate, a sapphire substrate or a silicon carbide substrate; in other embodiments, the substrate may also be a substrate 10 of other materials. After providing the substrate 10, the substrate 10 may be cleaned to remove organic and inorganic pollutants on the surface of the substrate 10.

[0060] S20, forming a first conductive type semiconductor layer on one side of the substrate, and patterning a surface of the first conductive type semiconductor layer away from the substrate to form a three-dimensional structure array.

[0061] Specifically, refer to Figure 3 The first conductive type semiconductor layer 20 can be formed on one side of the substrate 10 by a deposition process, for example, the first conductive type semiconductor layer 20 can be formed on one side of the substrate 10 by a MOCVD (Metal-organic Chemical Vapor Deposition) process; the first conductive type semiconductor layer 20 can also be formed by other processes. The semiconductor material of the first conductive type semiconductor layer 20 is doped with first conductive type doping ions. Figure 4, the surface of the first conductive type semiconductor layer 20 away from the substrate 10 is patterned to form a three-dimensional structure array 21. The three-dimensional structure array 21 includes a plurality of three-dimensional structures 201, and the three-dimensional structures 201 in the three-dimensional structure array 21 include at least one of a cone structure, a triangular pyramid structure, a hexagonal prism structure, a regular quadrangular pyramid structure, and a regular hexagonal pyramid structure. The process of patterning the surface of the first conductive type semiconductor layer 20 away from the substrate 10 to form the three-dimensional structure array 21 includes at least one of photolithography, dry etching, and wet etching.

[0062] S30, performing plasma activation treatment on the surface of the first conductive type semiconductor layer having the three-dimensional structure array.

[0063] Specifically, plasma is a mixture of high-energy particles and electrons, which has the characteristics of high temperature, high energy and high reactivity. The plasma activation treatment process places the substance in the plasma so that its surface is affected by the plasma, thereby achieving the purpose of surface cleaning, modification and coating. Plasma activation treatment of the surface of the first conductive type semiconductor layer 20 can remove organic and inorganic pollutants introduced on the surface, and can also make the surface of the first conductive type semiconductor layer 20 having the three-dimensional structure array 21 produce more dangling bonds, especially a large number of N dangling bonds, which are easy to combine with In in the subsequent pre-well layer or quantum well layer, which will make InGaN pinned to the surface of the three-dimensional structure, not only increasing its coverage area, but also improving its heat resistance, which is beneficial to the structural stability and three-dimensional lateral growth of InGaN at subsequent high temperatures.

[0064] S40. Forming an active layer on a side of the first conductive type semiconductor layer away from the substrate after plasma activation treatment; wherein the material of the active layer includes In; in the process of forming the active layer, the temperature of the formation environment of the active layer is greater than or equal to a first preset temperature value, and the pressure of the formation environment of the active layer is greater than or equal to a first pressure preset value.

[0065] Specifically, refer to Figure 5 The active layer 30 is formed on the side of the first conductive type semiconductor layer 20 away from the substrate 10 by a deposition process. The active layer 30 includes one or more quantum well layers. In the embodiment of the present invention, the material of the quantum well layer includes In element. For example, the quantum well layer includes In element stacked. y Ga 1-yN layer and GaN layer. During the formation of the active layer 30, the temperature of the formation environment of the active layer 30 is greater than or equal to the first preset temperature value, and the pressure of the formation environment of the active layer 30 is greater than or equal to the first preset pressure value. Among them, the first preset temperature value can be 650 °C, 700 °C, 720 °C, 750 °C, which can be set according to the actual situation. The first preset pressure value can be 350 Torr, 400 Torr, 450 Torr, which can be set according to the actual situation; where 1 torr is equal to 133.322 Pa. Optionally, forming the active layer 30 on the side of the first-conductive-type semiconductor layer 20 away from the substrate 10 includes: forming a plurality of In y Ga 1-y N layer and GaN layer composed of quantum well layers, the active layer 30 includes a plurality of stacked In y Ga 1-y N layer and GaN layer composed of quantum well layers; where 0.05 < y < 0.95. Setting a plurality of quantum well layers can effectively increase the light emission amount of the active layer 30.

[0066] The content of In in the InGaN material is inversely proportional to the stress caused by lattice mismatch. Therefore, the premise of preparing a high-In component InGaN layer is the reduction or full release of stress. The three-dimensional structure array 21 on the surface of the first-conductive-type semiconductor layer 20 on the side away from the substrate 10 changes the geometric shape of the growth surface of the InGaN layer and the GaN layer during the epitaxial process, so that the stress in the InGaN layer and the stress in the GaN layer can be dispersed and relieved at the growth surface, reducing stress accumulation. In addition, this three-dimensional growth mode enables the crystals to fuse with each other on the sidewalls of the patterned area, providing more paths for stress release, effectively reducing the stress in the InGaN layer and the stress in the GaN layer. Therefore, by patterning the surface of the first-conductive-type semiconductor layer 20 on the side away from the substrate 10 and introducing the three-dimensional structure array 21 on the surface of the first-conductive-type semiconductor layer 20 on the side away from the substrate 10, the stress generated by lattice mismatch in the active layer 30 can be fully released, effectively improving the incorporation ability of the high-In component in the InGaN material, and enabling the controllable growth of high-In components of In 0.1 Ga 0.9 N ~ In 0.9 Ga 0.1 N. In addition, introducing the three-dimensional structure array 21 on the surface of the first-conductive-type semiconductor layer 20 on the side away from the substrate 10 can also prevent the occurrence of the quantum-confined Stark effect, thereby improving the problem of spatial separation of electron-hole pairs, reducing the wave function overlap, and decreasing the light emission efficiency.

[0067] The severity of phase separation in InGaN materials increases with the increase of In content and the thickness of InGaN layer. The temperature of the growth environment of InGaN materials with high In content is required to be low, but the low growth temperature will reduce the quality of the quantum well layer, and because the migration ability of N atoms is too poor at low temperature, the surface morphology of the quantum well layer during the growth process will be deteriorated. Therefore, how to increase the formation environment temperature of the quantum well layer without causing In enrichment due to phase separation is the key. By performing plasma activation treatment on the surface of the first conductive type semiconductor layer 20 having a three-dimensional structure array 21, not only can the organic and inorganic pollutants introduced on its surface be removed, but also more dangling bonds can be generated on the surface of the first conductive type semiconductor layer 20, which is beneficial to the structural stability of the quantum well layer at high temperature. In addition, the migration ability of In in the InGaN material at high temperature is too fast, and its migration needs to be suppressed. Compared with the traditional two-dimensional planar quantum well, the three-dimensional structure 201 has a larger surface energy and In is less likely to aggregate; and in combination with the high-pressure reaction environment, the high pressure can suppress the volatilization of In, making it difficult for In to escape from the growth surface during the formation of the InGaN layer, and reduce the surface migration ability of In, suppress the phase separation phenomenon, and increase the adsorption stability of In on the growth surface.

[0068] S50, forming a second conductive type semiconductor layer on a side of the active layer away from the substrate.

[0069] Specifically, refer to Figure 6 , a second conductive type semiconductor layer 40 is formed on the side of the active layer 30 away from the substrate 10 by a deposition process, wherein the semiconductor material of the second conductive type semiconductor layer 40 is doped with second conductive type doping ions. If the first conductive type is P-type, the second conductive type is N-type; if the first conductive type is N-type, the second conductive type is P-type. In an embodiment of the present invention, the first conductive type is N-type, the second conductive type is P-type, the first conductive type doping ions are N-type doping ions, and the second conductive type doping ions are P-type doping ions. Among them, the P-type doping ions include but are not limited to Mg ions, C ions, Fe ions and Zn ions; the N-type doping ions include but are not limited to Si ions and O ions. The materials of the first conductive type semiconductor layer 20 and the second conductive type semiconductor layer 40 include but are not limited to GaN, that is, the first conductive type semiconductor layer 20 is an N-GaN layer, and the second conductive type semiconductor layer 40 is a P-GaN layer.

[0070] The method for preparing a semiconductor epitaxial structure provided by an embodiment of the present invention can fully release the stress generated by lattice mismatch in the active layer 30 by patterning the surface of the first conductive type semiconductor layer 20 away from the substrate 10, thereby effectively improving the incorporation capacity of the high In component in the InGaN material of the active layer 30, and realizing In 0.1 Ga 0.9 N ~ In 0.9 Ga 0.1 The high In component of N can be controlled to grow, so as to realize the preparation of the active layer 30 emitting red light or light with a wavelength greater than red light; and this stress release can also reduce the QCSE effect and improve the luminous efficiency of the active layer 30 emitting red light or light with a wavelength greater than red light; in addition, the three-dimensional structure array 21 can enhance the surface energy of the InGaN material in the active layer 30, making In less likely to aggregate, thereby improving the problem of phase separation of the InGaN material with a high In component during the epitaxial growth process and improving its heat resistance; and the introduction of the three-dimensional structure 201 can induce the bending and offset of dislocations and reduce the dislocation density, thereby further improving the crystal quality of the quantum well, and the three-dimensional PN junction, holes are preferentially injected from the side wall of the V-shaped pit into the platform active layer 30, which can enhance hole injection and improve its luminous efficiency.

[0071] Moreover, by performing plasma activation treatment on the first conductive type semiconductor layer 20, not only can the organic and inorganic pollutants introduced on the surface be removed, but more dangling bonds will also be generated on the surface of the first conductive type semiconductor layer 20 away from the substrate 10, which is beneficial to the structural stability of the active layer 30 at high temperatures, and the high temperature growth of InGaN will improve the doping efficiency of In in the semiconductor epitaxial structure, further improve the quality of the quantum well, and improve the internal quantum efficiency. By using a high-pressure reaction environment, the high volatility of In at high temperature is suppressed, making it difficult to escape from the growth surface during the growth process and reducing the surface migration of In, suppressing the phase separation phenomenon, and increasing the adsorption stability of In on the surface.

[0072] In summary, the method for preparing a semiconductor epitaxial structure provided by an embodiment of the present invention improves the In doping efficiency in the semiconductor epitaxial structure, increases the In content in InGaN, reduces the dislocation density during the epitaxial process, effectively improves the crystal quality of the active layer 30, reduces the internal stress of the active layer 30, and improves the luminescence efficiency of the active layer 30 with a high In component.

[0073] Based on the above embodiments, optionally, in step S20, patterning is performed on a surface of the first conductive type semiconductor layer away from the substrate to form a three-dimensional structure array, including:

[0074] The surface of the first conductive type semiconductor layer away from the substrate is patterned by photolithography to form a three-dimensional structure array.

[0075] Specifically, refer to Figure 4 , the surface of the first conductive type semiconductor layer 20 away from the substrate 10 is patterned by a photolithography process to form a three-dimensional structure array 21, including: forming a mask layer on the side of the first conductive type semiconductor layer 20 away from the substrate 10; coating a photoresist on the surface of the mask layer away from the substrate 10; patterning the photoresist based on the mask to form a plurality of openings exposing the mask layer, thereby transferring the pattern of the mask to the photoresist; etching the mask layer based on the openings in the photoresist to form a plurality of openings exposing the first conductive type semiconductor layer 20, thereby transferring the pattern of the mask to the mask layer; etching the surface of the first conductive type semiconductor layer 20 away from the substrate 10 exposed by the mask layer by a dry etching process, thereby patterning the surface of the first conductive type semiconductor layer away from the substrate 10, and forming a three-dimensional structure array 21. Wherein, the etching gas in the dry etching process can be at least one of Ar, BCl3, and Cl2. The height of the three-dimensional structure 201 in the three-dimensional structure array 21 ranges from 50 nm to 400 nm, the diameter or side length of the bottom pattern ranges from 50 nm to 500 nm, and the distance between two adjacent three-dimensional structures 201 ranges from 50 nm to 300 nm.

[0076] For example, Figure 7 is a schematic cross-sectional structure diagram of a three-dimensional structure array in the shape of a cone provided by an embodiment of the present invention, with reference to Figure 7 The height h of the three-dimensional structure 201 is 150 nm, the bottom diameter a is 200 nm, and the minimum spacing d between adjacent three-dimensional structures 201 is 80 nm. Figure 8 is a schematic cross-sectional structure diagram of a three-dimensional structure array in the shape of a regular hexagonal pyramid provided by an embodiment of the present invention, with reference to Figure 8 The height h of the three-dimensional structure 201 is 100 nm, the bottom side length a2 is 120 nm, the top side length a1 is 70 nm, and the minimum spacing d between adjacent three-dimensional structures 201 is 100 nm.

[0077] Based on the above embodiments, optionally, in step S30, a plasma activation treatment is performed on the surface of the first conductive type semiconductor layer having the three-dimensional structure array, including:

[0078] The surface of the first conductive type semiconductor layer having the three-dimensional structure array is subjected to plasma activation treatment by plasma gas; wherein the plasma gas includes O2 and N2.

[0079] Specifically, a plasma gas is provided to the surface of the first-conductivity-type semiconductor layer by a plasma surface treatment instrument to achieve plasma activation treatment of the surface of the first-conductivity-type semiconductor layer having a three-dimensional structure array. During the process of performing plasma activation treatment on the surface of the first-conductivity-type semiconductor layer using the plasma surface treatment instrument, the operating frequency range of the plasma surface treatment instrument is 40KHz to 13.56MHz, and the power range is 100W to 400W; the time range for performing plasma activation treatment on the surface of the first-conductivity-type semiconductor layer having the three-dimensional structure array 21 is 5min to 15min.

[0080] Based on the above embodiments, optionally, during the formation of the active layer, the temperature range of the formation environment of the active layer is 770°C to 980°C; the pressure range of the formation environment of the active layer is 50000pa to 110000pa.

[0081] Based on the above embodiments, optionally, before step S40 forms the active layer on the side of the first-conductivity-type semiconductor layer away from the substrate after plasma activation treatment, it further includes:

[0082] Form a pre-well layer on the surface of the first-conductivity-type semiconductor layer after plasma activation treatment; the pre-well layer is used to reduce the internal stress of the active layer.

[0083] Specifically, please refer to Figure 5 , after forming the pre-well layer 31 on the surface of the first-conductivity-type semiconductor layer 20 after plasma activation treatment, form the active layer 30 on the side of the pre-well layer 31 away from the substrate 10. The pre-well layer 31 is used to reduce the internal stress of the active layer 30. Among them, forming the pre-well layer 31 on the surface of the first-conductivity-type semiconductor layer 20 after plasma activation treatment includes: forming a plurality of superlattice layers composed of In x Ga 1-x N layers and GaN layers on the surface of the first-conductivity-type semiconductor layer 20 after plasma activation treatment; the pre-well layer 31 includes a plurality of superlattice layers composed of In x Ga 1-x N layers and GaN layers stacked; where 0.05 < x < 0.2. Optionally, in the pre-well layer 31, the thickness range of the In x Ga 1-x N layer is 2 nm - 6nm, and the thickness range of the GaN layer is 2nm to 8nm; the number of superlattice layers included in the pre-well layer 31 ranges from 4 layers to 10 layers, and the growth temperature range of the pre-well layer 31 is 800°C to 950°C.

[0084] In the embodiment of the present invention, step S40 forms an active layer 30 on the side of the first conductive type semiconductor layer 20 away from the substrate 10 after the plasma activation treatment, comprising: forming a plurality of In y Ga 1-y Specifically, the pressure of the reaction chamber is increased to 400-800 Torr to grow a three-dimensional InGaN / GaN quantum well layer. The number of quantum well layers in the active layer 30 is in the range of 2-11, wherein the thickness of the GaN layer as the barrier layer is in the range of 5-12 nm, and the thickness of the InGaN layer as the potential well layer is in the range of 10-20 nm. y Ga 1-y The thickness of the N layer ranges from 2nm to 6nm, and the In y Ga 1-y The growth temperature range of the N layer is 770℃-980℃, of which 0.05 <y<0.95。

[0085] Based on the above embodiments, optionally, after forming an active layer on the side of the first conductive type semiconductor layer away from the substrate after the plasma activation treatment, step S40 further includes:

[0086] S401, performing annealing treatment on the active layer.

[0087] Specifically, after the active layer 30 is formed, the active layer 30 is annealed to make the GaN layer and the In layer in the active layer 30 y Ga 1-y The interface between the N layers becomes smoother and flatter, while reducing defects and dislocations, reducing stress in the quantum well layer, thereby further reducing the QCSE effect and improving the internal quantum efficiency of the semiconductor epitaxial structure. Optionally, during the annealing process of the active layer 30, the annealing temperature ranges from 850 to 1000°C, the annealing protective gas is a mixture of N2 and NH3, and the annealing time ranges from 1 min to 5 min.

[0088] Based on the above embodiments, optionally, before forming the second conductivity type semiconductor layer on the side of the active layer away from the substrate in step S50, the step further includes:

[0089] S402 , forming an electron blocking layer on a side of the active layer away from the substrate.

[0090] Specifically, after the annealing is completed, the growth pressure is adjusted to a pressure value between 100 Torr and 300 Torr to prepare an electron blocking layer (EBL layer). The electron blocking layer can be a P-type AlGaN layer doped with Mg ions, with a thickness ranging from 40 nm to 100 nm and a growth temperature ranging from 920° C. to 1020° C.

[0091] Step S50 forms a second conductive type semiconductor layer on the side of the active layer away from the substrate, including: forming a second conductive type semiconductor layer 40 on the surface of the side of the electron blocking layer away from the substrate. The second conductive type semiconductor layer 40 is a P-type conductive layer with a thickness ranging from 100nm to 300nm, wherein the magnesium doping concentration ranges from 1E19 / cm 2 ~5E19 / cm 2 .

[0092] Based on the above embodiments, optionally, before forming the first conductive type semiconductor layer on one side of the substrate in step S20, the step further includes:

[0093] A buffer layer is formed on one side of the substrate; the buffer layer is located between the substrate and the first conductive type semiconductor layer.

[0094] Specifically, refer to Figure 3 , after providing a substrate 10, a buffer layer 11 is first formed on one side of the substrate 10, and then a first conductive type semiconductor layer 20 is formed on the side of the buffer layer 11 away from the substrate 10. The buffer layer 11 may be in contact with the first conductive type semiconductor epitaxial layer, and the buffer layer 11 is used to reduce the lattice and thermal mismatch between the substrate 10 and the first conductive type semiconductor epitaxial layer, thereby solving the defects attributed to the mismatch / difference. The buffer layer 11 may include III-V compounds. The III-V compound may include but is not limited to aluminum, gallium, indium, nitrogen or a combination thereof. Therefore, exemplary materials of the buffer layer 11 may further include, for example but not limited to GaN, AlN, AlGaN, InAlGaN or a combination thereof. Exemplarily, an AlN buffer layer with a thickness range of 100nm~300nm is epitaxially grown using a MOCVD process, and an AlN / AlGaN superlattice composite buffer layer with a thickness range of 500nm~2000nm is epitaxially grown. Among them, the pressure range of the growth environment of the buffer layer 11 is 100Torr~500Torr.

[0095] Step S20 forms a first conductive type semiconductor layer on one side of the substrate, including: forming a first conductive type semiconductor layer 20 on the surface of the buffer layer 11 away from the substrate. The first conductive type semiconductor layer 20 is an N-type conductive layer with a thickness ranging from 1 micron to 5 microns, wherein the silicon doping concentration ranges from 8E18 / cm 2 ~8E19 / cm 2 .

[0096] Fig. 9 is a schematic diagram of an electron microscope image after an active layer is formed on one side of a three-dimensional structure array having a cone shape according to an embodiment of the present invention, Fig.10 is a schematic diagram of a high-angle annular dark-field image of an active layer provided by an embodiment of the present invention, Fig.11is an element analysis spectrum diagram of an active layer provided by an embodiment of the present invention, referring to Figure 9~Figure 11 , the active layer includes multiple In y Ga 1-y The quantum well layer is composed of the N layer 302 and the GaN layer 301. Fig.10 The high-angle annular dark-field image of the active layer shows that In y Ga 1-y The interface between the N layer 302 and the GaN layer 301 crystal layers becomes clear and smooth; Fig.11 The element analysis spectrum of the active layer shown (obtained using an energy spectrometer EDS) shows that the In element is evenly distributed in the active layer, with no In enrichment or phase separation.

[0097] The embodiment of the present invention further provides a semiconductor epitaxial structure, which is formed by the method for preparing the semiconductor epitaxial structure described in any embodiment of the present invention. Figure 6 , the semiconductor epitaxial structure includes:

[0098] Substrate 10;

[0099] A first conductive type semiconductor layer 20 is located on one side of the substrate 10; wherein a surface of the first conductive type semiconductor layer 20 away from the substrate 10 includes a three-dimensional structure array 21;

[0100] The active layer 30 is located on a side of the first conductive type semiconductor layer 20 away from the substrate 10; wherein the material of the active layer 30 includes In; the temperature of the formation environment of the active layer 30 is greater than or equal to the first preset temperature value, and the pressure of the formation environment of the active layer 30 is greater than or equal to the first preset pressure value;

[0101] The second conductive type semiconductor layer 40 is located on a side of the active layer 30 away from the substrate 10 .

[0102] Optionally, the three-dimensional structure array 21 includes a plurality of three-dimensional structures 201, and the three-dimensional structures 201 in the three-dimensional structure array 21 include at least one of a cone structure, a triangular pyramid structure, a hexagonal prism structure, a regular quadrangular pyramid structure, and a regular hexagonal pyramid structure;

[0103] The height of the three-dimensional structure 201 ranges from 50 nm to 400 nm, the diameter or side length of the bottom pattern ranges from 50 nm to 500 nm, and the distance between two adjacent three-dimensional structures 201 ranges from 50 nm to 300 nm.

[0104] The semiconductor epitaxial structure provided by the embodiment of the present invention improves the In doping efficiency and content in the semiconductor epitaxial structure, reduces the dislocation density in the epitaxial semiconductor structure, effectively improves the crystal quality of the active layer 30, reduces the internal stress in the active layer 30, and improves the light-emitting efficiency of the active layer 30 with a high In component.

[0105] Optionally, the semiconductor epitaxial structure further includes:

[0106] A pre-well layer 31, located between the first-conductivity-type semiconductor layer 20 and the active layer 30, and covering the surface of the three-dimensional structure array 21 and the surface of the first-conductivity-type semiconductor layer 20 between the three-dimensional structure arrays 21; the pre-well layer 31 includes a plurality of superlattice layers stacked and composed of In x Ga 1-x N layers and GaN layers; where 0.05 < x < 0.2; the active layer 30 includes a plurality of quantum well layers stacked and composed of In y Ga 1-y N layers and GaN layers; where 0.05 < y < 0.95;

[0107] And / or, an electron blocking layer, the electron blocking layer is located on the side of the active layer 30 away from the substrate 10;

[0108] And / or, a buffer layer 11, the buffer layer 11 is located between the substrate 10 and the first-conductivity-type semiconductor layer 20.

[0109] Note that the above is only the preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing a semiconductor epitaxial structure, characterized in that: include: providing a substrate; Forming a first conductive type semiconductor layer on one side of the substrate, and patterning a surface of the first conductive type semiconductor layer away from the substrate to form a three-dimensional structure array; Performing plasma activation treatment on the surface of the first conductive type semiconductor layer having the three-dimensional structure array; An active layer is formed on a side of the first conductive type semiconductor layer away from the substrate after the plasma activation treatment; wherein the material of the active layer includes In; in the process of forming the active layer, the temperature of the formation environment of the active layer is greater than or equal to a first preset temperature value, and the pressure of the formation environment of the active layer is greater than or equal to a first preset pressure value; the pressure range of the formation environment of the active layer is 50000Pa~110000Pa; A second conductive type semiconductor layer is formed on a side of the active layer away from the substrate.

2. The method for preparing a semiconductor epitaxial structure according to claim 1, characterized in that: The step of performing plasma activation treatment on the surface of the first conductive type semiconductor layer having the three-dimensional structure array comprises: The surface of the first conductive type semiconductor layer having the three-dimensional structure array is subjected to plasma activation treatment by plasma gas; wherein the plasma gas includes O2 and N2.

3. The method for preparing a semiconductor epitaxial structure according to claim 1, characterized in that: In the process of forming the active layer, the temperature range of the formation environment of the active layer is 770° C. to 980° C.

4. The method for preparing a semiconductor epitaxial structure according to claim 1, characterized in that: The patterning of the surface of the first conductive type semiconductor layer away from the substrate to form a three-dimensional structure array includes: Performing patterning on the surface of the first conductive type semiconductor layer away from the substrate by a photolithography process to form the three-dimensional structure array; Among them, the three-dimensional structure array includes multiple three-dimensional structures, and the three-dimensional structures in the three-dimensional structure array include at least one of a cone structure, a triangular pyramid structure, a hexagonal prism structure, a regular quadrangular pyramid structure and a regular hexagonal pyramid structure; the height of the three-dimensional structure ranges from 50nm to 400nm, the diameter or side length of the bottom pattern ranges from 50nm to 500nm, and the distance between two adjacent three-dimensional structures ranges from 50nm to 300nm.

5. The method for preparing a semiconductor epitaxial structure according to claim 1, characterized in that: Before forming an active layer on the side of the first conductive type semiconductor layer away from the substrate after the plasma activation treatment, the method further comprises: forming a pre-well layer on the surface of the first conductive type semiconductor layer after the plasma activation treatment; the pre-well layer is used to reduce the internal stress of the active layer; And / or, before forming the second conductivity type semiconductor layer on the side of the active layer away from the substrate, the method further comprises: forming an electron blocking layer on a side of the active layer away from the substrate; And / or, before forming the first conductive type semiconductor layer on one side of the substrate, the method further includes: A buffer layer is formed on one side of the substrate; the buffer layer is located between the substrate and the first conductive type semiconductor layer.

6. The method for preparing a semiconductor epitaxial structure according to claim 5, characterized in that: The method of forming a pre-well layer on the surface of the first conductive type semiconductor layer after the plasma activation treatment comprises: After the plasma activation treatment, a plurality of In x Ga 1-x N layer and GaN layer composed of a superlattice layer; wherein the pre-well layer comprises a plurality of stacked In x Ga 1-x The superlattice layer consists of N layer and GaN layer; among them, 0.05 <x<0.2; The active layer is formed on a side of the first conductive type semiconductor layer away from the substrate after the plasma activation treatment, comprising: A plurality of In y Ga 1-y N layer and GaN layer composed of quantum well layer; wherein the active layer comprises a plurality of stacked In y Ga 1-y The quantum well layer consists of N layer and GaN layer; among them, 0.05 <y<0.95。 7. The method for preparing a semiconductor epitaxial structure according to claim 1, characterized in that: After forming an active layer on the side of the first conductive type semiconductor layer away from the substrate after the plasma activation treatment, the method further comprises: The active layer is subjected to annealing treatment.

8. A semiconductor epitaxial structure, characterized in that: The method for preparing a semiconductor epitaxial structure according to any one of claims 1 to 7 comprises: substrate; A first conductive type semiconductor layer is located on one side of the substrate; wherein a surface of the first conductive type semiconductor layer away from the substrate includes a three-dimensional structure array; An active layer, located on a side of the first conductive type semiconductor layer away from the substrate; wherein the material of the active layer includes In; the temperature of the formation environment of the active layer is greater than or equal to a first preset temperature value, and the pressure of the formation environment of the active layer is greater than or equal to a first preset pressure value; The second conductive type semiconductor layer is located on a side of the active layer away from the substrate.

9. The semiconductor epitaxial structure according to claim 8, characterized in that: The three-dimensional structure array includes a plurality of three-dimensional structures, and the three-dimensional structures in the three-dimensional structure array include at least one of a cone structure, a triangular pyramid structure, a hexagonal prism structure, a regular quadrangular pyramid structure, and a regular hexagonal pyramid structure; The height of the three-dimensional structure is in the range of 50 nm to 400 nm, the diameter or side length of the bottom pattern is in the range of 50 nm to 500 nm, and the distance between two adjacent three-dimensional structures is in the range of 50 nm to 300 nm.

10. The semiconductor epitaxial structure according to claim 8, characterized in that: Also includes: A pre-well layer, located between the first-conductivity-type semiconductor layer and the active layer, and covering the surface of the three-dimensional structure array and the surface of the first-conductivity-type semiconductor layer between the three-dimensional structure arrays; the pre-well layer includes a plurality of superlattice layers stacked by In x Ga 1-x N layers and GaN layers; where 0.05 < x < 0.2; the active layer includes a plurality of quantum well layers stacked by In y Ga 1-y N layers and GaN layers; where 0.05 < y < 0.95; and / or, an electron blocking layer, wherein the electron blocking layer is located on a side of the active layer away from the substrate; and / or, a buffer layer, wherein the buffer layer is located between the substrate and the first conductive type semiconductor layer.

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